A hybrid memory structure and a manufacturing method and an operating method thereof

Abstract

The application relates to a hybrid memory structure and a manufacturing method and an operating method thereof, the memory structure comprising a laminated structure on a substrate, the laminated structure comprising alternately arranged main gate layers and isolation layers, and the bottom layer and the top layer of the laminated structure being isolation layers, the laminated structure comprising a first / laminated structure and a second / laminated structure separated from each other; a first memory cell comprising the first laminated structure, a first through hole and a barrier layer, a charge trapping layer, a tunneling layer, a first channel layer and a first support layer arranged in sequence on the sidewall of the first through hole; and a second memory cell comprising the second laminated structure, a second through hole and a dielectric layer, a ferroelectric layer, a auxiliary gate material layer, a second channel layer and a second support layer arranged in sequence on the sidewall of the second through hole. The technical scheme of the application avoids data transmission between chips, realizes data transmission within the chip, avoids the influence of transmission delay of an external data bus, and improves the data transmission speed.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a hybrid memory structure and its manufacturing and operation methods. Background Technology

[0002] 3D NAND flash memory is currently the most mainstream non-volatile memory, ensuring data retention even after power loss. Its biggest advantage over other types of memory lies in its extremely high storage density. The amount of data stored per unit area is primarily due to its three-dimensional structure, utilizing a multi-layered stacked architecture to store data in both horizontal and vertical directions. However, 3D NAND flash memory has a relatively slow read speed, typically on the order of tens to hundreds of microseconds. In applications such as solid-state drives (SSDs), 3D NAND flash memory is often used in conjunction with DRAM, with DRAM acting as a cache for the 3D NAND flash. However, because they reside on separate chips, data transfer between them is delayed and slow.

[0003] Based on the above analysis, there is an urgent need to find a memory structure that can improve data transmission speed while meeting the requirements of memory storage capacity and read / write speed. Summary of the Invention

[0004] Based on the above analysis, the present invention aims to provide a hybrid memory structure and its manufacturing and operation methods to solve the problems of data transmission delay and low transmission speed between existing 3D NAND memory and DRAM when they are used together.

[0005] On one hand, embodiments of the present invention provide a hybrid memory structure, including a stacked structure located on a substrate, the stacked structure including alternating main gate layers and isolation layers, and the bottom and top layers of the stacked structure are both isolation layers, the stacked structure including a first stacked structure and a second stacked structure separated from each other;

[0006] The first storage cell includes the first stacked structure, a first through-hole penetrating the first stacked structure, and a barrier layer, a charge trapping layer, a tunneling layer, a first channel layer, and a first support layer sequentially disposed from the outside to the inside on the sidewall of the first through-hole.

[0007] The second memory cell includes the second stacked structure, a second via penetrating the second stacked structure, and a dielectric layer, a ferroelectric layer, a secondary gate material layer, a second channel layer, and a second support layer sequentially disposed from the outside to the inside on the sidewall of the second via.

[0008] Furthermore, the memory structure includes multiple memory matrices, each memory matrix including a first memory region and a second memory region, the first memory region including multiple first memory cells, and the second memory region including multiple second memory cells.

[0009] Furthermore, the first storage area is a 3D NAND memory area, the second storage area is a ferroelectric memory area, and the area of ​​the first storage area is larger than the area of ​​the second storage area.

[0010] Furthermore, both the first through hole and the second through hole are cylindrical, and the diameters of the first through hole and the second through hole are equal, with the diameters of the first through hole and the second through hole selected from 90nm-110nm.

[0011] Furthermore, the charge trapping layer is a silicon nitride material, the tunneling layer is a silicon oxide material, and the first channel layer is a polycrystalline silicon material.

[0012] Furthermore, the ferroelectric layer material is HZO, the auxiliary gate material layer is a metal nitride, and the second channel layer is polysilicon or a metal conductive material.

[0013] In another aspect, embodiments of the present invention provide a method for fabricating a hybrid memory structure, comprising:

[0014] Provide a base;

[0015] A stacked structure is formed on the substrate, the stacked structure including alternating main gate layers and isolation layers, and the bottom and top layers of the stacked structure are both isolation layers, the stacked structure including a first stacked structure and a second stacked structure that are separated from each other;

[0016] A barrier layer, a charge trapping layer, a tunneling layer, a first channel layer, and a first support layer are deposited sequentially from the outside to the inside of the sidewall of the first through-hole penetrating the first stacked structure to form a first memory cell.

[0017] A dielectric layer, a ferroelectric layer, a secondary gate material layer, a second channel layer, and a second support layer are deposited sequentially from the outside to the inside of the sidewall of the second via penetrating the second stacked structure to form a second memory cell.

[0018] Furthermore, a laminated structure is formed on the substrate, including:

[0019] An initial layered structure is formed on the substrate;

[0020] The initial stacked structure is etched to obtain a separating groove that separates the first stacked structure from the second stacked structure, a first through hole that penetrates the first stacked structure, and a second through hole that penetrates the second stacked structure.

[0021] The dividing groove is filled to obtain the dividing line that separates the first stacked structure and the second stacked structure.

[0022] Furthermore, the method also includes

[0023] The surfaces of the first storage unit, the second storage unit, and the dividing line away from the substrate are polished.

[0024] In another aspect, embodiments of the present invention provide an operation method applied to any of the hybrid memory structures described above, the method comprising:

[0025] When data needs to be stored, it is first stored in the second storage unit.

[0026] Determine whether the hybrid memory structure is in an idle state;

[0027] If the hybrid memory structure is in an idle state, the data stored in the second memory cell will be stored in the first memory cell.

[0028] Compared with the prior art, the present invention can achieve at least the following beneficial effects:

[0029] This application employs a technical solution that places the first and second memory cells on the same substrate (i.e., on the same chip), and combines the first memory cell with a first stacked structure, a first via, and a barrier layer, a charge trapping layer, a tunneling layer, a first channel layer, and a first support layer sequentially arranged from the outside to the inside on the sidewall of the first via, and the second memory cell with a second stacked structure, a second via, and a dielectric layer, a ferroelectric layer, a secondary gate material layer, a second channel layer, and a second support layer sequentially arranged from the outside to the inside on the sidewall of the second via. This eliminates the need to embed DRAM as a cache in the SSD, directly using the second memory cell instead of DRAM as a cache. Furthermore, the second memory cell is located on the same chip as the first memory cell, and the second memory cell is non-volatile, retaining data even after power failure, thus extending data availability. The data transmission distance is shorter, eliminating the need for chip-to-chip data transmission, and instead enabling internal chip-level data transmission, avoiding the impact of external data bus transmission delays and improving data transmission speed.

[0030] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from the description and drawings, which are particularly pointed out. Attached Figure Description

[0031] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0032] Figure 1 This is a schematic diagram of a hybrid memory structure according to an embodiment of this application;

[0033] Figure 2 This is a schematic diagram of multiple storage matrix structures in one embodiment of this application;

[0034] Figure 3 This is a schematic diagram of a method for fabricating a hybrid memory structure according to an embodiment of this application;

[0035] Figures 4(a) to 4(d) This is a schematic diagram of the structure corresponding to each step in a method for fabricating a hybrid memory structure.

[0036] Figure 5 This is a schematic diagram of an operation method in one embodiment of this application.

[0037] Figure label:

[0038] 1-First memory cell; 11-First stacked structure; 12-First via; 13-Barrier layer; 14-Charge trapping layer; 15-Tunneling layer; 16-First channel layer; 17-First support layer; 2-Second memory cell; 21-Second stacked structure; 22-Second via; 23-Dielectric layer; 24-Ferroelectric layer; 25-Second gate material layer; 26-Second channel layer; 27-Second support layer; 3-Substrate; 4-Isolation layer; 5-Main gate layer; 6-Separator trench; 7-Divider line; 10-First memory region; 20-Second memory region Detailed Implementation

[0039] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0040] One specific embodiment of the present invention discloses a hybrid memory structure, such as... Figure 1 As shown.

[0041] The structure includes a stacked structure on a substrate, the stacked structure including alternating main gate layers and isolation layers, and the bottom and top layers of the stacked structure are both isolation layers. The stacked structure includes a first stacked structure and a second stacked structure separated from each other. The first memory cell includes the first stacked structure, a first via penetrating the first stacked structure, and a barrier layer, a charge trapping layer, a tunneling layer, a first channel layer, and a first support layer arranged sequentially from the outside to the inside on the sidewall of the first via. The second memory cell includes the second stacked structure, a second via penetrating the second stacked structure, and a dielectric layer, a ferroelectric layer, a secondary gate material layer, a second channel layer, and a second support layer arranged sequentially from the outside to the inside on the sidewall of the second via.

[0042] Compared with the prior art, the hybrid memory array structure provided in this embodiment, by adopting a technical solution that places the first memory unit and the second memory unit on the same substrate, that is, the first memory unit and the second memory unit on the same chip, and combining the first memory unit including a first stacked structure, a first via, and a barrier layer, a charge trapping layer, a tunneling layer, a first channel layer and a first support layer arranged sequentially from the outside to the inside on the sidewall of the first via, and the second memory unit including a second stacked structure, a second via, and a dielectric layer, a ferroelectric layer, a secondary gate material layer, a second channel layer and a second support layer arranged sequentially from the outside to the inside on the sidewall of the second via, eliminates the need to embed DRAM as cache in SSD, and directly uses the second memory unit to replace DRAM as cache. Moreover, the second memory unit and the first memory unit are located on the same chip, and the second memory unit is non-volatile, and the data can still be retained after power failure, which extends the data timeliness, shortens the data transmission distance, and eliminates the need for chip-to-chip data transmission, but rather internal chip data transmission, avoiding the impact of external data bus transmission delay and improving data transmission speed.

[0043] Specifically, please see Figures 1 to 4(d) The hybrid memory structure in this application includes a stacked structure on a substrate 3. The stacked structure includes alternating main gate layers 5 and isolation layers 4, and the bottom and top layers of the stacked structure are both isolation layers 4. The stacked structure includes a first stacked structure 11 and a second stacked structure 21 that are separated from each other. The first memory cell 1 includes the first stacked structure 11, a first via 12 penetrating the first stacked structure 11, and a barrier layer 13, a charge trapping layer 14, a tunneling layer 15, a first channel layer 16, and a first support layer 17 arranged sequentially from the outside to the inside on the sidewall of the first via 12. The second memory cell 2 includes the second stacked structure 21, a second via 22 penetrating the second stacked structure 21, and a dielectric layer 23, a ferroelectric layer 24, a secondary gate material layer 25, a second channel layer 26, and a second support layer 27 arranged sequentially from the outside to the inside on the sidewall of the second via. Figure 1The first and second memory units are shown to each include four operation units corresponding to four main gate layers. The specific number of operation units corresponding to the first and second memory units can be determined according to actual needs, and this application does not limit this.

[0044] Optionally, the isolation layer 4 is made of silicon oxide with a thickness of 25 nm to 35 nm, for example, 30 nm; the main gate layer 5 is made of polysilicon or metal with a thickness of 20 nm to 30 nm, for example, 25 nm.

[0045] In one specific embodiment, the memory structure includes multiple memory matrices, each memory matrix including a first memory region and a second memory region, the first memory region including multiple first memory cells, and the second memory region including multiple second memory cells.

[0046] Specifically, such as Figure 2 As shown, taking the memory structure as an example, which includes four memory matrices, the four memory arrays are located on the same chip. Each memory matrix includes a first memory region 10 and a second memory region 20. The first memory region 10 includes multiple first memory cells 1, and the second memory region 20 includes multiple second memory cells 2.

[0047] Setting up multiple storage areas on the same chip makes data transfer between different storage areas more convenient and efficient, avoiding the delay caused by the data bus in data transfer between chips.

[0048] Further reading is available upon request. Figure 2 Each storage matrix also includes an addressing circuit region and a peripheral circuit region, with the addressing circuit region located in... Figure 2 The peripheral circuit area is located to the right of the second storage area 20, below the first storage area 10, the second storage area 20, and the addressing circuit area. Specifically, the addressing circuit area is used to select the smallest operating unit and determine the position of the operating unit through row and column decoding circuits, thereby performing corresponding data operations; the peripheral circuit area is used to send read and write operation voltage control signals and generate operating voltages.

[0049] In one specific embodiment, the first storage region 10 is a 3D NAND memory region, the second storage region 20 is a ferroelectric memory region, and the area of ​​the first storage region 10 is larger than the area of ​​the second storage region 20.

[0050] Specifically, the main function of the first storage area is to store data, and it has a larger area; the main function of the second storage area is to pre-store data or cache data. The read speed of the second storage unit in the second storage area is higher than that of the first storage unit in the first storage area, and the area of ​​the second storage area is smaller than that of the first storage area.

[0051] The first storage area is a 3D NAND memory area, and the second storage area is a ferroelectric memory area. 3D NAND memory has high storage density, and ferroelectric memory has fast operation speed. This configuration increases the storage capacity of the memory while ensuring the operation speed.

[0052] In one specific embodiment, both the first through hole 12 and the second through hole 22 are cylindrical, and the diameters of the first through hole and the second through hole are equal, with the diameters of the first through hole and the second through hole selected from 90nm-110nm.

[0053] The first through hole and the second through hole have the same diameter, which makes it easy to obtain the first through hole and the second through hole in one step of the process, reducing the number of process steps and reducing the difficulty of the process.

[0054] In one specific embodiment, the charge trapping layer is a silicon nitride material, the tunneling layer is a silicon oxide material, and the first channel layer is a polycrystalline silicon material.

[0055] Specifically, the barrier layer is made of silicon oxide with a thickness of 5nm-7nm, for example, 6nm; the charge trapping layer is made of silicon nitride with a thickness of 5nm-7nm, for example, 6nm; the tunneling layer is made of silicon oxide with a thickness of 5nm-7nm, for example, 6nm; the first channel layer is made of polycrystalline silicon with a thickness of 5nm-7nm, for example, 6nm; and the first support layer is made of silicon oxide with a diameter of 45-55nm, preferably 52nm.

[0056] In one specific embodiment, the ferroelectric layer material is HZO, the auxiliary gate material layer is a metal nitride, and the second channel layer is polysilicon or a metal conductive material.

[0057] Specifically, the dielectric layer is made of silicon oxide with a thickness of 5nm-7nm, for example, 6nm; the ferroelectric layer is made of HZO with a thickness of 8nm-12nm, for example, 9nm; the auxiliary gate material layer is made of metal nitride, such as titanium nitride or tantalum nitride, with a thickness of 5nm-7nm, for example, 6nm; the second channel layer is made of polysilicon or a metal conductive material with a thickness of 5nm-7nm, for example, 6nm; and the second support layer is made of silicon oxide with a diameter of 45-55nm, preferably 46nm.

[0058] A specific embodiment of the present invention discloses a method for fabricating a hybrid memory structure; please refer to the detailed flowchart. Figure 3 as well as Figures 4(a) to 4(d) The method includes:

[0059] Step S10: Provide a substrate;

[0060] Step S20: A stacked structure is formed on the substrate. The stacked structure includes alternating main gate layers and isolation layers, and the bottom and top layers of the stacked structure are both isolation layers. The stacked structure includes a first stacked structure 11 and a second stacked structure 12 that are separated from each other.

[0061] Step S30: Deposit a barrier layer, a charge trapping layer, a tunneling layer, a first channel layer, and a first support layer sequentially from the outside to the inside on the sidewall of the first through-hole penetrating the first stacked structure to form a first memory cell;

[0062] Specifically, a barrier layer, a charge trapping layer, a tunneling layer, a first channel layer, and a first support layer are deposited sequentially from the outside to the inside on the sidewall of the first via by ALD (atomic layer deposition) to form a first memory cell. Please refer to Figure 4(d) for a schematic diagram of the structure after step S30.

[0063] Step S40: Deposit a dielectric layer, a ferroelectric layer, a secondary gate material layer, a second channel layer, and a second support layer sequentially from the outside to the inside of the sidewall of the second via penetrating the second stacked structure to form a second memory cell.

[0064] Specifically, a dielectric layer, a ferroelectric layer, a secondary gate material layer, a second channel layer, and a second support layer are sequentially deposited from the outside to the inside on the sidewall of the second via using ALD (atomic layer deposition) to form the second memory cell. For a schematic diagram of the structure after step S40, please refer to [link to schematic diagram]. Figure 1 .

[0065] This embodiment employs a technical solution that forms the first and second memory cells on the same substrate (i.e., on the same chip). The first memory cell includes a first stacked structure, a first via, and a barrier layer, a charge trapping layer, a tunneling layer, a first channel layer, and a first support layer sequentially disposed from the outside to the inside on the sidewall of the first via. The second memory cell includes a second stacked structure, a second via, and a dielectric layer, a ferroelectric layer, a secondary gate material layer, a second channel layer, and a second support layer sequentially disposed from the outside to the inside on the sidewall of the second via. This eliminates the need to embed DRAM as a cache in the SSD, directly using the second memory cell instead of DRAM as a cache. Furthermore, the second memory cell is located on the same chip as the first memory cell, and the second memory cell is non-volatile, retaining data even after power failure, thus extending data availability. The data transmission distance is shorter, eliminating the need for chip-to-chip data transmission, and instead enabling internal chip-level data transmission, avoiding the impact of external data bus transmission delays and improving data transmission speed.

[0066] In one specific embodiment, step S20 includes:

[0067] Step S21: Form an initial stacked structure on the substrate;

[0068] Specifically, the substrate material is silicon. An isolation layer and a main gate layer are alternately deposited on the substrate by a thin film deposition method to form an initial stacked structure on the substrate. The bottom layer of the initial stacked structure near the substrate and the top layer away from the substrate are both isolation layers. Please refer to Figure 4(a) for a schematic diagram of the structure after step S21.

[0069] Step S22: Etch the initial stacked structure to obtain a separating groove 6 that separates the first stacked structure and the second stacked structure, a first through hole 12 that penetrates the first stacked structure, and a second through hole 22 that penetrates the second stacked structure.

[0070] Specifically, the partition groove 6 is obtained by the first dry etching, and the first through hole 12 and the second through hole 22 are obtained by the second dry etching; or, the first through hole 12 and the second through hole 22 are obtained by the first dry etching, and the partition groove 6 is obtained by the second dry etching. The first stacked structure and the second stacked structure obtained by the partition groove 6 are insulated from each other. Please refer to Figure 4(b) for a schematic diagram of the structure after step S22.

[0071] Step S23: Fill the dividing groove 6 to obtain the dividing line 7 that separates the first stacked structure and the second stacked structure.

[0072] Specifically, silicon oxide is deposited in the separator trench 6 by thin film deposition to form the separator line 7, as shown in Figure 4(c).

[0073] The dividing line separates the first storage unit and the second storage unit, allowing different storage units to operate independently without interfering with each other, thus improving work efficiency.

[0074] In one specific embodiment, the method further includes polishing the surfaces of the first storage cell, the second storage cell, and the dividing line away from the substrate.

[0075] Polishing flattens the surface, preparing it for subsequent processes and improving the reliability of the deposited film.

[0076] A specific embodiment of the present invention discloses an operation method applied to any of the above-described hybrid memory structures. Please refer to [link to relevant documentation]. Figure 5 The operation method includes:

[0077] When data needs to be stored, it is first stored in the second storage unit.

[0078] Determine whether the hybrid memory structure is in an idle state;

[0079] If the hybrid memory structure is in an idle state, the data stored in the second memory cell will be stored in the first memory cell.

[0080] Specifically, a hybrid memory being in an idle state means that there are no read or write operations on the hybrid memory. For example, during the power-on state, when the hard drive is idle, the memory does not perform read or write operations; during the system preparation process, because the second storage unit is non-volatile, the data in the memory will not be lost even after the power is turned off. During this period of system preparation (i.e., from turning on the power to the system completing preparation and powering on), the data stored in the second storage unit can be stored in the first storage unit; in sleep mode, when the system is in sleep mode, the memory is in an idle state, and the data stored in the second storage unit is stored in the first storage unit.

[0081] The operating method based on the above hybrid memory structure does not require data transmission between chips, but rather data transmission within the chip. This avoids the transmission delay of the external data bus and improves the data transmission speed while ensuring storage capacity.

[0082] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0083] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A hybrid memory structure, characterized in that, The stacked structure includes a stacked structure located on a substrate, the stacked structure including alternating main gate layers and isolation layers, and the bottom and top layers of the stacked structure are both isolation layers, the stacked structure including a first stacked structure and a second stacked structure separated from each other by a separator line; The first storage cell includes the first stacked structure, a first through-hole penetrating the first stacked structure, and a barrier layer, a charge trapping layer, a tunneling layer, a first channel layer, and a first support layer sequentially disposed from the outside to the inside on the sidewall of the first through-hole. The second memory cell includes the second stacked structure, a second via penetrating the second stacked structure, and a dielectric layer, a ferroelectric layer, a secondary gate material layer, a second channel layer, and a second support layer sequentially disposed from the outside to the inside on the sidewall of the second via; the dielectric layer is made of silicon oxide. The hybrid memory structure includes multiple memory matrices, each memory matrix including a first memory region and a second memory region, the first memory region including multiple first memory cells, and the second memory region including multiple second memory cells; each memory matrix also includes an addressing circuit region and a peripheral circuit region. The first storage area is a 3D NAND memory area, and the second storage area is a ferroelectric memory area; The first storage area is used to store data, and the second storage area is used to pre-store data or cache data.

2. The memory structure according to claim 1, characterized in that, The addressing circuit area is used to select the smallest operating unit and determine the position of the operating unit through the row and column decoding circuit, thereby performing the corresponding data operation; the peripheral circuit area is used to send read and write operation voltage control signals and generate operating voltage; the read speed of the second storage cell in the second storage area is higher than the read speed of the first storage cell in the first storage area.

3. The memory structure according to claim 2, characterized in that, The area of ​​the first storage region is larger than the area of ​​the second storage region.

4. The memory structure according to claim 1, characterized in that, Both the first through hole and the second through hole are cylindrical, and the diameters of the first through hole and the second through hole are equal, with the diameters selected from 90nm-110nm.

5. The memory structure according to claim 1, characterized in that, The charge trapping layer is a silicon nitride material, the tunneling layer is a silicon oxide material, and the first channel layer is a polycrystalline silicon material.

6. The memory structure according to claim 1, characterized in that, The ferroelectric layer material is HZO, the auxiliary gate material layer is a metal nitride, and the second channel layer is polysilicon or a metal conductive material.

7. A method for fabricating a hybrid memory structure, characterized in that, The manufacturing method includes: Provide a base; A stacked structure is formed on the substrate, the stacked structure including alternating main gate layers and isolation layers, and the bottom and top layers of the stacked structure are both isolation layers. The stacked structure includes a first stacked structure and a second stacked structure separated from each other by a separator line. A barrier layer, a charge trapping layer, a tunneling layer, a first channel layer, and a first support layer are deposited sequentially from the outside to the inside of the sidewall of the first through-hole penetrating the first stacked structure to form a first memory cell. A dielectric layer, a ferroelectric layer, a secondary gate material layer, a second channel layer, and a second support layer are deposited sequentially from the outside to the inside of the sidewall of the second via penetrating the second stacked structure to form a second memory cell. The dielectric layer is made of silicon oxide. The hybrid memory structure includes multiple memory matrices, each memory matrix including a first memory region and a second memory region, the first memory region including multiple first memory cells, and the second memory region including multiple second memory cells; each memory matrix also includes an addressing circuit region and a peripheral circuit region. The first storage area is a 3D NAND memory area, and the second storage area is a ferroelectric memory area; the first storage area is used to store data, and the second storage area is used to pre-store data or cache data.

8. The manufacturing method according to claim 7, characterized in that, A laminated structure is formed on the substrate, including: An initial stacked structure is formed on the substrate; The initial stacked structure is etched to obtain a separating groove that separates the first stacked structure from the second stacked structure, a first through hole that penetrates the first stacked structure, and a second through hole that penetrates the second stacked structure. The dividing groove is filled to obtain the dividing line that separates the first stacked structure and the second stacked structure.

9. The manufacturing method according to claim 8, characterized in that, The method further includes: The surfaces of the first storage unit, the second storage unit, and the dividing line away from the substrate are polished.

10. An operating method applied to the hybrid memory structure as described in any one of claims 1-6, characterized in that, The method includes: When data needs to be stored, it is first stored in the second storage unit. Determine whether the hybrid memory structure is in an idle state; If the hybrid memory structure is in an idle state, the data stored in the second memory cell will be stored in the first memory cell.

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