Semiconductor device and method of forming a semiconductor device

Abstract

This invention discloses a semiconductor device, comprising: a semiconductor substrate having a well region; a gate structure formed above the well region of the semiconductor substrate, wherein the gate structure has a first sidewall and a second sidewall opposite to the first sidewall; a gate spacer structure including two asymmetrical portions respectively covering the first sidewall and the second sidewall of the gate structure; and a source region and a drain region formed in the semiconductor substrate, wherein the source region and the drain region are respectively aligned with the outer edges of the two asymmetrical portions of the gate spacer structure, wherein the lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure. The above-described solution of this invention enables the semiconductor device to have a greater withstand voltage capability, improves the high-voltage capability of the semiconductor device, and enhances the electrical performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor device and a method for forming a semiconductor device. Background Technology

[0002] In recent years, with the increasing demand for high-voltage devices, research on high-voltage metal-oxide-semiconductor (MOS) transistors used in high-voltage devices has received increasing attention. High-voltage (HV) MOS devices used at high voltages can be, but are not limited to, voltages higher than the voltage supplied to I / O circuits. MOS devices such as HVMOS devices can be used as switches and are widely used in audio output drivers, CPU power supplies, power management systems, AC / DC converters, LCD or plasma TV drivers, automotive electronic components, PC peripherals, small DC motor controllers, and other consumer electronics devices.

[0003] While existing semiconductor devices, such as MOS devices, and their fabrication methods are sufficient to meet their intended purposes, they are not entirely satisfactory in all aspects. For example, the complexity of semiconductor device processing and manufacturing increases as the size of semiconductor devices shrinks. With the reduction in semiconductor device size, the lateral distance between electrodes decreases, which can have a significant impact on the electrical performance of the semiconductor device. Furthermore, with advancements in semiconductor manufacturing, the breakdown voltage of high-voltage MOS devices needs to be further increased to meet device performance requirements, as the demand for high-voltage semiconductor devices continues to grow. Therefore, there are still some problems to be overcome in semiconductor devices within semiconductor integrated circuits and technologies. Summary of the Invention

[0004] In view of the above, the present invention provides a semiconductor device and a method for forming a semiconductor device to solve the above problems.

[0005] According to a first aspect of the present invention, a semiconductor device is disclosed, comprising:

[0006] A semiconductor substrate having a well region;

[0007] A gate structure is formed above the well region of the semiconductor substrate, wherein the gate structure has a first sidewall and a second sidewall opposite to the first sidewall;

[0008] A gate spacing structure, comprising two asymmetrical portions respectively covering the first sidewall and the second sidewall of the gate structure; and

[0009] A source region and a drain region are formed in the semiconductor substrate, wherein the source region and the drain region are respectively aligned with the outer edges of the two asymmetrical portions of the gate spacer structure.

[0010] The lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure.

[0011] According to a second aspect of the present invention, a method for forming a semiconductor device is disclosed, comprising:

[0012] A semiconductor substrate is provided, the semiconductor substrate having a well region and an isolation structure adjacent to the well region;

[0013] A gate structure is formed above the well region of the semiconductor substrate, wherein the gate structure has a first sidewall and a second sidewall opposite to the first sidewall.

[0014] A gate spacer structure is formed, the gate spacer structure including two asymmetric portions, the two asymmetric portions respectively covering the first sidewall and the second sidewall of the gate structure; and

[0015] A source region and a drain region are formed in the semiconductor substrate, wherein the source region and the drain region are respectively aligned with the outer edges of the two asymmetric portions of the gate spacer structure.

[0016] The lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure.

[0017] The semiconductor device of the present invention includes: a semiconductor substrate having a well region; a gate structure formed above the well region of the semiconductor substrate, wherein the gate structure has a first sidewall and a second sidewall opposite to the first sidewall; a gate spacer structure including two asymmetrical portions respectively covering the first sidewall and the second sidewall of the gate structure; and a source region and a drain region formed in the semiconductor substrate, wherein the source region and the drain region are respectively aligned with the outer edges of the two asymmetrical portions of the gate spacer structure, and wherein the lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure. The above-described solution of the present invention enables the semiconductor device to have a greater withstand voltage capability, improves the high-voltage capability of the semiconductor device, and enhances the electrical performance of the semiconductor device. Attached Figure Description

[0018] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H and Figure 1IThis is a cross-sectional view of an intermediate stage of a method for forming a semiconductor device according to some embodiments of the present invention.

[0019] Figure 2 This is a cross-sectional view of the intermediate stage of a semiconductor device according to some embodiments of the present invention.

[0020] Figure 3 This is a cross-sectional view of an intermediate stage of a semiconductor device according to some embodiments of the present invention. Detailed Implementation

[0021] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.

[0022] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary element, component, region, layer, or portion discussed below may be referred to as a second or secondary element, component, region, layer, or portion.

[0023] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of an element or feature to it. Another element or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0024] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0025] It will be understood that when an “element” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intermediate elements or layers.

[0026] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0027] According to some embodiments of the present invention, a semiconductor device (or semiconductor apparatus, semiconductor structure) and a method thereof are described below, wherein a gate spacer structure having two spacer portions with different bottom widths is formed to extend the distance between the gate structure and the drain region of the semiconductor device. In some embodiments, the semiconductor device includes a semiconductor substrate having a well region, a gate structure formed above the well region of the semiconductor substrate, a source region and a drain region formed in the semiconductor substrate and separated from the gate structure, and gate spacer structures on two opposite sidewalls of the gate structure. The source region and the drain region are located near opposite sides of the gate structure. The gate spacer structure includes a first spacer portion and a second spacer portion located on opposite sidewalls of the gate structure. The first spacer portion is adjacent to the source region, while the second spacer portion is adjacent to the drain region. In some embodiments, the bottom width of the second spacer portion is greater than the bottom width of the first spacer portion.

[0028] The electrical performance of semiconductor devices according to some embodiments of the present invention can be significantly improved. For example, the safe operating area (SOA) diagram, which defines the maximum values ​​of the drain-source voltage (VDS) and drain current (ID), can be improved to ensure proper operation of semiconductor devices (e.g., metal-oxide-semiconductor field-effect transistors, MOSFETs). In some embodiments, the extended distance between the drain region and the gate structure of the semiconductor device increases the breakdown voltage and expands the SOA area. Additionally, when the bottom width of the second spacer portion adjacent to the drain region is greater than the bottom width of the first spacer portion adjacent to the source region, the lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure of the semiconductor device, thereby reducing undesirable parasitic capacitance between the gate structure and the drain contact plug connected to the drain region. Therefore, semiconductor devices according to some embodiments of the present invention can be operated (or run) at higher switching speeds. In this case, asymmetrical first and second spacer portions are provided on both sides of the gate structure, wherein the second spacer portion closer to the drain region has a larger lateral width than the first spacer portion closer to the source region. The larger extension distance between the drain region and gate structure of a semiconductor device increases the breakdown voltage and the safe operating area (SOA). The above-described solution of the present invention enables the semiconductor device to have a larger withstand voltage, improves its high-voltage capability, and enhances its electrical performance. Furthermore, the use of the first and second spacers (formed before the source and drain regions) allows for automatic alignment of the subsequently formed source and drain regions, enabling them to automatically align with the sidewalls of the first and second spacers, respectively. This saves shielding and process steps, reduces manufacturing costs, and improves production efficiency. In addition, the larger extension distance between the drain region and gate structure of the semiconductor device reduces unwanted parasitic capacitance between the gate structure and the contact plug connected to the drain region.

[0029] The following provides some methods for forming a semiconductor device according to some embodiments of the present invention. It should be noted that the present invention is not limited to the exemplary methods and structures described herein. The steps and structures described below are merely examples for providing examples of the fabrication and configuration of semiconductor devices.

[0030] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H and Figure 1I This is a cross-sectional view of an intermediate stage of a method for forming a semiconductor device according to some embodiments of the present invention. For simplicity, only a single transistor is depicted here. However, the number of transistors is not limited to this.

[0031] refer to Figure 1A A semiconductor substrate 100 is provided, having a well region 104 and an isolation structure 108 adjacent to the well region 104. Furthermore, a gate structure 110 is formed above the well region 104 of the semiconductor substrate 100. In some embodiments, the semiconductor substrate 100 is a silicon substrate. The semiconductor substrate 100 may have a first conductivity type, such as P-type. The well region 104 is formed in the semiconductor substrate 100 and may have a second conductivity type, such as N-type.

[0032] Although only well region 104 is depicted in semiconductor substrate 100 for simplicity, semiconductor substrate 100 may also include other features, such as other well regions. For example, semiconductor substrate 100 may also include a deep well region (not shown) having a second conductivity type opposite to the first conductivity type, such as N-type. Furthermore, semiconductor substrate 100 may also include a well region (not shown) formed in the deep well region having a first conductivity type such as P-type (referred to as a P-well region), wherein a portion of the P-well region extends between the deep well region and well region 104. Well region 104 may be formed within the P-well region and surrounded by isolation structure 108 and the P-well region.

[0033] like Figure 1A As shown, an isolation structure 108 extending downward from the upper surface 100a of the semiconductor substrate 100 is embedded in the semiconductor substrate 100. In some embodiments, the isolation structure 108 includes a shallow trench isolation (STI) element. In some embodiments, the isolation structure 108 includes a field oxide (FOX) isolation element. The isolation structure 108 may include silicon oxide, another suitable insulating material, or a combination thereof.

[0034] In some embodiments, a gate structure 110 is formed on the upper surface 100a of a semiconductor substrate 100 and above a well region 104 of the semiconductor substrate 100. The gate structure 110 has a first sidewall 110S1 and a second sidewall 110S2 opposite to the first sidewall 110S1. The gate structure 110 may include a gate dielectric layer 111 and a conductive layer 113 located on the gate dielectric layer 111. The gate structure 110 can be formed by a photolithography process that patterns the material layers of the gate dielectric layer 111 and the conductive layer 113. Although only the gate structure 110 of a single transistor is shown in the figure, multiple gate structures 110 of multiple transistors can be formed in applications, and these gate structures 110 may be spaced apart from each other in a first direction D1 (e.g., the X direction). Furthermore, in some embodiments, the gate structure 110 extends along a second direction D2 (e.g., the Y direction).

[0035] The gate dielectric layer 111 can be a single layer or a multilayer structure. In some embodiments, the gate dielectric layer 111 is a silicon oxide layer. In some embodiments, the gate dielectric layer 111 is formed of oxides, oxide oxynitrides, nitrides, high-k materials, other suitable materials, or combinations thereof. In one example, the gate dielectric layer 111 may include an interface layer (not shown) and a high-k dielectric layer formed on the interface layer. The interface layer, the high-k dielectric layer, and the conductive layer 113 are stacked on a third direction D3 (e.g., the Z direction). For example, the interface layer may be formed on a semiconductor substrate 100 and include a silicon oxide layer. The high-k dielectric layer can be formed on the interface layer by atomic layer deposition (ALD) or other suitable techniques. The conductive layer 113 may be formed on the high-k dielectric layer. The high-k dielectric layer may include hafnium oxide (HfO2). Alternatively, the high-k dielectric layer may optionally include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), and combinations thereof. It should be noted that the gate dielectric layer 111 of the present invention is not limited to the materials described above.

[0036] The conductive layer 113 of the gate structure 110 may be referred to as the gate electrode. In some embodiments, the conductive layer 113 comprises polysilicon, metal, metal silicide, metal nitride, another suitable material, or a combination thereof. Exemplary metal materials for the conductive layer 113 include TiN, TaN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, or other suitable metal materials. Furthermore, in some embodiments, the conductive layer 113 is formed of polysilicon, such as doped polysilicon. The conductive layer 113 of the gate structure 110 may be formed by deposition methods, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electroplating, or other suitable methods.

[0037] In some embodiments, the gate structure 110 further includes a hard mask (not shown) formed over the conductive layer 113. The hard mask can be formed by a deposition process or other suitable process. The hard mask may include silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof. For simplicity, a gate dielectric layer 111 and a conductive layer 113 are depicted herein to illustrate the gate structure 110.

[0038] Furthermore, in some embodiments, a lightly doped region (LDD) 120 is further formed in the semiconductor substrate 100. For example... Figure 1A As shown, the lightly doped region (LDD) 120 includes a first lightly doped region 121 and a second lightly doped region 122. The first lightly doped region 121 is adjacent to the first sidewall 110S1 of the gate structure 110. The second lightly doped region 122 is adjacent to the second sidewall 110S2 of the gate structure 110. In some embodiments, the lightly doped region (LDD) 120 can be formed by using the gate structure as an implantation shield. Therefore, this process method of the present invention can eliminate the need for additional shielding, which not only simplifies the manufacturing process but also reduces the number of components used, improving production efficiency and saving production costs.

[0039] Next, as Figure 1B As shown, a gate spacer material layer 130 comprising one or more spacer material layers (or spacer material layers) is formed over a semiconductor substrate 100, and the gate spacer material layer 130 covers the gate structure 110 (e.g., Figure 1B Then, an initial gate spacer layer (e.g., ) is formed having symmetrical portions covering the first sidewall 110S1 and the second sidewall 110S2 of the gate structure 110, respectively. Figure 1CIn this exemplary embodiment, for illustrative purposes, three spacer material layers formed over the semiconductor substrate 100 are depicted. However, it should be noted that the number of spacer (or spacer) material layers formed is not limited to the exemplary embodiment provided herein.

[0040] Reference Figure 1B A gate spacer material layer 130 having three spacer material layers is formed over the semiconductor substrate 100 and covers the gate structure 110. In some embodiments, the gate spacer material layer 130 includes a first spacer material layer 131, a second spacer material layer 132, and a third spacer material layer 133.

[0041] First, a first spacer material layer 131 is formed on the upper surface 100a of the semiconductor substrate 100, and conformally formed on the first sidewall 110S1 and the second sidewall 110S2 of the gate structure 110. In this exemplary embodiment, the first sidewall 110S1 of the gate structure 110 includes the first sidewall 111S1 of the gate dielectric layer 111 and the first sidewall 113S1 of the conductive layer 113. The second sidewall 110S2 of the gate structure 110 includes the second sidewall 111S2 of the gate dielectric layer 111 and the second sidewall 113S2 of the conductive layer 113. Therefore, the first spacer material layer 131 is formed on the isolation structure 108 and the lightly doped region (LDD) 120 (e.g., including the first lightly doped region 121 and the second lightly doped region 122), and is conformally formed on the first sidewall 111S1 of the gate dielectric layer 111, the first sidewall 113S1 of the conductive layer 113, the top surface (or upper surface) 113a of the conductive layer 113, the second sidewall 113S2 of the conductive layer 113, and the second sidewall 111S2 of the gate dielectric layer 111, as shown. Figure 1B As shown.

[0042] Then, a second spacer material layer 132 is conformally formed on the first spacer material layer 131, and a third spacer material layer 133 is conformally formed on the second spacer material layer 132. The thickness of the third spacer material layer 133 can be determined based on the additional spacer portion (e.g., the second spacer portion GS-2) near the drain region in subsequent processes. Figure 1E The bottom width of the remaining initial interval (symmetrical part) 1332 needs to be adjusted.

[0043] The spacer material can be selected and varied based on the design requirements for forming the semiconductor device. In some embodiments, the first spacer layer 131 (as a liner spacer layer) is formed of silicon oxide, oxide nitride, silicon nitride, or other suitable materials. Furthermore, the second spacer layer 132 and the third spacer layer 133 are, for example, dielectric layers having a low-k dielectric constant. The k-values ​​of the second spacer layer 132 and the third spacer layer 133 can range from about 4.2 to about 5.5. In some embodiments, the first spacer layer 131, the second spacer layer 132, the third spacer layer 133, and the fourth spacer layer 134 are low-k dielectrics containing impurities. The precursor for the deposition process of the low-k dielectric with impurities can include boron-containing gases, such as BCl3, BH3, or B2H6, or carbon-containing gases, such as C2H4 or C2H6. In some embodiments, the spacer material includes oxides, nitrides, boron-containing oxide nitrides, carbon, fluorine, or combinations thereof. In some embodiments, the spacer material comprises silicon carbide having boron, nitrogen, fluorine, or a combination thereof. Furthermore, it should be noted that a suitable dielectric material for the third spacer layer 133 will exhibit low-k characteristics and high etch selectivity compared to the underlying second spacer layer 132.

[0044] In this embodiment, the first spacer layer 131 and the third spacer layer 133 include, but are not limited to, silicon oxide, while the second spacer layer 132 includes, but is not limited to, silicon nitride. In some other embodiments, the second spacer layer 132 is a silicon nitride layer or a combination thereof containing boron, carbon, fluorine impurities. Precursors for the deposition process used to form the silicon nitride layer include silicon-containing gases, such as SiH₂Cl₂, Si₂H₆, SiH₄, Si₂Cl₆, or BTBAS, and nitrogen-containing gases, such as NH₃, N₂, or N₂O. The arrangement of these materials facilitates the patterning of the third spacer layer 133 in subsequent processes.

[0045] Furthermore, the first spacer material layer 131, the second spacer material layer 132, and the third spacer material layer 133 can be formed using plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), atomic layer deposition (ALD), or other suitable and commonly used deposition techniques.

[0046] refer to Figure 1C A third spacer layer (patterning the third spacer layer) 133 is patterned to form an initial gate spacer layer 133' having symmetrical portions 1331 and 1332 covering the second spacer layer 132. In some embodiments, the symmetrical portions 1331 and 1332 of the initial gate spacer layer 133' are located near the first sidewall 110S1 and the second sidewall 110S2 of the gate structure 110, respectively. Furthermore, after forming the symmetrical portions 1331 and 1332, the top surface 132a of the second spacer layer 132 above the gate structure 110 is exposed. The symmetrical portion 1331 may be referred to as the first symmetrical portion, and the symmetrical portion 1332 may be referred to as the second symmetrical portion. The top surfaces of the first and second symmetrical portions may be below or flush with the top surface 132a of the second spacer layer 132, but not above it.

[0047] The third spacer layer 133 can be patterned using wet etching, dry etching, or a combination thereof. In some embodiments, the third spacer layer 133 is patterned using a dry etching process. In some embodiments, the third spacer layer 133 is patterned using anisotropic dry etching. Furthermore, the patterning step is performed on the third spacer layer 133 without any shielding over the gate spacer layer 130. Additionally, in this exemplary embodiment, the anisotropic etching of the third spacer layer 133 (e.g., a silicon oxide layer) provides high selectivity for the second spacer layer 132 (e.g., a silicon nitride layer), and the second spacer layer 132 is substantially not etched during the patterning step performed on the third spacer layer 133.

[0048] Please refer to Figure 1D , Figure 1E , Figure 1F , Figure 1G and Figure 1H , Figure 1D , Figure 1E , Figure 1F , Figure 1G and Figure 1H The steps described are as follows: forming a gate spacer structure GS comprising two asymmetrical (or non-symmetrical) portions (e.g., a first spacer portion GS-1 and a second spacer portion GS-2 with different bottom widths) on opposite sidewalls of a gate structure 110 according to some embodiments of the present invention. According to this embodiment, the asymmetrical portions of the gate spacer structure GS on opposite sidewalls of the gate structure 110 are introduced into the semiconductor device to extend the gate structure 110 and the subsequently formed drain region (e.g., Figure 1H The lateral distance between the drain regions 162 in the middle (e.g., in the first direction D1, i.e., the X direction).

[0049] refer to Figure 1D A patterned shielding layer 150 is provided over the semiconductor substrate 100 to expose one of the symmetrical portions 1331 and 1332 of the initial gate spacer layer 133'. In some embodiments, a source region and a drain region (e.g., ...) are subsequently formed adjacent to the first sidewall 110S1 and the second sidewall 110S2 of the gate structure 110, respectively. Figure 1H The source region 161 and drain region 162 are shown in the diagram. Therefore, the patterned shielding layer 150 exposes the symmetrical portion 1331 near the first sidewall 110S1 of the gate structure 110, but covers the symmetrical portion 1332 near the second sidewall 110S2 of the gate structure 110. Additionally, in some embodiments, the patterned shielding layer 150 includes a material such as photoresist.

[0050] Reference Figure 1E In some embodiments, the symmetrical portion 1331 on the first sidewall 110S1 of the gate structure 110 that is not covered by the patterned shielding layer 150 is removed. It should be noted that the symmetrical portion 1331 of the initial gate spacer layer 133' can be partially or completely removed, as long as the remaining portion after the removal of the symmetrical portion 1331, or the width from the outer surface of the second spacer material layer 132 to the bottom of the first sidewall 110S1 near the gate structure 110 (in the first direction D1), is less than the width from the symmetrical portion 1332 to the bottom of the second sidewall 110S2 near the gate structure 110 (in the first direction D1). In this exemplary embodiment, as... Figure 1E As shown, the symmetrical portion 1331 of the initial gate spacing 133' is completely removed, exposing at least a portion of the second spacer material layer 132 near the first sidewall 110S1 of the gate structure 110. In this embodiment, after the symmetrical portion 1331 of the initial gate spacing 133' is completely removed, the first spacer portion GS-1 and the second spacer portion GS-2 formed in subsequent processes have different amounts of material layers.

[0051] In some embodiments, the symmetrical portion 1331 of the initial gate spacer layer 133' is removed by a selective etching process. The etching process may include a dry etching process, a wet etching process, another suitable process, or a combination thereof. In this exemplary embodiment, the symmetrical portion 1331 of the initial gate spacer layer 133' may be removed by a wet etching process.

[0052] Furthermore, since the patterned shielding layer 150 completely covers the symmetrical portion 1332 of the initial gate spacer layer 133', the symmetrical portion 1332 is completely retained near the second sidewall 110S2 of the gate structure 110 after the patterned shielding layer 150 is removed. For simplicity, in the following description, the remaining symmetrical portion 1332 near the second sidewall 110S2 of the gate structure 110 can also be referred to as the remaining initial spacer portion 1332 (or the second symmetrical portion 1332). The remaining initial spacer portion 1332 is formed to increase the bottom width of the second spacer portion GS-2 formed in subsequent processes. The bottom width of the remaining initial spacer portion (symmetrical portion) 1332 is, for example, width W. A .

[0053] After removing the symmetrical portion 1331 of the initial gate spacer layer 133', the patterned shielding layer 150 is removed. The patterned shielding layer 150 can be removed by stripping, ashing, another suitable process, or a combination thereof.

[0054] Next, as Figure 1F In some embodiments, one or more spacer material layers are formed on the exposed second spacer material layer 132 and the remaining initial spacer portion 1332 near the second sidewall 110S2 of the gate structure 110. In this exemplary embodiment, a spacer material layer conformally formed on the substrate 100 is described herein. However, the number of spacer material layers of the present invention is not limited thereto.

[0055] refer to Figure 1F In some embodiments, a fourth spacer material layer 134 is conformally formed on the exposed second spacer material layer 132 and the remaining initial spacer portion 1332. Specifically, the fourth spacer material layer 134 covers the top surface 132a of the exposed second spacer material layer 132 and the outer surface of the remaining initial spacer portion 1332. Figure 1F As shown, the remaining initial spacer portion 1332 is sandwiched between the fourth spacer (or spacer) material layer 134 and the second spacer material layer (or spacer material layer) 132.

[0056] In some embodiments, the fourth spacer layer 134 is formed of silicon oxide, oxynitride, silicon nitride, or other suitable materials. Furthermore, the fourth spacer layer 134 is, for example, a dielectric layer having a low dielectric constant (low-k). The k value of the fourth spacer layer 134 can range from about 4.2 to about 5.5. In some embodiments, the fourth spacer layer 134 is made of a low-k dielectric having impurities therein. Precursors for the deposition process of the low-k dielectric with impurities may include boron-containing gases, such as BCl3, BH3, or B2H6, or carbon-containing gases, such as C2H4 or C2H6. In some embodiments, the fourth spacer layer 134 comprises oxides, nitrides, oxynitrides, or combinations thereof having impurities such as boron, carbon, or fluorine. In some embodiments, the fourth spacer layer 134 comprises silicon carbide having impurities (e.g., boron, nitrogen, fluorine, or combinations thereof).

[0057] In some embodiments, the fourth spacer layer 134 and the second spacer layer 132 are made of the same material. In one example, the fourth spacer layer 134 and the second spacer layer 132 include, but are not limited to, silicon nitride. However, the fourth spacer layer 134 and the second spacer layer 132 may be made of different materials. For example, the fourth spacer layer 134 may be made of silicon oxide, while the second spacer layer 132 may be made of silicon nitride. Suitable materials can be used to form the fourth spacer layer 134 and the second spacer layer 132, thereby subsequently forming portions with asymmetric portions (e.g., Figure 1H The gate spacing structure GS has a first spacing portion GS-1 and a second spacing portion GS-2 with different bottom widths.

[0058] Next, in some embodiments, the fourth spacer material layer 134 and the second spacer material layer 132 formed over the upper surface 100a of the semiconductor substrate 100 and covering the gate structure 110 are patterned to form gate spacer portions on opposite sidewalls of the gate structure 110.

[0059] refer to Figure 1GIn some embodiments, a patterning step is performed on the spacer material layers, including blanket deposition of a fourth spacer material layer 134 and a second spacer material layer 132 to form asymmetric portions on opposite sidewalls of the gate structure 110. In this embodiment, the patterned fourth spacer material layer (patterned fourth spacer material layer) 134' includes patterned fourth spacer portions 1341 and 1342 respectively located above the first sidewall 110S1 and the second spacer 110S2 of the gate structure 110. The patterned second spacer material layer (patterned second spacer material layer) 132' includes patterned second spacer portions 1321 and 1322 respectively adjacent to the first sidewall 110S1 and the second sidewall 110S2 of the gate structure 110. After the patterning step, as Figure 1G As shown, the remaining initial spacer portion 1332 is disposed between the patterned fourth spacer portion 1342 and the patterned second spacer portion 1322.

[0060] In some embodiments, the fourth spacer layer 134 and the second spacer layer 132 are patterned using a dry etching process. In some embodiments, the fourth spacer layer 134 and the second spacer layer 132 are patterned using an anisotropic dry etching process. Furthermore, the fourth spacer layer 134 and the second spacer layer 132 can be patterned to form those asymmetric portions without providing any shielding over the fourth spacer layer 134 and the second spacer layer 132. Moreover, in this exemplary embodiment, the anisotropic etching of the fourth spacer layer 134 and the second spacer layer 132 (e.g., silicon nitride layers) provides high selectivity for the remaining initial spacer portions 1332 (e.g., silicon oxide portions), and the remaining initial spacer portions 1332 are substantially unetched in this anisotropic etching step. Since the material of the first spacer layer 131 is different from the materials of the second spacer layer 132 and the fourth spacer layer 134, the first spacer layer 131 can provide protection against etching.

[0061] Next, refer to Figure 1HIn some embodiments, the exposed portion of the first spacer material layer 131, which is not covered by the unpatterned fourth spacer material layer (or spacer material layer) 134' and the patterned second spacer material layer (or spacer material layer) 132', on the upper surface 100a of the semiconductor substrate 100 is removed. Therefore, the patterned first spacer material layer (patterned first spacer material layer) 131' is formed in a manner aligned with the outer edges of the patterned second spacer material layer (patterned second spacer material layer) 132' and the patterned fourth spacer material layer (patterned fourth spacer material layer) 134'. In this embodiment, the patterned first spacer material layer (patterned first spacer material layer) 131' includes patterned first spacer portions 1311 and 1312, respectively, adjacent to the first sidewall 110S1 and the second sidewall 110S2 of the gate structure 110. The patterned first spacer portion 1311 includes a vertical portion that is in direct contact with the first sidewall 110S1 and a lateral portion that is in direct contact with the first lightly doped region 121 (first lightly doped region 123). The patterned first spacer portion 1312 includes a vertical portion that is in direct contact with the first sidewall 110S2 and a lateral portion that is in direct contact with the second lightly doped region 122 (first lightly doped region 124).

[0062] In some embodiments, the exposed portions of the first spacer layer 131 that are not covered by the patterned fourth spacer layer 134' and the patterned second spacer layer (patterned second spacer layer) 132' are removed by a wet etching process. In one example, for such... Figure 1G The structure shown undergoes a wet cleaning step to remove the exposed portion of the first spacer material layer 131 and unwanted native oxides that spontaneously form on the surface of the material layer.

[0063] In some embodiments, such as Figure 1HAs shown, after removing the exposed portion of the first spacer material layer 131 to form a patterned first spacer material layer 131', a gate spacer structure GS comprising two asymmetrical portions is formed on opposite sidewalls of the gate structure 110. The gate spacer structure GS includes a first spacer portion GS-1 on the first sidewall 110S1 of the gate structure 110 and a second spacer portion GS-2 on the second spacer 110S2 of the gate structure 110. In this exemplary embodiment, the patterned first spacer portion 1311, the patterned second spacer portion 1321, and the patterned fourth spacer portion 1341 on the first sidewall 110S1 of the gate structure 110 collectively form the first spacer portion GS-1 of the gate spacer structure GS. In some embodiments, the patterned first spacer portion 1312, the patterned second spacer portion 1322, the remaining initial spacer portion 1332, and the patterned fourth spacer portion 1342 on the second sidewall 110S2 of the gate structure 110 collectively form the second spacer portion GS-2 of the gate spacer structure GS.

[0064] In addition, refer to Figure 1H Heavily doped regions 160, such as source region 161 and drain region 162, are formed in a semiconductor substrate 100. Source region 161 and drain region 162 are located near a first sidewall 110S1 and a second sidewall 110S2, respectively, of the gate structure 110. According to one embodiment, source region 161 and drain region 162 are formed using asymmetrical portions (i.e., first spacer portion GS-1 and second spacer portion GS-2) of the gate structure 110 and the gate spacer structure GS as implantation (or injection) shields. Therefore, according to some embodiments of the present invention, no additional shielding is required during the formation of source region 161 and drain region 162. The embodiments of the present invention provide an automated alignment process for forming source region 161 and drain region 162, which facilitates manufacturing and eliminates the need for additional shielding, saving shielding costs and shielding steps, and improving manufacturing efficiency and yield.

[0065] Furthermore, according to some embodiments of the present invention, the inner edges of the source region 161 and the drain region 162 can be self-aligned with the outer edges of the first spacing portion GS-1 and the second spacing portion GS-2 of the gate spacing structure GS. For example... Figure 1HAs shown, the inner edge (inner edge) of the source region 161 is aligned with the outer edge OE1 of the first spacer GS-1, and the inner edge of the drain region 162 is aligned with the outer edge OE2 of the second spacer GS-2. In other words, according to some embodiments of the present invention, no spacer material covers the top surface 161a of the source region 161 and the top surface 162a of the drain region 162. Therefore, according to some embodiments, the entire top surface 161a of the source region 161 and the entire top surface 162a of the drain region 162 provide a large area for forming silicide regions (not shown) on the source region 161 and drain region 162 in subsequent processes.

[0066] also, Figure 1G and Figure 1H The bottom width and lateral extension length of the asymmetrical portion of the gate spacer structure GS are depicted. (Reference) Figure 1G and Figure 1H In some embodiments, the first spacing portion GS-1 of the gate spacing structure GS has a bottom width WB1 between the outer edge OE1 of the first spacing portion GS-1 and the gate structure 110 (e.g., defined on the first direction D1, for example...). Figure 1G The second spacing portion GS-2 of the gate spacing structure GS has a bottom width WB2 between the outer edge OE2 of the second spacing portion GS-2 and the gate structure 110 (e.g., defined on the first direction D1, for example). Figure 1G (in the X direction). The bottom width WB2 is greater than the bottom width WB1 (WB2>WB1), such as... Figure 1G As shown.

[0067] In some embodiments, the bottom width WBl of the first spacing portion GS-1 can be defined as the lateral distance Wl between the source region 161 and the gate structure 110. Figure 1H That is, the bottom width WB1 of the first interval portion GS-1 ( Figure 1G The width WB2 of the second spacer GS-2 is equal to the lateral distance W1 between the source region 161 and the gate structure 110. In some embodiments, the lateral distance W1 may be referred to as the first width W1 of the bottom surface of the first spacer GS-1. Similarly, the bottom width WB2 of the second spacer GS-2 may be defined as the lateral distance W2 between the drain region 162 and the gate structure 110. That is, the bottom width WB2 of the second spacer GS-2 is equal to the lateral distance W2 between the drain region 162 and the gate structure 110. In some embodiments, the lateral distance W2 may be referred to as the second width W2 of the bottom surface of the second spacer GS-2.

[0068] According to some embodiments, the bottom width WB2 of the second spacer portion GS-2 (e.g., in the first direction D1) is greater than the bottom width WBl of the first spacer portion GS-1 (e.g., in the first direction D1), such as... Figure 1G As shown. In other words, in some embodiments, the lateral distance W2 (e.g., the second width W2) between the drain region 162 and the gate structure 110 is greater than the lateral distance W1 (e.g., the first width W1; W2>W1) between the source region 161 and the gate structure 110, as shown. Figure 1H As shown.

[0069] In some embodiments, the first spacer portion GS-1 covering the first sidewall 110S1 of the gate structure 110 has a first bottom surface B1, and the second spacer portion GS-2 covering the second sidewall 110S2 of the gate structure 110 has a second bottom surface B2. The second bottom surface B2 is larger than the first bottom surface B1. Furthermore, the bottom width WB1 can be a critical dimension (i.e., the maximum width in the first direction D1) of the first bottom surface B1 of the first spacer portion GS-1, and the bottom width WB2 can be a critical dimension (i.e., the maximum width in the first direction D1) of the second bottom surface B2 of the second spacer portion GS-2. The second bottom surface B2 of the second spacer portion GS-2 has the maximum width in the first direction D1. Therefore, the bottom width WB2 of the second spacer portion GS-2 is larger than the bottom width WB1 of the first spacer portion GS-1. According to one embodiment, the remaining initial spacing portion 1332 of the second spacing portion GS-2 is formed to increase the bottom width WB2 of the second spacing portion GS-2, thereby extending the lateral length W2 between the drain region 162 and the gate. That is, the bottom width WB2 of the second spacing portion GS-2 can be controlled by adjusting the bottom width of the remaining initial spacing portion 1332. Alternatively, if a larger bottom width is required for the remaining initial spacing portion 1332, then... Figure 1B A thicker third spacer material layer 133 is deposited in the middle. According to one embodiment, the larger bottom width WB2 of the second spacer portion GS-2 (or the lateral length W2 between the drain region 162 and the gate structure 110) does indeed increase the breakdown voltage and expand the safe operating area (SOA) of the semiconductor device, thereby improving the electrical performance of the semiconductor device.

[0070] Furthermore, in some embodiments, after forming the source region 161 and the drain region 162, a first lightly doped region 123 is located between the source region 161 and the gate structure 110, and a second lightly doped region 124 is located between the drain region 162 and the gate structure 110. Additionally, a first spacer portion GS-1 of the gate spacer structure GS is formed above the first lightly doped region 123, and a second spacer portion GS-2GS of the gate spacer structure is formed above the second lightly doped region 124. Specifically, as... Figure 1H As shown, the first lightly doped region 123 is located below the first spacer GS-1 and adjacent to the first sidewall 110S1 of the gate structure 110, and the second lightly doped region 124 is located below the second spacer GS-2 and adjacent to the second sidewall 110S2 of the gate structure 110 (opposite to the first sidewall 110S1).

[0071] Furthermore, according to some embodiments of the present invention, such as Figure 1H As shown, after forming the source region 161 and drain region 162, the first lightly doped region 123 and the second lightly doped region 124 have different widths along the upper surface 100a of the semiconductor substrate 100. In this embodiment, the width (in the first direction D1) of the second lightly doped region 124 between the gate structure 110 and the drain region 162 is greater than the width (in the first direction D1) of the first lightly doped region 123 between the gate structure 110 and the source region 161. Figure 1H As shown, the width of the second lightly doped region 124 between the gate structure 110 and the source region 161 can be referred to as the first width W1 of the first bottom surface B1 of the first spacer portion GS-1. Similarly, the width of the second lightly doped region 124 between the gate structure 110 and the drain region 162 can be referred to as the second width W2 of the second bottom surface B2 of the second spacer portion GS-2. The first width W1 can also be described as the lateral distance from the first sidewall 110S1 of the gate structure 110 (or the inner edge IE1 of the first spacer portion GS-1) to the outer edge OE1 of the first spacer portion GS-1. The second width W2 can also be described as the lateral distance from the second sidewall 110S2 of the gate structure 110 (or the inner edge IE2 of the second spacer portion GS-2) to the outer edge OE2 of the second spacer portion GS-2.

[0072] Furthermore, in some embodiments, the inner edges (inner edges) of the first lightly doped region 123 and the second lightly doped region 124 in the semiconductor substrate 100 are aligned with the inner edges IE1 of the first spacer portion GS-1 and IE2 of the second spacer portion GS-2, respectively. Figure 1FAs shown. Furthermore, since the source region 161 and drain region 162 are formed using the gate structure 110 and the gate spacer structure GS as implantation shields, the outer edges (outer edges) of the first lightly doped region 123 and the second lightly doped region 124 are aligned with the outer edges of the two asymmetrical portions of the gate spacer structure GS after the formation of the source region 161 and drain region 162. For example, the outer edge of the first lightly doped region 123 is aligned with the outer edge OE1 of the first spacer portion GS-1, and the outer edge of the second lightly doped region 124 is aligned with the outer edge OE2 of the second spacer portion GS-2. Therefore, this process method of the present invention can provide automatic alignment of the source region 161 and drain region 162 without additional shielding, which not only simplifies the manufacturing process but also reduces the number of components used, improving production efficiency and saving production costs.

[0073] refer to Figure 1I In some embodiments, an inter-layer dielectric (ILD) layer 170 is formed over the semiconductor substrate 100. Contact plugs are then formed by filling contact openings (not shown) in the inter-layer dielectric layer 170 with a conductive material. Figure 1I As shown, contact plugs 181, 182 and 183 contact the source region 161, the gate structure 110 and the drain region 162, respectively.

[0074] In some embodiments, prior to the deposition of the interlayer dielectric layer 170, silicide regions (not shown) may be further formed on the source region 161, gate structure 110, and drain region 162 to reduce the gate (e.g., polysilicon gate) contact resistance and the source / drain contact resistance. In some embodiments, this can be achieved by... Figure 1H A metal layer (not shown) is deposited over the structure to form silicide regions, and an annealing process is performed. During annealing, the metal layer reacts with the underlying silicon, forming silicide regions on the source region 161, gate structure 110, and drain region 162. The unreacted metal layer is then removed after the annealing process.

[0075] Furthermore, in some embodiments, after forming the silicide region, a contact etch stop layer (not shown) is further formed by blanket deposition to cover it. Figure 1HThe entire structure is as follows. The contact etch stop layer can act as an etch stop layer during the formation of the contact openings, thereby protecting the underlying area from over-etching. Furthermore, the contact etch stop layer provides stress to the semiconductor device, preferably tensile stress for NMOS transistors, and improves carrier mobility. Next, an interlayer dielectric layer 170 is deposited on the contact etch stop layer. Then, contact openings are formed through the interlayer dielectric layer 170, and these contact openings are filled with a conductive material layer. A planarization process, such as chemical mechanical planarization, another suitable planarization method, or a combination thereof, is then performed to planarize the conductive material layer and the interlayer dielectric material, thereby forming contact plugs 181, 182, and 183 and the intermediate layer. Figure 1I As shown, a dielectric layer 170 has a planarized top surface. In some embodiments, contact plugs 181, 182, and 183 contact silicide regions (not shown) on the source region 161, the gate structure 110, and the drain region 162, respectively. Contact plug 181 provides a source voltage to the source region 161, contact plug 182 provides a gate voltage to the gate structure 110, and contact plug 183 provides a drain voltage to the drain region 162.

[0076] According to some embodiments, a semiconductor device includes a gate spacer structure GS with a first spacer portion GS-1 and a second spacer portion GS-2 having different bottom widths, respectively covering (or located on) two opposing sidewalls (e.g., first sidewall 110S1 and second sidewall 110S2) of a gate structure 110. In some embodiments, a source region 161 and a drain region 162 are respectively aligned with the outer edges (e.g., OE1 and OE2) of the asymmetrical first spacer portion GS-1 and the second spacer portion GS-2 of the gate spacer structure GS. Furthermore, the bottom width WB2 of the second spacer portion GS-2 between the drain region 162 and the gate structure 110 (e.g., equal to the lateral distance / second width W2) is greater than the bottom width WB1 of the first spacer portion GS-1 between the source region 161 and the gate structure 110 (e.g., equal to the lateral distance / first width W1). According to some embodiments, the extended distance between the drain region 162 and the gate structure 110 (i.e., W2 > W1) does indeed increase the breakdown voltage and expand the safe operating area (SOA) of the semiconductor device. Furthermore, the extended distance between the drain region 162 and the gate structure 110 of the semiconductor device reduces the undesirable parasitic capacitance between the gate structure 110 and the drain contact plug 183 connected to the drain region 162. Therefore, in some embodiments of the present invention, the source-to-drain current of the semiconductor device is larger, enabling the semiconductor device to operate at higher switching speeds. Consequently, the electrical performance of the semiconductor device according to some embodiments of the present invention can be significantly improved.

[0077] Furthermore, the configuration of the gate spacing structure GS in the aforementioned embodiments, for example... Figure 1G , Figure 1H and Figure 1I The shapes and arrangements of the spacer material layers in the first spacer portion GS-1 and the second spacer portion GS-2 are only for illustrating some applicable types. It should be noted that the present invention is not limited to the structural configuration of the gate spacer structure GS in the foregoing embodiments. According to the present invention, the first spacer portion GS-1 and the second spacer portion GS-2 of the gate spacer structure GS can have spacer material layers of different shapes and arrangements to achieve a larger bottom width for the spacer portion (i.e., GS-2) near the drain region 162 than for the spacer portion (i.e., GS-1) near the source region 161. In this embodiment, the first spacer portion GS-1 includes a patterned first spacer portion 1311, a patterned second spacer portion 1321, and a patterned fourth spacer portion 1341. The second spacer portion GS-2 includes a patterned first spacer portion 1312, a patterned second spacer portion 1322, a second symmetrical portion 1332, and a patterned fourth spacer portion 1342. Therefore, the number of material layers in the second spacer portion GS-2 can be greater than the number of material layers in the first spacer portion GS-1. For example, in this embodiment, the second spacer portion GS-2 has four layers, and the first spacer portion GS-1 has three layers. Of course, this is just an example, and the number of material layers can be freely set according to requirements. However, generally speaking, the number of material layers in the second spacer portion GS-2 can be greater than the number of material layers in the first spacer portion GS-1. Furthermore, in other embodiments, the number of material layers in the second spacer portion GS-2 can be equal to the number of material layers in the first spacer portion GS-1, but the thickness of at least one material layer in the first spacer portion GS-1 can be smaller than the thickness of the corresponding material layer in the second spacer portion GS-2. For example, in... Figure 1D In the manufacturing process, the first symmetrical portion 1331 is thinned rather than completely removed. In one embodiment, a process that completely removes the first symmetrical portion 1331 is easier to implement and more convenient to manufacture.

[0078] Figure 2 This is a cross-sectional view of an intermediate stage of a semiconductor device according to some embodiments of the present invention. Apart from the configuration of the gate spacing structure GS, Figure 2 The intermediate structure and Figure 1H The intermediate structure is the same.

[0079] For simplicity, Figure 2 and Figure 1H Features with the same or similar structure are numbered in a similar manner. Figure 2 and Figure 1HThe configuration of the same or similar features has been described in the foregoing embodiments and will not be repeated here. Furthermore, the formation... Figure 2 The semiconductor substrate 100 includes a well region 104 and an isolation structure 108, a gate structure 110, a gate spacer structure GS with two asymmetrical portions (e.g., a first spacer portion GS-1 and a second spacer portion GS-2) on opposite sidewalls of the gate structure 110, a first lightly doped region 123, a second lightly doped region 124, a source region 161, and a drain region 162, similar to those described in the foregoing embodiments. For the sake of brevity, the materials of the same or similar components / layers and the processes for forming these components / layers will not be described again here.

[0080] According to the above Figure 1G , Figure 1H and Figure 1I The intermediate structure, formed to increase the bottom width WB2 of the second spacer portion GS-2, completely encloses the remaining initial spacer portion 1332 by the patterned fourth spacer portion 1342 and the patterned second spacer portion 1322. The fourth spacer portion 1342 and the patterned second spacer portion 1322. However, the present invention is not limited to the structural configuration of the second spacer portion GS-2 in the foregoing embodiment. Reference Figure 3 In some embodiments, the remaining initial spacer portion 1332 may be located between the fourth spacer material layer 134 and the second spacer material layer 132, but is not completely enclosed by the fourth spacer material layer 134 and the second spacer material layer 132.

[0081] refer to Figure 1F and Figure 1G In the intermediate stage of forming a semiconductor device, the fourth spacer material layer 134 and the second spacer material layer 132 may include silicon nitride, and the remaining initial spacer portion 1332 may include silicon oxide. When anisotropic etching is performed to pattern the fourth spacer material layer 134 and the second spacer material layer 132 (e.g., as shown in the image), Figure 1G As shown, the anisotropic etching of the fourth spacer layer 134 and the second spacer layer 132 provides high selectivity for the remaining initial spacer portion 1332, and the remaining initial spacer portion 1332 is substantially not etched during the patterning step. Therefore, after performing the anisotropic etching step to form the gate spacer structure GS, the remaining initial spacer portion 1332 can protrude slightly between the patterned second spacer portion 1322 and the patterned fourth spacer portion 1342 of the second spacer portion GS-2.

[0082] In this example, such as Figure 2As shown, the top surface 1332a of the remaining initial spacer portion 1332 is exposed through the patterned second spacer portion 1322 and the patterned fourth spacer portion 1342. In some embodiments, the top surface 1332a of the remaining initial spacer portion 1332 is higher than the top surface 1322a of the patterned second spacer portion 1322 and the uppermost surface 1342a of the patterned fourth spacer portion 1342. Furthermore, the top surface 1322a of the patterned second spacer portion 1322 and the surface 1342a of the uppermost patterned fourth spacer portion 1342 may be lower than the top surface 1312a of the patterned first spacer portion 1312, wherein the patterned first spacer portion 1312 covers the second sidewall 110S2 of the gate structure 110.

[0083] Regardless of whether the patterned second spacer portion 1322 is a patterned fourth spacer portion 1342 or a patterned second spacer portion 1322 (e.g.) Figure 1G (As shown) The encapsulation is still achieved through a patterned fourth spacer portion 1342 and a patterned second spacer portion 1322 (as shown) Figure 2 As shown, due to the formation of the remaining initial spacing portion 1332, the bottom width WB2 of the second spacing portion GS-2 can be extended to increase the distance between the drain region 162 and the gate structure 110. Therefore, undesirable parasitic capacitance between the gate structure 110 and the drain contact plug 183 connected to the drain region 162 can be reduced. Furthermore, the breakdown voltage and safe operating area (SOA) of the semiconductor device can be significantly increased. The embodiments of the present invention provide different process methods, and the process steps of the embodiments of the present invention are fewer and simpler, resulting in higher manufacturing efficiency.

[0084] Figure 3 This is a cross-sectional view of an intermediate stage of a semiconductor device according to some embodiments of the present invention. Apart from the configuration of the gate spacing structure GS, Figure 3 The intermediate structure and Figure 1H The intermediate structure is the same.

[0085] Figure 3 and Figure 1H Features with the same or similar structure are numbered in a similar manner for simplicity and clarity. Figure 3 and Figure 1H The configuration of the same or similar features has been described in the foregoing embodiments and will not be repeated here. Furthermore, the formation... Figure 3The semiconductor substrate 100 includes a well region 104 and an isolation structure 108, a gate structure 110, a gate spacer structure GS with two asymmetrical portions (e.g., a first spacer portion GS-1 and a second spacer portion GS-2) on opposite sidewalls of the gate structure 110, a first lightly doped region 123, a second lightly doped region 124, a source region 161, and a drain region 162, similar to those described in the foregoing embodiments. For the sake of brevity, the materials of identical or similar components and layers, as well as the processes for forming these components and layers, will not be described further here.

[0086] Reference Figure 1F and Figure 1G In the intermediate stage of forming a semiconductor device, the fourth spacer layer 134 and the second spacer layer 132 may include silicon nitride, and the remaining initial spacer portion 1332 may include silicon oxide.

[0087] refer to Figure 1E , Figure 1F and Figure 1G In the intermediate stage of forming a semiconductor device, the remaining initial spacer portion 1332 can influence the deposition of the fourth spacer material layer 134, causing a smaller amount of the fourth spacer material layer 134 to be deposited on the remaining initial spacer portion 1332. (Refer to...) Figure 3 When anisotropic etching is performed to pattern the fourth spacer material layer 134 and the second spacer material layer 132 (e.g., as...) Figure 1G As shown, the patterned fourth spacer portion 1341 of the first spacer portion GS-1 can be higher than the patterned fourth spacer portion 1342 of the second spacer portion GS-2. Specifically, the uppermost surface 1342a of the patterned fourth spacer portion 1342 is lower than the uppermost surface 1341a of the patterned fourth spacer portion 1341. The top surface 1322a of the patterned second spacer portion 1322 and the uppermost surface 1342a of the patterned fourth spacer portion 1342 can be substantially aligned with the top surface 1332a of the remaining initial spacer portion 1332. Furthermore, the top surface 1322a of the patterned second spacer portion 1322 and the uppermost surface 1342a of the patterned fourth spacer portion 1342 can be lower than the top surface 1312a of the patterned first spacer portion 1312, wherein the patterned first spacer portion 1312 covers the second sidewall 110S2 of the gate structure 110.

[0088] Regardless of whether the patterned fourth spacer portion 1342 is the same as the patterned fourth spacer portion 1341 (e.g. Figure 1G (As shown) Coplanar or lower than the patterned fourth spacer portion 1341 (e.g.) Figure 3As shown, due to the formation of the remaining initial spacing portion 1332, the bottom width WB2 of the second spacing portion GS-2 can be extended to increase the distance between the drain region 162 and the gate structure 110. Therefore, undesirable parasitic capacitance between the gate structure 110 and the drain contact plug 183 connected to the drain region 162 can be reduced. Furthermore, the breakdown voltage and safe operating area (SOA) of the semiconductor device can be significantly increased. The embodiments of the present invention provide different process methods, and the process steps of the embodiments of the present invention are fewer and simpler, resulting in higher manufacturing efficiency.

[0089] According to the above embodiments, the semiconductor device and its formation method achieve several advantages. In some embodiments, the gate spacer structure GS includes a first spacer portion GS-1 and a second spacer portion GS-2 respectively covering opposite sidewalls (e.g., first spacer 110S1 and second spacer 110S2) of the gate structure 110 in the semiconductor device. The first spacer portion GS-1 and the second spacer portion GS-2 are adjacent to the source region 161 and the drain region 162, respectively. The bottom width WB2 of the second spacer portion GS-2 is greater than the bottom width WB1 of the first spacer portion GS-1. According to one embodiment, the larger bottom width WB2 of the second spacer portion GS-2 extends the lateral distance between the gate structure 110 and the drain region 162, thereby increasing the breakdown voltage and safe operating area (SOA) region of the semiconductor device. Furthermore, the extended distance between the drain region 162 and the gate structure 110 of the semiconductor device reduces undesirable parasitic capacitance between the gate structure 110 and the drain contact plug 183 connected to the drain region 162. Therefore, allowing more current to flow from the source to the drain terminal of the semiconductor device according to some embodiments of the present invention enables the semiconductor device to operate at higher switching speeds. Furthermore, according to some embodiments, the method for forming the semiconductor device is simple and compatible with current manufacturing processes. The structural configuration of features in the semiconductor device formed according to the method of some embodiments also offers several advantages. For example, the source region 161 and drain region 162 formed in the semiconductor substrate are self-aligned with the outer edges (e.g., OE1 and OE2) of the asymmetric portion of the gate spacing structure GS, thereby providing a large contact area for the contact plug to be disposed on the source region 161 and drain region 162 in subsequent processes. Based on the foregoing description, the electrical performance of the semiconductor device according to some embodiments of the present invention can be significantly improved.

[0090] It should be noted that the structural and manufacturing details of the embodiments are for illustrative purposes only, and the details described in the embodiments are not intended to limit the present invention. It should be noted that not all embodiments of the present invention are shown. Modifications and variations can be made to meet the needs of practical applications without departing from the spirit of the present invention. Therefore, the present invention may also have other embodiments not specifically described. Furthermore, the drawings are simplified for clear illustration of the embodiments. The dimensions and scales in the drawings may not be proportional to the actual product. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

[0091] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

Claims

1. A semiconductor device, characterized by comprising: include: A semiconductor substrate having a well region; A gate structure is formed above the well region of the semiconductor substrate; A gate spacing structure includes a first spacing portion and a second spacing portion located on two opposite sidewalls of the gate structure, respectively. as well as A source region and a drain region are formed in the semiconductor substrate and separated from the gate structure, wherein the source region is adjacent to the first spacer portion of the gate spacer structure, and the drain region is adjacent to the second spacer portion of the spacer structure. The bottom width of the second interval is greater than the bottom width of the first interval. The second spacing portion of the gate spacing structure includes a patterned first spacing portion, a patterned second spacing portion, a remaining initial spacing portion, and a patterned fourth spacing portion, wherein the remaining initial spacing portion is located between the patterned second spacing portion and the patterned fourth spacing portion; The top surface of the remaining initial spacing portion is higher than the top surface of the patterned second spacing portion and the top surface of the patterned fourth spacing portion; the top surface of the patterned second spacing portion and the top surface of the patterned fourth spacing portion are lower than the top surface of the patterned first spacing portion.

2. The semiconductor device according to claim 1, wherein The bottom surface of the second interval is larger than the bottom surface of the first interval.

3. The semiconductor device according to claim 1, wherein The bottom width of the first interval portion is defined as the first lateral distance between the source region and the gate structure, and the bottom width of the second interval portion is defined as the second lateral distance between the drain region and the gate structure, wherein the second lateral distance is greater than the first lateral distance.

4. The semiconductor device according to claim 1, wherein The gate structure has a first sidewall and a second sidewall opposite to the first sidewall, and the first spacer portion and the second spacer portion are respectively formed on the first spacer and the second spacer of the gate structure.

5. The semiconductor device according to claim 4, wherein The first spacer portion is disposed between the source region and the first sidewall of the gate structure, and the second spacer portion is disposed between the drain region and the second sidewall of the gate structure.

6. The semiconductor device according to claim 1, wherein The gate spacer structure is composed of multiple spacer material layers, and the first spacer portion and the second spacer portion of the gate spacer structure on opposite sidewalls of the gate structure each have a different number of spacer material layers.

7. The semiconductor device as claimed in claim 1, characterized in that, The number of spacer material layers forming the second spacer portion is greater than the number of spacer material layers forming the first spacer portion.

8. The semiconductor device as claimed in claim 1, characterized in that, The upper surface of the remaining initial interval portion is exposed through the upper surface of the patterned second interval portion and the upper surface of the patterned fourth interval portion.

9. The semiconductor device as claimed in claim 1, characterized in that, The remaining initial spacer portion includes an initial oxide spacer portion, and the patterned second spacer portion and the patterned fourth spacer portion include patterned nitride spacer portions.

10. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A lightly doped region is formed in the semiconductor substrate and below the first and second spacer portions of the gate spacer structure. The lightly doped region has different widths extending along the upper surface of the semiconductor substrate.

11. The semiconductor device as claimed in claim 10, characterized in that, The outer edges of the lightly doped regions that are in contact with the source region and the drain region are aligned with the outer edges of the first spacer portion and the second spacer portion of the gate spacer structure, respectively.

12. A method for forming a semiconductor device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having a well region and an isolation structure adjacent to the well region; A gate structure is formed above the well region of the semiconductor substrate; A gate spacer structure is formed, including a first spacer portion and a second spacer portion respectively covering a first sidewall and a second sidewall of the gate structure; as well as A source region and a drain region are formed in the semiconductor substrate, wherein the source region is adjacent to the first spacer portion, and the drain region is adjacent to the second spacer portion. The bottom width of the second interval is greater than the bottom width of the first interval. The second interval portion includes forming a patterned first interval portion, a patterned second interval portion, a remaining initial interval portion, and a patterned fourth interval portion, wherein the remaining initial interval portion is located between the patterned second interval portion and the patterned fourth interval portion. The top surface of the remaining initial interval portion is higher than the top surface of the patterned second interval portion and the top surface of the patterned fourth interval portion; the top surfaces of the patterned second interval portion and the top surface of the patterned fourth interval portion are lower than the top surface of the patterned first interval portion.

13. The method as described in claim 12, characterized in that, The gate spacer structure comprises: An initial gate spacer layer with symmetrical portions is formed, which covers the first sidewall and the second sidewall of the gate structure, respectively. Remove the symmetrical portion located on the first sidewall of the gate structure, while the other symmetrical portion remains on the second sidewall of the gate structure, which is the remaining initial spacing portion; as well as A spacer material is formed over the semiconductor substrate, the gate structure, and the remaining initial spacer portion.

14. The method of claim 13, wherein, Removing the symmetrical part includes: A patterned shielding layer is provided above the semiconductor substrate, wherein the patterned shielding layer exposes the symmetrical portion located above the first sidewall of the gate structure and covers the other symmetrical portion located above the second sidewall of the gate structure; The symmetrical portion above the first sidewall of the gate structure is removed by selective etching; and Remove the patterned shielding layer. The spacer material is formed after the patterned shielding layer is removed.

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