Peak power management for multi-die operation

Abstract

A peak power management (PPM) method for two NAND memory dies is provided. Each NAND memory die includes a PPM circuit having a PPM contact pad held at a potential common to the two NAND memory dies. The method includes the steps of detecting the potential during a first peak power check (PPC) routine for a first NAND memory die, driving the potential to a second voltage level if the detected potential is at a first voltage level higher than the second voltage level, generating a suspend signal in the potential to suspend a second PPC routine for a second NAND memory die if a suspend signal is not detected, and generating a resume signal in the potential to resume the second PPC routine for the second NAND memory die after the first NAND memory die completes a first peak power operation.

Description

[0001] This application is a divisional application of the patent filed on February 7, 2021, with application number PCT / CN2021 / 075725, entitled "Peak Power Management for Multi-Die Operation". Technical Field

[0002] This disclosure relates generally to the field of semiconductor technology, and more specifically to circuit designs and methods for peak power management in memory systems. Background Technology

[0003] NAND flash memory systems are widely used as primary non-volatile storage devices in many servers and mobile devices due to their high storage density and relatively low access latency. However, the performance of high-density storage systems (e.g., 3D NAND flash memory systems) is often limited by the maximum amount of power (or peak current) they can utilize. Currently, high-power operations (e.g., peak power operations) performed by various dies of a NAND flash memory system can be staggered by a system controller. Only a limited number of peak power operations can be performed simultaneously. This approach can also lead to increased system load due to unnecessary over-management. It is desirable to establish communication between different dies to coordinate peak power operations. In this disclosure, cooperation between two or more dies can be arranged via peak power management (PPM) circuitry on each die, wherein the PPM contact pads of the PPM circuitry can be kept at the same potential. Peak power operations can be coordinated between two or more dies by adjusting the potential of the PPM contact pads and by implementing unique delay periods for each die. Summary of the Invention

[0004] One aspect of this disclosure provides a method for peak power management (PPM) for a plurality of NAND memory dies. The plurality of NAND memory dies have a first NAND memory die and a second NAND memory die, and each of the first NAND memory die and the second NAND memory die includes a PPM circuit having PPM contact pads held at a common potential between the first NAND memory die and the second NAND memory die. The method includes the following steps: detecting the potential of the PPM contact pad at a first moment during a first peak power check (PPC) routine for a first NAND flash memory die; if the detected potential is at a first voltage level at the first moment, driving the potential of the PPM contact pad to a second voltage level, wherein the second voltage level is lower than the first voltage level; causing the first NAND flash memory die to wait for a first delay period; determining at a second moment during the first PPC routine for the first NAND flash memory die whether there is a pause signal in the potential of the PPM contact pad, wherein the second moment is later than the first moment; if no pause signal is detected at the second moment, generating a pause signal in the potential of the PPM contact pad to pause a second PPC routine for a second NAND flash memory die; causing the first NAND flash memory die to perform a first peak power operation; and generating a recovery signal in the potential of the PPM contact pad after the first NAND flash memory die completes the first peak power operation to resume the second PPC routine for the second NAND flash memory die.

[0005] In some embodiments, the method further includes detecting the potential of the PPM contact pads at a third moment during a second PPC routine for a second NAND memory die.

[0006] In some embodiments, the method further includes: if the detected potential is at a second voltage level at a third time, then suspending the second PPC routine on the second NAND memory die.

[0007] In some embodiments, the method further includes: resuming a second PPC routine for a second NAND memory die in response to a recovery signal generated after the first NAND memory die has completed a first peak power operation.

[0008] In some embodiments, restoring the second PPC routine for the second NAND memory die includes: driving the potential of the PPM contact pads to a second voltage level; and causing the second NAND memory die to wait for a third delay period, wherein the third delay period of the second NAND memory die is different from the first delay period of the first NAND memory die.

[0009] In some embodiments, resuming the second PPC routine for the second NAND memory die includes: determining at a fourth time during the second PPC routine for the second NAND memory die whether there is a pause signal in the potential of the PPM contact pad, wherein the fourth time is later than the third time; and if no pause signal is detected at the fourth time, generating a pause signal in the potential of the PPM contact pad to pause the third PPC routine for the third NAND memory die among the plurality of NAND memory dies.

[0010] In some embodiments, restoring the second PPC routine for the second NAND memory die further includes: causing the second NAND memory die to perform a second peak power operation; and generating a recovery signal in the potential of the PPM contact pad after the second NAND memory die has completed the second peak power operation, so as to restore the third PPC routine for the third NAND memory die.

[0011] In some embodiments, the method further includes: if the detected potential is at a first voltage level at a third time, then causing the second NAND memory die to wait for a third delay period, wherein the third delay period of the second NAND memory die is different from the first delay period of the first NAND memory die.

[0012] In some embodiments, the method further includes: determining at a fourth time point during a second PPC routine for a second NAND memory die whether there is a pause signal in the potential of the PPM contact pad, wherein the fourth time point is later than the third time point.

[0013] In some embodiments, the method further includes pausing the second PPC routine for the second NAND memory die if a pause signal is detected at the fourth time.

[0014] In some embodiments, the method further includes: resuming a second PPC routine for a second NAND memory die in response to a recovery signal generated after the first NAND memory die has completed a first peak power operation.

[0015] In some embodiments, the method further includes: waiting for a second delay period in a first PPC routine for a first NAND memory die before performing a first peak power operation.

[0016] In some embodiments, generating a recovery signal includes driving the potential of the PPM contact pad to a first voltage level.

[0017] In some embodiments, generating a pause signal includes generating a positive pulse in the potential of the PPM contact pad, the positive pulse having a pulse width in the range of about 0.1 μS and about 10 μS.

[0018] In some embodiments, determining whether there is a pause signal includes measuring the potential of the PPM contact pad at a first probe and a second probe, wherein the first probe and the second probe are separated by a measurement period longer than the pulse width.

[0019] Another aspect of this disclosure provides a peak power management (PPM) circuit for managing peak power operation among multiple NAND flash dies in a memory chip. The PPM circuit has PPM contact pads maintained at a common potential between a PPM circuit disposed on a first NAND flash die and a PPM circuit disposed on a second NAND flash die. The PPM circuit is configured to: detect the potential of the PPM contact pad at a first moment during a first peak power check (PPC) routine for a first NAND memory die; if the detected potential is at a first voltage level at the first moment, drive the potential of the PPM contact pad to a second voltage level, wherein the second voltage level is lower than the first voltage level; cause the first NAND memory die to wait for a first delay period; determine at a second moment during the first PPC routine for the first NAND memory die whether there is a pause signal in the potential of the PPM contact pad, wherein the second moment is later than the first moment; if no pause signal is detected at the second moment, generate a pause signal in the potential of the PPM contact pad to pause a second PPC routine for the second NAND memory die; cause the first NAND memory die to perform a first peak power operation; and after the first NAND memory die completes the first peak power operation, generate a recovery signal in the potential of the PPM contact pad to resume the second PPC routine for the second NAND memory die.

[0020] In some embodiments, the PPM circuit is further configured to detect the potential of the PPM contact pads at a third moment during a second PPC routine for a second NAND memory die.

[0021] In some embodiments, the PPM circuit is further configured to: if the detected potential is at a second voltage level at a third moment, then suspend the second PPC routine of the second NAND memory die.

[0022] In some embodiments, the PPM circuit is further configured to: recover a second PPC routine for a second NAND memory die in response to a recovery signal generated after the first NAND memory die has completed a first peak power operation.

[0023] In some embodiments, the PPM circuit is further configured to: drive the potential of the PPM contact pad to a second voltage level; cause the second NAND memory die to wait for a third delay period, wherein the third delay period of the second NAND memory die is different from the first delay period of the first NAND memory die; determine at a fourth time during a second PPC routine for the second NAND memory die whether there is a pause signal in the potential of the PPM contact pad, wherein the fourth time is later than the third time; if no pause signal is detected at the fourth time, generate a pause signal in the potential of the PPM contact pad to pause a third PPC routine for a third NAND memory die among a plurality of NAND memory dies; cause the second NAND memory die to perform a second peak power operation; and generate a recovery signal in the potential of the PPM contact pad after the second NAND memory die has completed the second peak power operation to resume the third PPC routine for the third NAND memory die.

[0024] In some embodiments, the PPM circuit is further configured to pause the second PPC routine for the second NAND memory die if a pause signal is detected at the fourth time.

[0025] In some embodiments, the recovery signal includes a first voltage level in the potential of the PPM contact pad.

[0026] In some embodiments, the pause signal comprises a positive pulse in the potential of the PPM contact pad, the positive pulse having a pulse width in the range of about 0.1 μS to about 10 μS.

[0027] In some embodiments, the PPM circuit further includes: a first pull-up driver electrically connected to a first power supply and a first end of the PPM resistor; a second pull-up driver electrically connected to a second power supply and a second end of the PPM resistor; and a pull-down driver electrically connected to the second end of the PPM resistor, wherein the PPM contact pads are connected to the second end of the PPM resistor.

[0028] In some embodiments, the PPM circuit further includes a comparator having a first input terminal electrically connected to a reference voltage and a second input terminal electrically connected to a PPM contact pad.

[0029] In some embodiments, the potential of the PPM contact pad is higher than the reference voltage when the pull-down driver is off, and lower than the reference voltage when the pull-down driver is on.

[0030] In some embodiments, the first pull-up driver and the second pull-up driver include p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0031] In some embodiments, the pull-down driver includes an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET).

[0032] In some embodiments, the PPM contact pads of the PPM circuit on the first NAND memory die are electrically connected to the PPM contact pads of the PPM circuit on the second NAND memory die via a die-to-die connection. In some embodiments, the die-to-die connection includes a metal interconnect formed by flip-chip bonding, die-to-die bonding, or wire bonding.

[0033] Another aspect of this disclosure provides a peak power management (PPM) system for managing peak power operation across multiple NAND memory dies. The PPM system includes PPM circuitry on each of the multiple NAND memory dies as described above.

[0034] Other aspects of this disclosure will be understood by those skilled in the art based on the specification, claims and drawings. Attached Figure Description

[0035] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0036] Figure 1A A storage system having one or more memory chips is shown according to some embodiments of the present disclosure.

[0037] Figure 1B A top view of a memory die according to some embodiments of the present disclosure is shown.

[0038] Figure 2A A peak power management system in a memory chip according to some embodiments of the present disclosure is illustrated.

[0039] Figure 2B Another peak power management system in a memory chip according to some embodiments of the present disclosure is shown.

[0040] Figure 3 Peak power management circuitry according to some embodiments of the present disclosure is shown.

[0041] Figure 4 Peak power checking routines according to some embodiments of this disclosure are shown.

[0042] Figure 5-7 Two memory dies according to some embodiments of the present disclosure are shown. Figure 4 The implementation of the peak power check routine shown is illustrated.

[0043] Figure 8 A measurement scheme for a pause signal according to some embodiments of the present disclosure is shown.

[0044] Figure 9-10 Three memory dies according to some embodiments of this disclosure are shown. Figure 4 The implementation of the peak power check routine shown is illustrated.

[0045] The features and advantages of the invention will become more apparent when considered in conjunction with the accompanying drawings, in which similar reference numerals denote corresponding elements throughout. Similar reference numerals in the drawings generally indicate equivalent, functionally similar, and / or structurally similar elements.

[0046] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0047] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other constructions and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0048] Note that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0049] Generally, terms can be understood at least in part based on their use in context. For example, at least in part based on context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or a combination of features, structures, or characteristics in a plural sense. Similarly, at least in part based on context, terms such as "a" or "described" can also be understood to express either a singular or a plural usage. Additionally, at least in part based on context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily clearly described.

[0050] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter for a component or process step, set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may be attributable to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a given quantity value that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate a given quantity value that varies, for example, within 10%–30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0051] Figure 1A A storage system 10 according to some embodiments of the present disclosure is illustrated. The storage system 10 (also referred to as a NAND storage system or solid-state drive) may include a host controller 20 and one or more storage chips 25-1, 25-2, 25-3…25-n. Each semiconductor storage chip 25 (hereinafter simply referred to as a “storage chip”) may be a NAND chip (i.e., “flash memory”, “NAND flash”, or “NAND”). The solid-state drive (SSD) 10 may communicate with a host computer 15 via the host controller 20, wherein the host controller 20 may be connected to one or more storage chips 25-1, 25-2, 25-3…25-n via one or more storage channels 30-1, 30-2, 30-3…30-n. In some embodiments, each storage chip 25 may be managed by the host controller 20 via a storage channel 30.

[0052] The host computer 15 sends data to be stored in the NAND storage system or SSD 10, or retrieves data by reading from the SSD 10. The host controller 20 can process I / O requests received from the host computer 15, ensure data integrity and effective storage, and manage the storage chips 25. The storage channel 30 can provide data and control communication between the host controller 20 and each storage chip 25 via a data bus. The host controller 20 can select one of the storage chips 25 based on a chip enable signal.

[0053] Figure 1B A top view of a NAND flash memory 100 according to some embodiments of the present disclosure is shown. The NAND flash memory 100 may be a memory die (or a module) or any portion thereof. In some embodiments, Figure 1AEach memory chip 25 may include one or more memory dies, such as one or more NAND flash memory 100s. In some embodiments, each NAND flash memory 100 may include one or more memory surfaces 101, and each memory surface may include multiple memory blocks 103. Equal and concurrent operations can occur at each memory surface 101. A memory block 103, which may have a size of several megabytes (MB), is the minimum size for performing an erase operation. Figure 1B As shown, the exemplary NAND flash memory 100 includes four storage surfaces 101, and each storage surface 101 includes six storage blocks 103. Each storage block 103 may include multiple storage cells, wherein each storage cell can be addressed via interconnects such as bit lines and word lines. The bit lines and word lines may be vertically arranged (e.g., by rows and columns, respectively), thereby forming an array of metal lines. Figure 1B In this disclosure, the directions of the word line and bit line are marked as "BL" and "WL". The memory block 103 is also referred to as a "memory array" or "array". The memory array is the core area on the memory die that performs memory functions.

[0054] The NAND flash memory 100 also includes a peripheral region 105, which is the area surrounding the storage surface 101. The peripheral region 105 contains a variety of digital, analog, and / or mixed-signal circuitry to support the functionality of the storage array, such as page buffers 50, row decoders 40, column decoders 60, peripheral circuitry 70, and sense amplifiers 80. The peripheral circuitry 70 includes active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., which will be readily apparent to those skilled in the art.

[0055] It should be pointed out that, Figure 1A and Figure 1B The layout of the electronic components in the SSD 10 and NAND flash memory 100 is shown as an example only. The SSD 10 and NAND flash memory 100 may have other layouts and may include additional components. For example, the NAND flash memory 100 may also have a high-voltage charge pump, I / O circuitry, etc. The SSD 10 may also include firmware, a data scrambler, etc.

[0056] Figure 2A A peak power management system 200A for a memory chip 25 according to some embodiments of the present disclosure is shown. The peak power management (PPM) system 200A can be implemented in... Figure 1A In each memory chip 25 of the NAND memory system 10, each memory chip 25 may include multiple memory dies 100-1, 100-2...100-(n-1), 100-n, and each memory die may be connected to the aforementioned reference. Figure 1BThe NAND flash memory 100 discussed is similar. In some embodiments, each NAND flash memory 100 may include peak power management (PPM) circuitry 202 (e.g., 202-1, 202-2…202-(n-1), 202-n), wherein each PPM circuitry 202 may include PPM contact pads 204 (also referred to as PPM pins). The PPM circuitry 202-1, 202-2…202-(n-1), 202-n on different NAND flash memories 100-1, 100-2…100-(n-1), 100-n of memory chip 25 may communicate with each other via PPM contact pads 204 (e.g., 204-1, 204-2…204-(n-1), 204-n). In some embodiments, the PPM contact pads 204 between two NAND flash memories 100 may be electrically interconnected via multiple die-to-die connections 205. For example, PPM contact pad 204-1 on NAND flash memory 100-1 can be electrically connected to PPM contact pad 204-2 on NAND flash memory 100-2 via die-to-die connection 205. PPM contact pad 204-(n-1) on NAND flash memory 100-(n-1) can also be electrically connected to PPM contact pad 204-n on NAND flash memory 100-n via die-to-die connection 205. In some embodiments, the die-to-die connection 205 can be a metal interconnect formed by wire bonding. In some embodiments, the metal interconnect can be a metal wire formed by flip-chip bonding or die-to-die bonding, or any suitable metal or conductive material. In some embodiments, the metal interconnect can be formed by through-silicon VIA (e.g., through-array structure).

[0057] By using the die-to-die connection 205 described above, communication between two different memory dies (e.g., between NAND flash memory 100-1 and 100-2) can be established as PPM group 203 in PPM system 200A. Accordingly, NAND memory system 10 can send operation commands to memory chip 25, wherein NAND memory system 10 can control the power consumption of the system via PPM circuit 202 at any time by selecting one of the two memory dies in PPM group 203.

[0058] Figure 2B A PPM system 200B according to some embodiments of the present disclosure is shown. Similar to the PPM system 200A, the PPM system 200B can also be implemented in… Figure 1AIn each memory chip 25 of the NAND flash memory system 10, each memory die (e.g., NAND flash memory 100) includes a PPM circuit 202 (e.g., 202-1, 202-2, 202-3...202-n). Each PPM circuit 202 includes PPM contact pads 204 (e.g., 204-1, 204-2, 204-3...204-n), and the PPM circuits 202 on different NAND flash memories 100 can communicate with each other through the PPM contact pads 204. In some embodiments, the PPM contact pads 204 between NAND flash memories 100 can be electrically interconnected through multiple die-to-die connections 205. For example, PPM contact pad 204-1 on NAND flash memory 100-1 can be electrically connected to PPM contact pad 204-2 on NAND flash memory 100-2 via die-to-die connection 205, while PPM contact pad 204-2 on NAND flash memory 100-2 can be electrically connected to PPM contact pad 204-3 on NAND flash memory 100-3 via another die-to-die connection 205. Accordingly, the PPM contact pads 204 for the entire PPM system 200B can be electrically connected via die-to-die connection 205. In other words, PPM system 200B can be considered as a PPM group 203. This allows communication between different memory dies on the same memory chip to be established through PPM system 200B. NAND memory system 10 can send operation commands to memory chip 25, wherein NAND memory system 10 can control the power consumption of the system through PPM circuit 202 at any time by selecting one of the memory dies.

[0059] Figure 3 An exemplary PPM circuit 202 on a NAND flash memory 100 according to some embodiments of the present disclosure is shown. The PPM circuit 202 may include a first pull-up driver 314, wherein one terminal of the first pull-up driver 314 is connected to a voltage V. dd_1 The first power supply 312. In some embodiments, the first pull-up driver 314 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). In some embodiments, the first pull-up driver 314 may be a p-channel MOSFET (i.e., pFET), wherein the source terminal of the first pull-up driver 314 may be connected to the first power supply 312, and the drain terminal of the first pull-up driver 314 may be connected to a resistor R. ppm The first end of the PPM resistor 318.

[0060] In some embodiments, the PPM circuit 202 may further include a second pull-up driver 315, wherein one terminal of the second pull-up driver 315 is connected to a voltage V.dd_2 The second power supply 313. In some embodiments, the second pull-up driver 315 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). In some embodiments, the second pull-up driver 315 may be a p-channel MOSFET (i.e., pFET), wherein the source terminal of the second pull-up driver 315 may be connected to the second power supply 313, and the drain terminal of the second pull-up driver 315 may also be connected to the second end of the PPM resistor 318. In this configuration, the first pull-up driver 314 and the second pull-up driver 315 are connected in parallel.

[0061] In some embodiments, the first pull-up driver 314 may have a first current I. up_1 Furthermore, the second pull-up driver 315 may have a second current I. up_2 The current flowing through the first pull-up driver 314 and the second pull-up driver 315 can be controlled by applying a bias to the gate terminal 316 of the first pull-up driver and / or the gate terminal 317 of the second pull-up driver 315. In one example, the first pull-up driver 314 may remain slightly on or weakly on (e.g., with low transconductance), and is thus referred to as a "weak pull-up driver". In some embodiments, the second pull-up driver 315 may be fully on (e.g., with high transconductance), and is thus referred to as a "strong pull-up driver". First current I up_1 It can be compared to the second current I up_2 Much smaller. In some embodiments, the first current I... up_1 It can be in the range of approximately 100 nA to approximately 1 μA. In some embodiments, the second current I... up_2 It can be in the range of approximately 10 μA to approximately 1 mA. In some embodiments, the first voltage V... dd_1 Second voltage V dd_2 They can have the same amplitude.

[0062] In some embodiments, the PPM circuit 202 further includes a pull-down driver 336. In some embodiments, the pull-down driver 336 may be a MOSFET. In some embodiments, the pull-down driver 336 may be an n-channel MOSFET (i.e., an nFET). The source terminal of the pull-down driver 336 may be grounded, and the drain terminal of the pull-down driver 336 may be connected to the second end of the PPM resistor 318 at node 322.

[0063] In some embodiments, the second end of the PPM resistor 318, the drain terminal of the second pull-up driver 315, and the drain terminal of the pull-down driver 336 are also electrically connected to the PPM contact pad 204 at node 322. For a PPM system 200A having two PPM circuits 202 in each PPM group 203 (e.g., ... Figure 2A As shown in the diagram, the PPM contact pads 204 in the same PPM group 203 can be maintained at node 322 at a potential V common to both PPM contact pads 204 and both PPM circuits 202. ppm Because the two PPM contact pads 204 are electrically connected via die-to-die connection 205 (see...) Figure 2A For a PPM system 200B having two or more PPM circuits 202 in each PPM group 203 (e.g. Figure 2B As shown, the PPM contact pads 204 in the same PPM group 203 can be maintained at node 322 at a potential V common to all PPM contact pads 204 and PPM circuits 202 in the PPM system 200B. ppm Because all PPM contact pads 204 are electrically connected via die-to-die connections 205 (see...) Figure 2B ).

[0064] In some embodiments, the PPM circuit 202 may further include a comparator 328, the comparator 328 having a reference voltage V ref The first input terminal 324 and the second input terminal 326 are connected to node 322 (or PPM contact pad 204). The comparator 328 can be used to convert the input voltage V at the second input terminal 326 into a single input terminal. in The reference voltage V at the first input terminal 324 ref The operational amplifier being compared, wherein the output voltage V at output terminal 330 is... out It can indicate the input voltage V in Is it higher or lower than the reference voltage V? ref For example, at the input voltage V in Greater than the reference voltage V ref At that time, the output voltage V out It can be a positive voltage. On the other hand, the input voltage V in Less than the reference voltage V ref At that time, the output voltage V out It can be a negative voltage.

[0065] In some embodiments, the PPM circuit 202 may further include an inverter 332 having an input terminal connected to the output terminal 330 of the comparator 328. The inverter 332 can invert the input signal. For example, at the output voltage V of the comparator 328... out When the voltage is positive, the PPM enable signal enPPM generated by inverter 332 at output terminal 334 can be zero, that is, PPM enable signal enPPM = 0. On the other hand, when the output voltage V of comparator 328 is positive... outWhen the voltage is negative, the PPM enable signal enPPM = 1. In other words, the potential V at node 322... ppm Greater than (or higher than) the reference voltage V ref (that is, V) ppm >V ref When ), the PPM enable signal enPPM = 0. The potential V at node 322... ppm Less than (or lower than) the reference voltage V ref (that is, V) ppm <V ref When ), the PPM enable signal enPPM = 1.

[0066] In some embodiments, an optional RC filter 344 may be connected between node 322 and the second input terminal 326 of comparator 328. The RC filter 344 can be used to filter out unwanted signals within a certain frequency range.

[0067] As discussed above, for the PPM system 200A ( Figure 2A (China) and PPM system 200B ( Figure 2B In the case of PPM, the PPM contact pads 204 in the same PPM group 203 can be electrically connected, that is, the PPM contact pads 204 in the same PPM group 203 can maintain the common potential V of all PPM contact pads 204 in the same PPM group 203. ppm Therefore, each PPM group 203 requires only one comparator 328, which is electrically connected at node 322 to one of the PPM contact pads 204. Furthermore, the PPM enable signal enPPM indicates the potential V of two or more memory dies in the PPM group 203. ppm .

[0068] refer to Figure 3 During operation, a first control signal 340 can be sent to the gate terminal 317 of the second pull-up driver 315, thereby turning the second pull-up driver 315 on or off. For example, if the voltage of the first control signal 340 is lower than the threshold voltage of the second pull-up driver 315, the second pull-up driver 315 can be turned on, and the second current I... up_2 The current can flow through the second pull-up driver 315. If the voltage of the first control signal 340 is higher than the threshold voltage of the second pull-up driver 315, the second pull-up driver 315 can be turned off.

[0069] The current flowing through the pull-down driver 336 is also known as the pull-down current I. pull_dn .exist Figure 3 In its construction, the pull-down current I pull_dn It can be the first current I up_1 Second current Iup_2 The sum. When the second pull-up driver 315 is turned on, the pull-down current I. pull_dn It can be controlled by the second current I up_2 Dominant, because the second current I flowing through the "strong pull-up driver" up_2 Compared to the first current I flowing through the "weak pull-up driver" up_1 Much larger, as discussed earlier. When the second pull-up driver 315 is turned off, only the first current I... up_1 The flow is directed down to the driver 336 through the PPM resistor 318 and node 322.

[0070] When the second control signal 342 is sent to the gate terminal 338 of the pull-down driver 336, the pull-down driver 336 can be turned on or off. For example, if the voltage of the second control signal 342 is higher than the threshold voltage of the pull-down driver 336, the pull-down driver 336 can be turned on, and a conductive path from node 322 to ground can be formed. If the voltage of the second control signal 342 is lower than the threshold voltage of the pull-down driver 336, the pull-down driver 336 can be turned off.

[0071] In some embodiments, the pull-down driver 336 can operate as a current controller. In this example, when the pull-down driver 336 is turned on, the current flowing from node 322 to ground through the pull-down driver 336 (i.e., the pull-down current I) pull_dn The amplitude depends on the second control signal 342. When the pull-down driver 336 is an nFET, such as... Figure 3 As shown, the pull-down current I pull_dn The voltage level of the second control signal 342 and the transconductance of the pull-down driver 336 can be determined. According to some embodiments of this disclosure, the current distribution I of the memory die (e.g., NAND flash memory 100-1) cc This can correspond to the voltage level of the second control signal 342, and thus to the pull-down current I. pull_dn Therefore, the pull-down current I pull_dn It can serve as the current distribution I of the memory die cc The current mirror.

[0072] In some embodiments, the pull-down current I pull_dn It can be related to the current distribution I cc The current level is proportional to the pull-down current I. pull_dn Based on current distribution I cc Scaled down proportionally. For example, if the memory die is operating at a current of 200mA, the pull-down current I of the PPM circuit 202 will be... pull_dn It can be 200μA. Therefore, it can be controlled by the pull-down current I. pull_dnThe storage operation and corresponding current are adjusted for each memory die. Furthermore, through die-to-die connections at the PPM contact pads, peak power operation in PPM group 203 can be coordinated between two or more memory dies, such as... Figure 2A and Figure 2B As shown in the image.

[0073] For example, when the PPM circuit 202 is in the reset state, the second pull-up driver 315 can be turned off, and there is no second current I. up_2 The current flows through node 322. Meanwhile, the first pull-up driver 314 can be kept on by default, and the pull-down driver 336 can be turned off. Accordingly, the potential V at node 322 (or at PPM contact pad 204) can be made possible via the conductive path from the PPM resistor 318 and the first pull-up driver 314 to the first power supply 312. ppm Maintain above the reference voltage V ref The first voltage level.

[0074] In some embodiments, in the reset state, the pull-down driver 336 may also be kept slightly on or weakly on (e.g., with low transconductance), thereby enabling V ppm The potential remains close to, but still higher than, the reference voltage V. ref The first voltage level. In this example, the pull-down current I... pull_dn It is possible to have no second current I up_2 In the case of the first current I up_1 Confirmed. This low-level pull-down current I pull_dn This corresponds to the low-level current I flowing on the memory die. L The memory die can perform operations that consume a low-level current I. L The operation.

[0075] In some embodiments, the pull-down driver 336 can be fully turned on (e.g., having high transconductance). In this example, the potential V at node 322 (or PPM contact pad 204) can be made possible via another conductive path from the pull-down driver 336 to ground. ppm Keep below the reference voltage V ref The second voltage level.

[0076] In some embodiments, a potential V can be formed by turning on the second pull-up driver 315 and then (e.g., after approximately 1 μs) turning on the pull-down driver 336. ppm The positive pulse in.

[0077] As discussed above, when the second pull-up driver 315 is turned on, the pull-down current I... pull_dn It can be the first current I up_1Second current I up_2 The sum of these. This high-level pull-down current I pull_dn Corresponding to the high-level current I flowing on the memory die H The memory die can perform operations that consume a high-level current I. H Peak power operation (PPO).

[0078] Figure 4 Some embodiments of the present disclosure and their use are illustrated. Figure 3 PPM circuit 202 in Figure 2A Peak power management system 200A or Figure 2B The peak power check routine 400 associated with the peak power management system 200B is described. It should be understood that the peak power check (PPC) routine 400 is not exclusive and other operating steps may be performed before, after, or between the illustrated operating steps. In some embodiments, some operating steps of the PPC routine 400 may be omitted, or may include other operating steps not described herein for brevity. In some embodiments, the operating steps of the PPC routine 400 may be performed in a different order and / or may vary.

[0079] PPC routine 400 provides an exemplary method for managing peak power operation in a PPM group 203 having two or more memory dies. Each memory die includes at least one PPM circuit 202. The following example is illustrated for a specific memory die, wherein the peak power operation of that memory die will not be performed simultaneously with another peak power operation on another memory die in the same PPM group 203. Accordingly, the total power (or current) consumed by the PPM group 203 can be regulated and controlled below a predetermined value.

[0080] like Figure 4 As shown, PPC routine 400 begins at operation step S405, where the PPM circuit 202 on a specific memory die is in a reset state. (See previous reference...) Figure 3 As discussed, in the reset state, the pull-down driver 336 of the PPM circuit 202 can be turned off.

[0081] When a specific memory die is about to perform peak power operation, PPC routine 400 can be started for that specific memory die, and PPC routine 400 can proceed to operation step S410, which is the first checkpoint in PPC routine 400. At operation step S410, the potential V of PPM contact pad 204 is first detected. ppm And then the potential V ppm With reference voltage V ref Compare them.

[0082] If the potential V is determinedppm Greater than or higher than the reference voltage V ref If the voltage level is at the first voltage level (also known as the "high" level), the PPC routine can proceed to operation step S415. As discussed above, the potential V ppm It is common to all PPM contact pads 204 of the PPM circuit 202 in the same PPM group 203. At potential V ppm At the first voltage level, this indicates that no memory die in the same PPM group 203 is performing peak power operation. Accordingly, the specific memory die can continue with its PPC routine 400.

[0083] To prevent other memory dies in the same PPM group 203 from performing peak power operation, and to reserve power / current budget for a specific memory die, at operation step S415, the potential V of the PPM contact pad 204 is... ppm It can be driven to a voltage less than or below the reference voltage V. ref The second voltage level. The potential V can be increased by turning on the pull-down driver 336 of the PPM circuit 202 on a specific memory die. ppm Set to the second voltage level (also known as the "low" level).

[0084] Subsequently, PPC routine 400 proceeds to operation step S420, in which a specific memory die is made to wait for a first delay period t. dly_1 In some embodiments, the first delay period t dly_1 This is specific to a particular memory die in PPM group 203. In other words, each memory die in PPM group 203 has a different first delay period t. dly_1 .For example, Figure 2A The NAND flash memory 100-1 and NAND flash memory 100-2 have a first delay period t with different values. dly_1 When any other memory die and a specific memory die simultaneously start the PPC routine 400 and begin the first checkpoint (i.e., operation step S410), due to the different first delay periods t dly_1 The PPC routine 400 for other memory dies and specific memory dies will not proceed to operation step S425 (i.e., the second checkpoint) simultaneously. Accordingly, memory dies in the same PPM group 203 are desynchronized when PPO is executed.

[0085] Then, PPC routine 400 proceeds to operation step S425, the second checkpoint, where the potential V at PPM contact pad 204 is determined. ppm Is there a pause signal? In some embodiments, the pause signal includes a potential V. ppm A positive pulse.

[0086] If no pause signal is detected, PPC routine 400 continues to operation step S430, where a pause signal may be generated. The pause signal includes a potential V. ppm In the example of the positive pulse, a pause signal can be generated by turning on the second pull-up driver 315 and then (e.g., after approximately 1 μs) turning on the pull-down driver 336. The pause signal is generated such that other PPC routines for other memory dies in PPM group 203 can be paused according to the pause signal.

[0087] At operation step S435, PPC routine 400 waits for the second delay period t. ppm In some embodiments, the second delay period t ppm Two or more memory dies in the same PPM group 203 can be different. (This is in contrast to the first delay period t.) dly_1 Unlike other embodiments, in some implementations, the second delay period t ppm Two or more memory dies in the same PPM group 203 can be identical. Second delay period t ppm This can be any suitable time period predetermined by the NAND storage system 10 to include the communication delay between the PPC routine 400 and the PPO. In some embodiments, the second delay time period t ppm It depends on the firmware design of the NAND storage system 10.

[0088] When PPC routine 400 begins operation step S440, a specific memory die can begin executing PPO, wherein the high current level I on the specific memory die... H This can correspond to the pull-down current I of the pull-down driver 336 flowing through the PPM circuit 202. pull_dn The pull-down current I pull_dn It is the first current I up_1 Second current I up_2 sum.

[0089] After the PPO is completed on a specific memory die, PPC routine 400 proceeds to operation step S445, where the potential V of the PPM contact pad 204 can be adjusted. ppm A recovery signal is generated. This recovery signal can be used in other memory dies to resume their suspended PPC routines. In some embodiments, this can be achieved by applying a potential V... ppm A recovery signal is generated by driving to a first voltage level (e.g., from low to high). For example, the second pull-up driver 315 of the PPM circuit 202 on a particular memory die can be turned off. The pull-down driver 336 can also be turned off. In some embodiments, the pull-down driver 336 can be kept slightly on or weakly on, such that the pull-down current I... pull_dnWith the first current I up_1 Broadly the same, it corresponds to the low current level I used by the operation on the memory die. L .

[0090] If the potential V is determined at operation step S410 ppm Less than or below the reference voltage V ref If the voltage level is at the second voltage level, it indicates that at least one of the other memory dies in PPM group 203 is performing or about to perform PPO, and the potential V has been set. ppm The signal was driven from high to low. Then, at operation step S450, the PPC routine 400 for the specific memory die is paused.

[0091] Similarly, if a pause signal is detected at operation step S425, the PPC routine 400 for a specific memory die is also paused at operation step S450. In some embodiments, the PPC routine 400 is paused during a first delay period t at operation step S420. dly_1 During the waiting period, the system continuously checks for pause signals. In this example, the first delay period t at operation step S420... dly_1 If a pause signal is detected during the process, the PPC routine 400 can be paused at operation step S450.

[0092] When the PPC routine 400 for a specific memory die pauses at operation step S450, the PPC routine 400 continuously checks the potential V at the PPM contact pad 204. ppm Is there a recovery signal? By passing the potential V... ppm In the example of generating a recovery signal by driving to a first voltage level (i.e., from low to high), a potential V can be used. ppm The rising edge of the signal causes the PPC routine 400, which was paused at operation step S450, to resume. If a resumption signal is detected at operation step S455, the PPC routine 400 continues to operation step S460, where the potential V... ppm Driven to the second voltage level (i.e., low level), power / current resources are reserved for a specific memory die. If no recovery signal is detected, PPC routine 400 remains suspended at operation step S450.

[0093] Next, PPC routine 400 proceeds to operation step S420. In some embodiments, when there are only two memory dies in a PPM group, PPC routine 400 may proceed to operation step S435. In this example, for a specific memory die after PPC routine 400 is restored, the waiting period t can be skipped. dly_1This is because other memory dies have already completed their Pre-Proofing Processing (PPO). Therefore, there is no overlap in two memory dies performing PPO simultaneously after a pause-resume cycle.

[0094] Figure 5-7 It shows the use of Figure 2A Three exemplary implementations of the PPC routine 400 of the PPM system 200A are provided, wherein each PPM group 203 includes two memory dies, for example, "die 0" (also referred to as the first NAND memory die) and "die 1" (also referred to as the second NAND memory die). Die 0 and die 1 may be similar to the NAND flash memory 100 shown in Figures 1-2.

[0095] exist Figure 5 In the example shown, at the start of the time series, both memory dies, die 0 and die 1, are in a reset state. Die 0 receives the command signal to execute the first PPO, and then die 1 receives its command signal to execute the second PPO. Therefore, the first PPC routine 400 for die 0 is started first. Die_0 At time t1 (i.e., the first moment), the first PPC routine 400 for die 0 is executed. Die_0 Initiate operation step S410 to detect the potential V of the PPM contact pad 204 of the PPM circuit 202 on die 0. ppm Since neither die 0 nor die 1 is performing the first PPO or the second PPO, the potential V ppm It is maintained at a negligible amplitude or approximately the first current I on both die 0 and die 1. up_1 The amplitude of the pull-down current I pull_dn The high level (first voltage level). That is, both die 0 and die 1 are operating at a low current level I. L Perform the operation.

[0096] Determine the potential V ppm After being high at time t1, according to the first PPC routine 400 for die 0 Die_0 Operating steps S415, potential V ppm It is driven to a low level (i.e., the second voltage level).

[0097] When die 1 receives its command signal for executing PPO, the second PPC routine 400 for die 1 can be started. Die_1 And at time t2 (i.e., the third moment), operation step S410 is performed. In this example, time t2 is later than time t1. This is because the first PPC routine 400 for die 0 has already been performed. Die_0 electric potential V ppmDriven low, thus pausing the second PPC routine 400 for die 1 at operation step S450. Die_1 .

[0098] When the potential V ppm After being driven low, the first PPC routine 400 Die_0 The die 0 waits for the first delay period t at operation step S420. dly_1_Die 0. Because no pause signal was detected at operation step S425 (e.g., potential V). ppm The positive pulse), and therefore at time t3 (i.e., the second moment), according to the first PPC routine 400 for die 0. Die_0 The operation step S430 generates a pause signal. During the second delay period t... ppm After (operation step S435), die 0 can proceed according to the first PPC routine 400. Die_0 Operation step S440 begins the first PPO at time t4. At time t5 (i.e., the fifth moment), die 0 completes the first PPO and follows the first PPC routine 400. Die_0 Operation step S445 generates a recovery signal. In this example, by using the potential V ppm A recovery signal is generated when the drive is brought to a high level.

[0099] Between time t2 and time t5, the second PPC routine 400 for die 1 is paused at operation step S450. Die_1 At time t5, the potential V ppm When a recovery signal is detected, the second PPC routine 400 for die 1 is resumed. Die_1 In this example, the potential V at time t5 ppm The rising edge can be used to trigger the second PPC routine 400. Die_1 The recovery was then performed according to the second PPC routine 400. Die_1 In operation step S460, at time t6 (i.e., the sixth moment), the potential V ppm Drive to low level. Figure 5 Thus, an electric potential V is generated. ppm The falling edge. It should be noted that at time t5, according to the first PPC routine 400 for die 0. Die_0 The generated rising edge and at time t6 according to the second PPC routine 400 for die 1 Die_1 The duration between the generated falling edges is greater than the time t3 according to the first PPC routine 400 for die 0. Die_0 The generated positive pulse has a long pulse width. This is achieved by adjusting the potential V... ppmDriving to a low level allows for the storage of power / current resources for die 1. For example, in the case of requesting another PPO for die 0, the new PPC routine will be paused after the first checkpoint (operation step S410). Accordingly, the second PPC routine 400 for die 1, which was already paused at operation step S450, will be suspended. Die_1 It can be completed without further delay.

[0100] Next, the second PPC routine 400 for die 1 Die_1 Proceed to operation step S420, in which die 1 waits for the first delay period t. dly_1_Die 1. In the second PPC routine 400 Die_1 In operation step S425, check the potential V. ppm Is there a pause signal? If no pause signal is detected, a pause signal (e.g., potential V) is generated at time t7 (also known as the fourth time point). ppm (positive pulse). During the second delay period t at the waiting operation step S435. ppm Subsequently, die 1 follows the second PPC routine 400. Die_1 The second PPO is initiated at operation step S440. At time t8 (i.e., the eighth moment), die 1 completes the second PPO, and at operation step S445, the potential V is changed. ppm A recovery signal is generated when the drive is brought to a high level.

[0101] Accordingly, die 0 and die 1 completed the first PPO and the second PPO, respectively. This was achieved using the first PPC routine 400. Die_0 Second PPC routine 400 Die_1 Two memory dies (e.g., die 0 and die 1) in the same PPM group 203 (see Figure 2) can coordinate their PPO via PPM circuit 202. This is achieved by adjusting the potential V shared by the PPM contact pads 204. ppm It can synchronize the PPO of two memory chips.

[0102] Figure 6 Another exemplary implementation of the PPC routine 400 according to some embodiments of this disclosure is shown. Figure 6 In this process, die 0 (i.e., the first NAND storage die) and die 1 (i.e., the second NAND storage die) simultaneously receive command signals from the NAND storage system 10 for the first PPO and the second PPO. Therefore, the first PPC routine 400... Die_0 Second PPC routine 400 Die_1 Simultaneously, the first checkpoint is reached (operation step S410). At potential V... ppm When determined to be at a high level (i.e., the first voltage level), the potential Vppm At operation step S415, the diode is driven to a low level (i.e., the second voltage level) at time t1 (the first moment). Afterwards, both die 0 and die 1 follow the corresponding first PPC routine 400. Die_0 Second PPC routine 400 Die_1 Wait for the corresponding first delay period t at operation step S420. dly_1_Die 0 and t dly_1_Die 1.

[0103] exist Figure 6 In the example, the first delay period t of die 0 dly_1_Die 0 is shorter than the first delay period t of die 1 dly_1_Die 1. Accordingly, the first PPC routine 400 for die 0. Die_0 In the second PPC routine 400 used for die 1 Die_1 Previously completed operation step S420. When according to the first PPC routine 400 for die 0. Die_0 Operating procedure S425: Determine the potential V at the second check point. ppm If there is no pause signal (e.g., a positive pulse) in operation step S430, a pause signal is generated at time t3 (i.e., the second moment).

[0104] When die 1 is in the first delay period t at operation step S420 dly_1_Die While waiting during step 1, according to the second PPC routine 400 Die_1 Operating steps S425 at potential V ppm A pause signal was detected. In this example, during the first delay period t... dly_1_Die 1. Able to complete (e.g.) Figure 6 Prior to (as described above), after a pause signal is detected, the pause signal is used in the second PPC routine 400 of die 1. Die_1 Pause at operation step S450.

[0105] In the second PPC routine 400 used for die 1 Die_1 During the pause, the first PPC routine 400 for die 0 is used. Die_0 Continue to operation step S435, that is, wait for the second delay period t. ppm Subsequently, die 0 begins the first PPO at operation step S440 at time t4. When die 0 completes the first PPO at time t5, the first PPC routine 400 for die 0 is executed. Die_0 Operation step S445 generates a recovery signal. In this example, the potential V ppm It is driven to a high level.

[0106] According to the second PPC routine 400 for die 1 Die_1 When the operation step S455 detects a recovery signal (e.g., via potential V), ppm (triggered by the rising edge), second PPC routine 400 Die_1 Recover and by changing the potential V at time t6 ppm The drive is pulled low to proceed to operation step S460. Next, the second PPC routine 400... Die_1 Proceed directly to operation step S435, because there are only two memory dies in the same PPM group 203, and die 0 has already completed the first PPO. While waiting for the second delay period t at time t7. ppm Subsequently, die 1 begins the second PPO at operation step S440. When die 1 completes the second PPO, the second PPC routine 400 is executed. Die_1 Operation step S445 generates a recovery signal at time t8. Here, the potential V ppm It is driven high again.

[0107] Figure 7 Some embodiments according to this disclosure are shown. Figure 4 Another exemplary implementation of the PPC routine 400 shown. Figure 7 In the process, in die 0 (i.e., the first NAND memory die), according to the first PPC routine 400 for die 0... Die_0 After the operation step S425 has completed the second checkpoint, die 1 (i.e., the second NAND memory die) receives a command signal for the second PPO.

[0108] In this example, the first PPC routine 400 is used for die 0. Die_0 Operation step S410 begins at time t1 (i.e., the first moment) and the potential V is determined. ppm It is held at a high level (i.e., the first voltage level). Then, according to operation step S415, the potential V is... ppm Driven to a low level (i.e., the second voltage level). Then, die 0 waits for the first delay period t at operation step S420. dly_1_Die 0. Because according to operation step S425, the potential V was not... ppm A pause signal (e.g., a positive pulse) is detected, and therefore a pause signal is generated at time t3 (i.e., the second moment) at operation step S430. During the second delay period t... ppm Following operation step S435, die 0 begins the first PPO at time t4 (operation step S440). At time t5, die 0 completes the first PPO and generates a recovery signal (operation step S445). For example, the potential V ppm It can be driven to a high level.

[0109] exist Figure 7 In the example, when die 1 receives a command signal to execute the second PPO after time t3, the second PPC routine 400 for die 1... Die_1 It is initiated and proceeds to operation step S410. This is because at time t3, the first PPC routine 400 for die 0 has already been executed. Die_0 electric potential V ppm Driven low, die 1 pauses the second PPC routine 400 at operation step S450. Die_1 .

[0110] At time t5, when the recovery signal is detected according to operation step S455, due to the second PPC routine 400 of die 1... Die_1 Recovery is performed at time t6 (operation step S460), where the potential V ppm It can be driven to a low level. Here, it can be driven by the potential V. ppm The rising edge triggers the second PPC routine 400 for die 1 at time t5. Die_1 The recovery. Furthermore, the potential V ppm The falling edge at time t6 is due to the potential V being driven low. ppm It is generated by the drive.

[0111] Next, the second PPC routine 400 for die 1 Die_1 Proceed to operation step S420, in which die 1 waits for the first delay period t. dly_1_Die 1. Subsequently, die 1 checks the potential V at operation step S425. ppm Is there a pause signal? If no pause signal is detected, a pause signal (i.e., potential V) is generated at time t7 (i.e., the fourth moment). ppm (positive pulse). After waiting for the second delay period t ppm Following operation step S435, die 1 begins the second PPO at operation step S440. At time t8, die 1 completes the second PPO and follows the second PPC routine 400. Die_1 Operating step S445, for example, by using the potential V ppm A high level is driven to generate a recovery signal. In this way, die 0 and die 1 sequentially complete the first PPO and the second PPO.

[0112] Figure 8 A measurement scheme for a pulse according to some embodiments of the present disclosure is illustrated. As an example, pulse 850 has a pulse width t. pulse Pulse width t pulseThis can be a predetermined value, for example, within the range of approximately 0.1 μS to 10 μS. Pulse 850 can be a reference. Figure 4-7 and Figure 9-10 The described electric potential V ppm A positive pulse.

[0113] To determine pulse 850, two measurements can be performed, including a first detector 852 and a second detector 854. The first detector 852 and the second detector 854 can be measured over a time interval t. mea Separate. Measurement time period t mea It can be compared to the pulse width t of pulse 850. pulse Long. For example, the measurement period t mea It can be approximately 20 μS.

[0114] For example, when the first detector 852 and the second detector 854 are used, when the potential V ppm Pulse 850 can be determined when there is a change in voltage level and both the first detector 852 and the second detector 854 detect the second voltage level (i.e., low level) and return a value of "0". See PPC routine 400 (see...). Figure 4 In operation step S425, if the potential V ppm When there is a change and both the first detector 852 and the second detector 854 detect the second voltage level and return a value of "0", the potential V is detected. ppm If a pause signal (e.g., a positive pulse) is received, the PPC routine 400 pauses at operation step S450.

[0115] On the other hand, for example, if at operation step 410, both the first detector 852 and the second detector 854 detect a first voltage level (i.e., a high level) and return a value of "1", then the potential V can be determined. ppm The PPC routine 400 for storing the die remains at a high level and can continue to operation steps S415 and S420. If the first probe 852 and the second probe 854 obtain different results, such as "0" and "1", operation step 410 is repeated until both the first probe 852 and the second probe 854 measure a high potential and return a value of "1".

[0116] When the first detector 852 detects a low level (returns "0") and the second detector 854 detects a high level (returns "1"), it indicates that a potential V has been detected. ppm The rising edge (not a positive pulse).

[0117] Figure 9-10 It shows Figure 2BTwo exemplary implementations of the PPC routine 400 in the PPM system 200B are provided, wherein each PPM group 203 includes three memory dies (e.g., "die 0", "die 1", and "die 2"). Die 0 is also referred to as the first NAND memory die. Die 1 is also referred to as the second NAND memory die. Die 2 is also referred to as the third NAND memory die.

[0118] exist Figure 9 In the example shown, at the beginning of the time series, all three memory dies in the same PPM group 203, namely die 0, die 1, and die 2, are in a reset state. Die 0 receives the command signal for executing the first PPO before dies 1 and dies 2. The first PPC routine 400 for die 0... Die_0 It begins at time t1 (first moment) and proceeds to operation step S410. Since no memory die is performing PPO, the potential V... ppm Maintain the first voltage level (e.g., high level). As discussed above, at potential V ppm When held at a high level, the pull-down current I pull_dn It has a negligible or approximately first current I up_1 The amplitude. That is, all memory dies in PPM group 203 (e.g., die 0, die 1, and die 2) operate at a low current level I. L Execute the operation. When the potential V is determined at time t1 in operation step S410... ppm After maintaining the first voltage level, at operation step S415, according to the first PPC routine 400 for die 0. Die_0 electric potential V ppm Drive to a second voltage level (i.e., low level) that is lower than the first voltage level.

[0119] When die 1 receives its command signal for executing the second PPO, die 1 begins the second PPC routine 400 at time t2 (the third moment). Die_1 Operation step S410. Here, time t2 is later than time t1. Due to the potential V ppm It has been driven low by die 0, therefore the second PPC routine 400 is used for die 1. Die_1 The operation is paused at step S450. Similarly, when die 2 receives its command signal for executing the third PPO, it proceeds according to the third PPC routine 400. Die_2 Operating steps S410, potential V ppm It is detected as being held low, and then the third PPC routine 400 is used for die 2. Die_2 Also pause according to operating procedure S450.

[0120] When the potential Vppm After being set to low level, die 0 waits for the first delay period t. dly_1_Die 0 (Operation step S420). Because no potential V was detected at operation step S425 at time t3 (i.e., the second moment). ppm The pause signal (e.g., a positive pulse) is thus triggered according to the first PPC routine 400 for die 0. Die_0 The operation step S430 generates a pause signal. During the second delay period t... ppm After (operation step S435), die 0 can begin the first PPO at time t4 (operation step S440). At time t5, die 0 completes the first PPO and, for example, by adjusting the potential V... ppm Drive to a high level to generate a recovery signal (operation step S445).

[0121] Between time t2 and time t5, the second PPC routine 400 for die 1 is used. Die_1 and the third PPC routine 400 for die 2 Die_2 Pause at the corresponding operation step S450. When a recovery signal is detected at time t5 (operation step S455), the second PPC routine 400 for die 1 is activated. Die_1 and the third PPC routine 400 for die 2 Die_2 All can be recovered. According to the second PPC routine 400 used for die 1. Die_1 and the third PPC routine 400 for die 2 Die_2 The corresponding operation step S460, potential V ppm It is driven low at time t6. It should be noted that at time t5, according to the first PPC routine 400 for die 0... Die_0 The generated rising edge and at time t6 according to the second PPC routine 400 for die 1 Die_1 And the third PPC routine 400 for die 2 Die_2 The duration between the generated falling edges is greater than the time t3 according to the first PPC routine 400 for die 0. Die_0 The generated positive pulse (i.e., pause signal) has a long pulse width. This is achieved by adjusting the potential V... ppm Driven low, other PPC routines 400 for other memory dies in the same PPM group cannot pass the first checkpoint (at operation step S410). Accordingly, memory dies that have already paused at operation step S450 (e.g., die 1 and die 2) are then able to complete the second and third PPOs without further delay.

[0122] Next, the second PPC routine 400 for die 1 Die_1and the third PPC routine 400 for die 2 Die_2 The corresponding operation step S420 is performed, in which die 1 waits for the first delay period t. dly_1_Die1 And die 2 waits for the first delay period t dly_1_Die 2a In this example, the first delay period t of die 1 dly_1_Die The first delay period t is shorter than that of die 2. dly_1_Die 2a Accordingly, the second PPC routine 400 for die 1 Die_1 In the third PPC routine 400 used for die 2 Die_2 Previously, we reached operation step S425. After determining the potential V... ppm When there is no pause signal, according to the second PPC routine 400 for die 1 Die_1 Operation step S430 at time t7 (fourth moment) at potential V ppm A pause signal (i.e., a positive pulse) is generated in the middle.

[0123] In the third PPC routine 400 used for die 2 Die_2 Wait for the first delay period t at operation step S420. dly_1_Die 2a At the same time, the potential V was detected. ppm The pause signal (operation step S425) is in the process. In this example, after the first delay period t is completed... dly_1_Die 2a Previously, the pause signal was used in the third PPC routine 400 of die 2. Die_2 Pause at operation step S450.

[0124] In the third PPC routine 400 used for die 2 Die_2 During the pause, the second PPC routine 400 for die 1 is... Die_1 Proceed to step S435. After waiting for the second delay period t ppm Following operation step S435, die 1 then begins the second PPO at operation step S440. At time t8, die 1 completes the second PPO and, according to the second PPC routine 400... Die_1 Operation step S445 involves, for example, changing the potential V ppm A high-level drive generates a recovery signal. Up to this point, die 0 and die 1 have completed the first PPO and the second PPO respectively, and the first PPC routine 400 for die 0 is also included. Die_0 and the second PPC routine 400 for die 1 Die_1 All were completed.

[0125] When a recovery signal is detected at time t8 according to operation step S455 (e.g., at potential V), ppm At the rising edge of the die, the third PPC routine 400 is used for die 2. Die_2 Recovery. At operation step S460, the potential V ppm It is driven low to prevent other memory dies in the same PPM group 203 from starting PPO or PPC routine 400.

[0126] Afterwards, die 2 waits for the first delay period t at operation step S420. dly_1_Die 2b In this example, the first delay period t dly_1_Die 2b Unlike the first delay period t dly_1_Die 2a Because of the first delay period t dly_1_Die 2b and t dly_1_Die 2a It is randomly generated. In some embodiments, the first delay period t dly_1_Die2b and t dly_1_Die 2a This can be the same for die 2, as long as the first delay period is unique to each memory die in the same PPM group 203. In determining the potential V... ppm When there is no pause signal, according to the third PPC routine 400 Die_2 In operation step S430, a pause signal is generated at time t9. After waiting for the second delay period t... ppm Following operation step S435, die 2 can begin the third PPO at operation step S440. At time t 10 Above, die 2 completed the third PPO, and by, for example, by applying potential V ppm Drive to a high level to generate a recovery signal (operation step S445).

[0127] By using PPC routine 400, multiple memory dies can coordinate their PPOs via their PPM circuits 202. This is achieved by adjusting the potential V shared by the PPM contact pads 204 of the PPM circuits 202 in the same PPM group 203. ppm It can synchronize the PPO of the memory chip.

[0128] Figure 10 Another exemplary implementation of the PPC routine 400 according to some embodiments of this disclosure is shown. Figure 10In this process, die 0 (first NAND storage die), die 1 (second NAND storage die), and die 2 (third NAND storage die) simultaneously receive command signals from the NAND storage system 10 for the first PPO, second PPO, and third PPO. First PPC routine 400 Die_0 Second PPC routine 400 Die_1 And the third PPC routine 400 Die_2 Simultaneously, the first checkpoint is reached (operation step S410). At potential V... ppm When determined to be maintained at the first voltage level (i.e., high level), the potential V ppm Therefore, at operation step S415, they are driven to the second voltage level (i.e., low level) at time t1 (the first moment). Dies 0, 1, and 2 then wait for the corresponding first delay period t at operation step S420. dly_1_Die 0, t dly_1_Die 1a and t dly_1_Die 2a .

[0129] exist Figure 10 In the example, the first delay period t for die 0 dly_1_Die 0 is the shortest. Accordingly, die 0 completes operation step S420 before dies 1 and dies 2. This is based on the first PPC routine 400 for die 0. Die_0 Operation step S425 determines the potential V at the second check point at time t3 (second moment). ppm When there is no pause signal (e.g., a positive pulse), a pause signal is generated according to operation step S430.

[0130] While die 1 and die 2 are performing operation step S420, that is, waiting for the first delay period t respectively. dly_1_Die 1a and t dly_1_Die 2a At the same time, both die 1 and die 2 detected a potential V. ppm The pause signal (operation step S425) triggers both die 1 and die 2 to begin operation step S450, and each completes the first delay period t. dly_1_Die 1a and t dly_1_Die 2a Previously, the second PPC routine was paused 400. Die_1 And the third PPC routine 400 Die_2 .

[0131] In the second PPC routine 400 used for die 1 Die_1 and the third PPC routine 400 for die 2 Die_2While suspended, the first PPC routine 400 used for die 0... Die_0 Proceed to operation step S435, where die 0 waits for the second delay period t. ppm Subsequently, die 0 begins the first PPO at time t4 in operation step S440. When die 0 completes the first PPO at time t5, it proceeds according to the first PPC routine 400. Die_0 Operation step S445, by, for example, changing the potential V ppm A recovery signal is generated when the drive is brought to a high level.

[0132] When die 1 and die 2 detect a recovery signal (e.g., potential V) at operation step S455 ppm At the rising edge of the die, the second PPC routine 400 is used for die 1. Die_1 and the third PPC routine 400 for die 2 Die_2 The process is resumed and proceeds to operation step S460, wherein the potential V ppm It is driven low at time t6. Next, both die 1 and die 2 execute operation step S420, in which die 1 waits for the first delay period t. dly_1_Die 1b And die 2 waits for the first delay period t dly_1_Die 2b In this example, the first delay period is randomly generated, and the first delay period t is... dly_1_Die 1a and t dly_1_Die 1b It is different for die 1, and the first time period t dly_1_Die 2a and t dly_1_Die 2b This is different for die 2. In some embodiments, the first delay period t dly_1_Die 1a and t dly_1_Die 1b For die 1, it can be the same, and the first time period t dly_1_Die 2a and t dly_1_Die 2b The same can be true for die 2. In this example, the first time period t dly_1 It can be pre-defined by the NAND storage system 10, as long as it is unique to each storage die.

[0133] exist Figure 10 In the example, the first delay period t for die 1 dly_1_Die 1b Compared to the first delay period t used for die 2 dly_1_Die 2bShort. Accordingly, die 1 begins operation step S425 (i.e., the second check point) before die 2. According to the second PPC routine 400 for die 1... Die_1 In operation step S425, the potential V is determined at time t7 (the fourth moment). ppm Is there a pause signal? If no pause signal is detected, a potential V is generated. ppm The pause signal generated by die 1 triggers die 2 to stop operation step S420, and pauses the third PPC routine 400 at operation step S450. Die_2 .

[0134] For die 1, after waiting for the second delay period t ppm After operation step S435, die 1 can begin the second PPO at time t8 at operation step S440. When die 1 completes the second PPO, according to the second PPC routine 400... Die_1 Operation step S445, by, for example, changing the potential V at time t9 ppm A recovery signal is generated when the drive is brought to a high level.

[0135] When a recovery signal generated by die 1 is detected while die 2 is paused at operation step S450, the third PPC routine 400 for die 2 is executed. Die_2 The process is resumed and proceeds to operation step S460, wherein the potential V ppm It is driven to a low level. Afterwards, die 2 executes operation step S420 and waits for the first delay period t. dly_1_Die 2c The third PPC routine 400 for die 2 Die_2 Proceed to step S425 (i.e., the second checkpoint). As discussed above, die 2 checks the potential V. ppm The pause signal in, and when no pause signal is detected at time t 10 A pause signal is generated (operation step S430). After waiting for the second delay period t... ppm Following operation step S435, die 2 begins the third PPO at operation step S440. When die 2 completes the third PPO, according to operation step S445, by, for example, at time t... 11 General's potential V ppm The drive goes high to generate a recovery signal. At this point, all three memory dies, namely die 0, die 1, and die 2, have completed PPO one by one.

[0136] In summary, this disclosure provides a method for peak power management (PPM) for multiple NAND memory dies. The multiple NAND memory dies include a first NAND memory die and a second NAND memory die, and each of the first and second NAND memory dies includes a PPM circuit having PPM contact pads held at a common potential between the first and second NAND memory dies. The method includes the following steps: detecting the potential of the PPM contact pad at a first moment during a first peak power check (PPC) routine for a first NAND flash memory die; if the detected potential is at a first voltage level at the first moment, driving the potential of the PPM contact pad to a second voltage level, wherein the second voltage level is lower than the first voltage level; causing the first NAND flash memory die to wait for a first delay period; determining at a second moment during the first PPC routine for the first NAND flash memory die whether there is a pause signal in the potential of the PPM contact pad, wherein the second moment is later than the first moment; if no pause signal is detected at the second moment, generating a pause signal in the potential of the PPM contact pad to pause a second PPC routine for a second NAND flash memory die; causing the first NAND flash memory die to perform a first peak power operation; and generating a recovery signal in the potential of the PPM contact pad after the first NAND flash memory die completes the first peak power operation to resume the second PPC routine for the second NAND flash memory die.

[0137] Another aspect of this disclosure provides a peak power management (PPM) circuit for managing peak power operation among multiple NAND flash dies in a memory chip. The PPM circuit has PPM contact pads maintained at a common potential between a PPM circuit disposed on a first NAND flash die and a PPM circuit disposed on a second NAND flash die. The PPM circuit is configured to: detect the potential of the PPM contact pad at a first moment during a first peak power check (PPC) routine for a first NAND memory die; if the detected potential is at a first voltage level at the first moment, drive the potential of the PPM contact pad to a second voltage level, wherein the second voltage level is lower than the first voltage level; cause the first NAND memory die to wait for a first delay period; determine at a second moment during the first PPC routine for the first NAND memory die whether there is a pause signal in the potential of the PPM contact pad, wherein the second moment is later than the first moment; if no pause signal is detected at the second moment, generate a pause signal in the potential of the PPM contact pad to pause a second PPC routine for the second NAND memory die; cause the first NAND memory die to perform a first peak power operation; and after the first NAND memory die completes the first peak power operation, generate a recovery signal in the potential of the PPM contact pad to resume the second PPC routine for the second NAND memory die.

[0138] The foregoing description of specific embodiments will thus fully reveal the general nature of this disclosure, enabling others to readily modify and / or adapt them to various applications, such as the specific embodiments, by applying knowledge of the art without departing from the general concept of this disclosure, without excessive experimentation. Therefore, based on the disclosure and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for descriptive rather than restrictive purposes, and that the terminology or terminology of this specification should be interpreted by those skilled in the art in light of the disclosure and guidance.

[0139] Embodiments of this disclosure have been described above using functional building blocks that illustrate implementations of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternating boundaries can be defined as long as the specific functions and their relationships are properly performed.

[0140] The Summary and Abstract sections may set forth one or more, but not all, exemplary embodiments of this disclosure as conceived by the inventors, and are therefore not intended to limit this disclosure and the appended claims in any way.

[0141] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A peak power management (PPM) method for multiple memory dies, characterized in that, The plurality of memory dies includes a first memory die and a second memory die. The first memory die includes a first PPM circuit with a first PPM contact pad, and the second memory die includes a second PPM circuit with a second PPM contact pad. The first PPM contact pad and the second PPM contact pad are electrically connected so that the first PPM contact pad and the second PPM contact pad have a common potential. The method includes: Before the first peak power operation during the execution of the first peak power check routine of the first memory die, a pause signal is generated in the potential; wherein the pause signal is used to pause the second peak power check routine of the second memory die; After the first memory die completes the first peak power operation, a recovery signal is generated in the potential; wherein the recovery signal is used to recover the second peak power check routine.

2. The method according to claim 1, characterized in that, The step of generating a pause signal in the potential includes generating a pulse in the potential.

3. The method according to claim 2, characterized in that, The pulse is a positive pulse.

4. The method according to claim 2, characterized in that, The pulse has a pulse width in the range of 0.1 μS to 10 μS.

5. The method according to claim 1, characterized in that, Generating a recovery signal in the potential includes: The potential is driven from a second voltage level to a first voltage level, generating a rising edge of the potential; wherein the second voltage level is lower than the first voltage level.

6. The method according to claim 1, characterized in that, The method further includes: The potential is driven from a first voltage level to a second voltage level, generating a falling edge of the potential; wherein the second voltage level is lower than the first voltage level.

7. The method according to claim 6, characterized in that, The pause signal includes the falling edge of the potential.

8. The method according to claim 1, characterized in that, The method further includes: Before generating the pause signal, the first memory die waits for a first delay period; wherein the first delay period is different from any delay period during the second peak power check routine.

9. The method according to claim 1, characterized in that, The method further includes: Before performing the first peak power operation, the first memory die waits for a second delay period.

10. A peak power management (PPM) method for multiple memory dies, characterized in that, The plurality of memory dies includes a first memory die and a second memory die. The first memory die includes a first PPM circuit with a first PPM contact pad, and the second memory die includes a second PPM circuit with a second PPM contact pad. The first PPM contact pad and the second PPM contact pad are electrically connected so that the first PPM contact pad and the second PPM contact pad have a common potential. The method includes: When the potential is at the first voltage level, the first peak power check routine of the first memory die is started; At a first moment after the start of the first peak power check routine, the potential is driven to a second voltage level; wherein the second voltage level is lower than the first voltage level; After the potential is driven to the second voltage level, the first memory die waits for a first delay period. At a second time after the first time, a pause signal is generated in the potential; The first memory die performs a first peak power operation; At the fifth moment after the first memory die has completed the first peak power operation, a recovery signal is generated in the potential.

11. The method according to claim 10, characterized in that, Each of the memory dies has a different first delay period.

12. The method according to claim 10, characterized in that, The step of generating a pause signal in the potential includes generating a pulse in the potential.

13. The method according to claim 12, characterized in that, The pulse has a pulse width in the range of 0.1 μS to 10 μS.

14. The method according to claim 10, characterized in that, The generation of the recovery signal in the potential includes: The potential is driven to the first voltage level; wherein the recovery signal includes the rising edge of the potential.

15. The method according to claim 10, characterized in that, The method further includes: At a third time after the first time and before the second time, the second peak power check routine of the second memory die begins; When the potential is detected to be at the second voltage level, the second peak power check routine is paused. At the fifth moment, in response to the recovery signal, the second peak power check routine is resumed.

16. The method according to claim 15, characterized in that, The method further includes: After the first moment and before the second moment, the third peak power check routine of the third memory die begins; When the potential is detected to be at the second voltage level, the third peak power check routine is paused. At the fifth moment, in response to the recovery signal, the second peak power check routine and the third peak power check routine are simultaneously recovered.

17. The method according to claim 10, characterized in that, The method further includes: When the first peak power check routine begins, the second peak power check routine for the second memory die begins. After driving the potential to the second voltage level, the second memory die waits for a first delay period; wherein the first delay period of the second memory die is longer than the first delay period of the first memory die; At the second moment, in response to the pause signal, the second peak power check routine is paused; At the fifth moment, in response to the recovery signal, the second peak power check routine is resumed.

18. The method according to claim 17, characterized in that, The method further includes: At the sixth moment after resuming the second peak power check routine, the potential is driven to the second voltage level; The second memory die awaits the second delay period; At the fourth time point following the sixth time point, the pause signal is generated in the potential. The second memory die performs a second peak power operation; After the second storage die completes the second peak power operation, a recovery signal is generated in the potential.

19. The method according to claim 17, characterized in that, The method further includes: When the first peak power check routine is started, the third peak power check routine for the third memory die is started; After driving the potential to the second voltage level, the third memory die waits for a first delay period; wherein the first delay period of the third memory die is longer than the first delay period of the first memory die; At the second moment, in response to the pause signal, the third peak power check routine is paused; At the fifth moment, in response to the recovery signal, the second peak power check routine and the third peak power check routine are simultaneously recovered.

20. The method according to claim 10, characterized in that, The method further includes: After the second time point and before the fifth time point, the second peak power check routine of the second memory die is started; When the potential is detected to be at the second voltage level, the second peak power check routine is paused. At the fifth moment, in response to the recovery signal, the second peak power check routine is resumed.

21. A peak power management (PPM) circuit for managing peak power operation among multiple memory dies in a memory chip, characterized in that, The PPM circuit includes: PPM contact pads maintain a common potential between the PPM circuitry disposed on the first memory die and the PPM circuitry disposed on the second memory die. The PPM circuit is configured as follows: When the potential is at the first voltage level, the first peak power check routine of the first memory die is started; At a first moment after the start of the first peak power check routine, the potential is driven to a second voltage level; wherein the second voltage level is lower than the first voltage level; After the potential is driven to the second voltage level, the first memory die waits for a first delay period. At a second time after the first time, a pause signal is generated in the potential; The first memory die performs a first peak power operation; At the fifth moment after the first memory die has completed the first peak power operation, a recovery signal is generated in the potential.

22. The PPM circuit according to claim 21, characterized in that, Each of the memory dies has a different first delay period.

23. The PPM circuit according to claim 21, characterized in that, The PPM circuit is specifically configured to generate pulses in the potential.

24. The PPM circuit according to claim 23, characterized in that, The pulse has a pulse width in the range of 0.1 μS to 10 μS.

25. The PPM circuit according to claim 21, characterized in that, The PPM circuit is specifically configured as follows: The potential is driven to the first voltage level; wherein the recovery signal includes the rising edge of the potential.

26. The PPM circuit according to claim 21, characterized in that, The PPM circuit is also configured to: At a third time after the first time and before the second time, the second peak power check routine of the second memory die begins; When the potential is detected to be at the second voltage level, the second peak power check routine is paused. At the fifth moment, in response to the recovery signal, the second peak power check routine is resumed.

27. The PPM circuit according to claim 26, characterized in that, The PPM circuit is also configured to: After the first moment and before the second moment, the third peak power check routine of the third memory die begins; When the potential is detected to be at the second voltage level, the third peak power check routine is paused. At the fifth moment, in response to the recovery signal, the second peak power check routine and the third peak power check routine are simultaneously recovered.

28. The PPM circuit according to claim 21, characterized in that, The PPM circuit is also configured to: When the first peak power check routine begins, the second peak power check routine for the second memory die begins. After driving the potential to the second voltage level, the second memory die waits for a first delay period; wherein the first delay period of the second memory die is longer than the first delay period of the first memory die; At the second moment, in response to the pause signal, the second peak power check routine is paused; At the fifth moment, in response to the recovery signal, the second peak power check routine is resumed.

29. The PPM circuit according to claim 28, characterized in that, The PPM circuit is also configured to: At the sixth moment after resuming the second peak power check routine, the potential is driven to the second voltage level; The second memory die awaits the second delay period; At the fourth time point following the sixth time point, the pause signal is generated in the potential. The second memory die performs a second peak power operation; After the second storage die completes the second peak power operation, a recovery signal is generated in the potential.

30. The PPM circuit according to claim 28, characterized in that, The PPM circuit is also configured to: When the first peak power check routine is started, the third peak power check routine for the third memory die is started; After driving the potential to the second voltage level, the third memory die waits for a first delay period; wherein the first delay period of the third memory die is longer than the first delay period of the first memory die; At the second moment, in response to the pause signal, the third peak power check routine is paused; At the fifth moment, in response to the recovery signal, the second peak power check routine and the third peak power check routine are simultaneously recovered.

31. The PPM circuit according to claim 21, characterized in that, The PPM circuit is also configured to: After the second time point and before the fifth time point, the second peak power check routine of the second memory die is started; When the potential is detected to be at the second voltage level, the second peak power check routine is paused. At the fifth moment, in response to the recovery signal, the second peak power check routine is resumed.

32. The PPM circuit according to claim 21, characterized in that, The PPM circuit also includes: A first pull-up driver, the first pull-up driver being electrically connected to a first power supply and a first end of a PPM resistor; The second pull-up driver is electrically connected to the second power supply and the second end of the PPM resistor; A pull-down driver electrically connected to the second end of the PPM resistor, wherein the PPM contact pad is connected to the second end of the PPM resistor.

33. The PPM circuit according to claim 32, characterized in that, The PPM circuit also includes: A comparator having a first input terminal electrically connected to a reference voltage and a second input terminal electrically connected to the PPM contact pad.

34. The PPM circuit according to claim 33, characterized in that, When the pull-down driver is off, the potential of the PPM contact pad is higher than the reference voltage, and when the pull-down driver is on, the potential of the PPM contact pad is lower than the reference voltage.

35. The PPM circuit according to claim 21, characterized in that, The PPM contact pads of the PPM circuit on the first memory die are electrically connected to the PPM contact pads of the PPM circuit on the second memory die via a die-to-die connection.

36. The PPM circuit according to claim 35, characterized in that, The die-to-die connection includes metal interconnects formed by flip chip bonding, die-to-die bonding, or wire bonding.

37. A peak power management (PPM) system, characterized in that, The PPM system includes: First memory die and second memory die; The PPM circuit according to any one of claims 21-36 is disposed on the first memory die; The PPM circuit according to any one of claims 21-36 is disposed on the second memory die. Each of the PPM circuits has a PPM contact pad that maintains a common potential between the first memory die and the second memory die.

38. The PPM system according to claim 37, characterized in that, The PPM system also includes: A host controller, connected to the first memory die and the second memory die, is configured to control the first memory die and the second memory die.

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