Wafer image chip cutting lane automatic positioning method

By combining template matching and region growing algorithms with grayscale thresholding algorithms, the positioning problem of dicing channels for irregularly shaped wafers was solved, achieving high-precision wafer dicing and improving the dicing yield.

CN115423864BActive Publication Date: 2026-06-12BEIJING UNIV OF TECH
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
BEIJING UNIV OF TECH
Filing Date
2022-07-26
Publication Date
2026-06-12

AI Technical Summary

⚠Technical Problem

Existing technologies struggle to precisely position irregularly shaped and rough-edged wafer dicing tracks during the cutting process, resulting in large cutting errors and impacting the yield rate.

⚗Method used

Coarse localization is achieved by using template matching and region growing algorithms, and fine localization is achieved by combining gray value thresholding algorithms based on the differences in gray value distribution between the inner and outer regions of the chip. Wafer dicing channels are located by using the edge lines of the inner regions of the chip.

🎯Benefits of technology

It improves the positioning accuracy of images of irregularly shaped and rough-edged wafers, expands the scope of application, and ensures the accuracy and efficiency of the dicing process.

✦ Generated by Eureka AI based on patent content.

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Abstract

The present application relates to a wafer image chip cutting path automatic positioning method, a wafer is fixed in a full-automatic wafer cutting system, and the chip shape in the wafer is a rounded square. The method first coarsely positions the inner region edge position of each chip in the wafer through a template matching algorithm and an image region growing algorithm, then finely positions the inner region edge position of the chip through a gray value threshold algorithm based on the distribution difference of the gray value of the pixel points in the inner and outer regions of the chip to obtain the inner region edge point coordinates of the chip, and then the inner region edge line of each column of chips in the wafer is obtained by straight line fitting from the edge points, so as to position the wafer cutting path. For the wafer, the method can effectively solve the problem of large positioning error of the wafer cutting path, and effectively improve the positioning accuracy.
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