Method for forming a cis device
By using a bottom anti-reflective layer and photoresist technology during the formation of CIS devices, the height difference between the nitride layers in the pixel area and the logic area is eliminated, the problem of improper polishing is solved, and the device yield is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUALI MICROELECTRONICS CORP
- Filing Date
- 2022-08-29
- Publication Date
- 2026-05-29
AI Technical Summary
During the formation of CIS devices, the height difference of the nitride layer between the pixel area and the logic area can lead to improper polishing, which may result in over-polishing or under-polishing, affecting device quality and yield.
By forming a bottom anti-reflective layer in the pixel area and the logic area, and forming photoresist on the bottom anti-reflective layer in the logic area, the bottom anti-reflective layer in the pixel area is etched to make the nitride layer flush, eliminating height differences and avoiding improper grinding.
It effectively eliminates the height difference of the nitride layer, avoids over-grinding or under-grinding, improves the yield of devices, and reduces the occurrence of defects.
Smart Images
Figure CN115425037B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming a CIS device. Background Technology
[0002] In the formation of CIS, CIS is generally divided into pixel area and logic area. In order to meet the filling effect of subsequent processes, shallow trench isolation (STI) of pixel area requires a small aspect ratio. Therefore, the STI depth of pixel area needs to be reduced compared with logic area. So two STI etchings are required to form STI of pixel area and STI of logic area with different depths.
[0003] Please refer to Figure 1 A substrate 110 is provided, along with an oxide layer 120 and a nitride layer 130 sequentially disposed on the substrate 110. The oxide layer 120 has a thickness of 90 angstroms, and the nitride layer 130 has a thickness of 810 angstroms. The substrate 110 is divided into adjacent pixel regions 110A and logic regions 110B. Simultaneously, the substrate 110 of the pixel regions 110A and the substrate 110 of the logic regions 110A are etched to form a first shallow trench 140 within the substrate 110 of the pixel regions 110A and a second shallow trench 150 within the substrate 110 of the logic regions 110B. The depth of both the first shallow trench 140 and the second shallow trench 150 is 1500 angstroms. Next, please refer to... Figure 2 A layer of photoresist 160 is formed on the surface of the nitride layer 130 in pixel region 110A and within the first shallow trench 140 to protect the nitride layer 130 in pixel region 110A from etching. Please refer to... Figure 2 and Figure 3 The second shallow trench 150 is etched further, increasing its depth to 3000 angstroms. Then, the surface of the nitride layer 130 in pixel region 110A and the photoresist 160 within the first shallow trench 140 are removed. During the etching of the second shallow trench 150, the nitride layer 130 in logic region 110B is partially etched away, with approximately 170 angstroms remaining. This means that only 640 angstroms of the nitride layer 130 in logic region 110B remain. Therefore, a height difference exists between the nitride layer 130 in pixel region 110A and the nitride layer 130 in logic region 110B. It is even possible that the thickness of the nitride layer 130 in logic region 110B etched away increases, further increasing the height difference between the nitride layer 130 in pixel region 110A and the nitride layer 130 in logic region 110B. Next, please refer to... Figure 4Silicon oxide 170 is filled into the first shallow trench 140 and the second shallow trench 150 to form the first shallow trench isolation structure 141 and the second shallow trench isolation structure 151, respectively. The silicon oxide 170 covers the surface of the nitride layer 130 of the pixel region 110A and the nitride layer 130 of the logic region 110B. Then, the surface silicon oxide and nitride layer 130 covering the nitride layer 130 of the pixel region 110A and the nitride layer 130 of the logic region 110B are ground to remove the nitride layer 130 of the pixel region 110A and the logic region 110B, exposing the oxide layer 120 of the pixel region 110A and the logic region 110B.
[0004] During the polishing process of the nitride layer 130, if the polishing amount is insufficient, the nitride layer 130 will not be polished cleanly, causing a short circuit in the device. If the polishing amount is increased to polish the nitride layer 130 cleanly, it will cause partial removal of the second shallow trench isolation structure 151, such as... Figure 5 This results in the surface of the second shallow trench isolation structure 151 being lower than the surface of the substrate 110 of the logic region 110B, meaning the surface of the second shallow trench isolation structure 151 is lower than the surface of AA, thus affecting subsequent polysilicon gate processes and causing device defects. In summary, if there is a height difference between the nitride layer 130 of the pixel region 110A and the nitride layer 130 of the logic region 110B, it may lead to device defects. Summary of the Invention
[0005] The purpose of this invention is to provide a method for forming a CIS device, which can eliminate the height difference between the nitride layer in the pixel area and the nitride layer in the logic area before grinding the nitride layer, so that over-grinding or under-grinding will not occur when grinding the nitride layer in the pixel area and the nitride layer in the logic area.
[0006] To achieve the above objectives, the present invention provides a method for forming a CIS device, comprising:
[0007] A substrate is provided, and an oxide layer and a nitride layer are sequentially located on the substrate. The substrate is divided into adjacent pixel areas and logic areas. The oxide layer and the nitride layer are both located on the substrate of the pixel areas and the substrate of the logic areas.
[0008] The nitride layer, oxide layer and substrate are etched to form a first shallow trench and a second shallow trench in the substrate of the pixel area and the substrate of the logic area, respectively;
[0009] The bottom of the second shallow trench is etched to increase the depth of the second shallow trench to form a third shallow trench. At the same time, the surface of the nitride layer of the logic region is partially etched, and a height difference is formed between the nitride layer of the pixel region and the nitride layer of the logic region.
[0010] A bottom anti-reflective layer is formed on the surface of the nitride layer in the pixel area and on the surface of the nitride layer in the logic area. The bottom anti-reflective layer fills both the first shallow trench and the third shallow trench.
[0011] Photoresist is formed on the bottom anti-reflection layer of the logic region;
[0012] The bottom anti-reflective layer of the pixel area is etched to expose the nitride layer of the pixel area;
[0013] The silicon nitride in the pixel area is etched so that the remaining nitride layer in the pixel area is flush with the thickness of the nitride layer in the logic area.
[0014] Optionally, in the method for forming the CIS device, after etching the silicon nitride in the pixel area so that the thickness of the remaining nitride layer in the pixel area is flush with the thickness of the nitride layer in the logic area, the method further includes: removing the photoresist and the remaining bottom anti-reflective layer.
[0015] Optionally, in the method for forming the CIS device, O2 is used to remove the photoresist and the remaining bottom anti-reflective layer.
[0016] Optionally, in the method for forming the CIS device, after removing the photoresist and the remaining bottom anti-reflective layer, the method further includes:
[0017] Silicon oxide is filled into the first shallow trench and the third shallow trench to form a first shallow trench isolation structure and a second shallow trench isolation structure, respectively; and
[0018] The remaining nitride layer in the pixel area and the remaining nitride layer in the logic area are ground to expose the surface of the oxide layer in the pixel area and the surface of the oxide layer in the logic area.
[0019] Optionally, in the method for forming the CIS device, after forming photoresist on the bottom anti-reflective layer of the logic region, the method further includes: hardening the photoresist and all the bottom anti-reflective layers.
[0020] Optionally, in the method for forming the CIS device, HBr is used to harden the photoresist and all of the bottom anti-reflective layers.
[0021] Optionally, in the method for forming the CIS device, after etching the bottom anti-reflective layer of the pixel area to expose the nitride layer of the pixel area, the method further includes: hardening the bottom anti-reflective layer in the first shallow trench.
[0022] Optionally, in the method for forming the CIS device, the depth of the first shallow trench and the depth of the second shallow trench are both 1400 angstroms to 1600 angstroms.
[0023] Optionally, in the method for forming the CIS device, the depth of the third shallow trench after the depth is increased is 2900 angstroms to 3100 angstroms.
[0024] Optionally, in the method for forming the CIS device, CF4 or CHF3 is used to etch the silicon nitride in the pixel area so that the thickness of the remaining nitride layer in the pixel area is flush with the thickness of the nitride layer in the logic area.
[0025] In the method for forming a CIS device provided by the present invention, the height difference between the nitride layer in the pixel area and the nitride layer in the logic area is eliminated before grinding the nitride layer. This prevents over-grinding or under-grinding when grinding the nitride layer in the pixel area and the nitride layer in the logic area, thereby reducing the probability of device defects and improving the device yield. Attached Figure Description
[0026] Figures 1 to 5 This is a schematic diagram of a method for forming a CIS device in the prior art;
[0027] Figure 6 This is a flowchart of a method for forming a CIS device according to an embodiment of the present invention;
[0028] Figures 7 to 14 This is a schematic diagram of a method for forming a CIS device in the prior art;
[0029] In the diagram: 110-substrate, 110A-pixel area, 110B-logic area, 120-silicon oxide layer, 130-silicon nitride layer, 140-first shallow trench, 141-first shallow trench isolation structure, 150-second shallow trench, 151-second shallow trench isolation structure, 160-photoresist, 170-silicon oxide, 210-substrate, 210A-pixel area, 210B-logic area, 220-oxide layer, 230-nitride layer, 240-first shallow trench, 241-first shallow trench isolation structure, 250-second shallow trench, 250A-third shallow trench, 251-second shallow trench isolation structure, 260-first photoresist layer, 270-bottom anti-reflective layer, 280-second photoresist layer. Detailed Implementation
[0030] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0031] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.
[0032] Please refer to Figure 6 The present invention provides a method for forming a CIS device, comprising:
[0033] S11: Provides a substrate and an oxide layer and a nitride layer sequentially located on the substrate. The substrate is divided into adjacent pixel areas and logic areas. The oxide layer and the nitride layer are both located on the substrate of the pixel areas and the substrate of the logic areas.
[0034] S12: Etch the nitride layer, oxide layer and substrate to form a first shallow trench and a second shallow trench in the substrate of the pixel area and the substrate of the logic area, respectively.
[0035] S13: Etch the bottom of the second shallow trench to increase the depth of the second shallow trench to form the third shallow trench. At the same time, the surface of the nitride layer of the logic region is partially etched, and the nitride layer of the pixel region and the nitride layer of the logic region form a height difference.
[0036] S14: A bottom anti-reflection layer is formed on the surface of the nitride layer in the pixel area and the surface of the nitride layer in the logic area. The bottom anti-reflection layer fills the first shallow trench and the third shallow trench at the same time.
[0037] S15: Form photoresist on the bottom anti-reflection layer of the logic region;
[0038] S16: Etch the bottom anti-reflection layer of the pixel area to expose the nitride layer of the pixel area; and
[0039] S17: Etch the silicon nitride in the pixel area so that the remaining nitride layer in the pixel area is flush with the thickness of the nitride layer in the logic area.
[0040] Please refer to Figure 7First, a substrate 210 is provided, along with an oxide layer 220 and a nitride layer 230 sequentially located on the substrate 210. The substrate 210 can be a wafer, the oxide layer 220 can be silicon oxide, and the nitride layer 230 can be silicon nitride. The substrate 210 is divided into adjacent pixel regions 210A and logic regions 210B. Simultaneously, the substrate 210 of pixel region 210A and the substrate 210 of logic region 210B are etched to form a first shallow trench 240 in the substrate 210 of pixel region 210A and a second shallow trench 250 in the substrate 210 of logic region 210B. The depth of both the first shallow trench 240 and the second shallow trench 250 is 1400 angstroms to 1600 angstroms, for example, 1500 angstroms.
[0041] Next, please refer to Figure 8 and Figure 9 A first photoresist layer 260 is formed on the surface of the nitride layer 230 in pixel region 210A. Simultaneously, the first photoresist layer 260 fills the first shallow trench 240, shielding the surface of the nitride layer 230 in pixel region 210A to protect it from etching. The second shallow trench 250 is then etched, increasing its depth to form a third shallow trench 250A, becoming 2900 angstroms to 3100 angstroms, for example, 3000 angstroms. Finally, the first photoresist layer 260 is removed. While etching the second shallow trench 250, the nitride layer 230 of the logic region 210B is partially etched away, with a thickness of about 170 angstroms. This means that only 640 angstroms of the nitride layer 230 of 210B remain. As a result, a height difference appears between the nitride layer 230 of pixel region 210A and the nitride layer 230 of 210B.
[0042] Next, please refer to Figure 10 A bottom anti-reflective layer 270 is formed, covering the surface of the nitride layer 230 of pixel region 210A and the surface of the nitride layer 230 of logic region 210B. At this time, the bottom anti-reflective layer 270 fills the first shallow trench 240 and the second shallow trench 250. Next, a second photoresist layer 280 is formed on the surface of the bottom anti-reflective layer 270 of logic region 210B, covering the bottom anti-reflective layer 270. The surface of the bottom anti-reflective layer 270 is hardened using HBr plasma, and the surface bottom anti-reflective layer (Barc) is etched using CF4. The HBr plasma flow rate is 50 sccm~150 sccm, the TCP power is 800 W~1200 W, and the hardening time for the bottom anti-reflective layer 270 is 5 s~10 s.
[0043] Next, please refer to Figure 11The bottom anti-reflective layer 270 on the surface of the nitride layer 230 of pixel region 210A is removed to expose the surface of the nitride layer 230 of pixel region 210A. Specifically, the bottom anti-reflective layer 270 on the surface of the nitride layer 230 of pixel region 210A is etched using CF4. The CF4 flow rate is 50 sccm ~ 100 sccm, the TCP power is 300 W ~ 400 W, the Bias Power is 100 V ~ 200 V, and the etching time is 15 s ~ 20 s. The bottom anti-reflective layer 270 in the first shallow trench 240 is cured to prevent excessive etching of the bottom anti-reflective layer 270 in the first shallow trench 240 during subsequent etching of the nitride layer 230, which would affect the morphology of the first shallow trench 240. The curing process uses HBr plasma. Specifically, the HBr plasma flow rate is 50 sccm~150 sccm, the TCP power is 800 W~1200 W, and the curing time is 5s~10s.
[0044] Next, please refer to Figure 12 Subsequently, the nitride layer 230 of pixel region 210A is partially etched using CF4 or CHF3, so that the nitride layer 230 of pixel region 210A after etching has the same thickness as the nitride layer 230 of logic region 210B. In other words, the nitride layer 230 of pixel region 210A is flush with the nitride layer 230 of logic region 210B after etching. If CF4 is used, the flow rate is 30 sccm ~ 50 sccm; if CHF3 is used, the flow rate is 50 sccm ~ 100 sccm. Regardless of whether CF4 or CHF3 is used, the TCP power is 300 W ~ 400 W, the Bias Power is 100 V ~ 200 V, and the etching time is 10 s ~ 15 s.
[0045] Next, please refer to Figure 12 and Figure 13 Finally, the remaining bottom anti-reflective layer 270 and the second photoresist layer 280 are removed. Specifically, O2 can be used to remove the remaining bottom anti-reflective layer 270 and the second photoresist layer 280.
[0046] Next, please refer to Figure 13 and Figure 14 Silicon oxide is filled into the first shallow trench 240 and the third shallow trench 250A to form the first shallow trench isolation structure 241 and the second shallow trench isolation structure 242, respectively. The silicon oxide covers the surface of the nitride layer 230 of the pixel region 210A and the nitride layer 230 of the logic region 210B. Then, the silicon oxide and the nitride layer 230 of the pixel region 210A and the nitride layer 230 of the logic region 210B are ground to remove the nitride layer 230 of the pixel region 210A and the nitride layer 230 of the logic region 210B.
[0047] In summary, in the method for forming a CIS device provided in this embodiment of the invention, the height difference between the nitride layer in the pixel area and the nitride layer in the logic area is eliminated before grinding the nitride layer. This prevents over-grinding or under-grinding when grinding the nitride layer in the pixel area and the nitride layer in the logic area, thereby reducing the probability of device defects and improving the device yield.
[0048] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A method for forming a CIS device, characterized in that, include: A substrate is provided, and an oxide layer and a nitride layer are sequentially located on the substrate. The substrate is divided into adjacent pixel areas and logic areas. The oxide layer and the nitride layer are both located on the substrate of the pixel areas and the substrate of the logic areas. The nitride layer, the oxide layer, and the substrate are etched to form a first shallow trench and a second shallow trench in the substrate of the pixel region and the substrate of the logic region, respectively. The bottom of the second shallow trench is etched to increase the depth of the second shallow trench to form a third shallow trench. At the same time, the surface of the nitride layer of the logic region is partially etched, and a height difference is formed between the nitride layer of the pixel region and the nitride layer of the logic region. A bottom anti-reflective layer is formed on the surface of the nitride layer in the pixel area and on the surface of the nitride layer in the logic area. The bottom anti-reflective layer fills both the first shallow trench and the third shallow trench. Photoresist is formed on the bottom anti-reflection layer of the logic region; The bottom anti-reflective layer of the pixel area is etched to expose the nitride layer of the pixel area; as well as The silicon nitride in the pixel area is etched so that the remaining nitride layer in the pixel area is flush with the thickness of the nitride layer in the logic area.
2. The method for forming a CIS device as described in claim 1, characterized in that, After etching the silicon nitride in the pixel area so that the remaining nitride layer in the pixel area is flush with the thickness of the nitride layer in the logic area, the process further includes removing the photoresist and the remaining bottom anti-reflective layer.
3. The method for forming a CIS device as described in claim 2, characterized in that, The photoresist and the remaining bottom anti-reflective layer were removed using O2.
4. The method for forming a CIS device as described in claim 2, characterized in that, After removing the photoresist and the remaining bottom anti-reflective layer, the process further includes: Silicon oxide is filled into the first shallow trench and the third shallow trench to form a first shallow trench isolation structure and a second shallow trench isolation structure, respectively; and The remaining nitride layer in the pixel area and the remaining nitride layer in the logic area are ground to expose the surface of the oxide layer in the pixel area and the surface of the oxide layer in the logic area.
5. The method for forming a CIS device as described in claim 2, characterized in that, After forming photoresist on the bottom anti-reflective layer of the logic region, the process further includes: hardening the photoresist and all of the bottom anti-reflective layers.
6. The method for forming a CIS device as described in claim 5, characterized in that, The photoresist and all of the bottom anti-reflective layers were hardened using HBr.
7. The method for forming a CIS device as described in claim 1, characterized in that, After etching the bottom anti-reflective layer of the pixel area to expose the nitride layer of the pixel area, the method further includes: hardening the bottom anti-reflective layer within the first shallow trench.
8. The method for forming a CIS device as described in claim 1, characterized in that, The depth of the first shallow trench and the depth of the second shallow trench are both 1400 angstroms to 1600 angstroms.
9. The method for forming a CIS device as described in claim 1, characterized in that, The depth of the third shallow trench after the depth was increased is 2900 angstroms to 3100 angstroms.
10. The method for forming a CIS device as described in claim 1, characterized in that, The silicon nitride in the pixel area is etched using CF4 or CHF3 so that the remaining nitride layer in the pixel area is flush with the thickness of the nitride layer in the logic area.