Display panel and electronic device

Abstract

The application discloses a display panel and an electronic device. The display panel has a display area and a non-display area surrounding the display area at least partially. The display panel comprises: a plurality of signal lines extending along a first direction, the signal lines being located in the display area; the display area comprises a first display area and a second display area arranged adjacently along a second direction; the display area has a first side extending along the first direction, the first display area being located between the first side and the second display area; a first signal connection line extending through the display area along a first non-display area on one side of the display area to a second non-display area on the other side of the display area, wherein the first non-display area comprises a binding area; a second signal connection line extending along the second non-display area, one end of the second signal connection line being connected to the first signal connection line, and the other end of the second signal connection line being connected to any one of the signal lines in the first display area. The technical scheme can reduce the frame width of the non-display area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic equipment, and more particularly to a display panel and an electronic device. BACKGROUND

[0002] With the continuous progress of science and technology, more and more electronic devices with display function are widely used in people's daily life and work, which brings great convenience to people's daily life and work and becomes an important tool indispensable to people's daily life and work.

[0003] The main component of electronic devices to realize display function is a display panel. The display panel includes a display area and a frame area. The pixel structure for image display is arranged in the display area, and the layout of the trace and the display driving chip are arranged in the frame area.

[0004] In the existing display panel, with the continuous improvement of resolution, the signal lines connected to the non-display area in the display area are more and more, resulting in a larger frame area width. SUMMARY

[0005] Therefore, the present application provides a display panel and an electronic device, and the scheme is as follows:

[0006] A display panel, the display panel has a display area and a non-display area surrounding the display area at least partially, and the display panel comprises:

[0007] A plurality of signal lines extending along a first direction, the signal lines are located in the display area;

[0008] The display area includes a first display area and a second display area arranged adjacent along a second direction; the display area has a first side extending along the first direction, and the first display area is located between the first side and the second display area;

[0009] A first signal connection line extending through the display area along a first non-display area on one side of the display area to a second non-display area on the other side of the display area, wherein the first non-display area includes a binding area;

[0010] A second signal connection line extending along the second non-display area, one end of the second signal connection line is connected to the first signal connection line, and the other end of the second signal connection line is connected to any signal line in the first display area.

[0011] The present application also provides an electronic device comprising the above display panel.

[0012] As can be known from the above description, in the display panel and the electronic device provided by the technical scheme, the signal lines in the first display area are connected to the first signal connection lines in the second display area through the second signal connection lines in the second non-display area, so that at least part of the signal lines in the first display area can be led out from the second display area to the first non-display area, thereby saving the wiring space of the area opposite to the first display area in the first non-display area and at least reducing the frame width of the display panel in the area. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the related art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of the provided drawings.

[0014] The structures, proportions, sizes, etc. shown in the drawings of the present specification are only used to cooperate with the content disclosed in the present specification, to be understood and read by those skilled in the art, and do not define the limiting conditions for the implementation of the present application, so they do not have technical significance. Any modification of structure, change of proportion relationship or adjustment of size, which does not affect the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0015] Figure 1 FIG. 1 is a structural schematic diagram of a display panel;

[0016] Figure 2 FIG. 2 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0017] Figure 3 FIG. 3 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0018] Figure 4 FIG. 4 is a circuit diagram of a display pixel structure in the display panel shown in FIG. 1; Figure 3

[0019] FIG. 5 is a circuit diagram of a pseudo-pixel structure in the display panel shown in FIG. 1; Figure 5 Figure 3 FIG. 6 is a partial enlarged view of the display panel shown in FIG. 1;

[0020] Figure 6a Figure 3 FIG. 7 is a layout schematic diagram of a conductive hole for connecting a scanning circuit and a signal line in a display area in a conventional display panel;

[0021] Figure 6b FIG. 8 is a layout schematic diagram of a conductive hole for connecting a scanning circuit and a signal line in a display area in a conventional display panel;

[0022] ​​Figure 7 A structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0023] Figure 8 A structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 6; Figure 7 A partial enlarged view of one top corner region of the display panel shown in FIG. 6 is shown in FIG. 7;

[0024] Figure 9 A structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 6; Figure 7 A partial enlarged view of another top corner region of the display panel shown in FIG. 6 is shown in FIG. 8;

[0025] Figure 10 A structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 6; Figure 7 A sectional view of the display panel shown in FIG. 6 is shown in FIG. 9;

[0026] Figure 11 A wiring mode schematic diagram of a display panel provided by an embodiment of the present application in a top corner region is shown in FIG. 10;

[0027] Figure 12 A wiring mode schematic diagram of another display panel provided by an embodiment of the present application in a top corner region is shown in FIG. 11;

[0028] Figure 13 A structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0029] Figure 14 A structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0030] Figure 15 A wiring layout of a display panel provided by an embodiment of the present application in a middle region of a display area is shown in FIG. 12;

[0031] Figure 16 A wiring layout of a display panel provided by an embodiment of the present application in a middle region of a display area is shown in FIG. 12;

[0032] Figure 17 A wiring layout of a display panel provided by an embodiment of the present application in a middle region of a display area is shown in FIG. 12;

[0033] Figure 18 A wiring mode schematic diagram of a display panel provided by an embodiment of the present application in a third edge adjacent region is shown in FIG. 13;

[0034] Figure 19 A structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0035] Figure 20 A structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 6; Figure 19 A partial enlarged view of one top corner region of the display panel shown in FIG. 6 is shown in FIG. 7;

[0036] Figure 21 A structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 6;

[0037] Figure 22 A structure schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 6;Figure 21 A partial enlarged view of the display panel shown;

[0038] Figure 23 for Figure 21 A cross-sectional view of the display panel in the first non-display area;

[0039] Figure 24 A schematic diagram of the wiring principle in a display panel provided in an embodiment of the present application;

[0040] Figure 25 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0041] Figure 26 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0043] refer to Figure 1 As shown, Figure 1 The structure diagram of a display panel includes a display area AA and a non-display area BB. The display area AA is provided with a pixel structure for image display ( Figure 1 The non-display area BB is provided with a scanning circuit 103. The pixel structure displays an image based on a scanning signal provided by the scanning circuit 103 and a setting signal provided by the signal line 101. The signal line 101 may be a data line for providing a data signal to the pixel structure.

[0044] The scanning circuit 103 and the signal line 101 at one end facing the first non-display area BB1 need to be connected to the fan-out line 102 so as to be connected to the binding area located in the first non-display area BB1. Figure 1 As shown, in the corner area of ​​the first non-display area BB1 close to the display area AA, the scanning circuit 103 and the fan-out line 102 of the signal line 101 need to be arranged at the same time, resulting in a larger frame width in the corner area.

[0045] Moreover, the four top corners of the display area AA in the current display panel are mostly set with R angles (such as Figure 1In the figure, the top corner area is a convex arc. To improve display quality, at the arc-shaped R corner position, the light-emitting elements in the pixel structure need to be arranged in a stepped manner to adapt to the arc-shaped R corner. The scan lines and signal lines connected to these light-emitting elements need to be arranged in the non-display area near the R corner. In addition, the various wiring connected to the light-emitting elements in the middle display area will also occupy a part of the non-display area near the R corner, resulting in a larger border width in this area, making the non-display area BB occupy a larger proportion of the panel.

[0046] To solve the above problems, embodiments of the present application provide a display panel and an electronic device. The display panel has a display area and a non-display area at least partially surrounding the display area. The display panel includes:

[0047] a plurality of signal lines extending along a first direction, the signal lines being located in a display area;

[0048] The display area includes a first display area and a second display area adjacent to each other along the second direction; the display area has a first side extending along the first direction, and the first display area is located between the first side and the second display area;

[0049] a first signal connection line extending along a first non-display area on one side of the display area, through the display area, and to a second non-display area on the other side of the display area, wherein the first non-display area includes a binding area;

[0050] The second signal connection line extends along the second non-display area, one end of the second signal connection line is connected to the first signal connection line, and the other end of the second signal connection line is connected to any signal line in the first display area.

[0051] In the technical solution of the present application, the signal lines in the first display area are connected to the first signal connection lines in the second display area through the second signal connection lines in the second non-display area, so that at least part of the signal lines in the first display area can be led out from the second display area to the first non-display area, thereby saving wiring space in the area opposite to the first non-display area and at least reducing the border width of the display panel in this area.

[0052] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0053] refer to Figure 2 As shown, Figure 2 This is a schematic structural diagram of a display panel provided in an embodiment of the present application. The display panel has a display area AA and a non-display area BB at least partially surrounding the display area AA. The display panel includes:

[0054] A plurality of signal lines 101 extending along a first direction Y, the signal lines 101 being located in the display area AA;

[0055] The display region AA includes a first display region AA1 and a second display region AA2 arranged adjacent along a second direction X; the display region AA has a first side L1 extending along a first direction Y, and the first display region AA1 is located between the first side L1 and the second display region AA2; the second direction X is perpendicular to the first direction Y, and both the first direction Y and the second direction X are parallel to the display panel;

[0056] The first signal connection line 11 extends through the display region AA along a first non-display region BB1 on one side of the display region AA to a second non-display region BB2 on the other side of the display region AA, wherein the first non-display region BB1 includes a binding region 104; the extension direction of the first signal connection line 11 is parallel to the first direction Y;

[0057] The second signal connection line 12 extends along the second non-display region BB2, one end of the second signal connection line 12 is connected to the first signal connection line 11, and the other end of the second signal connection line 12 is connected to the signal line 101 in any one of the first display regions AA1.

[0058] The first signal connection line 11 is connected to the signal line 101 in the second display region AA2 and the fan-out line 102 in the first non-display region BB1, and is led out to the binding region 104 through the fan-out line 102.

[0059] In the embodiment of the present application, the signal line 101 in the first display region AA1 is connected to the first signal connection line 11 in the second display region AA2 through the second signal connection line 12 in the second non-display region BB2, so that at least part of the signal line 101 in the first display region AA1 can be led out from the second display region AA2 to the first non-display region BB1, thereby saving the wiring space of the area opposite to the first display region AA1 in the first non-display region BB1, and at least reducing the frame width of the display panel in the area.

[0060] The top corner of the display region AA of the display panel can be designed as an R corner, and in this case, the end of the first display region AA1 close to the first non-display region BB1 is designed as an R corner with a circular arc shape. Figure 2 The display panel shown can save the wiring space of the area opposite to the first display region AA1 in the first non-display region BB1, so it can save Figure 2 the wiring space of the non-display region near the R corner shown by the lower left dashed oval.

[0061] Obviously, the top corner of the display region AA in the embodiment of the present application is not limited to the design of an R corner, but can also be designed as a rectangle.

[0062] Reference Figures 3-6a shown, Figure 3 is another structural schematic diagram of a display panel provided by the embodiment of the present application,Figure 4 As shown in FIG. 1, a display panel includes a display area AA and a non-display area BB. Figure 3 As shown in FIG. 2, a circuit diagram of a display pixel structure in the display panel is shown. Figure 5 As shown in FIG. 3, a circuit diagram of a pseudo pixel structure in the display panel is shown. Figure 3 As shown in FIG. 4, a partial enlarged view of the display panel is shown. Figure 6a As shown in FIG. 5, a partial enlarged view of the display panel is shown. Figure 3 As shown in FIG. 6, a partial enlarged view of the display panel is shown. As shown in FIG. 7, a partial enlarged view of the display panel is shown.

[0063] As shown in FIG. 8, a partial enlarged view of the display panel is shown. Figure 2 As shown in FIG. 9, a partial enlarged view of the display panel is shown. Figure 3 As shown in FIG. 6, the display area AA has a plurality of display pixel structures P, and each display pixel structure P includes a display pixel circuit 21 and a display light emitting element 22 connected to the display pixel circuit 21. The non-display area BB has a third non-display area BB3 adjacent to the first side L1, and the third non-display area BB3 has a scan circuit 103 connected to the scan line G through a first conductive hole Via1 (structure shown by the dashed circle in FIG. 6) to connect the display pixel circuit 21. The scan circuit 103 and the first side L1 have a plurality of pseudo pixel structures P' arranged in the first direction Y in sequence, and each pseudo pixel structure P' includes a pseudo pixel circuit 21' and a pseudo light emitting element 22'. The first conductive hole Via1 is arranged opposite to the pseudo pixel circuit 21' in a direction perpendicular to the display panel. Figure 6a As shown in FIG. 7, the display area AA has a plurality of display pixel structures P, and each display pixel structure P includes a display pixel circuit 21 and a display light emitting element 22 connected to the display pixel circuit 21. The non-display area BB has a third non-display area BB3 adjacent to the first side L1, and the third non-display area BB3 has a scan circuit 103 connected to the scan line G through a first conductive hole Via1 (structure shown by the dashed circle in FIG. 7) to connect the display pixel circuit 21. The scan circuit 103 and the first side L1 have a plurality of pseudo pixel structures P' arranged in the first direction Y in sequence, and each pseudo pixel structure P' includes a pseudo pixel circuit 21' and a pseudo light emitting element 22'. The first conductive hole Via1 is arranged opposite to the pseudo pixel circuit 21' in a direction perpendicular to the display panel. As shown in FIG. 8, the display area AA has a plurality of display pixel structures P, and each display pixel structure P includes a display pixel circuit 21 and a display light emitting element 22 connected to the display pixel circuit 21. The non-display area BB has a third non-display area BB3 adjacent to the first side L1, and the third non-display area BB3 has a scan circuit 103 connected to the scan line G through a first conductive hole Via1 (structure shown by the dashed circle in FIG. 8) to connect the display pixel circuit 21. The scan circuit 103 and the first side L1 have a plurality of pseudo pixel structures P' arranged in the first direction Y in sequence, and each pseudo pixel structure P' includes a pseudo pixel circuit 21' and a pseudo light emitting element 22'. The first conductive hole Via1 is arranged opposite to the pseudo pixel circuit 21' in a direction perpendicular to the display panel.

[0064] As shown in FIG. 9, the display area AA has a plurality of display pixel structures P, and each display pixel structure P includes a display pixel circuit 21 and a display light emitting element 22 connected to the display pixel circuit 21. The non-display area BB has a third non-display area BB3 adjacent to the first side L1, and the third non-display area BB3 has a scan circuit 103 connected to the scan line G through a first conductive hole Via1 (structure shown by the dashed circle in FIG. 9) to connect the display pixel circuit 21. The scan circuit 103 and the first side L1 have a plurality of pseudo pixel structures P' arranged in the first direction Y in sequence, and each pseudo pixel structure P' includes a pseudo pixel circuit 21' and a pseudo light emitting element 22'. The first conductive hole Via1 is arranged opposite to the pseudo pixel circuit 21' in a direction perpendicular to the display panel. Figure 3 As shown in FIG. 10, the first signal connection line 11, the signal line 101, and the second signal connection line 12 are not shown in FIG. 6.

[0065] The display light emitting element 22 can be an OLED or a micro LED, and the micro LED can be a Mini LED or a Micro LED, etc. The specific implementation of the display light emitting element 22 is not limited in the embodiments of the present application.

[0066] As shown in FIG. 11, a conductive hole layout diagram for connecting the scan circuit and the signal line of the display area in the conventional display panel is shown. Figure 6b As shown in FIG. 12, the scan circuit 103 is located in the third non-display area BB3 adjacent to the first display area AA1 in the second direction X. The third non-display area BB3 has a plurality of pseudo pixel structures P' arranged in the first direction Y in sequence, and each pseudo pixel structure P' is located between the scan circuit 103 and the first display area AA1. In this way, a line changing hole area K needs to be arranged between the scan circuit 103 and the pseudo pixel structure P' to arrange a line changing hole Via1. Figure 6b As shown in FIG. 13, the scan circuit 103 is located in the third non-display area BB3 adjacent to the first display area AA1 in the second direction X. The third non-display area BB3 has a plurality of pseudo pixel structures P' arranged in the first direction Y in sequence, and each pseudo pixel structure P' is located between the scan circuit 103 and the first display area AA1. In this way, a line changing hole area K needs to be arranged between the scan circuit 103 and the pseudo pixel structure P' to arrange a line changing hole Via1. Figure 1 As shown in FIG. 14, the scan circuit 103 is located in the third non-display area BB3 adjacent to the first display area AA1 in the second direction X. The third non-display area BB3 has a plurality of pseudo pixel structures P' arranged in the first direction Y in sequence, and each pseudo pixel structure P' is located between the scan circuit 103 and the first display area AA1. In this way, a line changing hole area K needs to be arranged between the scan circuit 103 and the pseudo pixel structure P' to arrange a line changing hole Via1. Figure 6b As shown in FIG. 15, the scan circuit 103 is located in the third non-display area BB3 adjacent to the first display area AA1 in the second direction X. The third non-display area BB3 has a plurality of pseudo pixel structures P' arranged in the first direction Y in sequence, and each pseudo pixel structure P' is located between the scan circuit 103 and the first display area AA1. In this way, a line changing hole area K needs to be arranged between the scan circuit 103 and the pseudo pixel structure P' to arrange a line changing hole Via1. Figure 6bThe third signal connection line 13 connected with the scan circuit 103 passes through the corresponding via hole Via in the display area AA and is connected with the corresponding wiring to connect with the display pixel circuit 21, so as to provide the display pixel circuit 21 with the scan signal S1 / S2, the reference voltage signal VREF1 / VREF2 and the light emitting control signal Emit.

[0067] In Figure 6b As shown in the figure, the via hole area K is needed to be arranged between the scan circuit 103 and the pseudo pixel structure P' for arranging the via hole Via, which results in a large frame width of the third non-display area BB3.

[0068] In order to reduce the frame width of the third non-display area BB3, in the embodiment of the present application, the via hole Via for connecting the scan circuit 103 and the display pixel circuit 21 is arranged in the area of the pseudo pixel structure P', specifically, in the direction perpendicular to the display panel, the via hole Via and the pseudo pixel circuit 21' in the pseudo pixel structure P' are arranged oppositely, so as to save Figure 6b the via hole area K and reduce the frame width of the third non-display area BB3.

[0069] In the embodiment of the present application, the scan circuit 103 is connected with the display pixel circuit 21 through the corresponding third signal connection line 13, and the scan circuit 103 provides the display pixel circuit 21 with the scan signal S1 / S2, the reference voltage signal VREF1 / VREF2 and the light emitting control signal Emit through the corresponding third signal connection line 13.

[0070] The via hole Via includes the first conductive hole Via1 for connecting the scan circuit 103 with the scan line G, and the first conductive hole Via1 is arranged in the pseudo pixel structure P' between the scan circuit 103 and the scan line G. Figure 6b In the embodiment of the present application, the first conductive hole Via1 for connecting the scan circuit 103 with the scan line G is arranged oppositely with the pseudo pixel circuit 21' in the direction perpendicular to the display panel, and the first conductive hole Via1 is multiplexed with the space layout of the pseudo pixel structure P', so as to reduce the frame width of the third non-display area BB3.

[0071] In the embodiment of the present application, at least one of the via hole Via corresponding to the scan signal S1, the via hole Via corresponding to the scan signal S2, the via hole Via corresponding to the reference voltage signal VREF1, the via hole Via corresponding to the reference voltage signal VREF2 and the via hole Via corresponding to the light emitting control signal Emit of the scan circuit 103 is arranged oppositely with the pseudo pixel circuit 21' in the pseudo pixel structure P'.

[0072] As Figure 4 shown, the display pixel circuit 21 includes a plurality of transistors and a storage capacitor Cst.Figure 4 For example, the 7T1C pixel circuit structure is taken as an example for illustration, which includes 7 pixel transistors T1-T7 and 1 storage capacitor Cst.

[0073] The pixel transistor T3 is a driving transistor, the gate electrode of which is connected to the first node N1, the first electrode of which is connected to the second node N2, and the second electrode of which is connected to the third node N3. The pixel transistor T2 is used for data voltage DATA writing, the gate electrode of which is connected to the scanning signal S2, the first electrode of which is connected to the data voltage DTAT, and the second electrode of which is connected to the second node N2. The pixel transistor T1 is a control transistor, the gate electrode of which inputs the light-emitting control signal Emit, the first electrode of which is connected to the positive power supply voltage PVDD and connected to the first node N1 through the storage capacitor Cst, and the second electrode of which is connected to the second node N2. The pixel transistor T4 is used for voltage reset of the first node N1, the gate electrode of which is connected to the scanning signal S1, the first electrode of which is connected to the reference voltage VREF1, and the second electrode of which is connected to the first node N1. The pixel transistor T5 is a threshold compensation transistor, the gate electrode of which inputs the scanning signal S2, the first electrode of which is connected to the first node N1, and the second electrode of which is connected to the third node N3. The pixel transistor T6 is a control transistor, the gate electrode of which inputs the light-emitting control signal Emit, the first electrode of which is connected to the third node N3, and the second electrode of which is connected to the fourth node N4. The fourth node N4 is used for connecting the anode of the display light-emitting element 22, and the cathode of the display light-emitting element 22 is connected to the negative power supply voltage PVEE. The pixel transistor T7 is used for voltage reset of the anode of the display light-emitting element 22, the gate electrode of which is connected to the scanning signal S1, the first electrode of which is connected to the reference voltage VREF2, and the second electrode of which is connected to the fourth node N4.

[0074] Obviously, the implementation of the display pixel circuit 21 can be selected based on requirements, and is not limited to Figure 4 The 7T1C pixel circuit structure shown in the figure can also be an 8T1C pixel circuit structure including 8 pixel transistors and 1 storage capacitor, or a 6T1C pixel circuit structure including 6 pixel transistors and 1 storage capacitor, and the like, which are not limited by the embodiments of the present application. The pixel circuit 21 is electrically connected to the anode 221 of the display light-emitting element 22 through a via hole.

[0075] The dummy pixel structure P' is arranged in the non-display area BB adjacent to the display area AA. As Figure 5 As shown in the figure, since the dummy light-emitting element 22' in the dummy pixel structure P' does not need to emit light for display, the dummy pixel circuit 21' and the dummy light-emitting element 22' are disconnected. The dummy light-emitting element 22' can be provided without an anode, so that the dummy pixel circuit 21' and the dummy light-emitting element 22' are disconnected.

[0076] Among them, since the dummy pixel circuit 21' does not need to perform display control, the dummy pixel circuit 21' can have the same structure as the display pixel circuit 21, or reduce some transistor layouts based on the circuit of the display pixel circuit 21, and the dummy pixel circuit 21' does not need to input and output electrical signals.

[0077] like Figure 6a As shown, the dummy pixel circuit 21' includes a plurality of dummy pixel transistors; wherein, in a direction perpendicular to the display panel, the first conductive hole Via1 at least partially overlaps with the gate of the dummy pixel transistor, as shown in FIG. Figure 6a The scan line G includes the gate of the dummy pixel transistor. Figure 6a The raised portion of the scan line G shown in the dotted circle area represents the gate of a dummy pixel transistor.

[0078] In the embodiment of the present application, the first conductive hole Via1 and the gate of the dummy pixel transistor are at least partially overlapped, and the first conductive hole Via1 is set in the area where the scanning line G has a larger area, which facilitates drilling and increases the contact area between the first conductive hole Via1 and the scanning line G, thereby reducing the contact impedance. In addition, the scanning line G does not need to be further extended to the gate position of the dummy pixel transistor. Figure 6a The left side extension can shorten the length of the gate line and reduce the width of the frame of the third non-display area BB3.

[0079] like Figure 3 and Figure 6a As shown, the scanning circuit 103 is connected to the third signal connection line 13 located in the third non-display area BB3 , and the third signal connection line 13 is connected to the scanning line G through the first conductive via Vai1 .

[0080] refer to Figures 7-10 As shown, Figure 7 This is a structural diagram of another display panel provided in an embodiment of the present application. Figure 8 for Figure 7 The enlarged view of a corner area of ​​the display panel is shown. Figure 9 for Figure 7 A partial enlarged view of another top corner area of ​​the display panel is shown. Figure 10 for Figure 7 The cross-sectional view of the display panel is shown, wherein Figure 8 for Figure 7 A partial enlarged view of the area near the upper left corner R, Figure 9 for Figure 7 A partial enlarged view of the area near the lower left R corner.

[0081] like Figures 7-9As shown, the display area AA has a plurality of scanning lines G arranged in sequence, the scanning lines G are located in the first metal layer M1 and extend along the second direction X. The non-display area BB has a third non-display area BB3 adjacent to the first side L1, and the third non-display area BB3 has a scan circuit 103. The third non-display area BB3 includes a first portion BB31, a second portion BB32 and a third portion BB33 arranged in sequence along the first direction Y. The scan circuit 103 is connected with the scanning lines G through a third signal connection line 13. In the first portion BB31, the third signal connection line 13 is located in the second metal layer M2, and the first metal layer M1 is different from the second metal layer M2.

[0082] In the embodiment of the present application, the first metal layer M1 and the second metal layer M2 are different layers, which facilitates the wiring of the second signal connection line 12 in the second non-display area BB2, and makes the third signal connection line 13 and the second signal connection line 12 insulated and cross in different layers.

[0083] The top corner non-display area (i.e. Figure 7 the non-display area near the lower left R corner) between the first non-display area BB1 and the third non-display area BB3, the conventional design scheme needs to set the scan circuit 103 and the fan-out line 102 of the signal line 101 in the first display area AA1, and also needs to set the third signal connection line 13 connected with the scan circuit 103 and the scanning lines G, and the wiring led out in the second display area AA2 also occupies some of the top corner non-display area, resulting in a large frame width of the top corner non-display area, which is not convenient for narrow frame design.

[0084] In the embodiment of the present application, as shown in Figure 8 and Figure 9 the signal line 101 in the first display area AA1 is connected with the second signal connection line 12 located in the second non-display area BB2, the second signal connection line 12 is connected with the first signal connection line 11 located in the second display area AA2, and then the first signal connection line 11 is connected with the fan-out line 102 of the first non-display area BB1, so that the signal line 101 in the first display area AA1 does not need to be provided with the fan-out line 102, which greatly reduces the frame width of the lower left top corner non-display area. At the same time, since the second non-display area BB2 does not need to be provided with the fan-out line 102, the second non-display area BB2 has relatively sufficient wiring space relative to the first non-display area BB1, and the second signal connection line 12 set in the second non-display area BB2 does not increase the frame width of the second non-display area BB2.

[0085] As shown in Figure 10 the display panel includes a substrate 31 and a transistor T0 located on the surface of the substrate 31, and the transistor T0 is used as a pixel transistor in a display pixel circuit 21 or a non-pixel transistor in a pseudo pixel circuit 21'. Figure 10The transistor T0 is a pixel transistor in a display pixel circuit 21, and a dummy pixel circuit structure is not shown. The substrate 31 can be a flexible substrate such as a PI (polyimide) or the like. In other modes, the substrate 31 can also be a hard substrate such as a glass plate or the like. Figure 10 A dummy pixel circuit structure is not shown.

[0086] The transistor T0 includes: an active layer 32; a gate g, a first electrode, and a second electrode on the side of the active layer 32 away from the substrate 31, one of the first electrode and the second electrode being a source s and the other being a drain d. The gate g and the scan line G are both on the first metal layer M1. The first electrode and the second electrode are both on the second metal layer M2. The first metal layer M1 is on the side of the second metal layer M2 facing the substrate 31. The substrate 31 has multiple metal layers of different layers on it, used as electrodes of the transistor and wiring required by the panel. A planarization layer PLN is formed on the surface of the uppermost metal layer, and a pixel definition layer PDL is on the surface of the planarization layer PLN, the pixel definition layer PDL having a pixel opening in which the display light emitting element 22 or the dummy light emitting element 22' is made. The anode 221 of the display light emitting element 22 is connected through a via and the transistor T0 in the display pixel circuit 21.

[0087] In the embodiment of the application, the signal line 101 and the first signal connection line 11 are both on the third metal layer M3. The fan-out line 102 is between the binding area 104 and the display area AA, part of the fan-out line 102 is on the first metal layer M1, and the other part of the fan-out line 102 is on the fourth metal layer MC, the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer MC are four metal layers of different layers; at least one of the first metal layer M1, the third metal layer M3, and the fourth metal layer MC includes the second signal connection line 12, and the third signal connection line 13 in the first part BB31 is on the second metal layer M2, so that the third signal connection line 13 and the second signal connection line 12 in the first part BB31 are different layers and cross insulated, facilitating the wiring of the top corner non-display area between the third non-display area BB3 and the second non-display area BB2.

[0088] Optionally, at least one second signal connection line 12 is provided in the first metal layer M1, the third metal layer M3, and the fourth metal layer MC, and the second signal connection line 12 is wired through three metal layers of different layers, which can reduce the wiring area required by the second signal connection line 12 in the parallel direction of the display panel, thereby reducing the frame width of the top corner non-display area between the second non-display area BB2 and the third non-display area BB3 and the frame width of the second non-display area BB2.

[0089] In the third non-display area BB3, for any third signal connection line 13 located in the second part BB32 and the third part BB33, the third signal connection line 13 is located in at least one of the first metal layer M1 to the fourth metal layer MC. Since in the second part BB32 and the third part BB33, there is no need for the third signal connection line 13 and the second signal connection line 12 to be insulated from each other, the third signal connection line 13 in the second part BB32 and the third part BB33 can be set in at least one of the first metal layer M1 to the fourth metal layer MC based on requirements.

[0090] In order to further reduce the frame width of the top corner non-display area between the second non-display area BB2 and the third non-display area BB3 of the display panel, the shape of the second signal connection line 12 and the shape of the top corner can be matched.

[0091] Reference Figure 11 As shown, Figure 11 A wiring mode schematic diagram of a display panel in a top corner region is provided for an embodiment of the present application. The non-display area BB has a third non-display area BB3 adjacent to the first side L1. The display area AA has a second side L2 adjacent to the second non-display area BB2. The first side L1 and the second side L2 of the display area AA are connected by a first curve R1 bending towards the display area AA. The second signal connection line 12 includes a second curve 121 connected to the signal line 101, and the second curve 121 bends towards the display area AA. Since the second signal connection line 12 includes the second curve 121 matched with the shape of the first curve R1, it is convenient to wire the second signal connection line 12 in the top corner non-display area, and the frame width of the non-display area BB and the top corner non-display area adjacent to the first curve R1 can be reduced.

[0092] Reference Figure 12 As shown, Figure 12 Another wiring mode schematic diagram of a display panel in a top corner region is provided for an embodiment of the present application. The non-display area BB has a third non-display area BB3 adjacent to the first side L1. The display area AA has a second side L2 adjacent to the second non-display area BB2. The first side L1 and the second side L2 of the display area AA are connected by a first curve R1 bending towards the display area AA. The non-display area has a first power signal line 41, and the first power signal line 41 at least surrounds the second side and the first curve. The part 411 opposite to the first curve R1 and the part 412 opposite to the second side L2 of the first power signal line 41 satisfy the same line width condition.

[0093] The part 411 of the first power signal line 41 and the part 412 of the first power signal line 41 satisfy the same line width condition, which means that the line widths of the two parts are not more than a set threshold, so that the line widths of the two parts are the same or approximately the same. The set threshold can be set based on requirements, for example, the threshold is not more than 1000 microns. The part 411 of the first power signal line 41 opposite to the first curve R1 and the part 412 of the first power signal line 41 opposite to the second side L2 satisfy the same line width condition, which avoids the problem that the line width of the part 411 of the first power signal line 41 opposite to the first curve R1 is large, thereby ensuring that the third non-display area BB3 and the second non-display area BB2 have sufficient wiring space, so as to facilitate the wiring of the second signal connection line 12 and the third signal connection line 13.

[0094] The first power signal line 41 is used to provide a negative power voltage PVEE. The first power signal line 41 at least surrounds part of the display area AA in the non-display area BB. The first power signal line 41 can not only provide a negative power voltage PVEE for the display pixel circuit 21 in the display area AA, but also can be used as a protective structure to protect the conductive components in the surrounded area from static electricity.

[0095] In the embodiment of the present application, the wiring spacing in the edge region of the display area AA is smaller than the wiring spacing in the middle region. In this way, in the display area AA, the region close to the non-display area BB has a smaller wiring spacing, thereby facilitating the wiring in the top corner non-display area. If the display area adopts an R corner design, the wiring space of the non-display area near the R corner can be reduced, thereby reducing the frame width of the non-display area near the R corner.

[0096] Under the premise of keeping the wiring spacing of the middle display region unchanged, the wiring spacing of the edge region is reduced, including: reducing the wiring spacing of the signal line 101 close to the edge of the display area AA, and / or reducing the wiring spacing of the scan line G close to the edge of the display area AA.

[0097] Reference Figure 13 As shown, Figure 13 Another structure schematic diagram of a display panel provided by the embodiment of the present application is based on the above-mentioned embodiment, Figure 13 In the shown manner, in the first display area AA1, at least part of the signal line 101 has a first spacing d1; in the second display area AA2, the signal line 101 has a second spacing d2; wherein the first spacing d1 is smaller than the second spacing d2. In this way, in the second direction X, the wiring spacing of the signal line 101 close to the non-display area BB in the display area AA is reduced.

[0098] In the second display area AA2, the intervals of the signal lines 101 are all the second interval d2, so that the signal lines 101 in the second display area AA2 are routed with a uniform line interval. In the first display area AA1, the intervals of the signal lines 101 can all be the first interval d1, so that the signal lines 101 in the first display area AA1 are routed with a uniform line interval.

[0099] In other manners, a part of the signal lines 101 in the first display area AA1 close to the first side L1 can have the first interval d1, and another part of the signal lines 101 in the first display area AA1 close to the second display area AA2 can have the second interval d2. In this way, the part of the signal lines 101 in the first display area AA1 close to the first side L1 can be routed with a uniform first interval d1, and the other part of the signal lines 101 close to the second display area AA2 can be routed with a uniform second interval d2 as the signal lines 101 in the second display area AA2.

[0100] It should be noted that in the above embodiment, only the scheme of the line interval of the signal lines 101 in the first display area AA1 close to the first side L1 and the connection of the first signal connection line 11 and the second signal connection line 12 is illustrated. Obviously, for the signal lines 101 in the third display area AA3 located on the side of the second display area AA2 away from the first display area AA1, the same scheme of the line interval of the signal lines 101 in the first display area AA1 and the connection of the first signal connection line 11 and the second signal connection line 12 can be adopted, and the present embodiment will not be illustrated.

[0101] In the display panel, the display area AA has a first side L1 and a fourth side L4 opposite in the second direction X. The second display area AA2 is located between the first display area AA1 and the third display area AA3. The first display area AA1 includes the first side L1, and the third display area AA3 includes the fourth side L4.

[0102] Reference Figure 14 As shown, Figure 14 Another structure of a display panel provided by the present embodiment is shown in FIG. 6. Based on the above embodiment, Figure 14 As shown in the above manner, the display area AA has a plurality of scanning lines G arranged in sequence, and the scanning lines G extend along the second direction X. In the display area AA, in the first direction Y, the scanning lines G in the middle region 50 have a third interval d3.

[0103] The display region AA has a second edge L2 adjacent to the second non-display region BB2, and a plurality of continuous scanning lines G adjacent to the second edge L2 have a fourth pitch d4; the fourth pitch d4 is smaller than the third pitch d3. And / or, the display region AA has a third edge L3 adjacent to the first non-display region BB1, and a plurality of continuous scanning lines G adjacent to the third edge L3 have a fifth pitch d5; the fifth pitch d5 is smaller than the third pitch d3. In this way, in the first direction Y, the pitch of the scanning lines G in the display region AA near the non-display region BB is reduced.

[0104] In the first direction Y, the display region AA includes a middle region 50 and first and second edge regions 51 and 52 located on both sides of the middle region 50. The first edge region 51 includes the third edge L3, and the second edge region 52 includes the second edge L2. For a display panel with an R-angle structure for the top corner, in the first direction Y, the first edge region 51 is the part of the display region adjacent to the R-angle corresponding to the first non-display region BB1, and the second edge region 52 is the part of the display region adjacent to the R-angle corresponding to the second non-display region BB2.

[0105] In the middle region 50, all the scanning lines G have a wiring pitch of the third pitch d3, so that the scanning lines G in the middle region 50 are wired with a uniform wiring pitch.

[0106] If the fourth pitch d4 is set to be smaller than the third pitch d3, the wiring pitch of all the scanning lines G in the edge region 52 can be set to be d4, or the wiring pitch of a part of the scanning lines G adjacent to the second edge L2 is set to be the fourth pitch d4, and the wiring pitch of another part of the scanning lines G near the middle region 50 is set to be the third pitch d3, so that the scanning lines G in the second edge region 52 are wired.

[0107] If the fifth pitch d5 is set to be smaller than the third pitch d3, the wiring pitch of all the scanning lines G in the edge region 51 can be set to be d5, or the wiring pitch of a part of the scanning lines G adjacent to the third edge L3 is set to be the fourth pitch d5, and the wiring pitch of another part of the scanning lines G near the middle region 50 is set to be the third pitch d3, so that the scanning lines G in the edge region 51 are wired.

[0108] Figure 13 And Figure 14 In the way shown in the figure, when the wiring pitch is reduced in the edge region of the display region AA relative to the middle region, the layout design in the display region AA can be as shown in the figure. Figures 15-17

[0109] Referring to the figure, Figures 15-17 Figure 15 The wiring layout of the middle region of the display region provided in the embodiments of the present application, Figure 16 is a wiring layout of the edge region of the display region provided in the present application,​​Figure 17 This is another wiring layout for the edge area of ​​the display area provided in this application.

[0110] like Figure 15 As shown, in the middle area of ​​the display area AA, the wiring pitch of the scan lines G is the third pitch d3, and the wiring pitch of the signal lines 101 is the second pitch d2.

[0111] like Figure 16 As shown, in the edge region parallel to the second direction X and close to the edge of the display area (such as the first side L1 and / or the fourth side L4), the wiring spacing of at least part of the signal lines 101 is the first spacing d1.

[0112] like Figure 17 As shown, in the edge region parallel to the first direction and close to the edge of the display area (such as the second side L2 and / or the third side L3), the wiring spacing of at least some of the scan lines G is the fourth spacing d4 or the fifth spacing d5. The fourth spacing d4 and the fifth spacing d5 can be the same or different. To facilitate unified wiring configuration, the fourth spacing d4 and the fifth spacing d5 can be set to be the same.

[0113] like Figures 15-17 As shown, in display area AA, the edge and middle regions have the same pixel structure P. That is, the edge and middle regions use the same display light-emitting elements 22 and display pixel circuits 21. The display light-emitting elements 22 in different regions of display area AA have the same size, and the transistors in the display pixel circuits 21 have the same size and layout. While the wiring spacing in the edge regions is reduced relative to the middle region, the pixel structure P remains unchanged. This allows the edge and middle regions of display area AA to be manufactured to the same standard, simplifying the manufacturing process.

[0114] refer to Figure 18 As shown, Figure 18 A schematic diagram of the wiring method of the display panel in the adjacent area of ​​the third side provided in an embodiment of the present application, wherein the first non-display area BB1 has a fan-out line 102, and the signal line 101 and the first signal connection line 11 both pass through the second conductive hole Via2 and a corresponding fan-out line 102; the second conductive hole Via2 is located in the display area AA, and the fan-out line 102 extends into the display area AA.

[0115] exist Figure 18 In the method shown, the fan-out line 102 is extended into the display AA, and the second conductive hole Via2 connecting the signal line 101 and the first signal connection line 11 is set in the display area AA, so that the length of the fan-out line 102 in the first non-display area BB1 can be shortened, and the border width of the first non-display area BB1 can be reduced.

[0116] In one embodiment of the present application,Figure 2 、 Figure 7 、 Figure 8 、 Figures 11-13 As shown, the first display area AA1 can be configured to have the 1st to Nth signal lines arranged sequentially along the second direction X, where N is a positive integer greater than 1. The second display area AA2 can be configured to have the 1st to Nth first signal connection lines arranged sequentially in the opposite direction of the second direction X; and the second non-display area BB2 can be configured to have the 1st to Nth second signal connection lines arranged sequentially along the first direction Y; wherein the i-th signal line is connected to the i-th first signal connection line via the i-th second signal connection line, where i is a positive integer not greater than N. In this approach, the first signal connection line 11 does not need to extend to the second non-display area BB2; the i-th signal line is connected to the i-th first signal connection line via the i-th second signal connection line, and the i-th second signal connection line and the x-th first signal connection line do not need to intersect, thereby facilitating the routing of the first signal connection line 11. Here, x is a positive integer not greater than N, and i≠x.

[0117] In the above manner, the 1st signal line to the Nth signal line in the first display area AA1 are arranged sequentially in the second direction X, and the 1st first signal connection line to the Nth first signal connection line connected to each signal line 101 in the first display area AA1 are arranged sequentially in the opposite direction of the second direction X.

[0118] refer to Figure 19 and Figure 20 As shown, Figure 19 This is a structural diagram of another display panel provided in an embodiment of the present application. Figure 20 for Figure 19 A partial enlarged view of the display panel is shown, in which the first display area AA1 has the 1st signal line to the Nth signal line arranged in sequence along the second direction X, where N is a positive integer greater than 1; the first signal connection line 11 extends to the second non-display area BB2; the second display area AA2 has the 1st first signal connection line to the Nth first signal connection line arranged in sequence along the second direction X; the second non-display area BB2 has the 1st second signal connection line to the Nth second signal connection line arranged in sequence along the first direction Y; wherein the i-th signal line is connected to the i-th signal line through the i-th second signal connection line; and i is a positive integer not greater than N.

[0119] exist Figure 19 and Figure 20 In the manner shown, the 1st signal line to the Nth signal line in the first display area AA1 are arranged sequentially in the second direction X, and the N first signal connection lines 11 connected to the N signal lines 101 are also arranged sequentially in the second direction X, namely the 1st first signal connection line to the Nth first signal connection line.

[0120] In Figure 1 In the manner shown, since all the signal lines 101 are arranged in the second direction X in sequence, when the fan-out lines 102 passing through the first non-display area BB1 are connected to the binding area, the fan-out lines 102 arranged in the second direction X in sequence have the same order as the corresponding connected signal lines 101, and the display driving chip arranged in the binding area can provide data signals for each signal line 101 based on the order.

[0121] If the signal lines 101 of the first display area AA1 are connected to the second display area AA2 and the fan-out lines 102 through the first signal connection line 11 and the second signal connection line 12, and the binding area 104 is directly connected through the fan-out lines 102, it will cause the order of the ports of the signal lines 101 connected to the binding area 104 to change. With respect to the manner shown in Figure 1 When the display driving is performed in the manner shown, the display driving chip needs to adjust the light display driving timing based on the change in the order, so that the display driving timing and the order of the ports of each signal line 101 drawn to the binding area 104 are adapted to normally perform image display.

[0122] In other manners, the order of the ports of each signal line 101 in the binding area 104 can be made the same as that in the manner shown in Figure 1 by performing line switching in the first non-display area BB1 when the signal lines 101 of the first display area AA1 are connected to the second display area AA2 and the fan-out lines 102 through the first signal connection line 11 and the second signal connection line 12, and by using a specific line switching manner, at this time, there is no need to change the display timing.

[0123] Referring to Figures 21-23 , Figure 21 is a structural schematic diagram of yet another display panel provided by an embodiment of the present application, Figure 22 is Figure 21 is a partial enlarged view of the display panel shown, Figure 23 is Figure 21 is a sectional view of the display panel in the first non-display area, in this manner, the first non-display area BB1 has a plurality of fourth signal connection lines 14, the fourth signal connection lines 14 are located between the binding area 104 and the display area AA; the fourth signal connection lines 14 and the display area AA have a plurality of fan-out lines 102, the signal lines 101 and the first signal connection lines 11 are respectively connected to the corresponding fourth signal connection lines 14 through different fan-out lines 102; the signal lines 101, the first signal connection lines 11 and the fourth signal connection lines 14 are located in the same metal layer, and are located in different metal layers from the fan-out lines 102.

[0124] In Figures 21-23In the illustrated manner, after the signal lines 101 and the first signal connection lines 11 are connected from the fan-out lines 102 in the second display area AA2 and the first non-display area BB1, the lines are changed through the fourth signal connection lines 14 in different layers from the fan-out lines 102, so that the order of the ports to which the respective signal lines 101 are connected in the second direction X of the binding area 104 is the same as the order of the respective signal lines 101 in the second direction X, and thus the signal lines 101 in the first display area AA1 can be led from the second display area AA2 to the first non-display area BB1 through the first signal connection lines 11 and the second signal connection lines 12 without changing the order of the ports to which the respective signal lines 101 are connected in the binding area 104.

[0125] Optionally, the fourth signal connection lines 14 and the binding area 104 have a fifth signal connection line 15 and a sixth signal connection line 16 in different layers, and each fourth signal connection line 14 is connected to the binding area 104 through a corresponding fifth signal connection line 15 or sixth signal connection line 16. The fifth signal connection line 15 can be in the same metal layer as the fourth signal connection line 14. The sixth signal connection line 16 can be in the same layer as the fan-out line 102.

[0126] In the embodiments of the present application, as shown in the drawings, Figure 23 The fan-out line 102 and the sixth signal connection line 16 can be connected through the fourth signal connection line 14 and the fifth signal connection line 15 in the same layer. As described in the above embodiments, the sixth signal connection line 16 and the fan-out line 102 can be in the first metal layer M1 and / or the fourth metal layer Mc, and the fifth signal connection line 15 and the fourth signal connection line 14 can be in M3. In Figure 23 In the illustrated manner, for a fan-out line 102 in the fourth metal layer Mc, the fourth signal connection line 14 and the fifth signal connection line 15 are connected through the conductive hole to a sixth signal connection line 16 in the first metal layer M1.

[0127] In Figure 23 the drawings, only one line changing manner of the fan-out line 102 is shown, and in the embodiments of the present application, the metal layers of the fan-out line 102, the fourth signal connection line 14, the fifth signal connection line 15 and the sixth signal connection line 16 can be set based on requirements, and in other manners, the fan-out line 102 and the sixth signal connection line 16 can be in the same layer, such as being in the first metal layer M1 or being in the fourth metal layer Mc.

[0128] The part of the first non-display area BB1 away from the display AA is the folding area BB0, which can be folded to the back of the display panel to reduce the frame width. The binding area 104 is located in the folding area BB0.

[0129] As Figure 21 and Figure 22 shown, the signal lines 101 in the second display area AA2 and the first signal connection lines 11 are each connected with a fan-out line 102 at one end facing the first non-display area BB1; in the second direction X, the display area AA has the 1st signal line to the Mth signal line arranged in sequence, the binding area 104 includes the 1st pad to the Mth pad arranged in sequence, and M is a positive integer greater than 1; wherein the fan-out line 102 is connected with the fourth signal connection line 14 through the second conductive hole for corresponding connection, so that the jth signal line is connected with the jth pad, and j is a positive integer not greater than M. In this way, the signal lines 101 in the first display area AA1 can be led out from the second display area AA2 to the first non-display area BB1 through the first signal connection line 11 and the second signal connection line 12 without changing the port of each signal line 101 connected to the binding area 104 in the premise of the ordering of the binding area 104, while reducing the frame width of the first non-display area BB1 and the region adjacent to the R angle without changing the driving timing.

[0130] Referring to Figure 24 shown, Figure 24 is a wiring principle diagram in a display panel provided by an embodiment of the present application, the display area AA has a plurality of second power signal lines 42 arranged in sequence, and the second power signal lines 42 extend along the first direction Y; wherein the second power signal lines 42 are different layers from the first signal connection lines 11, and in a direction perpendicular to the display panel, the first signal connection lines 11 at least partially overlap the adjacent second power signal lines 42. The second power signal lines 42 are used to provide a positive power voltage PVDD for the pixel circuit.

[0131] In the embodiment of the present application, in the direction perpendicular to the display panel, the first signal connection lines 11 are arranged to at least partially overlap the adjacent second power signal lines 42, so that the first signal connection lines 11 can reuse the space above the second power signal lines 42 for wiring, reducing the wiring space.

[0132] Referring to Figure 25 shown, Figure 25 is another structure diagram of a display panel provided by an embodiment of the present application, based on the above embodiment, Figure 25 shown, the display area AA further has at least one auxiliary wire 10; the auxiliary wire 10 penetrates the display area AA along the first direction Y; wherein along the second direction X, the auxiliary wire 10 and the first signal connection line 11 are uniformly distributed in the display area AA.

[0133] The first signal connection line 11 is arranged in the second display area AA2, which causes the flatness of the other areas in the display area AA, where the first signal connection line 11 is not arranged, to be inconsistent with the flatness of the second display area AA2. In addition, the difference in wiring density in different areas of the display area AA also causes the reflectivity to be different, which causes display differences. The auxiliary wiring 10 is arranged to solve the problem of the flatness of the display area AA being inconsistent in different areas and the reflectivity being different.

[0134] Optionally, the auxiliary wiring 10 and the first signal connection line 11 are located in the same metal layer, so as to better solve the problem of the flatness of the display area AA being inconsistent in different areas and the reflectivity being different.

[0135] In the embodiment of the application, the auxiliary wiring 10 is connected to a fixed potential to avoid the influence of induced electricity generated by the floating potential of the auxiliary wiring 10 on the performance of the display panel.

[0136] As described in the above embodiment, the display area AA has a display pixel structure P, the display pixel structure P includes a display pixel circuit 21 and a display light emitting element 22; the display pixel circuit 21 controls the display light emitting element to emit light based on a first fixed potential and a second fixed potential; the second fixed potential is less than the first fixed potential; and the auxiliary wiring 10 is connected to the first fixed potential or the second fixed potential. One of the first fixed potential and the second fixed potential is a positive power supply voltage PVDD, and the other is a negative power supply voltage PVEE. The auxiliary wiring 10 is input with a fixed voltage signal by using an existing voltage signal in the display panel, and does not need to separately increase other voltage signals.

[0137] Based on the above embodiment, another embodiment of the application further provides a display electronic device, which can be as shown in Figure 26 .

[0138] Referring to Figure 26 , Figure 26 is a structural schematic diagram of an electronic device provided in the embodiment of the application. The electronic device includes the display panel 100 disclosed in any one of the above embodiments.

[0139] In the embodiment of the application, the electronic device can be a smartphone, a tablet computer, a notebook computer, a smart wearable device, and an active light emitting display panel of a household appliance having a display function. The electronic device adopts the display panel 100 provided in the above embodiment, which can reduce the frame width of the side non-display area BB and can achieve a narrow frame design.

[0140] The various embodiments described in this specification are intended to be illustrative only and not in a limiting sense. Unless otherwise indicated herein, the same reference numerals and characters have been used throughout the description and figures to indicate functionally similar elements. As used in the description herein, the following terms have the following meanings.

[0141] It is also important to note that the construction and arrangement of the devices shown in the various embodiments are illustrative only and not restrictive in character, and that all equivalents, functions and / or steps according to embodiments illustrated and disclosed herein can be substituted for the devices and / or methods shown and such

[0142] The terms "upper," "lower," "top," "bottom," "inner," "outer," and the like refer to the orientation or position of the device or element as shown in the drawings, and are used only to facilitate the description of the application and the claims, and are not intended to limit or confine the application to a particular orientation, configuration, or operation, and thus should not be construed as limiting the application in this respect. When one component is said to be "connected" to another component, it can be directly connected to the other component or intervening components can be present.

[0143] It is also important to note that the construction and arrangement of the devices shown in the various embodiments are illustrative only and not restrictive in character, and that all equivalents, functions and / or steps according to embodiments illustrated and disclosed herein can be substituted for the devices and / or methods shown and such

[0144] The foregoing description of the disclosed embodiments enables a person skilled in the art to make or use the application. Modifications of these embodiments will occur to persons of skill in the art, and that the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Therefore, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel comprising a display area and a non-display area at least partially surrounding the display area, wherein: The display panel includes: a plurality of signal lines extending along a first direction, wherein the signal lines are located in the display area; The display area includes a first display area and a second display area adjacent to each other along a second direction; the display area has a first side extending along the first direction, and the first display area is located between the first side and the second display area; a first signal connection line extending along a first non-display area on one side of the display area, through the display area, and to a second non-display area on the other side of the display area, wherein the first non-display area includes a binding area; a second signal connection line extending along the second non-display area, one end of the second signal connection line being connected to the first signal connection line, and the other end of the second signal connection line being connected to any one signal line in the first display area; The non-display area has a third non-display area adjacent to the first side; the display area has a second side adjacent to the second non-display area, and the first side and the second side of the display area are connected by a first curve bent toward the display area; wherein the second signal connection line includes a second curve connected to the signal line, and the second curve bends toward the display area.

2. The display panel according to claim 1, wherein: The display area has a plurality of display pixel structures, each of which includes a display pixel circuit and a display light-emitting element connected to the display pixel circuit; The third non-display area has a scanning circuit, and the scanning circuit is connected to the scanning line through the first conductive hole to connect to the display pixel circuit; Among them, there are multiple pseudo-pixel structures arranged in sequence along the first direction between the scanning circuit and the first edge, and the pseudo-pixel structure includes a pseudo-pixel circuit and a pseudo-light-emitting element; in the direction perpendicular to the display panel, the first conductive hole and the pseudo-pixel circuit are arranged opposite to each other.

3. The display panel according to claim 2, wherein: The dummy pixel circuit includes a plurality of dummy pixel transistors; Wherein, in a direction perpendicular to the display panel, the first conductive hole at least partially overlaps with the gate of the dummy pixel transistor.

4. The display panel according to claim 1, wherein: The display area has a plurality of scan lines arranged in sequence, the scan lines are located in the first metal layer and extend along the second direction; The third non-display area has a scanning circuit; the third non-display area includes a first portion, a second portion, and a third portion arranged in sequence along the first direction; the scanning circuit is connected to the scanning line via a third signal connection line; In the first portion, the third signal connection line is located in a second metal layer, and the first metal layer and the second metal layer are different layers.

5. The display panel according to claim 4, wherein: The signal line and the first signal connection line are both located in the third metal layer; A fan-out line is provided between the binding area and the display area, a portion of the fan-out line is located in the first metal layer, and another portion of the fan-out line is located in the fourth metal layer, and the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are four different metal layers; At least one of the first metal layer, the third metal layer, and the fourth metal layer includes the second signal connection line.

6. The display panel according to claim 5, wherein: The first metal layer, the third metal layer, and the fourth metal layer each include at least one second signal connection line.

7. The display panel according to claim 5, wherein: For any one of the third signal connection lines located in the second portion and the third portion, the third signal connection line is located in at least one layer from the first metal layer to the fourth metal layer.

8. The display panel according to claim 1, wherein: The non-display area has a first power signal line, which surrounds at least the second side and the first curve; the first power signal line has the same line width as the first curve and the second side.

9. The display panel according to claim 1, wherein: In the display area, the wiring spacing in the edge area is smaller than the wiring spacing in the middle area.

10. The display panel according to claim 9, wherein: In the first display area, at least some of the signal lines have a first spacing; In the second display area, the signal lines have a second spacing; The first spacing is smaller than the second spacing.

11. The display panel according to claim 9, wherein The display area has a plurality of scan lines arranged in sequence, and the scan lines extend along the second direction; in the display area, in the first direction, the scan lines in the middle area have a third spacing; A plurality of continuously arranged scan lines adjacent to the second side have a fourth spacing; the fourth spacing is smaller than the third spacing; and / or the display area has a third side adjacent to the first non-display area, and a plurality of continuous scan lines adjacent to the third side have a fifth spacing; the fifth spacing is smaller than the third spacing.

12. The display panel according to claim 11, wherein: The first non-display area has a fan-out line, and the signal line and the first signal connection line both pass through a second conductive hole and a corresponding fan-out line; the second conductive hole is located in the display area, and the fan-out line extends into the display area.

13. The display panel according to claim 1, wherein The first display area has a 1st signal line to an Nth signal line sequentially arranged along the second direction, where N is a positive integer greater than 1; The second display area has a first signal connection line from the 1st to the Nth first signal connection line arranged in sequence along the opposite direction of the second direction; The second non-display area has a first second signal connection line to an Nth second signal connection line sequentially arranged along the first direction; The i-th signal line is connected to the i-th first signal connection line through the i-th second signal connection line, and i is a positive integer not greater than N.

14. The display panel according to claim 1, wherein The first display area has a 1st signal line to an Nth signal line sequentially arranged along the second direction, where N is a positive integer greater than 1; The first signal connection line extends to the second non-display area; the second display area has the first signal connection line to the Nth first signal connection line arranged in sequence along the second direction; The second non-display area has a first second signal connection line to an Nth second signal connection line sequentially arranged along the first direction; The i-th signal line is connected to the i-th signal line through the i-th second signal connecting line; i is a positive integer not greater than N.

15. The display panel according to claim 1, wherein The first non-display area has a plurality of fourth signal connection lines, and the fourth signal connection lines are located between the binding area and the display area; There are multiple fan-out lines between the fourth signal connection line and the display area, and the signal line and the first signal connection line are respectively connected to the corresponding fourth signal connection line through different fan-out lines; The signal line, the first signal connection line, and the fourth signal connection line are located in the same metal layer, and are located in a different metal layer from the fan-out line.

16. The display panel according to claim 15, wherein: The signal line in the second display area and the first signal connection line are respectively connected to one of the fan-out lines at one end facing the first non-display area; In the second direction, the display area has a first signal line to an Mth signal line arranged in sequence, and the binding area includes a first pad to an Mth pad arranged in sequence, where M is a positive integer greater than 1; The fan-out line and the fourth signal connection line are correspondingly connected through the second conductive hole, so that the j-th signal line is connected to the j-th pad, where j is a positive integer not greater than M.

17. The display panel according to claim 1, wherein: The display area has a plurality of second power signal lines arranged in sequence, and the second power signal lines extend along the first direction; The second power signal line and the first signal connection line are in different layers, and in a direction perpendicular to the display panel, the first signal connection line and the adjacent second power signal line at least partially overlap.

18. The display panel according to claim 1, wherein The display area further has at least one auxiliary wiring; the auxiliary wiring runs through the display area along the first direction; Wherein, along the second direction, the auxiliary wiring and the first signal connection line are evenly distributed in the display area.

19. The display panel according to claim 18, wherein: The auxiliary wiring is connected to a fixed potential.

20. The display panel according to claim 19, wherein The display area has a display pixel structure, the pixel structure including a display pixel circuit and a display light-emitting element; the display pixel circuit controls the light-emitting element to emit light based on a first fixed potential and a second fixed potential; wherein the second fixed potential is lower than the first fixed potential; The auxiliary wiring is connected to the first fixed potential or the second fixed potential.

21. An electronic device comprising the display panel according to any one of claims 1 to 20.

Images