A trench double-gate transistor cell structure and manufacturing method thereof

Abstract

The present application relates to a trench dual-gate transistor cell structure and a manufacturing method thereof. A trench dual-gate transistor cell structure includes a conductive substrate, a conductive epitaxial layer, a P-well junction region, a source junction region, and a source region lead metal. A closed-loop silicon trench is provided on the conductive epitaxial layer, the P-well junction region, and the source junction region. An insulating isolation oxide layer is formed on the trench wall of the closed-loop silicon trench. A dummy gate polysilicon and an effective gate polysilicon are provided in the closed-loop silicon trench. A dummy gate isolation oxide layer is further provided between the dummy gate polysilicon and the effective gate polysilicon. An effective gate isolation oxide layer is further provided between the effective gate polysilicon and the source region lead metal. The source junction region includes an alternating N+ source junction region and a P+ source junction region. An electrical connection slot is provided on the source region lead metal. The side of the source junction region close to the source region lead metal is inserted into the electrical connection slot. The trench dual-gate transistor cell structure of the present application reduces the structural size of the cell, reduces the on-resistance, conduction loss, and switching loss, and improves the cost performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor power devices, and in particular to a trench dual-gate transistor cell structure and a manufacturing method thereof. Background Art

[0002] Medium and low voltage trench MOSFET continues to develop in China. Thanks to the continuous demand from terminal boom, the demand in the domestic market has increased year by year. Figure 1 The device shown includes a source lead metal 1a, an active gate 2a, a dummy gate 3a, a channel formed between the active gates, and an N+ semiconductor doping region 4a and a P- semiconductor doping region 5a disposed in the channel. An insulating oxide layer 6a is provided outside the active gate 2a to insulate and isolate the active gate 2a from the N+ semiconductor doping region 4a and the P- semiconductor doping region 5a. An effective gate insulating oxide layer 7a is also provided outside the active gate 2a to insulate and isolate the active gate 2a from the source lead metal 1a. An insulating oxide layer 6a is also provided outside the dummy gate 3a. The source lead metal 1a is connected to the negative power supply, and the P- semiconductor doping region 5a is connected to the positive power supply. Contact holes 8a for inserting the source lead metal 1a are provided in both the active gate insulating oxide layer 7a and the N+ semiconductor doping region 4a.

[0003] The aforementioned prior art dual-gate trench low-voltage MOSFET transistors suffer from a problem with their relatively wide dimensions and large die area, resulting in high specific on-resistance, high conduction losses, high switching losses, and a low cost-performance ratio. As the market for trench low-voltage MOSFETs grows, the market demands higher cost-performance for these semiconductor power devices. Therefore, there is a need to design a trench dual-gate transistor with a small size, small die area, low specific on-resistance, low conduction losses, low switching losses, and high cost-performance, and that can be adapted for use in smaller packages to meet end-users' basic requirements for portable end products. Summary of the Invention

[0004] In order to improve the technical problems of the trench double-gate transistor in the above-mentioned prior art, such as wide size, large die area, high specific on-resistance, high conduction loss, high switching loss and low cost performance, the present application provides a trench double-gate transistor cell structure and a manufacturing method thereof.

[0005] In the first aspect, the trench dual-gate transistor cell structure provided by the present application adopts the following technical solutions:

[0006] A trench double-gate transistor primitive cell structure includes a conductive substrate, a conductive epitaxial layer, a P-well junction region, a source junction region, and a source region lead metal stacked in sequence. Closed-loop silicon trenches are correspondingly opened on the conductive epitaxial layer, the P-well junction region, and the source junction region. An insulating isolation oxide layer is formed on the trench wall of the closed-loop silicon trench. Virtual gate polysilicon and effective gate polysilicon are arranged in the closed-loop silicon trench. Both the virtual gate polysilicon and the effective gate polysilicon are closed-loop structures adapted to the shape of the closed-loop silicon trench. The virtual gate polysilicon is located at the bottom of the closed-loop silicon trench, and the effective gate polysilicon is located on the side of the virtual gate polysilicon away from the conductive substrate. The virtual gate polysilicon is located at the bottom of the closed-loop silicon trench. The effective gate polysilicon is located on the side of the virtual gate polysilicon away from the conductive substrate. At a position corresponding to the conductive epitaxial layer in the ring silicon trench, the effective gate polysilicon is located at a position corresponding to the P-well junction area in the closed-loop silicon trench. A virtual gate isolation oxide layer is provided between the virtual gate polysilicon and the effective gate polysilicon to insulate and isolate the two. An effective gate isolation oxide layer is also provided between the effective gate polysilicon and the source region lead metal to insulate and isolate the two. The source junction area includes an N+ source junction area and a P+ source junction area alternately arranged along the length direction of the closed-loop silicon trench. An electrical connection slot is provided on the source region lead metal at a position corresponding to the source junction area. The side of the source junction area close to the source region lead metal is inserted into the electrical connection slot and is in contact with the source region lead metal.

[0007] By adopting the above technical solution, the trench dual-gate transistor cell structure of the present application utilizes an electrical connection slot opened on the source region lead metal to plug into the source junction region to achieve electrical connection, without the need to open contact holes on the source junction region and the effective gate isolation oxide layer. The contact holes and the gap structure between the contact holes and the trench gate are eliminated, which is equivalent to reducing the structural size of the cell. Without the contact holes and the gap between the contact holes and the trench gate, the trench gate spacing in the cell structure can be reduced to 10%-30% of the original, and the cell density is increased by at least 50%. The current density of the trench dual-gate transistor is strongly positively correlated with the cell density, and the specific on-resistance increases by more than 50%. The area size of the transistor can be reduced by about 50%. This is an unprecedented optimization for the trench dual-gate transistor cell structure, which not only reduces the size of the trench dual-gate transistor, but also saves chip and packaging costs.

[0008] Optionally, the source junction region depth ranges from 0.1-1um, the P-well junction region depth ranges from 1.0-4.0um, the effective gate polysilicon top groove depth ranges from 0.2-1.0um, the effective gate polysilicon depth after excluding the effective gate polysilicon top groove depth ranges from 0.5-3um, the virtual gate polysilicon depth after excluding the effective gate polysilicon top groove depth and the effective gate polysilicon depth ranges from 0.5-3um, and the trench gate width and trench spacing dimensions are both 0.1-0.5um.

[0009] By adopting the above technical solution, it can be ensured that the current channel can be fully opened when a positive voltage is applied to the effective gate polysilicon; the trench gate width and the trench spacing are both between 0.1-0.5um, and the unit cell size is about 30%-50% of the conventional unit cell size in the existing technology, which greatly increases the source region's specific on-resistance, increases the source region's current density, and reduces the source region's area size.

[0010] Optionally, the length ratio of the N+ source junction regions and the P+ source junction regions alternately arranged along the length direction of the closed-loop silicon trench is in the range of 1.0-10.

[0011] By adopting the above technical solution, it is possible to ensure that the source region lead metal is short-circuited to the P-well junction region and the N+ source junction region, thereby ensuring the avalanche performance of the trench dual-gate transistor.

[0012] Optionally, a protruding plug-in structure is formed on the source region lead metal at a position corresponding to the closed-loop silicon groove, and the plug-in structure is adapted to be plugged into the notch of the closed-loop silicon groove, and the plug-in structure abuts against the effective gate isolation oxide layer.

[0013] By adopting the above technical solution, the connection between the source region lead metal and the source junction region can be made more reliable.

[0014] Optionally, the effective gate isolation oxide layer is a pure oxide layer TEOS.

[0015] Optionally, the source region lead metal is made of aluminum.

[0016] By adopting the above technical solution, the metal aluminum is light and has good conductivity, so that the overall mass of the trench double-gate transistor cell structure is relatively small.

[0017] Optionally, the conductive substrate is a heavily doped conductive substrate, and the conductive epitaxial layer is a lightly doped conductive epitaxial layer.

[0018] In a second aspect, the present application provides a method for manufacturing a trench dual-gate transistor cell structure using the following technical solutions:

[0019] A method for manufacturing a trench dual-gate transistor cell structure comprises the following steps: S1, preparing a conductive substrate, and depositing a conductive epitaxial layer on one surface of the conductive substrate;

[0020] S2, thermally growing a thermal oxide layer with a thickness of 300-600 Å on the surface of the conductive epitaxial layer away from the conductive substrate;

[0021] S3, using a chemical vapor deposition method to deposit a pure oxide layer TEOS with a thickness of 2000-6000Å on the surface of the thermal oxide layer away from the conductive substrate;

[0022] S4. Coating a photoresist with a thickness of 7000-12000Å on the surface of the pure oxide layer TEOS away from the conductive substrate, and using semiconductor-specific equipment to expose and develop the photoresist to open the photoresist at the location where the groove is to be formed, thereby forming a groove window;

[0023] S5. Thermally bake the photoresist to remove moisture from the photoresist, making the slotted window more accurate and reliable, and allowing the photoresist to better adhere to the pure oxide layer TEOS. The pure oxide layer TEOS and the thermal oxide layer at the slotted window are removed by dry etching, exposing a portion of the surface of the conductive epitaxial layer.

[0024] S6, removing the photoresist on the surface of the pure oxide layer TEOS by a combination of dry and wet methods;

[0025] S7, using the pure oxide layer TEOS and the thermal oxide layer at the slotted window as a hard mask to etch a closed-loop silicon groove on the surface of the conductive epitaxial layer, with a depth of 2-5 μm;

[0026] S8. Using wet cleaning and dry cleaning methods to remove the groove deposits in the closed-loop silicon groove, and remove the pure oxide layer TEOS and thermal oxide layer on the conductive epitaxial layer;

[0027] S9, thermally growing a sacrificial oxide layer with a thickness of 400-1000Å on the groove wall of the closed-loop silicon groove, and removing the sacrificial oxide layer on the groove wall with HF acid to improve the groove wall condition;

[0028] S10, thermally growing an oxide layer with a thickness of 500-7000Å on the groove wall of the closed-loop silicon groove, and depositing polysilicon with a thickness of 5000-20000Å by chemical vapor deposition to fill the closed-loop silicon groove;

[0029] S11, dry-etching the polysilicon filled in the closed-loop silicon trench to a depth of 0.5-3.0 μm to form dummy gate polysilicon, and exposing the oxide layer above the dummy gate polysilicon in the closed-loop silicon trench to the surface;

[0030] S12, removing the etching deposits in the closed-loop silicon trench by wet cleaning, and cleaning and etching the oxide layer above the dummy gate polysilicon in the closed-loop silicon trench with HF acid. At this time, the remaining oxide layer in the closed-loop silicon trench is the dummy gate oxide layer;

[0031] S13, depositing a dummy gate isolation oxide layer on the upper surface of the dummy gate polysilicon by chemical vapor deposition;

[0032] S14, thermally growing an effective gate oxide layer with a thickness of 350-1000Å on the trench wall above the dummy gate isolation oxide layer in the closed-loop silicon trench, with the thermal growth temperature being 950-1150°C;

[0033] S15, depositing polysilicon on the dummy gate isolation oxide layer in the closed-loop silicon trench by chemical vapor deposition, with a deposition thickness of 5000-10000Å;

[0034] S16, dry-etching the polysilicon deposited on the dummy gate isolation oxide layer so that the remaining polysilicon is 0.2-1 μm away from the plane of the outer edge of the closed-loop silicon trench, and the remaining polysilicon is effective gate polysilicon;

[0035] S17, using chemical vapor deposition to deposit a completely filled pure oxide layer TEOS on the upper surface of the effective gate polysilicon, and then dry-etching the pure oxide layer TEOS on the effective gate polysilicon so that the remaining pure oxide layer TEOS is half the thickness of the previous one, thereby obtaining an effective gate isolation oxide layer, and then removing the etched deposits in the closed-loop silicon trench by wet cleaning;

[0036] S18, implanting conductive impurities into the portion of the conductive epitaxial layer between the effective gate polysilicon using a dedicated semiconductor implantation doping device, and allowing the conductive impurities to diffuse to form a P-well junction region;

[0037] S19, coating a photoresist on the upper surface of the P-well junction area, and using semiconductor-specific equipment to expose and develop the photoresist, forming an implantation region and a barrier region for conductive impurities on the photoresist, then using semiconductor-specific implantation doping equipment to implant a high-dose conductive impurity of the desired type into the upper surface of the P-well junction area through the implantation region, then removing the photoresist using a combination of dry and wet methods, and then allowing the implanted high-dose conductive impurities to diffuse to form a corresponding N+ source junction area or P+ source junction area;

[0038] S20, removing particles remaining in the surface process by wet cleaning, and removing the effective gate oxide layer remaining on the upper surface by wet etching solution such as HF acid, so that the N+ source junction area or P+ source junction area on the surface is exposed;

[0039] S21, forming a dummy gate contact hole and an effective gate contact hole;

[0040] S22. A 3-5 μm metal layer is evaporated on the surface through a semiconductor-specific metal coating device, and a photoresist is coated on the metal layer. After exposure and development, source lead metal and gate lead metal are formed by etching.

[0041] By adopting the above technical solution, the trench dual-gate transistor cell structure is electrically connected to the source junction region through an electrical connection slot opened in the source region lead metal, without the need to open contact holes in the source junction region and the effective gate isolation oxide layer. The contact holes and the gap structure between the contact holes and the trench gate are eliminated, which is equivalent to reducing the structural size of the cell. Without the contact holes and the gap between the contact holes and the trench gate, the trench gate spacing in the cell structure can be reduced to 10%-30% of the original, and the cell density can be increased by at least 50%. The current density of the trench dual-gate transistor is strongly positively correlated with the cell density, and the on-resistance increases by more than 50%. The area size of the transistor can be reduced by about 50%. This is an unprecedented optimization for the trench dual-gate transistor cell structure, not only reducing the size of the trench dual-gate transistor, but also saving chip and packaging costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 1 is a schematic diagram of the original cell structure of a trench low-voltage MOSFET transistor in the background art;

[0043] Figure 2 2. It is a top view of the trench double-gate transistor cell structure according to an embodiment of the present application;

[0044] Figure 3 yes Figure 2 Structural schematic diagram of middle section 2;

[0045] Figure 4 yes Figure 2 Structural schematic diagram of middle section 1;

[0046] Figure 5 yes Figure 2 A schematic diagram of the structure of the middle section 3;

[0047] Figure 6 yes Figure 2 A schematic structural diagram of the middle section 4;

[0048] Figure 7 yes Figure 2 A schematic structural diagram of the middle section 5;

[0049] Figure 8 1 is a schematic diagram corresponding to steps S1-S5 in the method for manufacturing a trench double-gate transistor cell structure according to an embodiment of the present application;

[0050] Figure 9 is a schematic diagram corresponding to steps S7-S8;

[0051] Figure 10 is a schematic diagram corresponding to steps S10-S11;

[0052] Figure 11 is a schematic diagram corresponding to steps S12-S16;

[0053] Figure 12 is a schematic diagram corresponding to step S17;

[0054] Figure 13 is a schematic diagram corresponding to step S18;

[0055] Figure 14 and Figure 15 is a schematic diagram corresponding to step S19;

[0056] Figure 16 and Figure 17 It is a schematic diagram corresponding to step S20.

[0057] Explanation of reference numerals: 1a, source lead metal; 2a, effective gate; 3a, dummy gate; 4a, N+ semiconductor doping region; 5a, P- semiconductor doping region; 6a, insulating oxide layer; 7a, effective gate insulating oxide layer; 8a, contact hole; 1, conductive substrate; 2, conductive epitaxial layer; 3, P-well junction region; 4, source junction region; 41, N+ source junction region; 42, P+ source junction region; 5, source region lead metal; 51, electrical connection slot; 52 , plug-in structure; 6, closed-loop silicon groove; 61, gate lead metal; 62, dummy gate contact hole; 63, effective gate contact hole; 71, effective gate oxide layer; 72, dummy gate oxide layer; 73, dummy gate isolation oxide layer; 74, effective gate isolation oxide layer; 8, dummy gate polysilicon; 9, effective gate polysilicon; 101, thermal oxide layer; 102, pure oxide layer TEOS; 103, photoresist; 104, slotted window; 105, oxide layer. DETAILED DESCRIPTION

[0058] The present application is further described in detail below with reference to the accompanying drawings.

[0059] like Figure 1 As shown, the prior art trench low-voltage MOSFET transistor has a large primary cell structure, which prevents further improvement in current density, reduction in transistor area, and reduction in manufacturing cost. The inventors discovered that this is due to the presence of specialized contact holes 8a in the source region of the primary cell structure, as well as necessary dimensions such as the gap between the contact holes 8a and the trench gate. These two dimensions have reached their design limits and cannot be further reduced. To address the technical issues of trench dual-gate transistors, such as wide size, large die area, high specific on-resistance, high conduction losses, high switching losses, and low cost-performance, the present application provides a trench dual-gate transistor primary cell structure and a method for manufacturing the same.

[0060] Reference Figure 2 and Figure 3The embodiment of the present application discloses a trench double-gate transistor cell structure, comprising a conductive substrate 1, a conductive epitaxial layer 2, a P-well junction region 3, a source junction region 4, and a source region lead metal 5 stacked in sequence. The source region lead metal 5 serves as the source electrode, and the conductive substrate 1 serves as the drain electrode. In this embodiment, the source region lead metal 5 is made of metallic aluminum, the conductive substrate 1 is a heavily doped conductive substrate, and the conductive epitaxial layer 2 is a lightly doped conductive epitaxial layer. Referring again to Figure 4-Figure 7 A closed-loop silicon trench 6 is correspondingly formed on the conductive epitaxial layer 2, the P-well junction region 3, and the source junction region 4. An insulating isolation oxide layer is formed on the walls of the closed-loop silicon trench 6. A dummy gate polysilicon 8 and an effective gate polysilicon 9 are disposed within the closed-loop silicon trench 6. Both the dummy gate polysilicon 8 and the effective gate polysilicon 9 are closed-loop structures that conform to the shape of the closed-loop silicon trench 6. The dummy gate polysilicon 8 is located at the bottom of the closed-loop silicon trench 6, while the effective gate polysilicon 9 is located on the side of the dummy gate polysilicon 8 away from the conductive substrate 1. The dummy gate polysilicon 8 is located in the closed-loop silicon trench 6 at a position corresponding to the conductive epitaxial layer 2, while the effective gate polysilicon 9 is located in the closed-loop silicon trench 6 at a position corresponding to the P-well junction region 3. A dummy gate isolation oxide layer 73 is also disposed between the dummy gate polysilicon 8 and the effective gate polysilicon 9 to insulate and isolate them. An effective gate isolation oxide layer 74 is also disposed between the effective gate polysilicon 9 and the source lead metal 5 to insulate and isolate them. The insulating isolation oxide layer includes an effective gate oxide layer 71 and a dummy gate oxide layer 72 . The effective gate oxide layer 71 is arranged outside the effective gate polysilicon 9 , and the dummy gate oxide layer 72 is arranged outside the dummy gate polysilicon 8 .

[0061] Continue to refer to Figure 2 The source junction region 4 includes an N+ source junction region 41 and a P+ source junction region 42 alternately arranged along the length direction of the closed-loop silicon trench 6. Figure 3 and Figure 4An electrical connection slot 51 is provided on the source lead metal 5 at a position corresponding to the source junction region 4. The side of the source junction region 4 close to the source lead metal 5 is inserted into the electrical connection slot 51 and is in contact with the source lead metal 5. A protruding plug-in structure 52 is also formed on the source lead metal 5 at a position corresponding to the closed-loop silicon groove 6. The plug-in structure 52 is adapted to be inserted into the notch of the closed-loop silicon groove 6, and the plug-in structure 52 abuts against the effective gate isolation oxide layer 74. In this embodiment, the effective gate isolation oxide layer 74 is a pure oxide layer TEOS. The depth of the source junction region 4 ranges from 0.1 to 1 um, the depth of the P-well junction region 3 ranges from 1.0 to 4.0 um, and the depth of the top groove of the effective gate polysilicon 9 ranges from 0.2 to 1.0 um. After removing the depth of the top groove of the effective gate polysilicon 9, the depth of the effective gate polysilicon 9 ranges from 0.5 to 3 um. After removing the top trench depth of the effective gate polysilicon 9 and the depth of the effective gate polysilicon 9, the depth of the virtual gate polysilicon 8 ranges from 0.5 to 3 um. The trench gate width and the trench spacing are both 0.1 to 0.5 um. This design can ensure that the current channel can be fully opened when a positive voltage is applied to the effective gate polysilicon 9. The trench gate width and the trench spacing are both between 0.1 and 0.5 um. The size of the primitive cell is about 30% to 50% of the conventional primitive cell size in the prior art, which greatly increases the specific on-resistance of the source region, increases the current density of the source region, and reduces the area size of the source region. The length ratio of the N+ source junction region 41 and the P+ source junction region 42 alternately arranged along the length direction of the closed-loop silicon groove 6 is in the range of 1.0 to 10, which can ensure that the source region lead metal 5 is short-circuited to the P-well junction region 3 and the N+ source junction region 41 to ensure the avalanche performance of the trench dual-gate transistor.

[0062] The implementation principle of the trench dual-gate transistor cell structure of the embodiment of the present application is as follows: the trench dual-gate transistor cell structure of the present application utilizes an electrical connection slot 51 opened on the source region lead metal 5 to plug into the source junction region 4 to achieve electrical connection, without the need to open a contact hole on the source junction region 4 and the effective gate isolation oxide layer 74. The contact hole and the contact hole and trench gate gap structure are removed, which is equivalent to reducing the structural size of the cell. Without the contact hole and the contact hole and trench gate gap, the trench gate spacing in the cell structure can be reduced to 10%-30% of the original, and the cell density is increased by at least 50%. The current density of the trench dual-gate transistor is strongly positively correlated with the cell density, and the specific on-resistance increases by more than 50%. The area size of the transistor can be reduced by about 50%. This is an unprecedented optimization for the trench dual-gate transistor cell structure, which not only reduces the size of the trench dual-gate transistor, but also saves chip and packaging costs.

[0063] The present application also discloses a method for manufacturing the trench dual-gate transistor cell structure of the above embodiment, comprising the steps of: S1, preparing a conductive substrate 1, and depositing a conductive epitaxial layer 2 on one surface of the conductive substrate 1. In this embodiment, the conductive substrate 1 is a heavily doped silicon single crystal, and the conductive epitaxial layer 2 is a lightly doped silicon single crystal.

[0064] S2. Thermally grow a thermal oxide layer 101 with a thickness of 300-600Å on the surface of the conductive epitaxial layer 2 away from the conductive substrate 1.

[0065] S3. A pure oxide layer TEOS102 with a thickness of 2000-6000 Å is deposited on the surface of the thermal oxide layer 101 away from the conductive substrate 1 by chemical vapor deposition.

[0066] S4. Coat a photoresist 103 with a thickness of 7000-12000Å on the surface of the pure oxide layer TEOS 102 away from the conductive substrate 1, and use semiconductor dedicated equipment to expose and develop the photoresist 103 to open the photoresist 103 at the location where the groove is required to form a groove window 104.

[0067] S5, thermally bake the photoresist 103 to remove moisture inside the photoresist 103, so that the slot window 104 is more accurate and reliable, so that the photoresist 103 can better adhere to the pure oxide layer TEOS 102, and remove the pure oxide layer TEOS 102 and thermal oxide layer 101 at the slot window 104 by dry etching, so that part of the surface of the conductive epitaxial layer 2 is exposed. Figure 8 shown.

[0068] S6. Remove the photoresist 103 on the surface of the pure oxide layer TEOS 102 by a combination of dry and wet methods.

[0069] S7, using the pure oxide layer TEOS 102 and the thermal oxide layer 101 at the slot window 104 as hard masks, etching a closed-loop silicon groove 6 on the exposed surface of the conductive epitaxial layer 2, with a depth of 2-5 μm.

[0070] S8, using wet cleaning and dry cleaning to remove the groove deposits in the closed-loop silicon groove 6, and remove the pure oxide layer TEOS102 and thermal oxide layer 101 on the conductive epitaxial layer 2, as shown in FIG. Figure 9 Wet cleaning can use SC1, SC2, SC3 or HF acid, and dry cleaning can use CF4 gas.

[0071] S9. Thermally grow a sacrificial oxide layer with a thickness of 400-1000Å on the wall of the silicon trench, and remove the sacrificial oxide layer on the wall with HF acid to improve the state of the wall.

[0072] S10, thermally growing an oxide layer 105 with a thickness of 500-7000Å on the wall of the closed-loop silicon trench 6, and depositing polysilicon with a thickness of 5000-20000Å by chemical vapor deposition to fill the closed-loop silicon trench 6.

[0073] S11, dry-etching the polysilicon filled in the silicon trench to make the remaining polysilicon depth 0.5-3.0um, forming a dummy gate polysilicon 8, and exposing the oxide layer 105 above the dummy gate polysilicon 8 in the silicon trench to the surface. Figure 10 shown.

[0074] S12: Wet cleaning is performed to remove the etched deposits in the closed-loop silicon trench 6. HF acid is then used to clean and etch the oxide layer 105 above the dummy gate polysilicon 8 in the closed-loop silicon trench 6. The remaining oxide layer in the closed-loop silicon trench 6 is the dummy gate oxide layer 72. The wet cleaning method may be SC1, SC2, or SC3.

[0075] S13 , forming a dummy gate isolation oxide layer 73 on the upper surface of the dummy gate polysilicon 8 by chemical vapor deposition.

[0076] S14, thermally growing an effective gate oxide layer 71 with a thickness of 350-1000Å on the trench wall above the dummy gate isolation oxide layer 73 in the closed-loop silicon trench 6, with the thermal growth temperature being 950-1150°C.

[0077] S15. Deposit polysilicon on the dummy gate isolation oxide layer 73 in the closed-loop silicon trench 6 using chemical vapor deposition, with a deposition thickness of 5000-10000 Å.

[0078] S16, dry-etching the polysilicon deposited on the dummy gate isolation oxide layer 73 so that the remaining polysilicon is 0.2-1 μm away from the plane of the outer edge of the silicon trench, and the remaining polysilicon is the effective gate polysilicon 9, as shown in FIG. Figure 11 shown.

[0079] S17, using chemical vapor deposition to deposit a full-filled pure oxide layer TEOS on the upper surface of the effective gate polysilicon 9, and then dry-etching the pure oxide layer TEOS on the effective gate polysilicon 9, so that the thickness of the remaining pure oxide layer TEOS is half of the previous one, thereby obtaining an effective gate isolation oxide layer 74, and then removing the etched deposits in the closed-loop silicon groove 6 by wet cleaning, as shown in FIG. Figure 12 Wet cleaning can be done using SC1, SC2, or SC3.

[0080] S18, using semiconductor dedicated implantation doping equipment to implant conductive impurities into the conductive epitaxial layer 2 between the effective gate polysilicon 9, and diffuse the conductive impurities to form a P-well junction region 3, as shown in FIG. Figure 13 shown.

[0081] S19, coating the upper surface of the P-well junction area 3 with photoresist, and using semiconductor-specific equipment to expose and develop the photoresist, forming an implantation area and a barrier area for conductive impurities on the photoresist, and then using semiconductor-specific implantation doping equipment to implant the upper surface of the P-well junction area 3 with a high-dose conductive impurity of the required type through the implantation area, and then removing the photoresist by a combination of dry and wet methods, and then allowing the implanted high-dose conductive impurities to diffuse to form corresponding areas, such as the N+ source junction area 41 or the P+ source junction area 42, as shown in FIG. Figure 14 and Figure 15 shown.

[0082] S20, remove the particles remaining in the surface process by wet cleaning, and remove the effective gate oxide layer remaining on the upper surface by wet etching solution such as HF acid, so that the surface N+ source junction area 41 or P+ source junction area is exposed, such as Figure 16 and Figure 17 shown.

[0083] S21, forming a dummy gate contact hole 62 and an effective gate contact hole 63, as shown in FIG. Figure 2 The method of forming the dummy gate contact hole 62 and the effective gate contact hole 63 is conventional, so it will not be described in detail.

[0084] S22, using a semiconductor dedicated metal coating device to evaporate a 3-5um metal layer on the surface, and then coating the metal layer with photoresist. After exposure and development, the source lead metal 5 and the gate lead metal 61 are formed by etching to complete the production. Figure 2 、 Figure 3 and Figure 4 In this embodiment, the material of the metal layer is aluminum.

[0085] The manufacturing method of the trench dual-gate transistor cell structure of the embodiment of the present application is implemented as follows: the trench dual-gate transistor cell structure manufactured by the manufacturing method is electrically connected to the source junction region 4 by plugging the electrical connection slot 51 opened on the source region lead metal 5, without the need to open contact holes on the source junction region 4 and the effective gate isolation oxide layer 74. The contact holes and the contact hole and trench gate gap structure are removed, which is equivalent to reducing the structural size of the cell. Without the contact holes and the contact hole and trench gate gap, the trench gate spacing in the cell structure can be reduced to 10%-30% of the original, and the cell density is increased by at least 50%. The current density of the trench dual-gate transistor is strongly positively correlated with the cell density, and the specific on-resistance increases by more than 50%. The area size of the transistor can be reduced by about 50%. This is an unprecedented optimization for the trench dual-gate transistor cell structure, which not only reduces the size of the trench dual-gate transistor, but also saves chip and packaging costs.

[0086] The examples of this specific embodiment are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Identical components are represented by the same reference numerals. Therefore, any equivalent changes made based on the structure, shape, and principle of this application should be included in the scope of protection of this application.

Claims

1. A trench double-gate transistor cell structure, characterized in that: The invention comprises a conductive substrate (1), a conductive epitaxial layer (2), a P-well junction region (3), a source junction region (4) and a source region lead metal (5) which are stacked in sequence, a closed-loop silicon groove (6) is correspondingly opened on the conductive epitaxial layer (2), the P-well junction region (3) and the source junction region (4), an insulating isolation oxide layer is formed on the groove wall of the closed-loop silicon groove (6), a virtual gate polysilicon (8) and an effective gate polysilicon (9) are arranged in the closed-loop silicon groove (6), the virtual gate polysilicon (8) and the effective gate polysilicon (9) are both closed-loop structures adapted to the shape of the closed-loop silicon groove (6), the virtual gate polysilicon (8) is located at the bottom of the closed-loop silicon groove (6), the effective gate polysilicon (9) is located on the side of the virtual gate polysilicon (8) away from the conductive substrate (1), and the virtual gate polysilicon (8) is located in the closed-loop silicon groove (6) corresponding to the conductive substrate. The electrical epitaxial layer (2) is located at a position corresponding to the P-well junction region (3) in the closed-loop silicon groove (6); a virtual gate isolation oxide layer (73) is provided between the virtual gate polysilicon (8) and the effective gate polysilicon (9) to insulate and isolate the two; an effective gate isolation oxide layer (74) is provided between the effective gate polysilicon (9) and the source region lead metal (5) to insulate and isolate the two; the source junction region (4) includes an N+ source junction region (41) and a P+ source junction region (42) alternately arranged along the length direction of the closed-loop silicon groove (6); an electrical connection slot (51) is provided on the source region lead metal (5) at a position corresponding to the source junction region (4); a side of the source junction region (4) close to the source region lead metal (5) is inserted into the electrical connection slot (51) and is in contact with the source region lead metal (5).

2. The trench double-gate transistor cell structure according to claim 1, wherein: The depth of the source junction region (4) is in the range of 0.1-1 μm, the depth of the P-well junction region (3) is in the range of 1.0-4.0 μm, the depth of the top trench of the effective gate polysilicon (9) is in the range of 0.2-1.0 μm, the depth of the effective gate polysilicon (9) after excluding the top trench depth of the effective gate polysilicon (9) is in the range of 0.5-3 μm, the depth of the virtual gate polysilicon (8) after excluding the top trench depth of the effective gate polysilicon (9) and the depth of the effective gate polysilicon (9) is in the range of 0.5-3 μm, and the trench gate width and the trench spacing are both in the range of 0.1-0.5 μm.

3. The trench double-gate transistor cell structure according to claim 1, wherein: The length ratio of the N+ source junction region (41) and the P+ source junction region (42) alternately arranged along the length direction of the closed-loop silicon groove (6) is in the range of 1.0-10.

4. The trench double-gate transistor cell structure according to claim 1, wherein: A protruding plug-in structure (52) is also formed on the source region lead metal (5) at a position corresponding to the closed-loop silicon groove (6). The plug-in structure (52) is adapted to be plugged into the notch of the closed-loop silicon groove (6), and the plug-in structure (52) abuts against the effective gate isolation oxide layer (74).

5. The trench double-gate transistor cell structure according to claim 4, wherein: The effective gate isolation oxide layer (74) is a pure oxide layer TEOS.

6. The trench double-gate transistor cell structure according to claim 1, wherein: The source region lead metal (5) is made of metal aluminum.

7. The trench double-gate transistor cell structure according to claim 1, wherein: The conductive substrate (1) is a heavily doped conductive substrate, and the conductive epitaxial layer (2) is a lightly doped conductive epitaxial layer.

8. A method for manufacturing a trench double-gate transistor cell structure according to claim 1, characterized in that: The method comprises the following steps: S1, preparing a conductive substrate (1), and depositing a conductive epitaxial layer (2) on a surface of one side of the conductive substrate (1); S2, thermally growing a thermal oxide layer (101) with a thickness of 300-600 Å on the surface of the conductive epitaxial layer (2) away from the conductive substrate (1); S3, using a chemical vapor deposition method to deposit a pure oxide layer TEOS (102) with a thickness of 2000-6000 Å on the surface of the thermal oxide layer (101) away from the conductive substrate (1); S4, coating a photoresist (103) with a thickness of 7000-12000Å on the surface of the pure oxide layer TEOS (102) away from the conductive substrate (1), and exposing and developing the photoresist (103) using semiconductor-specific equipment to open the photoresist (103) at the location where the groove is to be formed, thereby forming a groove window (104); S5, thermally baking the photoresist (103) to remove moisture inside the photoresist (103), so that the slotted window (104) is more accurate and reliable, and the photoresist (103) can better adhere to the pure oxide layer TEOS (102), and removing the pure oxide layer TEOS (102) and the thermal oxide layer (101) at the slotted window (104) by a dry etching method, so that part of the surface of the conductive epitaxial layer (2) is exposed; S6, removing the photoresist (103) on the surface of the pure oxide layer TEOS (102) by a combination of dry and wet methods; S7, using the pure oxide layer TEOS (102) and the thermal oxide layer (101) at the slotted window (104) as hard masks, etching a closed-loop silicon groove (6) on the surface of the conductive epitaxial layer (2) where the closed-loop silicon groove (6) has a depth of 2-5 μm; S8, using wet cleaning and dry cleaning to remove the groove deposits in the closed-loop silicon groove (6), and remove the pure oxide layer TEOS (102) and the thermal oxide layer (101) on the conductive epitaxial layer (2); S9, thermally growing a sacrificial oxide layer with a thickness of 400-1000Å on the groove wall of the closed-loop silicon groove (6), and removing the sacrificial oxide layer on the groove wall with HF acid to improve the groove wall condition; S10, thermally growing an oxide layer (105) with a thickness of 500-7000Å on the wall of the closed-loop silicon groove (6), and depositing polysilicon with a thickness of 5000-20000Å to fill the closed-loop silicon groove (6) by chemical vapor deposition; S11, dry-etching the polysilicon filled in the closed-loop silicon groove (6) to a depth of 0.5-3.0 μm to form a virtual gate polysilicon (8), and exposing the oxide layer (105) above the virtual gate polysilicon (8) in the closed-loop silicon groove (6); S12, removing the etching deposits in the closed-loop silicon groove (6) by wet cleaning, and cleaning and etching the oxide layer (105) above the dummy gate polysilicon (8) in the closed-loop silicon groove (6) with HF acid. At this time, the remaining oxide layer in the closed-loop silicon groove (6) is the dummy gate oxide layer (72); S13, using chemical vapor deposition to deposit a virtual gate isolation oxide layer (73) on the upper surface of the virtual gate polysilicon (8); S14, thermally growing an effective gate oxide layer (71) with a thickness of 350-1000Å on the groove wall above the virtual gate isolation oxide layer (73) in the closed-loop silicon groove (6), with the thermal growth temperature being 950-1150°C; S15, depositing polysilicon on the virtual gate isolation oxide layer (73) in the closed-loop silicon trench (6) using a chemical vapor deposition method, with a deposition thickness of 5000-10000Å; S16, dry-etching the polysilicon deposited on the virtual gate isolation oxide layer (73) so that the remaining polysilicon is 0.2-1 μm away from the outer plane of the closed-loop silicon trench (6), and the remaining polysilicon is the effective gate polysilicon (9); S17, using chemical vapor deposition to deposit a completely filled pure oxide layer TEOS on the upper surface of the effective gate polysilicon (9), and then dry-etching the pure oxide layer TEOS on the effective gate polysilicon (9) so that the thickness of the remaining pure oxide layer TEOS is half of the previous thickness, thereby obtaining an effective gate isolation oxide layer (74), and then removing the etched deposits in the closed-loop silicon groove (6) by wet cleaning; S18, using a semiconductor dedicated implantation doping device, implanting conductive impurities into the portion of the conductive epitaxial layer (2) located between the effective gate polysilicon (9), and allowing the conductive impurities to diffuse to form a P-well junction region (3); S19, coating a photoresist on the upper surface of the P-well junction region (3), and using a dedicated semiconductor device to expose and develop the photoresist, forming an implantation region and a barrier region for conductive impurities on the photoresist, and then using a dedicated semiconductor implantation doping device to implant a high-dose conductive impurity of the desired type into the upper surface of the P-well junction region (3) through the implantation region, and then removing the photoresist by a combination of dry and wet methods, and then allowing the implanted high-dose conductive impurities to diffuse to form a corresponding N+ source junction region (41) or P+ source junction region (42); S20, removing particles remaining from the surface process by wet cleaning, and removing the effective gate oxide layer remaining on the upper surface by HF acid, so that the N+ source junction region (41) or the P+ source junction region (42) on the surface is exposed; S21, forming a dummy gate contact hole (62) and an effective gate contact hole (63); S22, using a semiconductor-specific metal coating device to evaporate a 3-5 μm metal layer on the surface, and coating the metal layer with photoresist, and after exposure and development, forming a source lead metal (5) and a gate lead metal (61) by etching.

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