A pentacene organic field effect transistor with improved fatigue resistance

Abstract

A kind of pentacene field effect transistor of improving anti-fatigue characteristic, n-type semiconductor layer and charge trapping layer with shallow energy level trap are arranged in pentacene field effect transistor structure;Device has bottom gate type structure: gate electrode / gate insulating layer / n-type semiconductor film / charge trapping dielectric layer with shallow energy level trap / tunneling layer / pentacene / source (drain) electrode;Gate electrode is conductor, resistivity is between 0.1-0.001 Ω·cm;Gate insulating layer dielectric film is insulator, thickness range is 5-150nm;The thickness of n-type semiconductor film layer is 1-200nm;Charge trapping dielectric layer with shallow energy level hole trap, thickness is 1-100nm;Tunneling layer is insulator, thickness range is 1-20nm;Pentacene thickness range is 1-100nm;Source-drain electrode is conductor, thickness range is 50-200nm;Gate electrode is conductor.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a pentacene organic field-effect transistor with improved fatigue resistance. Background Technology

[0002] Over the past two decades, non-volatile electronic devices based on organic field-effect transistors have received considerable attention due to their promising applications in fields ranging from radio frequency identification tags to flexible and large-area displays [1, 2]. To promote the practical application of organic field-effect devices, researchers have devoted considerable effort to studying charge-trapping materials such as p-type channel materials, n-type channel materials, and polymers. As one of the most promising p-type channel materials, pentacene, a small-molecule semiconductor material with a planar molecular structure of five benzene rings, has been widely used in the structural research of organic semiconductor field-effect devices. Studies have shown that polystyrene (PS), poly(2-vinylnaphthalene) (PVN), and poly(α-methylstyrene) (PαMS), when used as charge-trapping media in memory devices, exhibit large storage windows in their transfer characteristic curves at very high operating voltages [3]. In pentacene organic field-effect transistors using PαMS as the charge storage medium, Baeg et al. used a 200V / 1μs pulse voltage for programming and a -100V / 1μs pulse for erasing [1]. In pentacene organic field-effect transistors using styrene-poly(4-vinylpyridine) block copolymer (PS-b-P4VP) as the charge trapping medium, Leong et al. used a -30V / 1s pulse for programming and a 100V / 30s pulse for erasing [4]. Programming / erasing pentacene organic field-effect transistors with such high pulse amplitudes or such long pulse widths does not meet the industrial standards for modern electronic device applications. Therefore, pentacene organic field-effect transistors using polymer films as the charge trapping medium have not yet been practically applied.

[0003] In the context of pentacene organic field-effect transistor devices using polymer thin films as charge-trapping media, a variety of fundamental studies have been conducted. Theoretical and experimental studies [5, 6] have shown that positively charged defects related to the external environment (such as hydrogen and oxygen) exist near the pentacene grain boundaries in the pentacene thin film at the pentacene / polymer interface, with a bulk charge density as high as 4 × 10⁻⁶. 18 cm -3[7]. The positively charged defect layer is about 1.5 nm thick. Due to the formation of defects, this thin layer no longer has semiconductor properties. The electric field formed by the positive charge of this thin layer points towards the p-type semiconductor pentacene thin film, which hinders the migration of holes in the pentacene thin film into the polymer film. This positively charged defect layer acts as a positive charge barrier. The existence of this positive charge barrier leads to the high operating voltage of the pentacene organic field-effect memory device that uses the polymer film as the charge trapping medium.

[0004] This invention group's Chinese invention patent application, CN201911336850.8, "A method for enhancing the performance of a pentaphenyl organic field-effect transistor and the structure of a pentaphenyl organic field-effect transistor," and US invention patent application, 20255CJH, "A method for enhancing the performance of a pentaphenyl organic field-effect transistor and the structure of a pentaphenyl organic field-effect transistor," describes an n-type semiconductor thin film transition layer disposed between the polymer dielectric and the pentaphenyl in an organic field-effect transistor device with a structure of gate electrode / insulating layer / polymer dielectric film / pentaphenyl / source and drain electrodes. The thickness of the n-type semiconductor transition layer is 1-100 nm. The n-type semiconductor thin film is a crystalline thin film, a semi-crystalline thin film, or an amorphous thin film. By reducing the hole barrier height at the interface between pentacene and the charge-trapping dielectric through induced electrons at the interface in the n-type semiconductor transition layer, the programming / erasing operating voltage of the pentacene organic semiconductor transistor is effectively reduced. Furthermore, by preventing the escape of trapped positive charges (holes) from the polymer dielectric film to the pentacene film through the positively charged space charge region formed by ionized donors in the n-type semiconductor transition layer, the programming / erasing reliability and data retention capability of the pentacene organic semiconductor transistor device are improved, thereby enhancing the operating performance of the pentacene organic field-effect transistor.

[0005] This invention group's Chinese invention patent application CN202011153410.1, "An n-type semiconductor intercalated pentacene organic field-effect transistor and its application," and US invention patent application 20256CJH, "A PENTACENE ORGANIC FIELD-EFFECT TRANSISTOR WITH N-TYPE SEMICONDUCTOR INTERLAYER AND ITS APPLICATION," describe a method for improving the performance of a pentacene organic field-effect transistor memory device. The organic field-effect transistor device has a bottom-gate structure: from bottom to top, it consists of a gate electrode / insulating layer / polymer dielectric film / pentacene / source and drain electrodes; or a top-gate structure: from bottom to top, it consists of source and drain electrodes / pentacene / polymer dielectric film / insulating layer / gate electrode. An n-type semiconductor film is added between the polymer dielectric film and the pentacene as a transition layer; the n-type semiconductor film is an n-type inorganic semiconductor film or an n-type organic semiconductor film, with a thickness of 1-100 nm. The thickness of the pentacene electrode is 1-100 nm; the thickness of the source and drain electrodes is 50-200 nm. n-type semiconductor thin films are specifically divided into n-type small molecule thin films and n-type polymer thin films, such as NN”-di-3-n-pentyl-3,4,9,10-perylene diimide (PTCDI-C13), NN”-di-n-tetrazyl-3,4,9,10-perylene diimide (EP-PDI), and NN”-diphenyl-1,4,5,8-naphthyl diimide (NDI). n-type semiconductor thin films can be crystalline, semi-crystalline, or amorphous.

[0006] By reducing the hole barrier height at the interface between pentacene and the polymer dielectric through induced electrons at the interface of the n-type semiconductor intercalation layer, the programming / erasing operating voltage of the pentacene organic semiconductor transistor is effectively reduced. By adjusting the number of n-type charge carriers in the n-type semiconductor intercalation layer, the hole barrier height at the interface between pentacene and the polymer dielectric is adjusted to a reasonable range, enabling the pentacene organic field-effect transistor device to have a lower operating voltage, faster programming / erasing speed, better programming / erasing reliability, and better data retention capability, thereby improving the operating performance of the pentacene organic field-effect transistor.

[0007] In a pentacene OFET memory device using a polymer electret as the charge trapping medium, during programming, holes are driven by the electric field generated by the negative gate voltage to cross the interface barrier from the pentacene and enter the polymer electret. They are then captured by the shallow and deep level traps within the polymer and confined therein. The device's transfer characteristic curve at this point is illustrated in the diagram. Figure 1As shown in curve II, during the erase operation, a positive gate voltage is applied to the device. Some holes trapped in the shallow level receive the electric field energy provided by the positive gate voltage and are driven back into the pentacene channel. However, holes remaining in the deep level traps may not be released due to insufficient excitation energy and remain trapped in the deep trap levels of the polymer dielectric. During this repeated programming / erasing cycle, holes are continuously trapped in the empty deep level traps and cannot return to the pentacene channel. This physical characteristic is reflected in the macroscopic measurement data of the OFET device as follows: under a positive erase pulse, the device transfer characteristic curve cannot return to the position of the curve after the initial erase operation. Figure 1 As shown in curve I in the diagram, the threshold voltage deviates to a certain extent compared to it, as illustrated in the diagram. Figure 1 I in deg As shown. At this time, the same source-drain voltage is applied, and the current I between the source and drain of the device is read at the same gate voltage. DS You will find the device's I DS The rate of decrease is likely the fundamental reason for the degradation of fatigue resistance in pentacene OFET memory devices. Correspondingly, under the same programming pulse, holes driven from the pentacene channel into the polymer fill the remaining empty defect levels. Overall, the amount of charge captured in the polymer electret is not significantly different, and the transfer characteristic curve of the OFET memory device will basically coincide with the curve after the initial programming operation. Figure 1 As shown in curve II, the I reading from the source-drain electrode of the device at this time... DS There won't be any significant changes.

[0008] Due to the presence of various deep defect energy levels in polymer charge-trapping media (such as polystyrene (PS), poly(2-vinylnaphthalene) (PVN), poly(α-methylstyrene) (PαMS), etc.), these defects may originate from chemical defects in the polymer. These chemical defects in the polymer may include side chain defects, unsaturated chemical bonds, oxidized groups, additives and impurities, etc. [8], most pentacene organic field-effect transistors using polymers as charge-trapping media will experience a sharp decrease in the ratio of the on-state to the off-state current through the source and drain electrodes after hundreds of combined programming / erasing pulse gate voltage operations, resulting in a severe degradation of the device's endurance characteristics, making the device unsuitable for practical applications. [9-11]

[0009] References:

[0010] 1.Baeg,K.,-J,Noh,Y.Y.,Ghim,J.,Kang,S.J.,Lee,H.Kim,D.Y., Organic Non-volatile Memory Based on Pentancene Field-Effect Transistors Using aPolymeric Gate Electret.,Adv.Mater.18,3179-3183(2006).

[0011] 2.Dimitrakopoulos,C.D.&Malenfant,P.R.Adv.Mater.14, 99-117(2002).

[0012] 3.Baeg,K.,J.,Noh Y.Y.,Ghim J.,Lim B.,Kim D.Y.,Polarity Effects ofPolymer Gate Electrets on Non-Volatile Organic Field-Effect TransistorMemory,Adv.Funct.Mater.18,3678-3685(2008).

[0013] 4.Leong,W.L.,Mathews,N.,Mhaisalkar,S.,Lam Y.M.,Chen,T.,Lee, S.,Micellar poly(styrene-b-4-vinypyridine)-nanoparticle hybrid system for non-volatile organic transistor memory,J.Mater.Chem.19,7354-7361(2009).

[0014] 5.Knipp,D,Street,R.A.,Volkel,A.and Ho,J.,Pentacene thin filmtransistors on inorganic dielectrics:Morphology,structural properties,andelectronic transport,J.Appl.Phys.93,347-355(2003).

[0015] 6.Northrup J.E.,Chabinyc M.L.,Gap states in organic semiconductors:Hydrogen-and Oxygen-induced states in pentacene,Phys.Rev.B 68,041202(R):1-4(2003).

[0016] 7.Kalb,W.L.,Mattenberger,K.and Batlogg,B.,Oxygen-related traps inpentacene thin films:Energetic position and implications for transistorperformance,Phys.Rev.B,78,035334:1-11(2008).

[0017] 8.G.Teyssedre,F.H.Zheng,L.Boudou,and C.Laurent,Charge trapspectroscopy in polymer dielectrics:a critical review,J.Phys.D:Appl.Phys.54,263001(2021).

[0018] 9.Hsu,J.-C.,Lee,W.-Y.,Wu,H.-C.,Sugiyama,K.,Hirao A.,&Chen, W.-C.Nonvolatile memory based on pentacene organic field-effect transistors withpolystyrenepara-substituted oligofluorene pendent moieties as polymerelectrets.J.Mater.Chem.22,5820(2012).

[0019] 10.Li,W.,Guo,FN,Ling,HF,Zhang,P.,Yi,MD,Wang,LY, Wu,DQ,Xie,LH&Huang,W.High-Performance Nonvolatile Organic Field-Effect TransistorMemory Based on Organic Semiconductor Heterostructures of Pentacene / P13 / Pentacene as Both Charge Transport and Trapping Layers.Adv Sci. 4, 1700007 (2017).

[0020] 11.Yu,Y.,Bian,LY,Chen,JG,Ma,QH,Li,YX,Ling,HF,Feng,QY,Xie,LH,Yi,MD&Huang,W.4,5-Diazafluorene-Based Donor–Acceptor SmallMolecules as Charge Trapping Elements for Tunable Nonvolatile OrganicTransistor Memory.Adv.Sci.5,1800747(2018). Summary of the Invention

[0021] The purpose of this invention is to address the aforementioned problems by proposing a pentacene organic field-effect transistor (FET) with improved fatigue resistance, thereby promoting its practical application. In Chinese invention patent CN201911336850.8 and US invention patent application 20255CJH, our team proposed a method for improving the performance of pentacene organic field-effect transistor memory devices by introducing an n-type semiconductor transition layer at the pentacene / polymer interface. In Chinese invention patent CN202011153410.1 and US invention patent application 20256CJH, we proposed a method for improving the performance of pentacene organic field-effect transistor memory devices by introducing an n-type semiconductor intercalation layer at the polymer / insulator interface. Building upon these methods, we further propose a method that replaces the polymer dielectric in the original pentacene organic field-effect transistor with a charge-trapping dielectric having shallow energy level traps, further improving its fatigue resistance while maintaining other excellent device performance, thus promoting its practical application.

[0022] The technical solution of this invention is a transistor that improves the fatigue resistance of a pentacene organic field-effect transistor. The charge-trapping dielectric layer in the pentacene organic field-effect transistor device has a large number of shallow-level hole traps, and the device exhibits... Figure 2 The bottom-gate structure shown consists of: gate electrode / gate insulating layer / n-type semiconductor thin film / charge-trapping dielectric layer with shallow level traps / tunneling layer / pentaphenyl / source (drain) electrode; gate electrode 1 is a conductor with a resistivity between 0.1-0.001 Ω·cm; gate insulating layer dielectric thin film 2 is an insulator with a thickness ranging from 5-150 nm; n-type semiconductor thin film layer 3 has a thickness of 1-200 nm; charge-trapping dielectric layer 4 with shallow level hole traps has a thickness of 1-100 nm; tunneling layer 5 is an insulator. The thickness ranges from 1 to 20 nm; the thickness of pentacene 6 ranges from 1 to 100 nm; the source and drain electrodes 7 and 8 are conductors with a resistivity between 0.1 and 0.001 Ω·cm and a thickness range of 50 to 200 nm; another type is the top-gate type, which, from bottom to top, consists of source (drain) electrode / pentacene / tunneling layer / shallow level hole trap charge trapping dielectric layer / n-type semiconductor thin film / gate insulating layer / gate electrode, and is also included; the two types are essentially the same, so both structures fall within the scope of this invention.

[0023] The gate electrode can be a metal, a conductive nitride, or a conductive oxide material; the gate electrode of a bottom-gate field-effect transistor can also be a semiconductor material such as n-type heavily doped high-conductivity silicon or p-type heavily doped high-conductivity silicon; the gate electrode of a bottom-gate field-effect transistor can also be a flexible substrate with a conductive coating.

[0024] The gate insulating layer dielectric film can be an insulator such as silicon dioxide or aluminum oxide, and its function is to prevent the charge trapped by the n-type semiconductor film from escaping to the gate electrode; the gate insulating layer dielectric film can also be a polymer insulator, such as PMMA or P(VDF-TrFE).

[0025] n-type semiconductor thin films provide mobile n-type charge carriers (electrons) with a certain carrier concentration; based on the electrostatic induction effect, the hole barrier height at the interface between the pentene and the insulating layer is reduced by the induced electrons near the interface of the n-type semiconductor, effectively reducing the programming / erasing operating voltage of the pentene organic semiconductor transistor.

[0026] n-type semiconductor thin films are n-type inorganic semiconductor thin films, including zinc selenide (ZnSe). 1-x ), or zinc sulfide (ZnS) 1-x ), or zinc oxide (ZnO) 1-x x is between 0.001 and 0.5; or indium gallium zinc oxide (IGZO), or oxygen-deficient oxide thin films, or oxygen-deficient composite oxide thin films, such as ZrHfO. 2-δetc.; or metal nitrides, such as TiO2 x N y etc.; however, n-type semiconductor thin films are not limited to the above-mentioned organic thin films; the preparation methods include magnetron sputtering, thermal evaporation, or electron beam evaporation, and the thickness ranges from 1 to 200 nm. They are crystalline or amorphous thin films.

[0027] n-type semiconductor thin films can also be n-type organic small molecule semiconductor thin films, such as NN”-di-3-n-pentyl-3,4,9,10-perylenediimide (PTCDI-C13) and NN”-di-n-tetrazyl-3,4,9,10-perylenediimide (EP-PDI), but are not limited to the above-mentioned organic thin films; n-type semiconductor thin films can be crystalline, semi-crystalline, or amorphous thin films. Methods for preparing n-type organic semiconductor thin films include solution methods, such as spin-coating, sol-gel, spraying, screen printing, inkjet printing, thermal evaporation, or other similar physical and chemical thin film preparation methods; their thickness ranges from 1 to 100 nm.

[0028] n-type semiconductor thin films can also be composite structures of two n-type semiconductors; they can be formed by preparing an n-type inorganic semiconductor thin film on the surface of an n-type organic semiconductor thin film, or by preparing an n-type inorganic semiconductor thin film on the surface of an n-type organic semiconductor thin film; the thickness of the n-type organic semiconductor thin film in the composite structure film ranges from 0.5 to 60 nm, the thickness of the n-type inorganic semiconductor thin film ranges from 0.5 to 60 nm, but the thickness of the composite structure film ranges from 1 to 100 nm; n-type semiconductor thin films can also be combinations of multilayer inorganic semiconductor thin films and organic semiconductor thin films.

[0029] Charge-trapping dielectric layers with shallow energy level traps play a hole-trapping role in organic field-effect transistor structures. They can be polymer dielectric films with shallow energy level traps; organic small molecule dielectric films with shallow energy level traps; or inorganic dielectric films with shallow energy level traps.

[0030] The charge trapping dielectric film with shallow energy level traps allows the stored charges (holes) to be completely de-trapped under a positive pulsed gate voltage, or the vast majority of the stored charges (holes) to be de-trapped under a positive pulsed gate voltage; or in other words, the charge (hole) traps in the aforementioned charge trapping dielectric film are primarily shallow energy level traps, with extremely low density of deep energy level traps.

[0031] In theory, n-type semiconductors are ideal hole-trapping media.

[0032] The charge trapping layer dielectric with shallow energy level traps can be an n-type inorganic semiconductor thin film, including zinc selenide (ZnSe). 1-x ), or zinc sulfide (ZnS) 1-x ), or zinc oxide (ZnO) 1-x x is between 0.001 and 0.5; or indium gallium zinc oxide (IGZO), or oxygen-deficient oxide thin films, or oxygen-deficient composite oxide thin films, such as ZrHfO. 2-δ etc.; or metal nitrides, such as TiO2 x N y etc.; however, n-type semiconductor thin films are not limited to the above-mentioned organic thin films; the preparation methods include magnetron sputtering, thermal evaporation, or electron beam evaporation, and the thin films are crystalline or amorphous.

[0033] The charge trapping dielectric layer with shallow energy level traps can also be an n-type organic small molecule semiconductor thin film, such as NN”-di-3-n-pentyl-3,4,9,10-perylene diimide (PTCDI-C13), NN”-di-n-tetrazyl-3,4,9,10-perylene diimide (EP-PDI), etc., but not limited to the above-mentioned organic thin films; the n-type organic small molecule semiconductor thin film can be a crystalline thin film, a semi-crystalline thin film, or an amorphous thin film.

[0034] The charge trapping dielectric layer with shallow energy level traps can also be an n-type organic polymer semiconductor thin film, such as poly-{[N,N'-bis(2-octyldodecyl)naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5'-(2,2'-bithiophene)}(N2200), but is not limited to the above-mentioned organic thin films; the n-type organic polymer semiconductor thin film can be a crystalline thin film, a semi-crystalline thin film, or an amorphous thin film.

[0035] The preparation methods of n-type organic small molecule semiconductor thin films and n-type organic polymer semiconductor thin films include solution methods, such as spin-coating, sol-gel, spray, silk-screen printing, ink-jetting, thermal evaporation, or other similar physical and chemical thin film preparation methods; their thickness ranges from 1 to 100 nm.

[0036] The charge-trapping dielectric layer with shallow energy level traps can also be a composite thin film of two n-type semiconductors; it can be an n-type inorganic semiconductor thin film prepared on the surface of an n-type organic semiconductor thin film, or an n-type inorganic semiconductor thin film prepared on the surface of an n-type organic semiconductor thin film; the thickness of the n-type organic semiconductor thin film in the composite structure film ranges from 0.5 to 60 nm, the thickness of the n-type inorganic semiconductor thin film ranges from 0.5 to 60 nm, but the thickness of the composite structure film ranges from 1 to 100 nm; the n-type semiconductor thin film can also be a combination of multilayer inorganic semiconductor thin films and organic semiconductor thin films; but it is not limited to the above-mentioned film combination methods;

[0037] Methods for preparing pentacene thin films include solution methods, such as spin-coating, sol-gel, spray, silk-screen printing, ink-jetting, thermal evaporation, or other similar physical and chemical thin film preparation methods; the thickness ranges from 1 to 50 nm.

[0038] The tunneling layer between the pentacene film and the charge-trapping dielectric film with shallow energy level traps can be an insulator such as silicon dioxide or aluminum oxide. Its function is to prevent hole carriers from returning to or escaping into the pentacene film after the external voltage is removed, after the electric field drives holes from the pentacene to the charge-trapping dielectric film. The tunneling layer between the pentacene and the charge-trapping dielectric film with shallow energy level traps can also be a polymer insulator, such as PMMA or P(VDF-TrFE), with a thickness between 1 nm and 20 nm.

[0039] The organic field-effect transistor (OFET) memory device obtained by the method has a bottom-gate structure: from bottom to top, it consists of gate electrode / gate insulating layer / n-type semiconductor thin film / charge trapping dielectric layer with shallow energy level traps / tunneling layer / pentaphenyl / source (drain) electrode; the organic field-effect transistor device may also have a top-gate structure: from bottom to top, it consists of source (drain) electrode / pentaphenyl / tunneling layer / charge trapping dielectric layer with shallow energy level traps / n-type semiconductor thin film / gate insulating layer / gate electrode.

[0040] In n-type semiconductor thin films, induced charges (electrons) are generated by the electrostatic interaction of the positively charged interface layer near the tunneling layer interface of pentacene. These electrons are attracted to the interface near the charge-trapping layer, resulting in a high density of electrons. Meanwhile, ionized donors within the n-type semiconductor film form a positively charged space charge region. The high concentration of electrons at the charge-trapping layer / n-type semiconductor interface significantly reduces the overall positive electric field strength at the pentacene / tunneling layer interface, thereby significantly lowering the hole barrier height at the pentacene-tunneling layer interface. This significant reduction in the hole barrier height effectively lowers the operating voltage required to drive hole carriers from pentacene into the charge-trapping dielectric layer or back from the charge-trapping dielectric layer to the pentacene film, thus effectively reducing the programming / erasing voltage of organic semiconductor field-effect transistor devices.

[0041] The purpose of setting a tunneling layer thin film between pentacene and the charge trapping dielectric layer is to prevent holes that were originally accumulated (or trapped) in the charge trapping dielectric layer from returning to the pentacene thin film after the external pulse gate voltage is removed, thereby improving the retention characteristics of pentacene organic semiconductor field-effect transistor memory devices.

[0042] The purpose of using a charge-trapping dielectric layer with shallow defect energy levels is to allow holes trapped in the charge-trapping dielectric with shallow defect energy levels to be released and returned to the pentphenyl channel at a lower positive pulse gate voltage during erasing operations. After multiple program / erase operations, the threshold voltage of the erase operation transfer characteristic curve does not change or only changes slightly compared to the initial erase operation curve. This results in no change or only slight decay in the on-state / off-state current ratio read out by electrical methods, thereby improving the fatigue resistance of the pentphenyl field-effect transistor.

[0043] Beneficial effects: In organic field-effect transistor devices with a structure of gate electrode / gate insulating layer / n-type semiconductor thin film / charge trapping dielectric layer with shallow energy level traps / tunneling layer / pentaphenyl / source (drain) electrode, using a dielectric thin film that does not contain deep energy level traps, such as those in polymer dielectrics, or has an extremely low density of deep energy level traps as the hole trapping medium can effectively prevent holes from being trapped by deep energy level traps in the charge trapping medium during repeated programming / erasing operations. This prevents the threshold voltage of the device transfer characteristic curve from shifting after multiple programming / erasing cycles, thus degrading the device's fatigue resistance. Attached Figure Description

[0044] Figure 1 A schematic diagram illustrating the fatigue resistance degradation of an existing 5-pin MOSFET device, showing its transfer characteristics.

[0045] Figure 2 The present invention presents a schematic diagram of a pentacene organic field-effect transistor structure with a shallow-level trapping medium as the charge trapping layer, wherein 1 is the gate electrode, 2 is the gate insulating layer dielectric, 3 is an n-type semiconductor thin film, 4 is the charge trapping medium with shallow-level trapping, 5 is the tunneling layer thin film, 6 is pentacene, and 7 and 8 are the source and drain electrodes, respectively.

[0046] Figure 3 A schematic diagram of the pentacene OFET device structure using PVN as the charge trapping medium according to the present invention.

[0047] Figure 4 Transfer characteristic curves of a pentacene OFET device using PVN as the charge trapping medium.

[0048] Figure 5a , Figure 5b The fatigue resistance curve of a pentacene OFET device with PVN as the charge trapping medium. Figure 5a ), and the transfer characteristic curves before and after fatigue resistance testing ( Figure 5b ).

[0049] Figure 6a , Figure 6b and Figure 6c The pentacene OFET device with PVN as the charge trapping medium underwent 200 fatigue cycles in dark conditions, and subsequent tests were performed at 635nm. Figure 6a ), 532nm Figure 6b ) and 375nm ( Figure 6c Figure showing the results of fatigue resistance test under monochromatic light irradiation.

[0050] Figure 7a , Figure 7b , Figure 7c The transfer characteristic curves of the OFET device with PVN as the charge trapping medium under dark conditions and under illumination conditions of 635nm, 532nm and 375nm (after 30 minutes) are shown in Figure 7a. Figure 7b , Figure 7c As shown.

[0051] Figure 8 Schematic diagram of trap energy levels and their density distribution in PVN.

[0052] Figure 9 Transfer characteristic curves of OFET devices using N2200 as the charge trapping medium.

[0053] Figure 10a , Figure 10b OFET devices using N2200 as the charge trapping dielectric under dark conditions ( Figure 10a) and monochromatic light at 635nm, 532nm and 375nm ( Figure 10b The graph shows the change in the leakage current of the erase state source during 16,000 consecutive programming / erasing cycles of the device under irradiation.

[0054] Figure 11 The figure shows the transfer characteristic curves of a pentphenyl OFET device using an oxygen-deficient zinc oxide thin film as the charge trapping medium.

[0055] Figure 12 The programming / erasing (fatigue resistance) characteristic curves of a pentacene OFET device using an oxygen-deficient zinc oxide thin film as the charge trapping medium are shown.

[0056] Figure 13 The programming / erasing (fatigue resistance) characteristic curves of a pentphenyl OFET device with an oxygen-deficient zinc oxide thin film as the charge trapping medium and aluminum oxide as the tunneling layer are shown.

[0057] Figure 14 The programming / erasing (fatigue resistance) characteristic curves of the device. Detailed Implementation

[0058] Example 1

[0059] To conduct a comparative experiment, a pentacene OFET device with PVN as the charge trapping medium was first fabricated, and its structural schematic diagram is shown below. Figure 3 As shown. <100> The gate electrode is made of heavily doped p-Si with a resistivity of less than 0.005 Ω·cm; the gate insulating layer is made of thermally oxidized silicon dioxide with a thickness of 90 nm; the n-type semiconductor layer is made of oxygen-deficient zinc oxide (ZnO) with a thickness of 20 nm; the charge trapping medium is made of PVN with a thickness of 10 nm; the tunneling layer insulating medium is made of polymethyl methacrylate (PMMA) with a thickness of 4 nm; the thickness of pentacene is 40 nm; and the source and drain electrodes are made of copper film with a thickness of 80 nm.

[0060] The specific preparation process steps are as follows:

[0061] A 90 nm thick p-Si substrate covered with thermally oxidized SiO2 was ultrasonically cleaned for 10 minutes each with acetone, ethanol, and deionized water, and then dried with a nitrogen gun. A 20 nm thick zinc oxide (ZnO) film was grown on the p-Si substrate using magnetron sputtering. To maximize oxygen vacancies in the ZnO and thus increase carrier concentration and defect level density, pure argon was used as the sputtering gas. Due to the presence of oxygen vacancies, the ZnO film exhibited n-type semiconductor characteristics. A 2 mg / mL PVN toluene solution was spin-coated onto the ZnO film at 4000 rpm for 60 seconds, followed by drying at 80°C in a glove box for 30 minutes. Then, a 40 nm thick pentacene film was prepared using thermal evaporation with the aid of a mask at a growth rate of [missing information]. Finally, using the same thermal evaporation process with the aid of another mask, an 80 nm thick Cu film was prepared as the source and drain electrodes, with a growth rate of [missing information].

[0062] Next, a 4 nm PMMA layer was grown as a tunneling layer on a ZnO-grown substrate using spin coating. 10 mg of PMMA powder was weighed, and 10 ml of toluene was measured using a graduated cylinder as the solvent. The mixture was stirred at a constant temperature of 50 °C for 8 hours to prepare a 1 mg / ml PMMA solution. The PMMA solution was then spin-coated at a high speed of 3000 rpm for 60 seconds and annealed at a constant temperature of 80 °C for 30 minutes.

[0063] Next, a 40 nm pentacene was grown on the above-mentioned substrate after PMMA growth using a vacuum thermal evaporation method.

[0064] A copper (Cu) electrode with a side length of 300 μm and a thickness of 80 nm was grown on the sample after the growth of pentane was completed using a vacuum thermal evaporation method.

[0065] Use a diamond cutter to scribble a corner of the above device onto the substrate until p-Si is exposed, which serves as the gate electrode.

[0066] The electrical performance of the fabricated device was tested using a Keithley 4200 (4200-SCS) semiconductor analysis system. By testing the response relationship between current and applied voltage, the performance parameters of the device, such as output characteristics, transfer characteristics, erase / write speed, fatigue resistance, and retention performance, were analyzed.

[0067] The switching process of the device is as follows: During operation, a certain voltage is applied between the two adjacent Cu electrodes, i.e., the source and drain electrodes. If there is no gate voltage or the gate voltage is very small, the current in the pentoxide between the source and drain electrodes is usually very small, and the current characteristics are similar to those of an insulator, so the device is in the off state. When a sufficiently high voltage is applied to the gate electrode, a conductive channel is generated at the interface of the pentoxide near the insulating layer, and the current between the source and drain electrodes increases rapidly, causing the device to conduct and become the on state. In this way, the device realizes the switching process.

[0068] Figure 4 This is a transfer characteristic diagram of a pentacene OFET device with PVN as the charge trapping medium. At a lower operating voltage, the threshold voltage of the programming and erasing curves of the device shows a large offset, that is, the device has a large storage window.

[0069] Figure 5a This is the fatigue resistance characteristic curve of the device. Under a pulse gate voltage of ±30V / 1s, after 200 erase / program operation cycles, due to the shift in the threshold voltage of the erase state transition characteristic curve, the source-drain current in the erase state of the device increases from 9.6*10... -7 A decays to 7.2*10 -9 A. Figure 5b These are the transfer characteristic curves of the device before and after fatigue resistance testing, from... Figure 5b As can be seen, the threshold voltage shifts by 1.3V between the transition characteristic curves of the erased state before and after the fatigue resistance test. Using the formula:

[0070]

[0071] (where C) i It is the capacitance per unit area of ​​the gate dielectric (e is the basic unit of charge). It can be estimated that 9.3% of the charge (holes) trapped by the PVN dielectric before the start of the fatigue test cannot be released under a positive gate voltage.

[0072] We used photo-induced excitation to test the hole traps and their density distribution in PVN thin films, as follows. Theoretically, holes trapped in deep-level traps with a depth of -E0 can be excited by physical light with a single-photon energy greater than or equal to E0, and transferred to the pentacene channel under a suitable positive gate voltage; this is the photo-induced erase operation. We performed 200 fatigue tests on the above-mentioned pentacene OFET device under dark conditions, followed by subsequent fatigue tests under monochromatic light irradiation at 635nm, 532nm, and 375nm. The results are as follows. Figure 6a As shown in 6b and 6c.

[0073] from Figure 6aAs can be seen, under 635nm monochromatic light (corresponding to photons with an energy of 1.95eV), the current between the source and drain of the device continues to decrease after repeated programming / erasing operations. This means that holes excited in traps with a depth of less than 1.95eV are captured by traps at deeper energy levels in the PVN. Furthermore, it can be observed that in the fourth 200-programming / erasing cycle, the current between the source and drain of the device continues to decrease after repeated programming / erasing operations, and the current minimum also continues to decrease. This indicates that more holes excited in traps with a depth of less than 1.95eV are captured by traps at deeper energy levels in the PVN.

[0074] from Figure 6b As can be seen, under 532nm monochromatic light (corresponding to photons with energy of 2.33eV), the current between the source and drain of the device shows a change after repeated programming / erasing operations. Figure 5a The consistent trend means that the holes excited in traps with a depth of less than 2.33 eV are captured by traps at deeper energy levels in the PVN, indicating that there are many deeper traps in the PVN.

[0075] from Figure 6c As can be seen, under the illumination of monochromatic light at 375nm (corresponding to photons with energy of 3.31eV), the current between the source and drain of the device reaches its maximum value after repeated programming / erasing operations, and its peak value remains almost unchanged with only a very small decrease. This means that there are still traps deeper than 3.31eV in the PVN, but the density is extremely low.

[0076] We tested the transfer characteristics of another fresh OFET device under dark conditions and under illumination conditions of 635nm, 532nm, and 375nm (after 30 minutes), and the results are as follows. Figure 7a As shown in 7b and 7c. From Figure 7a From 7b and 7c, we can obtain that the storage windows of the devices after illumination are 15.9V, 18V, and 21.8V, respectively. According to formula (1), the areal density of hole traps in the PVN corresponding to illumination conditions of 635nm, 532nm, and 375nm are 2.13 × 10⁻⁶, respectively. 12 cm -2 2.41×10 12 cm -2 and 2.92×10 12 cm -2 Therefore, we can obtain the distribution map of hole traps in PVN as follows: Figure 8 As shown. From Figure 8We can clearly see that the highest density of hole traps exists in PVN within the excitation wavelength range of 532-375nm (2.33-3.71eV). The holes trapped in these traps cannot be released under the operating voltage used in our devices, meaning they cannot be erased. This is the direct cause of the degradation of its fatigue resistance.

[0077] To improve the fatigue resistance of pentacene OFET devices, we used an n-type polymer semiconductor poly-{[N,N'-bis(2-octyldodecyl)naphthalene-1,4,5,8-} with potential level hole traps.

[0078] As a charge trapping medium, the schematic diagram of the device structure is shown below. Figure 3 As shown, the thickness of each dielectric layer is consistent with that of the OFET device using PVN as the charge trapping medium, except that N2200 is used instead of PVN as the charge trapping medium.

[0079] Figure 9 The transfer characteristic curves of the OFET device using N2200 as the charge trapping medium are shown. The device exhibits an 8.5V storage window at an operating voltage of ±15V, from which the calculated switching current ratio is 1.25 × 10⁻⁶. 5 The field-effect mobility is 0.16 cm⁻¹. 2 V -1 s -1 .

[0080] Figure 9 The fatigue resistance curves of the OFET device using N2200 as the charge trapping dielectric are shown. After 4000 program / erase cycles, the source-drain current in the erase state only decreased from 3*10. -8 A changes to 1.4*10 -8 A. Compared with OFET devices using PVN as the charge storage medium, its stability has been significantly improved.

[0081] Figure 10a , Figure 10bThis graph shows the change in erase-state source leakage current during 16,000 consecutive program / erase cycles under dark conditions and monochromatic light illumination at 635nm, 532nm, and 375nm. We can observe that the erase-state source leakage current does not decrease particularly sharply under dark conditions and under 635nm and 532nm monochromatic light illumination. Especially under 375nm monochromatic light illumination, the erase-state source leakage current remains almost constant after reaching its peak. This implies that although deep level traps still exist in the N2200, their density is extremely low.

[0082] Example 2

[0083] The difference between Example 2 and Example 1 is that in Example 2, ZnO, which also has shallow-level hole trapping material, is used instead of N2200 in Example 1.

[0084] ZnO was grown in pure Ar using magnetron sputtering. Due to the presence of oxygen vacancies, the ZnO thin film exhibits n-type semiconductor characteristics.

[0085] Figure 11 The graph shows the transfer characteristic curves of a pentacene OFET device using an oxygen-deficient zinc oxide thin film as the charge trapping medium. At the programming / erase scan voltage V... GS At ±15V, there is a window of approximately 7.8V, I ON / I OFF =1×10 5 .

[0086] Figure 12 This is the programming / erasing (fatigue resistance) characteristic curve of a pentacene OFET device using an oxygen-deficient zinc oxide thin film as the charge trapping medium. The erase pulse gate voltage V... E =15V / s, read the gate voltage V R =0V and programming pulse gate voltage V P = -15V / s, read the gate voltage V R At 3V, the current density of the device in both the on and off states remains extremely stable after 10,000 programming / erasing cycles.

[0087] Example 3

[0088] The difference between this embodiment and Embodiment 2 is that the tunneling layer medium is Al2O3, and the preparation method is atomic layer deposition (ALD). Figure 13 This is the transfer characteristic curve of the device, at the programming / erasing scan voltage V. GS At ±15V, the device's memory window is approximately 4.6V. The device's programming / erasing (fatigue resistance) characteristic curves are shown below. Figure 14 As shown, the device maintained an extremely high on-state to off-state current ratio even after 1000 programming / erasing cycles.

Claims

1. A pentacene organic field-effect transistor with improved fatigue resistance, characterized in that, The pentacene organic field-effect transistor structure includes an n-type semiconductor layer and a charge trapping layer with shallow energy level traps; The device has a bottom-gate structure: from bottom to top, they are, Gate electrode / gate insulating layer / n-type semiconductor thin film / charge trapping dielectric layer with shallow energy level traps / tunneling layer / pentacene / source / drain electrode; the gate electrode is a conductor with a resistivity of 0.1-0.

001. Between; the gate insulating layer dielectric film is an insulator with a thickness ranging from 5 to 150 nm; the n-type semiconductor thin film layer has a thickness of 1 to 200 nm; the charge trapping dielectric layer with shallow energy level hole traps has a thickness of 1 to 100 nm; the tunneling layer is an insulator with a thickness ranging from 1 to 20 nm; The thickness of the pentacene ranges from 1 to 100 nm; the source and drain electrodes are conductors with a resistivity of 0.1-0.001 nm. The thickness ranges from 50 to 200 nm. The gate electrode is a conductor with a resistivity of 0.1-0.

001. Between; the gate insulating layer dielectric film is an insulator with a thickness ranging from 5 to 150 nm; the n-type semiconductor film has a thickness of 1 to 200 nm; the charge trapping medium with shallow energy level hole traps has a thickness of 1 to 100 nm; the tunneling layer is an insulator with a thickness ranging from 1 to 20 nm; The thickness of the pentacene ranges from 1 to 100 nm; the source and drain electrodes are conductors with a resistivity of 0.1-0.001 nm. The thickness ranges from 50 to 200 nm. The gate electrode is a metal, conductive nitride, or conductive oxide material; the gate electrode of a bottom-gate field-effect transistor is a semiconductor material such as n-type heavily doped high-conductivity silicon or p-type heavily doped high-conductivity silicon; the gate electrode of a bottom-gate field-effect transistor may be a flexible substrate with a conductive coating. The gate insulating layer dielectric film is a silicon dioxide or aluminum oxide insulator that prevents the charge trapped by the n-type semiconductor film from escaping to the gate electrode; the gate insulating layer dielectric film is a polymer insulator, including PMMA or P(VDF-TrFE).

2. The transistor according to claim 1, characterized in that, n-type semiconductor thin films provide mobile n-type charge carrier electrons; based on the electrostatic induction effect, the hole barrier height at the interface between the n-type semiconductor and the insulating layer is reduced by induced electrons near the interface of the insulating layer, effectively reducing the programming / erasing operating voltage of the n-type organic semiconductor transistor; the n-type semiconductor thin film is an n-type inorganic semiconductor thin film, including zinc selenide (ZnSe). 1-x Zinc sulfide (ZnS) 1-x or zinc oxide (ZnO) 1-x x is between 0.001 and 0.5, or indium gallium zinc oxide, or oxygen-deficient oxide thin films, or oxygen-deficient composite oxide thin films, including ZrHfO. 2-δ or metal nitrides, including TiO2 x N y The preparation methods include magnetron sputtering, thermal evaporation, or electron beam evaporation, with a thickness ranging from 1 to 200 nm, and the film can be crystalline or amorphous. The n-type semiconductor film or n-type organic small molecule semiconductor film includes N-N''-di-3-n-pentyl-3,4,9,10-perylene diimide (PTCDI-C13) and N-N''-di-n-tetrazyl-3,4,9,10-perylene diimide (EP-PDI). The n-type semiconductor film can be crystalline, semi-crystalline, or amorphous. Preparation methods for the n-type organic semiconductor film include spin coating, sol-gel method, spray coating, screen printing, inkjet printing, or thermal evaporation. The thickness of the n-type organic semiconductor film ranges from 1 to 100 nm.

3. The transistor according to claim 1, characterized in that, The n-type semiconductor thin film is a composite structure thin film of two n-type semiconductors; it is prepared by adding an n-type inorganic semiconductor thin film on the surface of an n-type organic semiconductor thin film, or by preparing an n-type inorganic semiconductor thin film on the surface of an n-type organic semiconductor thin film; the thickness of the n-type organic semiconductor thin film in the composite structure thin film ranges from 0.5 to 60 nm, the thickness of the n-type inorganic semiconductor thin film ranges from 0.5 to 60 nm, but the thickness of the composite structure thin film ranges from 1 to 100 nm; the n-type semiconductor thin film is also a combination of multilayer inorganic semiconductor thin films and organic semiconductor thin films.

4. The transistor according to claim 1, characterized in that, Charge trapping dielectrics with shallow energy level traps play a hole trapping role in organic field-effect transistor structures. They are polymer dielectric films with shallow energy level traps, organic small molecule dielectric films with shallow energy level traps, or inorganic dielectric films with shallow energy level traps. In the charge trapping dielectric film with shallow energy level traps, the charge or holes stored therein or most of the charge or holes stored therein are released under a positive pulsed gate voltage. In the above-mentioned charge trapping dielectric film, the charge or hole traps are basically shallow energy level traps, and the density of deep energy level traps is extremely low.

5. The transistor according to claim 4, characterized in that, The charge trapping medium with shallow energy level traps is an n-type organic small molecule semiconductor thin film, including N-N''-di-3-n-pentyl-3,4,9,10-perylene diimide and N-N''-di-n-tetrazyl-3,4,9,10-perylene diimide; the n-type organic small molecule semiconductor thin film is a crystalline thin film, a semi-crystalline thin film, or an amorphous thin film; the charge trapping medium with shallow energy level traps also includes an n-type organic polymer semiconductor thin film, including poly-{[N,N'-bis(2-octyldodecyl)naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5'-(2,2'-bithiophene)}; the n-type organic polymer semiconductor thin film is a crystalline thin film, a semi-crystalline thin film, or an amorphous thin film.

6. The transistor according to claim 5, characterized in that, The preparation methods for n-type organic small molecule semiconductor thin films and n-type organic polymer semiconductor thin films include spin coating, sol-gel method, spray coating, screen printing, inkjet printing or thermal evaporation method; their thickness ranges from 1 to 100 nm.

Images