A current-multiplexed phase-shift mixer with high harmonic suppression ratio

Abstract

The application discloses a current multiplexing phase-shifting mixer with high harmonic suppression ratio IN The I and Q two groups of differential signals generated by the quadrature generating unit are input into the I-path high harmonic suppression ratio phase-shifting mixing unit and the Q-path high harmonic suppression ratio phase-shifting mixing unit respectively, mixed with the differential local oscillator signal in the local oscillator signal and the control signal of the time sequence control unit, and phase-shifting is realized to generate the I and Q two paths of differential intermediate frequency signals; the positive terminal in the I-path differential intermediate frequency signal and the positive terminal in the Q-path differential intermediate frequency signal are input into the same load to generate an intermediate frequency positive output signal; the negative terminal in the I-path differential intermediate frequency signal and the negative terminal in the Q-path differential intermediate frequency signal are input into the same load to generate an intermediate frequency negative output signal; and the intermediate frequency positive output signal and the intermediate frequency negative output signal jointly constitute an intermediate frequency differential output signal. The application has the advantages of simple and compact structure, improved phase-shifting precision of the system, realized mixing, and reduced power consumption of the system.

Description

Technical Field

[0001] This invention relates to microwave monolithic integrated circuits and microelectronics technology, and particularly to a current multiplexing phase-shift mixer with a high harmonic suppression ratio. Background Technology

[0002] With the rapid development of wireless communication systems, phased array systems are widely used in various fields, particularly in aerospace, short-range detection, and precision guidance. Phase shifters and mixers are core modules in phased array systems. Phase shifters control the phase of the received or transmitted signals of each element in the antenna array to achieve beam scanning. Conventional active phase shifters typically employ a vector synthesis phase-shifting architecture, and their phase-shifting accuracy depends on the number of control bits and the phase-shifting range. However, as operating frequencies increase, simply increasing the number of control bits cannot further improve phase-shifting accuracy and requires more complex calibration circuits, while also consuming more power. Mixers, on the other hand, are responsible for up-mixing intermediate frequency (IF) signals in the transmit path to radio frequency (RF) signals, or down-mixing RF signals in the receive path to IF signals. Mixers have indicators such as conversion gain, noise figure, linearity, and power consumption. However, in conventional phased array architectures, the phase shifter and mixer are usually designed as two separate architectures, which results in high overall power consumption, which is not conducive to the service life of the overall system and also not in line with the current concept of green and environmentally friendly development. Summary of the Invention

[0003] The purpose of this invention is to propose a current multiplexing phase-shift mixer with a high harmonic suppression ratio to solve the problem of low phase shift accuracy in current traditional phase shifter architectures.

[0004] The technical solution to achieve the objective of this invention is: a current-multiplexed phase-shift mixer with high harmonic suppression ratio (HMR), comprising a quadrature generation unit, an I-channel HMR phase-shift mixer, a Q-channel HMR phase-shift mixer, and a timing control unit. Input radio frequency (RF) signal. INConnected to the input of the quadrature generation unit, the quadrature generation unit generates four input RF quadrature differential signals: IRF+, IRF-, QRF+, and QRF-. IRF+ and IRF- are connected to the RF signal input of the I-channel high harmonic rejection ratio (HMR) phase-shift mixer, and QRF+ and QRF- are connected to the RF signal input of the Q-channel HMR phase-shift mixer. The externally input local oscillator differential quadrature signals are ILO+, ILO-, QLO+, and QLO-, where ILO+ and ILO- are connected to the local oscillator signal of the I-channel HMR phase-shift mixer. The input terminals are connected, and QLO+ and QLO- are connected to the local oscillator signal input terminals of the Q-channel high harmonic rejection ratio (HMR) phase-shift mixer. The I-channel HMR phase-shift mixer and the Q-channel HMR phase-shift mixer each have two output terminals, generating I-channel intermediate frequency differential output signals IIF+ and IIF- and Q-channel intermediate frequency differential output signals QIF+ and QIF-. IIF+ and QIF+ are connected to the same load to achieve vector synthesis, and IIF- and QIF- are connected to the same load to achieve vector synthesis, finally generating a pair of differential output signals IF+ and IF-.

[0005] RF input signal IN Two sets of differential signals, I and Q, are generated by the quadrature generation unit. The I-channel differential RF signal enters the I-channel high harmonic rejection ratio (HMR) phase-shift mixer unit, where it is mixed with the I-channel differential local oscillator signal from the local oscillator signal and the control signal from the timing control unit to achieve phase shifting, generating the I-channel differential intermediate frequency (IF) signal. The Q-channel differential RF signal enters the Q-channel HMR phase-shift mixer unit, where it is mixed with the Q-channel differential local oscillator signal from the local oscillator signal and the control signal from the timing control unit to achieve phase shifting, generating the Q-channel differential IF signal. The positive terminals of the I-channel and Q-channel differential IF signals are input into the same load, generating the positive terminal output of the IF signal. The negative terminals of the I-channel and Q-channel differential IF signals are input into the same load, generating the negative terminal output of the IF signal. The positive and negative terminals of the IF signals together constitute the differential IF signal.

[0006] Furthermore, the I-channel high harmonic suppression ratio phase-shift mixer unit consists of NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M1. 10 NMOS transistor M 11 NMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14 NMOS transistor M 15 NMOS transistor M 16 Tail current source I SS1 Tail current source ISS2 Tail current source I SS3 Composition. The output signal IRF+ of the quadrature generator unit is connected to NMOS transistors M1, M4, M5, M8, M9, and M1. 12 The gates are connected; the output signal IRF of the quadrature generator is connected to NMOS transistors M2, M3, M6, M7, and M8. 10 NMOS transistor M 11 The gates of NMOS transistors M1, M2, M3, and M4 are connected; the drains of NMOS transistors M1, M2, M3, and M4 are connected to the tail current source I. SS1 Connected; the drains of NMOS transistors M5, M6, M7, and M8 are connected to the tail current source I. SS2 Connected; NMOS transistor M9, NMOS transistor M 10 NMOS transistor M 11 NMOS transistor M 12 Drain and tail current source I SS3 Connected; the body terminals of NMOS transistors M1 and M2 are connected to control bit IVbit1 generated by the timing control unit; the body terminals of NMOS transistors M3 and M4 are connected to control bit IVbit2 generated by the timing control unit; the body terminals of NMOS transistors M5 and M6 are connected to control bit IVbit3 generated by the timing control unit; the body terminals of NMOS transistors M7 and M8 are connected to control bit IVbit4 generated by the timing control unit; the body terminals of NMOS transistors M9 and M2 are connected to control bit IVbit4 generated by the timing control unit; 10 The body terminal is connected to the control bit IVbit5 generated by the timing control unit; NMOS transistor M 11 NMOS transistor M 12 The body terminal is connected to the control bit IVbit6 generated by the timing control unit; NMOS transistors M1, M3, M5, M7, M9, and M1... 11 The drain of the NMOS transistor M 13 NMOS transistor M 14 The source terminals of NMOS transistors M2, M4, M6, M8, and M1 are connected; 10 NMOS transistor M 12 The drain of the NMOS transistor M 15 NMOS transistor M 16 The source of the transistor is connected; in the externally input local oscillator signal, ILO+ is connected to the NMOS transistor M. 13 NMOS transistor M 16 The gate of the NMOS transistor is connected; the local oscillator signal ILO- is connected to the gate of the NMOS transistor M. 14NMOS transistor M 15 The gate of the NMOS transistor is connected; 13 NMOS transistor M 14 NMOS transistor M 15 NMOS transistor M 16 The body terminal is connected to ground; NMOS transistor M 13 With NMOS transistor M 15 The drains of the NMOS transistors are connected; 14 With NMOS transistor M 16 The drains are connected.

[0007] The Q-channel high harmonic suppression ratio phase-shift mixer unit consists of an NMOS transistor M 17 NMOS transistor M 18 NMOS transistor M 19 NMOS transistor M 20 NMOS transistor M 21 NMOS transistor M 22 NMOS transistor M 23 NMOS transistor M 24 NMOS transistor M 25 NMOS transistor M 26 NMOS transistor M 27 NMOS transistor M 28 NMOS transistor M 29 NMOS transistor M 30 NMOS transistor M 31 NMOS transistor M 32 Tail current source I SS4 Tail current source I SS5 Tail current source I SS6 Composition. The output terminal of the quadrature generator unit (QRF+) is connected to the NMOS transistor M. 17 NMOS transistor M 20 NMOS transistor M 21 NMOS transistor M 24 NMOS transistor M 25 NMOS transistor M 28 The gate of the quadrature generator is connected; the QRF-output terminal of the quadrature generator is connected to the NMOS transistor M. 18 NMOS transistor M 19 NMOS transistor M 22 NMOS transistor M 23 NMOS transistor M 26 NMOS transistor M 27 The gate of the NMOS transistor is connected; 17 NMOS transistor M 18 NMOS transistor M 19 NMOS transistor M 20 Drain and tail current source ISS4 Connected; NMOS transistor M 21 NMOS transistor M 22 NMOS transistor M 23 NMOS transistor M 24 Drain and tail current source I SS5 Connected; NMOS transistor M 25 NMOS transistor M 26 NMOS transistor M 27 NMOS transistor M 28 Drain and tail current source I SS6 Connected; NMOS transistor M 17 NMOS transistor M 18 The body terminal is connected to the control bit QVbit1 generated by the timing control unit; NMOS transistor M 19 NMOS transistor M 20 The body terminal is connected to the control bit QVbit2 generated by the timing control unit; NMOS transistor M 21 NMOS transistor M 22 The body terminal is connected to the control bit QVbit3 generated by the timing control unit; NMOS transistor M 23 NMOS transistor M 24 The body terminal is connected to the control bit QVbit4 generated by the timing control unit; NMOS transistor M 25 NMOS transistor M 26 The body terminal is connected to the control bit QVbit5 generated by the timing control unit; NMOS transistor M 27 NMOS transistor M 28 The body terminal is connected to the control bit QVbit6 generated by the timing control unit; NMOS transistor M 17 NMOS transistor M 19 NMOS transistor M 21 NMOS transistor M 23 NMOS transistor M 25 NMOS transistor M 27 The drain of the NMOS transistor M 29 NMOS transistor M 30 The source of the NMOS transistor is connected; 17 NMOS transistor M 20 NMOS transistor M 22 NMOS transistor M 24 NMOS transistor M 26 NMOS transistor M 28 The drain of the NMOS transistor M 31 NMOS transistor M 32 The source of the transistor is connected; the externally input local oscillator signal QLO+ is connected to the NMOS transistor M. 29 NMOS transistor M 32The gate of the transistor is connected; the local oscillator signal QLO- input terminal is connected to the NMOS transistor M. 30 NMOS transistor M 31 The gate of the NMOS transistor is connected; 29 NMOS transistor M 30 NMOS transistor M 31 NMOS transistor M 32 The body terminal is connected to ground; NMOS transistor M 29 With NMOS transistor M 31 The drains of the NMOS transistors are connected; 30 With NMOS transistor M 32 The drains are connected.

[0008] The current multiplexing phase-shift mixer with high harmonic suppression ratio (HMR) has an NMOS transistor M in its I-channel high HMR phase-shift mixer unit. 13 With NMOS transistor M 15 After the drain is connected, it is connected to the NMOS transistor M in the Q-path high harmonic suppression ratio phase shift mixer unit. 29 With NMOS transistor M 31 The drains of the transistors are connected together, and then a load is connected to complete the vector synthesis of current to obtain the intermediate frequency output signal IF+; the NMOS transistor M in the I-channel high harmonic suppression ratio phase-shift mixer unit... 14 With NMOS transistor M 16 After the drain is connected, it is connected to the NMOS transistor M in the Q-path high harmonic suppression ratio phase shift mixer unit. 30 With NMOS transistor M 32 The drains are connected, and then a load is connected to complete the vector synthesis in the form of current to obtain the intermediate frequency output signal IF-, and finally obtain the intermediate frequency signal in the form of differential output.

[0009] Furthermore, the quadrature generation unit consists of an input balun and an all-pass quadrature filter. The input radio frequency signal is connected to one input terminal of the input balun, and after passing through the input balun, differential input radio frequency signals RF+ and RF- are generated. Then, the differential input radio frequency signals RF+ and RF- are connected to the two input terminals of the quadrature all-pass filter, and after passing through the quadrature all-pass filter, quadrature differential signals IRF+, IRF-, QRF+, and QRF- are generated.

[0010] Furthermore, the timing control unit includes an FPGA, and the control signals output by the FPGA include IVbit1, IVbit2, IVbit3, IVbit4, IVbit5, IVbit6, QVbit1, QVbit2, QVbit3, QVbit4, QVbit5, and QVbit6, all of which are timing control signals with a period of T. pIVbit1-IVbit6 control the I-channel high harmonic suppression ratio (HMR) phase-shift mixer, realizing the phase control function of the I-channel HMR phase-shift mixer; QVbit1-QVbit6 control the Q-channel HMR phase-shift mixer, realizing the phase control function of the Q-channel HMR phase-shift mixer.

[0011] The timing control logic of the timing control unit is as follows: IVbit1 in a relative period T p From time 0 to T p IVbit2 is high at one time and low at the other time; IVbit2 is in a relative period T p From time 0 to T p When it is low, it is high at other times; IVbit3 is in a relative period T p The T p Time to T p It is high at one time and low at the other time; IVbit4 is in a relative period T p The T p Time to T p It is low at one time and high at the other time; IVbit5 is in a relative period T p The T p Time to T p It is high at one time and low at the other time; IVbit6 is in a relative period T p The T p Time to T p QVbit1 is at a low level at one time and at a high level at the other time; QVbit1 is in a relative period T p The T p Time to T p QVbit2 is high at one time and low at the other time; QVbit2 is in a relative period T p The T p Time to T p QVbit3 is at a low level at one time and at a high level at the other time; QVbit3 is at a high level in one relative period T p The T p Time to T pQVbit4 is high at one time and low at the other time; QVbit4 is in a relative period T p of T p Time to T p QVbit5 is at a low level at all times and at a high level at the rest of the time; QVbit5 is at a low level in one relative period T p The T p Time to T p QVbit6 is high at one time and low at the other time; QVbit6 is in a relative period T p The T p Time to T p It is at a low level at all times, and at a high level at the rest of the time.

[0012] Furthermore, in the current multiplexing phase-shift mixer with high harmonic suppression ratio, the tail current source I in the I-channel high harmonic suppression ratio phase-shift mixer unit... SS1 Tail current source I SS2 Tail current source I SS3 The current amplitude ratio is 1: 1. The tail current source I in the Q-path high harmonic suppression ratio phase-shifting mixer unit. SS4 Tail current source I SS5 Tail current source I SS6 The current amplitude ratio is 1: :1; Simultaneously, tail current source I SS1 The current amplitude and the tail current source I SS4 The current amplitudes are equal.

[0013] Furthermore, when the current amplitude ratio and the timing control logic are satisfied, the high harmonic suppression function of the current multiplexing phase-shift mixer with high harmonic suppression ratio can be realized.

[0014] Furthermore, the current-multiplexed phase-shift mixer with high harmonic suppression ratio utilizes a phase-shifting function that adjusts the pulse start time of the control signal output by the FPGA. To achieve this, if the beam pointing angle is θ0, then its relationship with the pulse start time point is as follows: By adjusting the pulse start time, a current multiplexed phase-shifting mixer with a high harmonic suppression ratio can achieve free phase change in the range of 0-2π.

[0015] Furthermore, the current multiplexing phase-shift mixer with high harmonic rejection ratio (HCR) uses an I-channel HCR phase-shift mixer unit and a Q-channel HCR phase-shift mixer unit to mix the quadrature differential input RF signal with the externally input quadrature differential local oscillator signal, ultimately achieving the function of mixing the RF input signal into the intermediate frequency output signal.

[0016] Compared with the prior art, the significant advantages of this invention are: simple and compact structure, improved phase shifting accuracy of the system while achieving frequency mixing, reduced power consumption of the system, and the use of current multiplexing structure to combine the mixer and phase shifter architecture, which can achieve a phase shifting range of 0-2π under the premise of low power consumption and low cost, while realizing the function of frequency mixing. Attached Figure Description

[0017] Figure 1 This is a topology diagram of the current multiplexing phase-shifting mixer with high harmonic suppression ratio of the present invention;

[0018] Figure 2 This is a circuit diagram of the current multiplexing phase-shift mixer with high harmonic suppression ratio of the present invention;

[0019] Figure 3 This is a schematic diagram and layout of the orthogonal generation unit of the present invention;

[0020] Figure 4 This is the timing control logic diagram of the timing control unit of the present invention;

[0021] Figure 5 This is a schematic diagram of the output signal relative to the harmonic suppression ratio of the current multiplexing phase-shift mixer with high harmonic suppression ratio of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0023] Figure 1 This is a topology diagram of a current-multiplexed phase-shift mixer with high harmonic rejection ratio (HMR). It includes a quadrature generator unit, an I-channel HMR phase-shift mixer, a Q-channel HMR phase-shift mixer, and a timing control unit. (RF signal) INThe quadrature generator unit is connected to its input. The quadrature generator unit generates four outputs: IRF+, IRF-, QRF+, and QRF-. IRF+ and IRF- are connected to the RF signal input of the I-channel high harmonic rejection ratio (HMR) phase-shift mixer, and QRF+ and QRF- are connected to the RF signal input of the Q-channel HMR phase-shift mixer. The externally input local oscillator differential quadrature signals are ILO+, ILO-, QLO+, and QLO-. ILO+ and ILO- are connected to the I-channel HMR phase-shift mixer. The local oscillator signal input terminals of the unit are connected, and QLO+ and QLO- are connected to the local oscillator signal input terminals of the Q-channel high harmonic suppression ratio (HMR) phase-shift mixer. The I-channel HMR phase-shift mixer and the Q-channel HMR phase-shift mixer each have two output terminals, generating IIF+, IIF- and QIF+, QIF- signals. IIF+ and QIF+ are connected to the same load to achieve vector synthesis, and IIF- and QIF- are connected to the same load to achieve vector synthesis, finally generating a pair of differential output signals IF+ and IF-.

[0024] RF input signal IN Two sets of differential signals, I and Q, are generated by the quadrature generation unit. The I differential signal enters the I-channel high harmonic rejection ratio (HCR) phase-shift mixer unit, where it is mixed with the I-channel differential local oscillator signal from the local oscillator signal and the control signal from the timing control unit, and phase-shifted to generate the I-channel differential intermediate frequency (IF) signal. The Q differential signal enters the Q-channel HCR phase-shift mixer unit, where it is mixed with the Q-channel differential local oscillator signal from the local oscillator signal and the control signal from the timing control unit, and phase-shifted to generate the Q-channel differential IF signal. The positive terminals of the I-channel and Q-channel differential IF signals are input into the same load, generating a positive IF output. The negative terminals of the I-channel and Q-channel differential IF signals are input into the same load, generating a negative IF output. Finally, these components form the IF differential signal, realizing the output of the IF differential signal.

[0025] Figure 2 This is a circuit diagram of a current-multiplexed phase-shift mixer with high harmonic suppression ratio (HMR) according to the present invention, including one-channel HMR phase-shift mixer unit and Q-channel HMR phase-shift mixer units. The one-channel HMR phase-shift mixer unit consists of NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M1. 10 NMOS transistor M 11 NMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14 NMOS transistor M 15 NMOS transistor M 16Tail current source I SS1 Tail current source I SS2 Tail current source I SS3 Composition. The signal IRF+ output terminal of the quadrature generator unit is connected to NMOS transistors M1, M4, M5, M8, M9, and M1. 12 The gates of the transistors are connected; the IRF-output terminal of the quadrature generator is connected to NMOS transistors M2, M3, M6, M7, and M8. 10 NMOS transistor M 11 The gates of NMOS transistors M1, M2, M3, and M4 are connected to the tail current source I. SS1 Connected; the drains of NMOS transistors M5, M6, M7, and M8 are connected to the tail current source I. SS2 Connected; NMOS transistor M9, NMOS transistor M 10 NMOS transistor M 11 NMOS transistor M 12 Drain and tail current source I SS3 Connected; the body terminals of NMOS transistors M1 and M2 are connected to control bit IVbit1 generated by the timing control unit; the body terminals of NMOS transistors M3 and M4 are connected to control bit IVbit2 generated by the timing control unit; the body terminals of NMOS transistors M5 and M6 are connected to control bit IVbit3 generated by the timing control unit; the body terminals of NMOS transistors M7 and M8 are connected to control bit IVbit4 generated by the timing control unit; the body terminals of NMOS transistors M9 and M2 are connected to control bit IVbit4 generated by the timing control unit; 10 The body terminal is connected to the control bit IVbit5 generated by the timing control unit; NMOS transistor M 11 NMOS transistor M 12 The body terminal is connected to the control bit IVbit6 generated by the timing control unit; NMOS transistors M1, M3, M5, M7, M9, and M1... 11 The drain of the NMOS transistor M 13 NMOS transistor M 14 The source terminals of NMOS transistors M2, M4, M6, M8, and M1 are connected; 10 NMOS transistor M 12 The drain of the NMOS transistor M 15 NMOS transistor M 16 The source of the transistor is connected; in the externally input local oscillator signal, ILO+ is connected to the NMOS transistor M. 13 NMOS transistor M 16The gate of the NMOS transistor is connected; the local oscillator signal ILO- is connected to the gate of the NMOS transistor M. 14 NMOS transistor M 15 The gate of the NMOS transistor is connected; 13 NMOS transistor M 14 NMOS transistor M 15 NMOS transistor M 16 The body terminal is connected to ground; NMOS transistor M 13 With NMOS transistor M 15 The drains of the NMOS transistors are connected; 14 With NMOS transistor M 16 The drains are connected.

[0026] The Q-channel high harmonic suppression ratio phase-shift mixer unit consists of an NMOS transistor M 17 NMOS transistor M 18 NMOS transistor M 19 NMOS transistor M 20 NMOS transistor M 21 NMOS transistor M 22 NMOS transistor M 23 NMOS transistor M 24 NMOS transistor M 25 NMOS transistor M 26 NMOS transistor M 27 NMOS transistor M 28 NMOS transistor M 29 NMOS transistor M 30 NMOS transistor M 31 NMOS transistor M 32 Tail current source I SS4 Tail current source I SS5 Tail current source I SS6 Composition. The output terminal of the quadrature generator unit (QRF+) is connected to the NMOS transistor M. 17 NMOS transistor M 20 NMOS transistor M 21 NMOS transistor M 24 NMOS transistor M 25 NMOS transistor M 28 The gate of the quadrature generator is connected; the QRF-output terminal of the quadrature generator is connected to the NMOS transistor M. 18 NMOS transistor M 19 NMOS transistor M 22 NMOS transistor M 23 NMOS transistor M 26 NMOS transistor M 27 The gate of the NMOS transistor is connected; 17 NMOS transistor M 18 NMOS transistor M 19NMOS transistor M 20 Drain and tail current source I SS4 Connected; NMOS transistor M 21 NMOS transistor M 22 NMOS transistor M 23 NMOS transistor M 24 Drain and tail current source I SS5 Connected; NMOS transistor M 25 NMOS transistor M 26 NMOS transistor M 27 NMOS transistor M 28 Drain and tail current source I SS6 Connected; NMOS transistor M 17 NMOS transistor M 18 The body terminal is connected to the control bit QVbit1 generated by the timing control unit; NMOS transistor M 19 NMOS transistor M 20 The body terminal is connected to the control bit QVbit2 generated by the timing control unit; NMOS transistor M 21 NMOS transistor M 22 The body terminal is connected to the control bit QVbit3 generated by the timing control unit; NMOS transistor M 23 NMOS transistor M 24 The body terminal is connected to the control bit QVbit4 generated by the timing control unit; NMOS transistor M 25 NMOS transistor M 26 The body terminal is connected to the control bit QVbit5 generated by the timing control unit; NMOS transistor M 27 NMOS transistor M 28 The body terminal is connected to the control bit QVbit6 generated by the timing control unit; NMOS transistor M 17 NMOS transistor M 19 NMOS transistor M 21 NMOS transistor M 23 NMOS transistor M 25 NMOS transistor M 27 The drain of the NMOS transistor M 29 NMOS transistor M 30 The source of the NMOS transistor is connected; 17 NMOS transistor M 20 NMOS transistor M 22 NMOS transistor M 24 NMOS transistor M 26 NMOS transistor M 28 The drain of the NMOS transistor M 31 NMOS transistor M 32 The source of the transistor is connected; the externally input local oscillator signal QLO+ is connected to the NMOS transistor M.29 NMOS transistor M 32 The gate of the transistor is connected; the local oscillator signal QLO- input terminal is connected to the NMOS transistor M. 30 NMOS transistor M 31 The gate of the NMOS transistor is connected; 29 NMOS transistor M 30 NMOS transistor M 31 NMOS transistor M 32 The body terminal is connected to ground; NMOS transistor M 29 With NMOS transistor M 31 The drains of the NMOS transistors are connected; 30 With NMOS transistor M 32 The drains are connected.

[0027] In the high harmonic suppression ratio phase-shift mixer unit, the NMOS transistor M 13 With NMOS transistor M 15 After the drain is connected, it is connected to the NMOS transistor M in the Q-path high harmonic suppression ratio phase shift mixer unit. 29 With NMOS transistor M 31 The drains of the transistors are connected together, and then a load is connected to complete the vector synthesis of current to obtain the intermediate frequency output signal IF+; the NMOS transistor M in the I-channel high harmonic suppression ratio phase-shift mixer unit... 14 With NMOS transistor M 16 After the drain is connected, it is connected to the NMOS transistor M in the Q-path high harmonic suppression ratio phase shift mixer unit. 30 With NMOS transistor M 32 The drains are connected, and then a load is connected to complete the vector synthesis in the form of current to obtain the intermediate frequency output signal IF-, and finally obtain the intermediate frequency signal in the form of differential output.

[0028] Figure 3 This is a schematic diagram and layout of the quadrature generation unit of the present invention. The quadrature generation unit consists of an input balun and an all-pass quadrature filter. The input radio frequency signal is connected to one input terminal of the input balun. After passing through the input balun, differential input radio frequency signals RF+ and RF- are generated. Then, the differential input radio frequency signals RF+ and RF- are connected to the two input terminals of the quadrature all-pass filter. After passing through the quadrature all-pass filter, quadrature differential signals IRF+, IRF-, QRF+, and QRF- are generated.

[0029] Figure 4 This is the timing control logic diagram of the timing control unit. The timing control logic of the timing control unit is as follows: IVbit1 in a relative period T p From time 0 to T p IVbit2 is high at one time and low at the other time; IVbit2 is in a relative period T p From time 0 to T p When it is low, it is high at other times; IVbit3 is in a relative period T p The T p Time to T p It is high at one time and low at the other time; IVbit4 is in a relative period T p The T p Time to T p It is low at one time and high at the other time; IVbit5 is in a relative period T p The T p Time to T p It is high at one time and low at the other time; IVbit6 is in a relative period T p The T p Time to T p QVbit1 is at a low level at one time and at a high level at the other time; QVbit1 is in a relative period T p The T p Time to T p QVbit2 is high at one time and low at the other time; QVbit2 is in a relative period T p The T p Time to T p QVbit3 is at a low level at one time and at a high level at the other time; QVbit3 is at a high level in one relative period T p The T p Time to T p QVbit4 is high at one time and low at the other time; QVbit4 is in a relative period T p of T p Time to T p QVbit5 is at a low level at all times and at a high level at the rest of the time; QVbit5 is at a low level in one relative period T p The T p Time to T p QVbit6 is high at one time and low at the other time; QVbit6 is in a relative period T p The T pTime to T p It is at a low level at all times, and at a high level at the rest of the time.

[0030] Figure 5 This is a normalized spectrum distribution of the output signal of the current-multiplexed phase-shift mixer with high harmonic suppression ratio (HMR) of this invention. The current-multiplexed phase-shift mixer with high HMR, and the tail current source I in the I-channel high HMR phase-shift mixer unit. SS1 Tail current source I SS2 Tail current source I SS3 The current amplitude ratio is 1: 1. The tail current source I in the Q-path high harmonic suppression ratio phase-shifting mixer unit. SS4 Tail current source I SS5 Tail current source I SS6 The current amplitude ratio is 1: 1. Simultaneously, tail current source I SS1 The current amplitude and the tail current source I SS4 The current amplitudes are equal. When the current amplitude ratio and the timing control logic are satisfied, the high harmonic suppression function of the current multiplexed phase-shift mixer with high harmonic suppression ratio can be achieved. As shown in the figure, taking the following mixing as an example, the useful sideband appears at the +1 harmonic, i.e., f. RF -f LO +f p The most useless sideband for a given frequency occurs at frequency -3, i.e., f. RF -f LO -3·f p The sideband corresponding to the frequency and the +5th harmonic, i.e., f RF -f LO +5·f p The corresponding sidebands at the frequencies. The -3rd harmonic rejection ratio reaches -38.218dBc, and the +5th harmonic rejection ratio reaches -70.385dBc, which greatly increases the bandwidth of the useful signal.

[0031] A current-multiplexed phase-shift mixer with a high harmonic rejection ratio. The phase-shifting function of the phase-shift mixer is achieved by adjusting the start time of the pulse. To achieve this, if the beam pointing angle is θ0, then its relationship with the pulse start time of the control signal is as follows: By continuously adjusting the pulse start time, the phase change of the current multiplexed phase-shift mixer with high harmonic rejection ratio is achieved continuously from 0 to 2π. The mixing function of the phase-shift mixer is to mix the externally input differential quadrature local oscillator signal with the I-channel high harmonic rejection ratio phase-shift mixer unit and the Q-channel high harmonic rejection ratio phase-shift mixer unit respectively, and finally realize the function of mixing the RF input signal into the intermediate frequency output signal.

[0032] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0033] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A current-multiplexed phase-shift mixer with a high harmonic suppression ratio, characterized in that, Includes a quadrature generator unit, an I-channel high harmonic rejection ratio (HCR) phase-shift mixer unit, a Q-channel HCR phase-shift mixer unit, a timing control unit, and an RF signal generator. IN The quadrature generator unit is connected to its input. The quadrature generator unit generates four outputs: IRF+, IRF-, QRF+, and QRF-. IRF+ and IRF- are connected to the RF signal input of the I-channel high harmonic rejection ratio (HMR) phase-shift mixer, and QRF+ and QRF- are connected to the RF signal input of the Q-channel HMR phase-shift mixer. The externally input local oscillator differential quadrature signals are ILO+, ILO-, QLO+, and QLO-. ILO+ and ILO- are connected to the I-channel HMR phase-shift mixer. The local oscillator signal input terminals of the unit are connected, and QLO+ and QLO- are connected to the local oscillator signal input terminals of the Q-channel high harmonic suppression ratio phase-shift mixer. The I-channel high harmonic suppression ratio phase-shift mixer and the Q-channel high harmonic suppression ratio phase-shift mixer each have two output terminals, generating IIF+, IIF- and QIF+, QIF- signals. IIF+ and QIF+ are connected to the same load to achieve vector synthesis, and IIF- and QIF- are connected to the same load to achieve vector synthesis, finally generating a pair of differential output signals IF+ and IF-. RF input signal IN Two sets of differential signals, I and Q, are generated by the quadrature generation unit. The I differential signal enters the I-channel high harmonic rejection ratio (HCR) phase-shift mixer unit, where it is mixed with the I-channel differential local oscillator signal from the local oscillator signal and the control signal from the timing control unit to achieve phase shifting, generating the I-channel differential intermediate frequency (IF) signal. The Q differential signal enters the Q-channel HCR phase-shift mixer unit, where it is mixed with the Q-channel differential local oscillator signal from the local oscillator signal and the control signal from the timing control unit to achieve phase shifting, generating the Q-channel differential IF signal. The positive terminals of the I-channel and Q-channel differential IF signals are input to the same load to generate the IF positive output signal. The negative terminal of the I-channel differential intermediate frequency signal and the negative terminal of the Q-channel differential intermediate frequency signal are input into the same load to generate a negative intermediate frequency output signal; The intermediate frequency positive output signal and the intermediate frequency negative output signal together constitute the intermediate frequency differential output signal; in: The timing control unit includes an FPGA, and the control signals output by the FPGA include IVbit1, IVbit2, IVbit3, IVbit4, IVbit5, IVbit6, QVbit1, QVbit2, QVbit3, QVbit4, QVbit5, and QVbit6, all of which are timing control signals with a period of T. p IVbit1-IVbit6 control the I-channel high harmonic suppression ratio (HMR) phase-shift mixer, realizing the phase control function of the I-channel HMR phase-shift mixer; QVbit1-QVbit6 control the Q-channel HMR phase-shift mixer, realizing the phase control function of the Q-channel HMR phase-shift mixer. The high harmonic suppression ratio phase-shift mixer unit consists of NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M1. 10 NMOS transistor M 11 NMOS transistor M 12 NMOS transistor M 13 NMOS transistor M 14 NMOS transistor M 15 NMOS transistor M 16 Tail current source I SS1 Tail current source I SS2 Tail current source I SS3 The quadrature generator unit consists of the signal IRF+ output terminal connected to NMOS transistors M1, M4, M5, M8, M9, and M1. 12 The gates of the transistors are connected; the IRF-output terminal of the quadrature generator is connected to NMOS transistors M2, M3, M6, M7, and M8. 10 NMOS transistor M 11 The gates of NMOS transistors M1, M2, M3, and M4 are connected to the tail current source I. SS1 Connected; the drains of NMOS transistors M5, M6, M7, and M8 are connected to the tail current source I. SS2 Connected; NMOS transistor M9, NMOS transistor M 10 NMOS transistor M 11 NMOS transistor M 12 Drain and tail current source I SS3 Connected; the body terminals of NMOS transistors M1 and M2 are connected to control bit IVbit1 generated by the timing control unit; the body terminals of NMOS transistors M3 and M4 are connected to control bit IVbit2 generated by the timing control unit; the body terminals of NMOS transistors M5 and M6 are connected to control bit IVbit3 generated by the timing control unit; the body terminals of NMOS transistors M7 and M8 are connected to control bit IVbit4 generated by the timing control unit; the body terminals of NMOS transistors M9 and M2 are connected to control bit IVbit4 generated by the timing control unit; 10 The body terminal is connected to the control bit IVbit5 generated by the timing control unit; NMOS transistor M 11 NMOS transistor M 12 The body terminal is connected to the control bit IVbit6 generated by the timing control unit; NMOS transistors M1, M3, M5, M7, M9, and M1... 11 The drain of the NMOS transistor M 13 NMOS transistor M 14 The source terminals of NMOS transistors M2, M4, M6, M8, and M1 are connected; 10 NMOS transistor M 12 The drain of the NMOS transistor M 15 NMOS transistor M 16 The source of the transistor is connected; in the externally input local oscillator signal, ILO+ is connected to the NMOS transistor M. 13 NMOS transistor M 16 The gate of the NMOS transistor is connected; the local oscillator signal ILO- is connected to the gate of the NMOS transistor M. 14 NMOS transistor M 15 The gate of the NMOS transistor is connected; 13 NMOS transistor M 14 NMOS transistor M 15 NMOS transistor M 16 The body terminal is connected to ground; NMOS transistor M 13 With NMOS transistor M 15 The drains of the NMOS transistors are connected; 14 With NMOS transistor M 16 The drains are connected; The Q-channel high harmonic suppression ratio phase-shift mixer unit consists of an NMOS transistor M 17 NMOS transistor M 18 NMOS transistor M 19 NMOS transistor M 20 NMOS transistor M 21 NMOS transistor M 22 NMOS transistor M 23 NMOS transistor M 24 NMOS transistor M 25 NMOS transistor M 26 NMOS transistor M 27 NMOS transistor M 28 NMOS transistor M 29 NMOS transistor M 30 NMOS transistor M 31 NMOS transistor M 32 Tail current source I SS4 Tail current source I SS5 Tail current source I SS6 The quadrature generator unit's signal QRF+ output terminal is connected to the NMOS transistor M. 17 NMOS transistor M 20 NMOS transistor M 21 NMOS transistor M 24 NMOS transistor M 25 NMOS transistor M 28 The gate of the quadrature generator is connected; the QRF-output terminal of the quadrature generator is connected to the NMOS transistor M. 18 NMOS transistor M 19 NMOS transistor M 22 NMOS transistor M 23 NMOS transistor M 26 NMOS transistor M 27 The gate of the NMOS transistor is connected; 17 NMOS transistor M 18 NMOS transistor M 19 NMOS transistor M 20 Drain and tail current source I SS4 Connected; NMOS transistor M 21 NMOS transistor M 22 NMOS transistor M 23 NMOS transistor M 24 Drain and tail current source I SS5 Connected; NMOS transistor M 25 NMOS transistor M 26 NMOS transistor M 27 NMOS transistor M 28 Drain and tail current source I SS6 Connected; NMOS transistor M 17 NMOS transistor M 18 The body terminal is connected to the control bit QVbit1 generated by the timing control unit; NMOS transistor M 19 NMOS transistor M 20 The body terminal is connected to the control bit QVbit2 generated by the timing control unit; NMOS transistor M 21 NMOS transistor M 22 The body terminal is connected to the control bit QVbit3 generated by the timing control unit; NMOS transistor M 23 NMOS transistor M 24 The body terminal is connected to the control bit QVbit4 generated by the timing control unit; NMOS transistor M 25 NMOS transistor M 26 The body terminal is connected to the control bit QVbit5 generated by the timing control unit; NMOS transistor M 27 NMOS transistor M 28 The body terminal is connected to the control bit QVbit6 generated by the timing control unit; NMOS transistor M 17 NMOS transistor M 19 NMOS transistor M 21 NMOS transistor M 23 NMOS transistor M 25 NMOS transistor M 27 The drain of the NMOS transistor M 29 NMOS transistor M 30 The source of the NMOS transistor is connected; 17 NMOS transistor M 20 NMOS transistor M 22 NMOS transistor M 24 NMOS transistor M 26 NMOS transistor M 28 The drain of the NMOS transistor M 31 NMOS transistor M 32 The source of the transistor is connected; the externally input local oscillator signal QLO+ is connected to the NMOS transistor M. 29 NMOS transistor M 32 The gate of the transistor is connected; the local oscillator signal QLO- input terminal is connected to the NMOS transistor M. 30 NMOS transistor M 31 The gate of the NMOS transistor is connected; 29 NMOS transistor M 30 NMOS transistor M 31 NMOS transistor M 32 The body terminal is connected to ground; NMOS transistor M 29 With NMOS transistor M 31 The drains of the NMOS transistors are connected; 30 With NMOS transistor M 32 The drains are connected.

2. The current multiplexing phase-shift mixer with high harmonic suppression ratio according to claim 1, characterized in that, The quadrature generation unit consists of an input balun and an all-pass quadrature filter. The input radio frequency signal is connected to one input terminal of the input balun. After passing through the input balun, differential input radio frequency signals RF+ and RF- are generated. Then, the differential input radio frequency signals RF+ and RF- are connected to the two input terminals of the quadrature all-pass filter, respectively. After passing through the quadrature all-pass filter, differential input radio frequency signals IRF+, IRF-, QRF+, and QRF- are generated.

3. The current multiplexing phase-shift mixer with high harmonic suppression ratio according to claim 1, characterized in that, In the high harmonic suppression ratio phase-shift mixer unit, the NMOS transistor M 13 With NMOS transistor M 15 After the drain is connected, it is connected to the NMOS transistor M in the Q-path high harmonic suppression ratio phase shift mixer unit. 29 With NMOS transistor M 31 The drains of the transistors are connected, and then a load is connected to complete the vector synthesis of the current form, obtaining the intermediate frequency output positive signal IF+; the NMOS transistor M in the I-channel high harmonic suppression ratio phase shift mixer unit... 14 With NMOS transistor M 16 After the drain is connected, it is connected to the NMOS transistor M in the Q-path high harmonic suppression ratio phase shift mixer unit. 30 With NMOS transistor M 32 The drains are connected, and then a load is connected to complete the vector synthesis in the form of current, to obtain the intermediate frequency output negative signal IF, and finally to obtain the intermediate frequency signal in the form of differential output.

4. The current multiplexing phase-shift mixer with high harmonic suppression ratio according to claim 1, characterized in that, The timing control logic is as follows: IVbit1 in one relative cycle From time 0 to It is high at one time and low at the other time; IVbit2 is in one relative cycle From time 0 to It is low at one time and high at the other time; IVbit3 is in one relative cycle The Time to It is high at one time and low at the other time; IVbit4 is in one relative cycle The Time to It is low at all times and high at all other times; IVbit5 is in one relative cycle The Time to It is high at one time and low at the other time; IVbit6 is in one relative cycle The Time to QVbit1 is at a low level at the beginning and at a high level at the end; QVbit1 is in a relative cycle The Time to QVbit2 is high at one time and low at the other time; QVbit2 is in a relative cycle The Time to QVbit3 is at a low level at the beginning and at a high level at the end; QVbit3 is in a relative cycle. The Time to QVbit4 is high at one time and low at the other time; QVbit4 is in a relative cycle of Time to It is low at the beginning and high at the end; QVbit5 is in one relative cycle. The Time to It is high at one time and low at the other time; IVbit6 is in one relative cycle The Time to It is at a low level at all times, and at a high level at the rest of the time.

5. The current multiplexing phase-shift mixer with high harmonic suppression ratio according to claim 1 or 3, characterized in that, The tail current source I in the high harmonic suppression ratio phase-shift mixer unit SS1 Tail current source I SS2 Tail current source I SS3 The current amplitude ratio is 1: :1; Tail current source I in Q-path high harmonic suppression ratio phase-shifting mixer unit SS4 Tail current source I SS5 Tail current source I SS6 The current amplitude ratio is 1: :1; Simultaneously, tail current source I SS1 The current amplitude and the tail current source I SS4 The current amplitudes are equal.

6. The current multiplexing phase-shift mixer with high harmonic suppression ratio according to claim 4, characterized in that, The phase-shifting function of the current-multiplexed phase-shift mixer is achieved by adjusting the pulse start time of the control signal output by the FPGA. To achieve this, if the beam pointing angle is Then its relationship with the pulse start time point is: By adjusting the pulse start time, a current multiplexed phase-shifting mixer with a high harmonic suppression ratio can achieve free phase change between 0 and 2π.

7. The current multiplexing phase-shift mixer with high harmonic suppression ratio according to claim 1, characterized in that, The mixing function of the phase-shift mixer is achieved by mixing the externally input differential quadrature local oscillator signals ILO+, ILO-, QLO+, and QLO- with the input RF differential quadrature signals IRF+, IRF-, QRF+, and QRF- generated by the quadrature generation unit through the I-channel high harmonic rejection ratio (HCR) phase-shift mixer unit and the Q-channel HCR phase-shift mixer unit, respectively. Ultimately, this achieves the function of mixing the RF input signal into an intermediate frequency differential output signal.

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