A multi-fanout circuit and clock driver

Abstract

The application discloses a multi-path fan-out circuit and a clock driver, and relates to the field of clock drivers, which comprises an amplification circuit, a bias circuit and a plurality of LVPECL output circuits, the bias circuit is connected with the amplification circuit and each LVPECL output circuit respectively, and is used for providing current bias and switching signals. The LVPECL output circuit comprises two mirror-symmetrical conversion circuits. The amplification circuit is connected with the LVPECL output circuit, and is used for amplifying a differential input signal and outputting a first level standard signal and a second level standard signal. The LVPECL output circuit is used for converting the first level standard signal and the second level standard signal into a first output signal and a second output signal. The application can realize the function of converting a group of differential input signals into multi-path high-speed data output, and due to the mirror-symmetrical arrangement of the two conversion circuits, the signal output by each conversion circuit can realize low skew when serving as a clock signal.

Description

Technical Field

[0001] This application relates to the field of clock technology, and in particular to a multi-fan-out circuit and a clock driver. Background Technology

[0002] Clock drivers are widely used in wireless communication, data networks, and other fields. Their basic function is to enhance the driving capability of clock signals, thereby enabling functions such as communication network timing synchronization, clock generation, clock recovery, and clock distribution. Clock signals typically have the highest switching frequency in the entire system, which can interfere with the normal operation of surrounding circuits. Furthermore, the larger the amplitude and the higher the frequency of the clock signal, the stronger the interference to surrounding circuits. Additionally, due to the parasitic capacitance on the circuit board where the clock driver is located, large-amplitude input clock signals require more time to charge and discharge, limiting the propagation speed of the clock signal. Therefore, in high-speed circuit systems with multiple clocks, a suitable clock driver is needed as a buffer to improve driving capability and enable the transmission of multiple clock signals. Summary of the Invention

[0003] This application provides a multi-channel fan-out circuit and a clock driver for converting a single-channel differential input signal into a multi-channel output signal.

[0004] The technical solution is as follows:

[0005] In a first aspect, a multi-fan-out circuit is provided, the circuit comprising: an amplifier circuit, a bias circuit, and a plurality of LVPECL output circuits, wherein the bias circuit is connected to the amplifier circuit and each of the LVPECL output circuits respectively, and the bias circuit is used to provide current bias and switching signals;

[0006] Each of the LVPECL output circuits includes two mirror-symmetric conversion circuits;

[0007] The amplifier circuit is connected to the two conversion circuits included in each of the LVPECL output circuits, and is used to amplify the received set of differential input signals to obtain a first-level standard signal and a second-level standard signal with opposite potentials.

[0008] The LVPECL output circuit is used to convert the first level standard signal into a first output signal using one of the two conversion circuits, and to convert the second level standard signal into a second output signal using the other of the two conversion circuits, wherein the second output signal and the first output signal have opposite potentials.

[0009] This application provides a multi-channel fan-out circuit. A set of differential input signals input to the amplifier circuit is amplified to obtain a first-level standard signal and a second-level standard signal, which are then provided to multiple LVPECL output circuits. Since the amplifier circuit is connected to multiple LVPECL output circuits, each LVPECL output circuit can convert the first-level standard signal and the second-level standard signal as input signals to obtain two output signals, namely a first output signal and a second output signal. Therefore, this scheme can realize the function of converting a set of differential input signals into multiple high-speed data outputs. Furthermore, since the two conversion circuits are mirror-symmetrically arranged, the parasitic capacitance of the circuit signal lines of the two conversion circuits is the same, which ensures that the output signal of each conversion circuit, when used as a clock signal, arrives at the device with low skew.

[0010] Optionally, the potential of the first level standard signal is opposite to the potential of the first output signal, and the potential of the second level standard signal is opposite to the potential of the second output signal.

[0011] Optionally, the conversion circuit includes an emitter follower circuit, a differential amplifier circuit, and an emitter coupling circuit. The emitter follower circuit is used to receive a level standard signal, and the emitter follower circuit is connected to the differential amplifier circuit. The level standard signal is either the first level standard signal or the second level standard signal.

[0012] The differential amplifier circuit is used to receive the signal output by the emitter follower circuit and to amplify the signal output by the emitter follower circuit. The differential amplifier circuit is connected to the emitter coupling circuit.

[0013] The emitter coupling circuit is used to receive the signal output by the differential amplifier circuit, and to make the potential of the output signal of the emitter coupling circuit opposite to the potential of the level standard signal.

[0014] Optionally, the emitter follower circuit includes a first transistor, the base of which is used to receive the level standard signal;

[0015] The differential amplifier circuit includes a second transistor and a first resistor. The base of the second transistor is connected to the emitter of the first transistor, and the collector of the second transistor is connected to the first end of the first resistor. The second end of the first resistor is used to receive the voltage provided by an external power supply.

[0016] The emitter coupling circuit includes a third transistor, the base of which is connected to the collector of the second transistor, and the emitter of the third transistor is used to output the output signal.

[0017] Optionally, the LVPECL output circuit further includes a first bias current source and a second bias current source. The first bias current source is connected to the emitter follower circuit in the first conversion circuit of the two conversion circuits, and the second bias current source is connected to the differential amplifier circuit in the first conversion circuit.

[0018] Optionally, one of the two conversion circuits may be copied from the other of the two conversion circuits.

[0019] Optionally, the set of differential input signals includes a first signal and a second signal with equal amplitude and opposite phase, and the amplification circuit includes an input circuit and an intermediate amplification circuit.

[0020] The first input terminal of the input circuit is used to receive the first signal, the second input terminal of the input circuit is used to receive the second signal, the first output terminal of the input circuit is connected to the first input terminal of the intermediate amplifier circuit, the second output terminal of the input circuit is connected to the second input terminal of the intermediate amplifier circuit, and the input circuit is used to pre-amplify the first signal to obtain a first-stage amplified signal, and to pre-amplify the second signal to obtain a second-stage amplified signal.

[0021] The output terminal of the intermediate amplifier circuit is connected to each of the LVPECL output circuits, and is used to amplify the first-stage amplified signal to obtain the first-level standard signal, and to amplify the second-stage amplified signal to obtain the second-level standard signal.

[0022] Optionally, the input circuit includes a first differential amplifier, and the intermediate amplifier circuit includes a second differential amplifier. The first input terminal of the first differential amplifier is used to receive the first signal, and the second input terminal of the first differential amplifier is used to receive the second signal.

[0023] The first input terminal of the second differential amplifier is used to receive the first-stage amplified signal, the second input terminal of the second differential amplifier is used to receive the second-stage amplified signal, and the output terminal of the second differential amplifier is connected to the first input terminal and the second input terminal of each of the LVPECL output circuits. The first input terminal of the LVPECL output circuit is used to receive the first level standard signal, and the second input terminal of the LVPECL output circuit is used to receive the second level standard signal.

[0024] Optionally, at least one of the first differential amplifier and the second differential amplifier includes the following structure: a fourth transistor, a fifth transistor, a third resistor, a fourth resistor, and a third bias current source;

[0025] The base of the fourth transistor is used to receive the first signal, and the base of the fifth transistor is used to receive the second signal.

[0026] The collector of the fourth transistor is connected to the first terminal of the third resistor, and the collector of the fifth transistor is connected to the first terminal of the fourth resistor.

[0027] The second end of the third resistor and the second end of the fourth resistor are used to receive voltage supplied by an external power source.

[0028] The emitter of the fourth transistor and the emitter of the fifth transistor are connected to the third bias current source.

[0029] Secondly, a clock driver is provided, which employs the multi-fan-out circuit described above. It is understood that the beneficial effects of the second aspect are described in the relevant section of the first aspect above, and will not be repeated here. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of a multi-fan-out circuit provided in an embodiment of this application;

[0032] Figure 2 This is a schematic diagram of a conversion circuit provided in an embodiment of this application;

[0033] Figure 3 This is a circuit structure diagram of an LVPECL output circuit provided in an embodiment of this application;

[0034] Figure 4 This is a schematic diagram of an amplifier circuit provided in an embodiment of this application;

[0035] Figure 5 This is a circuit diagram of a differential amplifier provided in an embodiment of this application;

[0036] Figure 6 This is a schematic diagram of a 1:16 fan-out circuit provided in an embodiment of this application;

[0037] Figure 7 This is a schematic diagram of an LVPECL output circuit provided in an embodiment of this application. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0039] It should be understood that "multiple" as mentioned in this application refers to two or more. In the description of this application, unless otherwise stated, " / " indicates "or," for example, A / B can mean A or B; "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist, for example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, to facilitate a clear description of the technical solutions of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0040] Before providing a detailed explanation of the embodiments of this application, the application scenarios of these embodiments will be described first.

[0041] The oscillator outputs a set of differential input signals. Since multiple channels need to use the same differential input signals, a clock driver is required to fan out the set of differential input signals.

[0042] The multi-fan-out circuit and clock driver provided in the embodiments of this application will be explained in detail below.

[0043] Figure 1A multi-fan-out circuit provided in this application includes: an amplifier circuit 101, a bias circuit 102, and multiple LVPECL output circuits 103. The amplifier circuit 101 is connected to the multiple LVPECL output circuits 103, and the bias circuit 102 is connected to both the amplifier circuit 101 and the multiple LVPECL output circuits 103. The bias circuit 102 provides current bias and switching signals to the amplifier circuit 101 and the multiple Low Voltage Positive Emitter Coupled Logic (LVPECL) output circuits 103. Each LVPECL output circuit includes two mirror-symmetrical conversion circuits. The amplifier circuit 101 is connected to the two conversion circuits included in each LVPECL output circuit 103, and is used to amplify a set of received differential input signals to obtain a first-level standard signal and a second-level standard signal with opposite potentials. The LVPECL output circuit 103 is used to convert a first-level standard signal into a first output signal using one of the two conversion circuits, and to convert a second-level standard signal into a second output signal using the other of the two conversion circuits, wherein the second output signal and the first output signal have opposite potentials.

[0044] The amplifier circuit 101 receives a set of differential input signals, namely a first signal and a second signal with equal amplitude and opposite phase. Examples include VINP and VINN signals. After receiving the VINP and VINN signals, the amplifier circuit 101 amplifies both signals so that the final output signal meets the standard conditions of the LVPECL output circuit 103.

[0045] In one embodiment of this application, the multi-fan-out circuit includes 16 LVPECL output circuits. The level standard signal received by each LVPECL output circuit needs to meet the LVPECL standard. Therefore, the amplifier circuit 101 outputs a first level standard signal OUTP and a second level standard signal OUTN that meet the conditions of the LVPECL output circuit.

[0046] This application provides a multi-channel fan-out circuit. A set of differential input signals input to the amplifier circuit is amplified to obtain a first-level standard signal and a second-level standard signal, which are then provided to multiple LVPECL output circuits. Since the amplifier circuit is connected to multiple LVPECL output circuits, each LVPECL output circuit can convert the first-level standard signal and the second-level standard signal as input signals to obtain two output signals, namely a first output signal and a second output signal. Therefore, this scheme can realize the function of converting a set of differential input signals into multiple high-speed data outputs. Furthermore, since the two conversion circuits are mirror-symmetrically arranged, the parasitic capacitance of the circuit signal lines of the two conversion circuits is the same, which ensures that the output signal of each conversion circuit, when used as a clock signal, arrives at the device with low skew.

[0047] In one embodiment of this application, the potential of the first level standard signal is opposite to the potential of the first output signal, and the potential of the second level standard signal is opposite to the potential of the second output signal.

[0048] As an example, when the potential of the first level standard signal is high, the first output signal is low; conversely, when the potential of the first level standard signal is low, the first output signal is high. The second level standard signal is the same as the second output signal, and will not be described again.

[0049] In one embodiment of this application, such as Figure 2 As shown, the conversion circuit 1031 includes an emitter follower circuit 201, a differential amplifier circuit 202, and an emitter coupling circuit 203. The emitter follower circuit 201 receives a first-level standard signal and is connected to the differential amplifier circuit 202. The differential amplifier circuit 202 receives the signal output from the emitter follower circuit 201, amplifies the signal output from the emitter follower circuit 201, and is connected to the emitter coupling circuit 203. The emitter coupling circuit 203 receives the signal output from the differential amplifier circuit and is used to make the potential of the output signal of the emitter coupling circuit 203 opposite to the potential of the level standard signal.

[0050] As an example, such as Figure 2 and Figure 3As shown, the emitter follower circuit 201 includes a transistor Q1 (i.e., the first transistor), whose base is used to receive a first-level standard signal. The differential amplifier circuit 202 includes a transistor Q2 (i.e., the second transistor) and a resistor R0 (i.e., the first resistor). The base of transistor Q2 is connected to the emitter of transistor Q1, and the collector of transistor Q2 is connected to the first terminal of resistor R0. The second terminal of resistor R0 is used to receive the voltage provided by the external power supply VDD. The emitter coupling circuit 203 includes a transistor Q3 (i.e., the third transistor), whose base is connected to the collector of transistor Q2, and whose emitter is used to output a first output signal. When the first-level standard signal is high and the second-level standard signal is low, the emitter coupling circuit 203 matches the levels of the first-level standard signal and the first output signal, as well as the levels of the second-level standard signal and the second output signal; that is, the first output signal is low and the second output signal is high.

[0051] In one embodiment of this application, the LVPECL output circuit 103 further includes a first bias current source and a second bias current source. The first bias current source is connected to an emitter follower circuit, and the second bias current source is connected to a differential amplifier circuit.

[0052] As an example, such as Figure 3 As shown, the positive terminal of bias current source Ibias1 (i.e., the first bias current source) is connected to the emitter of transistor Q1 (i.e., the first transistor), and the positive terminal of bias current source Ibias0 (i.e., the second bias current source) is connected to the emitter of diode Q2 (i.e., the second diode).

[0053] In one embodiment of this application, since the two conversion circuits 1031 have the same structure, as an example, refer to... Figure 3 The system is divided into a first conversion circuit 301 and a second conversion circuit 302. The second conversion circuit 302 includes transistors Q4, Q5, and Q6, and a resistor R1. The base of transistor Q4 receives a second-level standard signal. The base of transistor Q5 is connected to the emitter of transistor Q4, and the collector of transistor Q5 is connected to the first terminal of resistor R1. The second terminal of resistor R1 receives the voltage provided by the external power supply VDD. The base of transistor Q6 is connected to the collector of transistor Q5, and the emitter of transistor Q6 outputs a second output signal.

[0054] Among them, the positive terminal of bias current source Ibias1, which is the same as the first bias current source, is connected to the emitter of transistor Q5, and the positive terminal of bias current source Ibias0 (i.e. the second bias current source) is connected to the emitter of diode Q5.

[0055] In one embodiment of this application, reference is made to Figure 3One of the first conversion circuit 301 and the second conversion circuit 302 is obtained by copying the other.

[0056] As an example, the LVPECL output circuit 103 employs the HALF CELL layout technique. The HALF CELL technique involves the following steps: when drawing the circuit layout of the LVPECL output circuit 103, the first conversion circuit 301 is drawn first. The first conversion circuit 301 is multiplexed to generate the second conversion circuit 302, and the first conversion circuit 301 and the second conversion circuit 302 together form the circuit layout of the LVPECL output circuit.

[0057] For details, please refer to Figure 2 When drawing the LVPECL output circuit 103, the first conversion circuit 301 is drawn first, that is... Figure 3 After drawing the left half of the dashed line 1, copy the circuit diagram and mirror it. Connect the emitters of transistors Q2 and Q5 to complete the circuit diagram of LVPECL output circuit 103.

[0058] In one embodiment of this application, a set of differential input signals includes a first signal and a second signal with equal amplitude and opposite phase. For example... Figure 4 As shown, the amplifier circuit 101 includes an input circuit 401 and an intermediate amplifier circuit 402. The input terminal of the input circuit 401 receives a first differential input signal and a second differential input signal, and the output terminal of the input circuit 401 is connected to the input terminal of the intermediate amplifier circuit. The input circuit 401 pre-amplifies the first differential input signal to obtain a first-stage amplified signal and pre-amplifies the second differential input signal to obtain a second-stage amplified signal. The output terminal of the intermediate amplifier circuit 402 is connected to each LVPECL output circuit 103, and amplifies the first-stage amplified signal to obtain a first-level standard signal and amplifies the second-stage amplified signal to obtain a second-level standard signal. In one embodiment of this application, the input circuit 401 includes a first differential amplifier, and the intermediate amplifier circuit 402 includes a second differential amplifier. The first differential amplifier receives the first differential input signal and the second differential input signal, and the second differential amplifier receives the signal output from the input circuit. The first differential amplifier and the second differential amplifier have the same circuit structure.

[0059] As an example, the two input terminals of the first differential amplifier are used to receive the first differential input signal VINP and the second differential input signal VINN. After pre-amplifying and shaping the first and second differential input signals, the first differential amplifier outputs two output signals OUTP and OUTN. The input terminals of the second differential amplifier receive the signals OUTP and OUTN output by the first differential amplifier. That is, the second differential amplifier uses signals OUTP and OUTN as input signals, further amplifies signals OUTP and OUTN, and outputs a first-level standard signal and a second-level standard signal.

[0060] In one embodiment of this application, such as Figure 5 The circuit diagram of the first differential amplifier is shown. The first differential amplifier includes transistors Q7 (the fourth transistor), Q8 (the fifth transistor), resistors R2 (the third resistor), R3 (the fourth resistor), and a bias current source Ibias2 (the third bias current source). The base of transistor Q7 receives the first differential input signal, and the base of transistor Q8 receives the second differential input signal. The collector of transistor Q7 is connected to the first terminal of resistor R2, and the collector of transistor Q8 is connected to the first terminal of resistor R3. The second terminals of resistors R2 and R3 receive the voltage provided by the external power supply VDD. The emitters of transistors Q7 and Q8 are connected to the bias current source Ibias2.

[0061] The intermediate amplifier circuit 402 includes a second differential amplifier with the same structure as the first differential amplifier, such as... Figure 5 As shown. The bases of transistors Q7 and Q8 are used to receive the two output signals from the first differential amplifier. The collectors of transistors Q7 and Q8 are used to output the first-level standard signal and the second-level standard signal, respectively.

[0062] This application provides a clock driver for use in high-speed circuit systems with multiple clocks. The clock driver employs the aforementioned multi-fan-out circuit. The multi-fan-out circuit receives a set of clock input signals (e.g., a first differential input signal and a second differential input signal) and outputs multiple sets of clock output signals (e.g., multiple sets of first output signals and second output signals).

[0063] like Figure 6The diagram shows a multi-fan-out circuit in a clock driver according to an embodiment of this application. Input circuit 601 is a first differential amplifier used to receive differential input signals VINP and VINN. Intermediate amplifier circuit 602 is a second differential amplifier used to receive the differential input signal processed by input circuit 601 and amplify the signal into a first-level standard signal and a second-level standard signal. Bias circuit 603 connects input circuit 601, intermediate amplifier circuit 602, and 16 LVPECL output circuits 604, used to provide bias current and a turn-off signal. When input circuit 601 receives the first differential input signal VINP and the second differential input signal VINN, after processing by the first and second differential amplifiers, it outputs the first-level standard signal and the second-level standard signal to each LVPECL output circuit 604. Each LVPECL output circuit 604 amplifies the first-level standard signal and the second-level standard signal, outputting a first output signal and a second output signal, ultimately outputting 16 sets of first output signals OUTN and second output signals OUTP.

[0064] As another example, such as Figure 7 As shown in the figure, the structure of the LVPECL output circuit 701 is as follows. The first-level standard signal and the second-level standard signal are INP and INN, which are connected to the bases of transistors Q1 and Q4, and the tail current bias is provided by Vb. Transistors Q1 and Q4 have the same size. The output signal is connected to the bases of transistors Q2 and Q5. The amplified signal is output by transistors Q3 and Q6, where transistors Q2 and Q5 have the same size, and transistors Q3 and Q6 have the same size. The tail current bias is provided by Vb. After the first-level standard signal INP and the second-level standard signal INN pass through the emitter follower, i.e., transistors Q1 and Q4, the common-mode voltage is reduced, ensuring that the differential amplifier pair, i.e., transistors Q2 and Q5, are in the amplification region. The tail current Ib is controlled by Vb, and the output swing is Ib·R4. When INP is high, the base potential of transistor Q2 is high after passing through transistor Q1. Similarly, the base potential of transistor Q5 is low. Most of the tail current flows through transistor Q2, the base potential of transistor Q3 is low, and the base potential of transistor Q6 is high. Therefore, the output OUTN is low and OUTP is high. The reverse is also true, which will not be elaborated here.

[0065] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0066] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0067] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A multi-fanout circuit, characterized by, The circuit comprises an amplification circuit, a biasing circuit and a plurality of LVPECL output circuits, The biasing circuit is connected with the amplification circuit and each of the LVPECL output circuits, and is configured to provide current bias and switching signals; Each of the LVPECL output circuits comprises two mirror-symmetrical conversion circuits; The amplification circuit is connected with the two conversion circuits of each of the LVPECL output circuits, and is configured to amplify a group of received differential input signals to obtain first and second level standard signals with opposite potentials; The LVPECL output circuit is configured to convert the first level standard signal into a first output signal by using one of the two conversion circuits, and to convert the second level standard signal into a second output signal by using the other of the two conversion circuits, the second output signal having opposite potential to the first output signal; The conversion circuit comprises an emitter follower circuit, a differential amplification circuit and an emitter coupling circuit, the emitter follower circuit comprising a first transistor, a base of the first transistor being configured to receive the level standard signal; The differential amplification circuit comprises a second transistor and a first resistor, a base of the second transistor being connected with an emitter of the first transistor, a collector of the second transistor being connected with a first end of the first resistor, and a second end of the first resistor being configured to receive a voltage provided by an external power supply; The emitter coupling circuit comprises a third transistor, a base of the third transistor being connected with a collector of the second transistor, and an emitter of the third transistor being configured to output the output signal.

2. The circuit of claim 1, wherein, The first level standard signal has opposite potential to the first output signal, and the second level standard signal has opposite potential to the second output signal.

3. The circuit of claim 1, wherein, The emitter follower circuit is configured to receive a level standard signal, and the emitter follower circuit is connected with the differential amplification circuit; the level standard signal is the first level standard signal or the second level standard signal; The differential amplification circuit is configured to receive a signal output by the emitter follower circuit, and to amplify the signal output by the emitter follower circuit, and the differential amplification circuit is connected with the emitter coupling circuit; The emitter coupling circuit is configured to receive a signal output by the differential amplification circuit, and to make a potential of an output signal output by the emitter coupling circuit opposite to a potential of the level standard signal.

4. The circuit according to any one of claims 1 to 3, characterized in that The LVPECL output circuit further comprises a first biasing current source and a second biasing current source, the first biasing current source being connected with an emitter follower circuit of a first conversion circuit of the two conversion circuits, and the second biasing current source being connected with a differential amplification circuit of the first conversion circuit.

5. The circuit according to any one of claims 1 to 3, characterized in that One of the two conversion circuits is obtained by copying the other of the two conversion circuits.

6. The circuit according to any one of claims 1 to 3, characterized in that The group of differential input signals comprises first and second signals with equal amplitude and opposite phase, and the amplification circuit comprises an input circuit and an intermediate amplification circuit, The first input end of the input circuit is configured to receive the first signal, the second input end of the input circuit is configured to receive the second signal, the first output end of the input circuit is connected to the first input end of the intermediate amplification circuit, the second output end of the input circuit is connected to the second input end of the intermediate amplification circuit, the input circuit is configured to pre-amplify the first signal to obtain a first-level amplified signal, and configured to pre-amplify the second signal to obtain a second-level amplified signal; The output end of the intermediate amplification circuit is connected to each of the LVPECL output circuits, and is configured to amplify the first-level amplified signal to obtain the first-level standard signal, and configured to amplify the second-level amplified signal to obtain the second-level standard signal.

7. The circuit of claim 6, wherein, The input circuit comprises a first differential amplifier, and the intermediate amplification circuit comprises a second differential amplifier, The first input end of the first differential amplifier is configured to receive the first signal, and the second input end of the first differential amplifier is configured to receive the second signal; The first input end of the second differential amplifier is configured to receive the first-level amplified signal, and the second input end of the second differential amplifier is configured to receive the second-level amplified signal, and the output end of the second differential amplifier is connected to the first input end and the second input end of each of the LVPECL output circuits, the first input end of the LVPECL output circuit is configured to receive the first-level standard signal, and the second input end of the LVPECL output circuit is configured to receive the second-level standard signal.

8. The circuit of claim 7, wherein, At least one of the first differential amplifier and the second differential amplifier comprises the following structure: a fourth transistor, a fifth transistor, a third resistor, a fourth resistor, and a third bias current source, the base of the fourth transistor is configured to receive the first signal, and the base of the fifth transistor is configured to receive the second signal, the collector of the fourth transistor is connected to the first end of the third resistor, and the collector of the fifth transistor is connected to the first end of the fourth resistor, the second end of the third resistor and the second end of the fourth resistor are configured to receive a voltage provided by an external power supply, the emitter of the fourth transistor and the emitter of the fifth transistor are connected to the third bias current source.

9. A clock driver, characterized by The clock driver adopts the multi-fanout circuit according to any one of claims 1-8.

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