An FPGA-based ADC sampling data calibration method and system
By using an FPGA-based ADC sampling data calibration method, which utilizes neural network training and FPGA resources for data calibration, the problems of high resource consumption and slow speed in traditional ADC calibration technology are solved, and a fast and efficient data calibration effect is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHONGQING UNIV OF POSTS & TELECOMM
- Filing Date
- 2022-09-20
- Publication Date
- 2026-05-29
AI Technical Summary
Existing ADC digital calibration technology suffers from high overall resource consumption, slow data processing speed, and low data throughput.
An FPGA-based ADC sampling data calibration method is adopted. The neural network is trained by acquiring the original and standard sampling data of the ADC, the data calibration is performed using the internal resources of the FPGA, and the data processing is performed using the RAM memory and multiplier IP core of the FPGA to achieve rapid data calibration.
It enables fast and efficient ADC sampling data calibration, improves data throughput and processing speed, optimizes FPGA resource utilization, and matches higher system frequencies.
Smart Images
Figure CN115425976B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of artificial intelligence, and specifically relates to an FPGA-based ADC sampling data calibration method and system. Background Technology
[0002] Discrete digital signals are easier to process, store, and display. Nowadays, continuous signals are made discrete through analog-to-digital converters (ADCs). ADCs, acting as a bridge between the analog and digital worlds, are commonly used in modern information systems such as multimedia, communications, automation, and instrumentation. With the rapid growth of data, the demands on ADCs are increasing, requiring higher sampling rates, higher bandwidth, and sufficient quantization accuracy. This places higher demands on parameters such as the signal-to-noise ratio (SNR), differential nonlinearity (DNL), integral nonlinearity (INL), clutter-free dynamic range (SFDR), and effective bits per second (ENOB) of the ADC output data. Therefore, more optimized ADC calibration techniques are needed.
[0003] Currently, most ADC calibrations use traditional digital calibration techniques. Although compared to analog calibration, it can effectively eliminate various nonlinear errors such as non-ideal operational amplifiers, capacitor mismatch, charge injection, comparator offset, and process errors, the current ADC digital calibration technology still has disadvantages such as high overall resource consumption, slow data processing speed, and low data throughput. Summary of the Invention
[0004] This invention addresses the problems of high overall resource consumption, slow data processing speed, and low data throughput in existing ADC digital calibration technologies. It proposes an FPGA-based ADC sampling data calibration method and system, specifically including:
[0005] An FPGA-based ADC sampling data calibration method includes the following steps:
[0006] S1: Obtain the raw ADC sampling data and the standard ADC sampling data; train the neural network based on the raw ADC sampling data and the standard ADC sampling data to obtain the trained neural network parameters, which include: the first parameter and the second parameter;
[0007] S2: Input the first parameter into the FPGA's RAM memory, and build a top-level module inside the FPGA according to the second parameter;
[0008] S3: The FPGA acquires the ADC sampling data to be calibrated and saves it to the RAM memory;
[0009] S4: The FPGA acquires the user's control signal and shifts the ADC sampling data to be calibrated in the RAM memory to n registers in sequence according to the control signal. When all n registers contain the ADC sampling data to be calibrated, the FPGA generates a flag signal.
[0010] S5: The FPGA reads the first parameter from the RAM memory according to the flag signal; and repeatedly calls the multiplier IP core to multiply the ADC sampling data to be calibrated in the register with the first parameter in turn to obtain the first ADC calibration data;
[0011] S6: The FPGA inputs the first ADC calibration data into the top-level module, and processes the first ADC calibration data through the second parameter to obtain the final ADC calibration data;
[0012] S7: Repeat steps S4-S6 to calibrate all the ADC sampling data to be calibrated.
[0013] An FPGA-based ADC sampling data calibration system is provided. The ADC sampling data calibration system is used to execute the FPGA-based ADC sampling data calibration method. The ADC calibration system includes: a clock module, a RAM memory, an ADC digital-to-analog converter, a data receiving module, an input control module, a data processing module, a register group, a multiplier, and a top-level module. The top-level module is designed based on an FPGA programmable logic device and is constructed by calling logic gate control circuits according to a second parameter.
[0014] The clock module is used to provide clock signals to the entire system;
[0015] An ADC (Digital-to-Analog Converter) is used to acquire the sampling data of the ADC to be calibrated;
[0016] The data receiving module is used to receive the trained neural network parameters, which include: a first parameter and a second parameter.
[0017] The RAM memory is used to store the ADC sampling data and the first parameter to be calibrated;
[0018] The input control module is used to receive user input control signals;
[0019] The data processing module includes a data reading unit and a data calibration unit;
[0020] The data reading unit is used to read the ADC sampling data to be calibrated from the RAM memory according to the input control signal, and to shift the ADC sampling data to be calibrated to the register group in sequence. When the register group is full of ADC sampling data to be calibrated, the data processing module generates a flag signal.
[0021] The data calibration unit is used to read the first parameter from the RAM memory according to the flag signal; and repeatedly call the IP core of the multiplier to multiply the ADC sampling data to be calibrated in the register group with the first parameter in turn to obtain the first ADC calibration data;
[0022] The top-level module is used to process the first ADC calibration data according to the second parameter to obtain the final ADC calibration data.
[0023] The present invention has at least the following beneficial effects
[0024] This invention presents an FPGA-based ADC sampling data calibration method and system. It allows for batch input of different ADC sampling data, features a simple structure and excellent portability, and enables real-time calibration of ADC-acquired data via FPGA, resulting in faster calibration times. The method described in this invention rationally allocates FPGA on-chip resources, automatically calibrates ADC-acquired data, and improves data throughput. By repeatedly calling the multiplier IP core, multiple ADC sampling data in the registers are processed in parallel, accelerating the calibration speed. Furthermore, by calling the multiplier, computational latency can be reduced, allowing for matching with higher system frequencies and improving the calibration efficiency of ADC sampling data. Attached Figure Description
[0025] Figure 1 This invention provides an FPGA-based ADC sampling data calibration method.
[0026] Figure 2 : This is a schematic diagram of the neural network structure of the present invention;
[0027] Figure 3 This is a flowchart illustrating the ADC sampling data calibration process based on neural networks according to the present invention.
[0028] Figure 4 : This is a block diagram of the ADC sampling data calibration system of the present invention. Detailed Implementation
[0029] The specific embodiments of the present invention are described below with reference to the accompanying drawings and specific examples. The drawings are for illustrative purposes only and represent schematic diagrams, not actual objects. To better illustrate the embodiments of the present invention, some parts in the drawings may be omitted, enlarged, or reduced.
[0030] Please see Figure 1 This invention provides an FPGA-based ADC sampling data calibration method, which includes the following steps:
[0031] S1: Obtain the raw ADC sampling data and the standard ADC sampling data; train the neural network based on the raw ADC sampling data and the standard ADC sampling data to obtain the trained neural network parameters. The trained neural network parameters include: a first parameter and a second parameter. For ease of calculation, the first parameter is divided into X groups and the second parameter is divided into M groups in this invention. The raw ADC sampling data represents the actual data sampled by the ADC, and the standard ADC sampling data represents the predicted value calculated from the ADC factory parameters.
[0032] In a preferred embodiment, the neural network includes: an input layer, a hidden layer, an output layer, and a ReLU activation function, and the expression of the neural network includes:
[0033] Dividing the first parameter into X groups and the second parameter into M groups, the expression for the neural network is obtained as follows:
[0034]
[0035] Relu[i] = Max(Dout_L1[i], 0)
[0036]
[0037] Where D[j] represents the j-th raw ADC sample data, Weight_L1[i][j] represents the j-th weight parameter of the i-th group of the hidden layer of the neural network, Dout_L1[i] represents the i-th output result of the hidden layer of the neural network, Scale_L1 represents the coefficient of the hidden layer of the neural network, Bias_L1[i] represents the i-th bias parameter of the hidden layer of the neural network, Relu[i] represents the i-th activation function, Weight_L2 represents the i-th weight parameter of the output layer of the neural network, Scale_L2 represents the coefficient of the output layer of the neural network, Bias_L2 represents the bias parameter of the output layer of the neural network, Dout represents the output result of the output layer of the neural network, X represents the number of groups of the first parameter, and M represents the number of groups of the second parameter.
[0038] Please see Figure 2 Preferably, the first parameter includes: weight parameters of the hidden layer of the neural network; the second parameter includes: coefficients of the hidden layer of the neural network, bias parameters of the hidden layer of the neural network, coefficients of the output layer of the neural network, activation function of the neural network, bias parameters of the output layer of the neural network, and weight parameters of the output layer of the neural network.
[0039] In a preferred embodiment, the specific steps for training the neural network include:
[0040] S11: Input the raw ADC sampling data as training samples into the neural network to obtain the output result of the neural network;
[0041] S12: Calculate the loss function of the neural network based on the output of the neural network and the standard sampling data of the ADC;
[0042] S13: Continuously adjust the parameters of the neural network until the loss function is less than the set threshold, and complete the training of the model.
[0043] In a preferred embodiment, the loss function of the neural network includes:
[0044]
[0045] Where L represents the loss function, n represents the number of original ADC sampled data, and Y... k f(x) represents the value output by the neural network from the raw ADC sampled data of the kth ADC. k ) represents the standard ADC sampled data corresponding to the k-th ADC raw sampled data.
[0046] In a preferred embodiment, the specific steps for training the neural network further include:
[0047] Figure 3 The diagram below illustrates the neural network ADC calibration process of this invention. It comprises a three-layer network structure: the first layer is the input layer, the second layer is the hidden layer, and the third layer is the output layer. The entire process is described below with reference to the accompanying drawings: The raw ADC sampling data is used as the input data for this system. The first time, values 0-49 are taken, and Dout is calculated. The second time, values 1-50 are taken, and Dout is calculated again. This process continues until all values are taken. Each set of 50 values is multiplied by a corresponding weight_L1 value (each set of 50 weight_L1 values represents 1200 sets). The 50 values from each set are summed to form a single value, which is then multiplied by a coefficient Scal_L1 and added to the bias Bias_L1, resulting in one of 1200 possible values, C. The result C is activated by the ReLU function, and the output value is multiplied by the corresponding weights weight_L2 to obtain 1200 values. These values are then summed into one value, multiplied by the coefficient Scal_L2, and then added to the bias bias_L2 to obtain the final output result Dout. Based on the output result Dout and the standard ADC sampling data, the parameters in the neural network are adjusted using backpropagation. Compared with traditional neural networks, the network of this invention has fewer parameters and processes data faster.
[0048] A preferred embodiment of the present invention includes:
[0049] Step 1: First, use the raw ADC sampling data containing errors as the input data for the neural network. Based on the input data, design a reasonable overall architecture in Python, and adjust the network structure and determine the parameters of each layer according to the forward and backward propagation of the neural network.
[0050] Step 2: Based on the overall architecture diagram and parameters of each layer, evaluate the overall hardware resource utilization, make reasonable use of FPGA hardware resources, divide the FPGA into various modules, and connect all modules according to the previously designed overall architecture to form an overall processing system and realize the AI calibration function of ADC.
[0051] Step 3: Simulate and verify the processing system from Step 2 to obtain calibration results based on the AI algorithm. Compare these results with the simulation results from the Python model to verify the accuracy of the system. When the accuracy exceeds the set threshold, the system can be applied in batches to industrial manufacturing, electronic circuits, and other fields.
[0052] In a preferred embodiment, the FPGA is a Xilinx VC709 development board, which has 693,120 logic units and 3,600 DSP slice (digital signal processing) multipliers, and is a 40Gb / s connectivity platform for high-bandwidth, high-performance applications.
[0053] S2: Input the first parameter into the FPGA's RAM memory, and build a top-level module inside the FPGA according to the second parameter;
[0054] S3: The FPGA acquires the ADC sampling data to be calibrated and saves it to the RAM memory;
[0055] S4: The FPGA acquires the user's control signal and shifts the ADC sampling data to be calibrated in the RAM memory to n registers in sequence according to the control signal. When all n registers contain the ADC sampling data to be calibrated, the FPGA generates a flag signal.
[0056] S5: The FPGA reads the first parameter from the RAM memory according to the flag signal; and repeatedly calls the multiplier IP core to multiply the ADC sampling data to be calibrated in the register with the first parameter in turn to obtain the first ADC calibration data;
[0057] S6: The FPGA inputs the first ADC calibration data into the top-level module, and processes the first ADC calibration data through the second parameter to obtain the final ADC calibration data;
[0058] S7: Repeat steps S4-S6 to calibrate all the ADC sampling data to be calibrated.
[0059] In a preferred embodiment, the step of processing the first ADC calibration data using the second parameter to obtain the final ADC calibration data includes:
[0060] The first ADC calibration data is multiplied by the coefficients of the hidden layer of the neural network to obtain the second ADC calibration data;
[0061] The second ADC calibration data is added to the bias parameters of the hidden layer of the neural network to obtain the third ADC calibration data;
[0062] The third ADC calibration data is input into the ReLU activation function to calculate the fourth ADC calibration data;
[0063] The fifth ADC calibration data is obtained by multiplying the fourth ADC calibration data by the weight parameters of the neural network output layer;
[0064] The fifth ADC calibration data is multiplied by the coefficients of the neural network output layer to obtain the sixth ADC calibration data;
[0065] The final ADC calibration data is obtained by adding the sixth ADC calibration data to the bias parameters of the neural network output layer.
[0066] Please see Figure 4 An FPGA-based ADC sampling data calibration system is disclosed. The ADC calibration system is used to execute the FPGA-based ADC calibration method. The ADC calibration system specifically includes: a clock module, a RAM memory, an ADC digital-to-analog converter, a data receiving module, an input control module, a data processing module, a register group, a multiplier, and a top-level module.
[0067] The clock module is used to provide clock signals to the entire system;
[0068] An ADC (Digital-to-Analog Converter) is used to acquire the sampling data of the ADC to be calibrated;
[0069] The data receiving module is used to receive the trained neural network parameters, which include: a first parameter and a second parameter.
[0070] The RAM memory is used to store the ADC sampling data and the first parameter to be calibrated;
[0071] The input control module is used to receive user input control signals;
[0072] The data processing module includes a data reading unit and a data calibration unit;
[0073] The data reading unit is used to read the ADC sampling data to be calibrated from the RAM memory according to the input control signal, and to shift the ADC sampling data to be calibrated to the register group in sequence. When the register group is full of ADC sampling data to be calibrated, the data processing module generates a flag signal.
[0074] The data calibration unit is used to read the first parameter from the RAM memory according to the flag signal; and repeatedly call the IP core of the multiplier to multiply the ADC sampling data to be calibrated in the register group with the first parameter in turn to obtain the first ADC calibration data;
[0075] The top-level module is used to process the first ADC sampled data and calibration data according to the second parameter to obtain the final ADC calibration data.
[0076] A specific implementation of an FPGA-based ADC sampling data calibration system is described, wherein the clock module is used to provide clock signals to the input control module and the data processing module. Since this design uses a VC709 development board with a 200MHz differential crystal oscillator, the primitive IBUFGDS is used, and then a single-ended clock of 200MHz is obtained through a phase-locked loop (PLL) as the clock for the entire system.
[0077] A specific implementation of an FPGA-based ADC sampling data calibration system is provided. The input control module employs a state machine design, employing three states to control the receiving and transmitting of input control signals, including:
[0078] State 0: When an external input control signal pulse is received, the input control signal is pulled high when the pulse is detected, and the pulled-high input control signal is sent to the data processing module and jumps to State 1. Otherwise, the input control signal is low and State 0 is maintained.
[0079] State 1: After the input control signal is sent, the data processing module will return a completion signal. Upon detecting this signal, the input control signal will be pulled low, the sending of input control signals will stop, and the process will jump to State 2.
[0080] State 2: When an external signal is detected to be low, return to state 0 and wait for the next input control signal; otherwise, maintain state 1.
[0081] A specific implementation of an FPGA-based ADC sampling data calibration system is provided. The data reading unit is used to read the ADC sampling data to be calibrated from the RAM memory. All the ADC sampling data to be calibrated must be read from the RAM memory IP core, output through registers to the next stage for processing. This module adopts a state machine design, with nine states to read data from the RAM IP core, including:
[0082] State 0: When the input control module sends the input control signal, it jumps to state 1; otherwise, it remains in state 0.
[0083] State 1: Enable read in RAM IP core, start reading data from RAM, one reading of ADC sampling data to be calibrated is performed every clock cycle, and then jump to State 2.
[0084] State 2: Each ADC sampled data to be calibrated is sequentially placed into 50 registers D0, D1, D2...D49 for shifting. When the 50th value is read from RAM, the reading operation stops, and a flag signal is issued to start reading the first parameter, and then jumps to State 3.
[0085] State 3: Pull the flag signal low, stop the shift operation, and wait for the first parameter to be read. After the first parameter is read, a stop signal will be returned, and the process will jump to State 4.
[0086] State 4: Continue reading the value from the 51st RAM, perform register shifting, and then jump to State 5.
[0087] State 5: Stop reading RAM and shifting registers, pull the flag signal high again, and then jump to State 6.
[0088] State 6: Pull the flag signal low and wait for the first parameter to be read. After the first parameter is read, a stop signal will be returned and the process will jump to State 7.
[0089] State 7: If all the ADC sampling data to be calibrated in RAM has been read, jump to State 8 and send a data reading completion signal; otherwise, jump back to State 4.
[0090] State 8: Data reading is complete. Pull the data reading complete signal low and jump back to State 0.
[0091] In neural networks, since the first parameter data is relatively large and FPGA resources are limited, the first parameter data is added as a COE file and stored in the RAM IP core, while other parameters are directly defined as the second parameter.
[0092] A specific implementation of an FPGA-based ADC sampling data calibration system, wherein the data calibration unit includes:
[0093] The multiplier IP cores mult are called. By comparing the multiplier IP cores and directly using the multiplication symbol, the computation latency can be reduced and the system frequency can be matched.
[0094] One method of using the present invention. The method includes: overall hardware design process: First, the original sampled data in the ADC is used as the input data of this system and stored in the RAM IP core. The read enable in the RAM IP core is turned on, and data is read from the RAM. Data is read once every clock cycle. Values 0 to 49 are read from the RAM IP core. The reading operation is stopped, and the data is shifted to 50 registers in sequence. Second, the first parameter of the weight data in the RAM IP core is read. 50 values are grouped together, for a total of 1200 groups. One group is read every clock cycle. The weight data weight_L1[0][0] to weight_L1[0]
[49] read in the first group are multiplied by the input D0 to D49 in the multiply-accumulate module to obtain 50 values, which are then added to a single value. At the same time, the first parameter of the second group of weight data weight_L1[1][0] to weight_L1[1]
[49] is read. This process is repeated until all 1200 groups of weight data are read, resulting in 1200 values A. A pipelined design is implemented here, repeatedly calling 50 multipliers to reduce resource consumption. Each A is directly multiplied by the coefficient Scal_L1 in the top-level module, resulting in 1200 values B, which are placed in 1200 registers, plus 1200 bias values Bias_L1. After passing through the ReLU activation function, they are multiplied by the weight Weight_L2, resulting in 1200 values. These 12000 values are then summed into a single value. Finally, multiplied by the coefficient Scal_L2 and added to the bias Bias_L2, a final output result Dout is obtained. A completion signal is given to return to the input data module, and the above operation is repeated until the last data input is completed and the result is obtained, at which point the entire system stops.
[0095] In summary, this invention designs an FPGA-based ADC sampling data calibration method and device, which solves the problems of the traditional digital calibration structure needing improvement, overall resource consumption needing optimization, and data processing speed needing to be increased. Compared with the traditional digital calibration structure, this invention is more optimized and has a faster data processing speed. By reasonably allocating FPGA on-chip resources and optimizing the accelerator, the system operating clock is improved, further increasing the data throughput. This invention has a higher operation frequency and a higher data throughput.
[0096] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Without departing from the spirit and essence of the method of the present invention, those skilled in the art can make various corresponding changes according to the method of the present invention, and these all fall within the scope of protection of the claims of the present invention.
Claims
1. A method for calibrating ADC sampling data based on FPGA, characterized in that, include: S1: Acquire raw ADC sampling data and standard ADC sampling data; The neural network is trained based on the original sampling data and standard sampling data of the ADC to obtain the parameters of the trained neural network. The parameters of the trained neural network include: the first parameter and the second parameter. S2: Input the first parameter into the FPGA's RAM memory, and build a top-level module inside the FPGA according to the second parameter; S3: The FPGA acquires the ADC sampling data to be calibrated and saves it to the RAM memory; S4: The FPGA acquires the user's control signal and shifts the ADC sampling data to be calibrated in the RAM memory to n registers in sequence according to the control signal. When all n registers contain the ADC sampling data to be calibrated, the FPGA generates a flag signal. S5: The FPGA reads the first parameter from the RAM memory according to the flag signal; and repeatedly calls the multiplier IP core to multiply the ADC sampling data to be calibrated in the register with the first parameter in turn to obtain the first ADC calibration data; S6: The FPGA inputs the first ADC calibration data into the top-level module, and processes the first ADC calibration data through the second parameter to obtain the final ADC calibration data; S7: Repeat steps S4-S6 to calibrate all the ADC sampling data to be calibrated.
2. The FPGA-based ADC sampling data calibration method according to claim 1, characterized in that, The expression for the neural network includes: in, This represents the raw sampled data of the j-th ADC. This represents the j-th weight parameter in the i-th group of the hidden layer of the neural network. This represents the i-th set of output results from the hidden layer of the neural network. Represents the coefficients of the hidden layer in a neural network; This represents the i-th set of bias parameters for the hidden layer of the neural network; Denotes the activation function of the i-th group; This represents the i-th set of weight parameters of the output layer of the neural network; Represents the coefficients of the output layer of a neural network; This represents the bias parameters of the output layer of the neural network; This represents the output of the neural network output layer; X represents the number of groups for the first parameter; M represents the number of groups for the second parameter.
3. The FPGA-based ADC sampling data calibration method according to claim 1, characterized in that, The first parameter includes: the weight parameters of the hidden layer of the neural network; The second parameter includes: the coefficients of the hidden layer of the neural network, the bias parameters of the hidden layer of the neural network, the coefficients of the output layer of the neural network, the activation function of the neural network, the bias parameters of the output layer of the neural network, and the weight parameters of the output layer of the neural network.
4. The FPGA-based ADC sampling data calibration method according to claim 1, characterized in that, The process of training the neural network includes: S11: Input the raw ADC sampling data as training samples into the neural network to obtain the output result of the neural network; S12: Calculate the loss function of the neural network based on the output of the neural network and the standard sampling data of the ADC; S13: Continuously adjust the parameters of the neural network until the loss function is less than the set threshold, and complete the training of the model.
5. The FPGA-based ADC sampling data calibration method according to claim 1, characterized in that, The loss function of the neural network includes: Where L represents the loss function, and n represents the number of original ADC sample data. This represents the value output by the neural network from the raw ADC sample data of the kth ADC. This represents the standard ADC sampled data corresponding to the k-th raw ADC sampled data.
6. The FPGA-based ADC sampling data calibration method according to claim 1, characterized in that, The process of processing the first ADC calibration data using the second parameter to obtain the final ADC calibration data includes: The first ADC calibration data is multiplied by the coefficients of the hidden layer of the neural network to obtain the second ADC calibration data; The second ADC calibration data is added to the bias parameters of the hidden layer of the neural network to obtain the third ADC calibration data; The third ADC calibration data is input into the ReLU activation function to calculate the fourth ADC calibration data; The fifth ADC calibration data is obtained by multiplying the fourth ADC calibration data by the weight parameters of the neural network output layer; The fifth ADC calibration data is multiplied by the coefficients of the neural network output layer to obtain the sixth ADC calibration data; The final ADC calibration data is obtained by adding the sixth ADC calibration data to the bias parameters of the neural network output layer.
7. An FPGA-based ADC sampling data calibration system, said ADC calibration system being used to execute an FPGA-based ADC sampling data calibration method as described in any one of claims 1-6, characterized in that, The ADC sampling data calibration system includes: a clock module, a RAM memory, an ADC digital-to-analog converter, a data receiving module, an input control module, a data processing module, a register group, a multiplier, and a top-level module; The clock module is used to provide clock signals to the entire system; An ADC (Digital-to-Analog Converter) is used to acquire the sampling data of the ADC to be calibrated; The data receiving module is used to receive the trained neural network parameters, which include: a first parameter and a second parameter. The RAM memory is used to store the ADC sampling data and the first parameter to be calibrated; The input control module is used to receive user input control signals; The data processing module includes a data reading unit and a data calibration unit; The data reading unit is used to read the ADC sampling data to be calibrated from the RAM memory according to the input control signal, and to shift the ADC sampling data to be calibrated to the register group in sequence. When the register group is full of ADC sampling data to be calibrated, the data processing module generates a flag signal. The data calibration unit is used to read the first parameter from the RAM memory according to the flag signal; and repeatedly call the IP core of the multiplier to multiply the ADC sampling data to be calibrated in the register group with the first parameter in turn to obtain the first ADC calibration data; The top-level module is used to process the first ADC calibration data according to the second parameter to obtain the final ADC calibration data.