A strong signal comparison system for a data link communication dual-receiving channel

Abstract

The present invention discloses a strong signal comparison system for a data link communication dual-receiving channel, which includes a signal processing module and an AD conversion module. The output end of the AD conversion module is connected to the input end of the signal processing module. The AD conversion module is provided with two AD conversion channels with the same specifications; two impedance transformation modules for adapting the impedance of the AD conversion module, and their output ends are respectively connected to the input ends of the two AD conversion channels; two detection modules, whose input ends are respectively connected in series on two radio frequency microwave receiving channels of the data link communication system, and the output ends of each detection module are respectively connected to the input ends of each impedance transformation module. The present invention realizes the comparison of radio frequency microwave signals of two radio frequency microwave receiving channels, and can also use multiple such systems to compare the signal strengths of 4 or more channels, having the beneficial effects of intuitively feedbacking the signal strength, strong scalability, and being stable and reliable.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency and microwave communications, and more specifically, to a strong signal comparison system for a data link communication dual-receiving channel. Background Art

[0002] Data link communication generally refers to communication for transmitting data. A data link is a communication link that, among various users, based on a common communication protocol, uses automated radio transceiver equipment to transmit and exchange load data information.

[0003] During the use of multiple receiving channels of a data link communication system, interference signals with different pulse widths will be encountered, so the intensities of strong signals received by multiple receiving channels are different. During actual use, staff cannot compare the strong signals of multiple channels, so the optimal receiving channel cannot be directly selected for use. Comparing and combining the strong signals of multiple receiving channels can be used as a communication signal or a control signal to communicate or control with other related systems, realizing the scalability of the system. Therefore, how to achieve strong signal comparison in a data link communication system is a problem to be solved in this technical field. Summary of the Invention

[0004] One object of the present invention is to solve at least the above problems and / or deficiencies and provide at least the advantages described later.

[0005] To achieve these objects and other advantages of the present invention, a strong signal comparison system for a data link communication dual-receiving channel is provided, including a signal processing module and an AD conversion module, and the output end of the AD conversion module is connected to the input end of the signal processing module;

[0006] The AD conversion module is provided with two AD conversion channels of the same specification;

[0007] Two impedance transformation modules for adapting the impedance of the AD conversion module, and their output ends are respectively connected to the input ends of the two AD conversion channels;

[0008] Two detection modules, whose input ends are respectively connected in series to two radio frequency and microwave receiving channels of the data link communication system, and the output ends of each detection module are respectively connected to the input ends of each impedance transformation module.

[0009] Preferably, the AD conversion module includes:

[0010] An AD chip, and both of its two signal output ends are connected to the signal processing module;

[0011] Two pre-circuits, whose output ends are respectively connected to the signal input ends of the AD chip, and the input ends of each pre-circuit are connected to the output ends of each impedance transformation module.

[0012] Preferably, the pre-stage circuit includes: a DC-blocking capacitor C5, whose input end is connected to the output end of the impedance transformation module, and the output end of the DC-blocking capacitor C5 is connected to the signal input end of the AD chip; a pull-up resistor R4 and a pull-up resistor R5 are connected in parallel to the output end of the DC-blocking capacitor C5, and the input end of a filter capacitor C6 is connected in series between the pull-up resistor R4 and the pull-up resistor R5, and the output end of the filter capacitor C6 is grounded; an isolation capacitor C7 is also connected in parallel to the connection line between the DC-blocking capacitor C5 and the AD chip, a matching resistor R6 is connected in series to the input end of the isolation capacitor C7, a matching resistor R7 is connected in series to the input end of the isolation capacitor C7, and the output end of the isolation capacitor C7 is connected to the AD chip, and the input end of a filter capacitor C8 is connected in series between the matching resistor R6 and the matching resistor R7, and the output end of the filter capacitor C8 is grounded.

[0013] Preferably, the impedance transformation module includes: a single-supply broadband voltage-feedback operational amplifier, whose non-inverting input end is connected to one end of a capacitor C13, the other end of the capacitor C13 is connected to one end of a resistor R13, and the other end of the resistor R13 is connected to the output end of the detection module; one end of a resistor R14 is also connected to one end of the resistor R13, and the other end of the resistor R14 is grounded; the inverting input end of the single-supply broadband voltage-feedback operational amplifier is grounded, a resistor R15 is connected to the power supply terminal of the single-supply broadband voltage-feedback operational amplifier, the other end of the resistor R15 is connected to one end of the capacitor C13, the other end of the resistor R15 is also connected to one end of a resistor R16, and the other end of the resistor R16 is grounded, and the non-inverting input end and the output end of the single-supply broadband voltage-feedback operational amplifier are connected, and the output end of the single-supply broadband voltage-feedback operational amplifier is connected to the input end of the AD conversion channel.

[0014] Preferably, the detection module includes:

[0015] A detection chip, whose input end is connected to the RF input RFin of the RF microwave receiving channel through a DC-blocking capacitor C1, and one end of a bias resistor R1 is also connected to the input end of the detection chip, the other end of the bias resistor R1 is connected to a power supply voltage VB, and one end of a bypass capacitor C3 is also connected to the other end of the bias resistor R1, and the other end of the bypass capacitor C3 is grounded;

[0016] The output end of the detection chip is connected to the RF output RFout of the RF microwave receiving channel through a blocking capacitor C2. One end of a detection resistor R2 is connected to the output end of the detection chip. One end of a bypass capacitor C4 is connected to the other end of the resistor R2. The other end of the bypass capacitor C4 is grounded. The other end of the resistor R2 is also connected to one end of an external load resistor R3. One end of the external load resistor R3 is connected to the input end of the impedance transformation module, and the other end of the external load resistor R3 is grounded.

[0017] Preferably, the AD chip is set as the AD chip LTC2288IUP, the signal processing chip of the signal processing module is set as the FPGA chip XC7Z030-2FFG676I, and the output end of the AD chip LTC2288IUP is docked with the FPGA chip XC7Z030-2FFG676I.

[0018] Preferably, the detection chip is set as the detection chip VMMK-3213.

[0019] Preferably, the bias resistor R1 is calculated by the following formula:

[0020]

[0021] The present invention has at least the following beneficial effects:

[0022] First, through the present invention, two-channel signals with a maximum of 2W (33dBm) can be compared; the circuit has strong adaptability and can be connected in series to the receiving channel of an existing communication system for use; it has strong scalability. By processing signals in real time, some functions of a power meter device can be realized; by signal processing, interference signals with different pulse widths can be discovered; and other systems can be controlled and operated based on the judgment results; the structure is simple, the cost is low, and it is stable and reliable.

[0023] Second, through the present invention, the comparison of two strong signals is realized, and a suitable receiving channel can be selected in an electronic countermeasure battle; by using multiple such systems, convenient expansion can be achieved to realize the comparison of the signal intensities of 4 channels and above; it has little influence on the RF channel and can be easily introduced into an existing communication system.

[0024] Other advantages, objectives and features of the present invention will be partially reflected by the following description, and partially will also be understood by those skilled in the art through the research and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a system schematic diagram of the present invention.

[0026] Figure 2 It is a block diagram of the AD conversion module of the present invention.

[0027] Figure 3 This is a block diagram of the impedance transformation module of the present invention.

[0028] Figure 4 This is a block diagram of the detection module of the present invention. Specific embodiments

[0029] The following further describes the present invention in detail with reference to the accompanying drawings, so that those skilled in the art can implement it according to the description in the specification.

[0030] It should be understood that terms such as "having", "including", and "comprising" used herein do not exclude the presence or addition of one or more other elements or their combinations.

[0031] It should be noted that in the description of the present invention, the orientation or positional relationship indicated by the terms is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0032] In the description of the present invention, unless otherwise clearly specified and defined, terms such as "installed", "provided with", "sheathed / connected", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection, can be a mechanical connection, can be an electrical connection, can be directly connected, or can be indirectly connected through an intermediate medium, and can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0033] In addition, in the present invention, unless otherwise clearly specified and defined, the first feature being "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on" the second feature can be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "below" and "beneath" the second feature can be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0034] Figure 1 A strong signal comparison system for a data link communication dual-receiving channel of the present invention is shown, including a signal processing module 1 and an AD conversion module 2. The output end of the AD conversion module 2 is connected to the input end of the signal processing module 1;

[0035] The AD conversion module 2 is provided with two AD conversion channels with the same specifications;

[0036] Two impedance transformation modules 3 for adapting to the impedance of the AD conversion module 2, and their output ends are respectively connected to the input ends of the two AD conversion channels 2;

[0037] Two detection modules 4, whose input ends are respectively connected in series to the two radio frequency microwave receiving channels of the data link communication system, and the output ends of the detection modules 4 are respectively connected to the input ends of the impedance transformation modules 3.

[0038] Working principle: The two detection modules 4 are respectively connected in series to the two radio frequency microwave receiving channels of the data link communication system, and through the two detection modules 4, the two radio frequency microwave signals of the two radio frequency microwave receiving channels are respectively converted into two detection signals. The two detection signals are then respectively divided by the two impedance transformation modules 3 to meet the input level requirements of the AD conversion module 2, and at the same time, impedance conversion is realized to make the two detection signals match the input impedance of the AD conversion module 2. Then, the AD conversion module 2 realizes the analog-to-digital conversion of the two detection signals within the AD dynamic range, and transmits the two converted digital signals to the signal processing module 1. The signal processing module 1 processes the two digital signals, compares the strengths of the two digital signals, so as to realize the comparison of the radio frequency microwave signals of the two radio frequency microwave receiving channels. And the judgment result of the signal processing module 1 is used as a communication signal / control signal to communicate / control other related systems. And by using multiple such systems, convenient expansion can be achieved to compare the signal strengths of 4 channels and above. In this technical solution, the comparison of the radio frequency microwave signals of the two radio frequency microwave receiving channels is realized, and multiple such systems can also be used to compare the signal strengths of 4 channels and above, having the beneficial effects of intuitively feedbacking the signal strength, strong expansibility, stability and reliability.

[0039] As in the above solution, the AD conversion module 2 includes:

[0040] An AD chip 21, and its two signal output ends are both connected to the signal processing module 1;

[0041] Two pre-circuits, whose output ends are respectively connected to the signal input ends of the AD chip 21, and the input ends of the pre-circuits are connected to the output ends of the impedance transformation modules 3.

[0042] Working principle: Through two set pre-circuits, two RF signals can be sampled simultaneously, and the AD chip 21 can be protected by the two pre-circuits. At the same time, it ensures that the detection signals output by each impedance transformation module 3 can stably input into the AD chip 21. After the AD chip 21 converts the two detection signals into two digital signals, the AD chip 21 then transmits the two digital signals to the signal processing module 1 for processing. Adopting this method has the advantage of ensuring the system stability.

[0043] In the above solution, the pre-circuit includes: a DC-blocking capacitor C5, whose input end is connected to the output end of the impedance transformation module 3, and the output end of the DC-blocking capacitor C5 is connected to the signal input end of the AD chip 21; a pull-up resistor R4 and a pull-up resistor R5 are connected in parallel at the output end of the DC-blocking capacitor C5. The input end of a filtering capacitor C6 is also connected in series between the pull-up resistor R4 and the pull-up resistor R5, and the output end of the filtering capacitor C6 is grounded; an isolation capacitor C7 is also connected in parallel on the connection line between the DC-blocking capacitor C5 and the AD chip 21. The input end of the isolation capacitor C7 is connected in series with a matching resistor R6, and the input end of the isolation capacitor C7 is connected in series with a matching resistor R7. And the output end of the isolation capacitor C7 is connected to the AD chip 21. The input end of a filtering capacitor C8 is also connected in series between the matching resistor R6 and the matching resistor R7, and the output end of the filtering capacitor C8 is grounded.

[0044] As Figure 2 shown, the pre-circuit A22 includes a DC-blocking capacitor C5, a pull-up resistor R4, a pull-up resistor R5, a matching resistor R6, a matching resistor R7, an isolation capacitor C7, a filtering capacitor C6, and a filtering capacitor C8. The pre-circuit B23 includes a pull-up resistor R9, a matching resistor R10, a DC-blocking capacitor C9, a pull-up resistor R8, a matching resistor R11, an isolation capacitor C11, a filtering capacitor C10, and a filtering capacitor C12. Through the pre-circuit A22 and the pre-circuit B23, two RF signals can be sampled simultaneously; through the DC-blocking capacitor C5 and the DC-blocking capacitor C9, the two detection modules 4 and the AD conversion module 2 are isolated to protect the AD chip 21 from being damaged. The values of C5 and C9 should be 0.1 μF. The values of the matching resistor R6, the matching resistor R7, the matching resistor R10, and the matching resistor R11 should be 25 Ω, and the values of the isolation capacitor C7 and the isolation capacitor C11 should be 12 pF. The matching resistor R6, the matching resistor R7, and the isolation capacitor C7 constitute the isolation circuit of the pre-circuit A22, and the matching resistor R10, the matching resistor R11, and the isolation capacitor C11 constitute the isolation circuit of the pre-circuit B23. There are mainly two purposes for doing this: one is to isolate the drive circuit, sample and hold, and load circuit, and the other is to limit the broadband noise input to the AD chip 21.

[0045] In the above solution, the impedance transformation module 3 includes: a single - supply broadband voltage - feedback operational amplifier 31, one end of a capacitor C13 is connected to the non - inverting terminal thereof, the other end of the capacitor C13 is connected to one end of a resistor R13, the other end of the resistor R13 is connected to the output terminal of the detection module 4; one end of the resistor R13 is also connected to one end of a resistor R14, the other end of the resistor R14 is grounded; the inverting terminal of the single - supply broadband voltage - feedback operational amplifier 31 is grounded, a resistor R15 is connected to the power - supply terminal of the single - supply broadband voltage - feedback operational amplifier 31, the other end of the resistor R15 is connected to one end of the capacitor C13, the other end of the resistor R15 is also connected to one end of a resistor R16, the other end of the resistor R16 is grounded, and the non - inverting terminal and the output terminal of the single - supply broadband voltage - feedback operational amplifier 31 are connected, and the output terminal of the single - supply broadband voltage - feedback operational amplifier 31 is connected to the input terminal of the AD conversion channel.

[0046] Working principle: The impedance transformation module 3 is implemented by a single - supply broadband voltage - feedback operational amplifier 31. The resistors R13 and R14 perform voltage division on the detection voltage VD output by the detection module 4 to meet the input range of the AD conversion module 2; the resistors R15 and R16 provide a DC bias for the single - supply broadband voltage - feedback operational amplifier 31; the single - supply broadband voltage - feedback operational amplifier 31 is designed as a unity - gain follower circuit. The input impedance of the single - supply broadband voltage - feedback operational amplifier 31 is high - impedance, and the output is low - impedance, realizing the matching of the output impedance of the detection module 4 and the input impedance of the AD conversion module 2.

[0047] In the above solution, the detection module 4 includes:

[0048] A detection chip 41, its input terminal is connected to the RF input RFin of the RF microwave receiving channel through a DC - blocking capacitor C1, and one end of a bias resistor R1 is also connected to the input terminal of the detection chip 41, the other end of the bias resistor R1 is connected to a power - supply voltage VB, the other end of the bias resistor R1 is also connected to one end of a bypass capacitor C3, and the other end of the bypass capacitor C3 is grounded;

[0049] The output terminal of the detection chip 41 is connected to the RF output RFout of the RF microwave receiving channel through a DC - blocking capacitor C2, one end of a detection resistor R2 is connected to the output terminal of the detection chip 41, the other end of the resistor R2 is connected to one end of a bypass capacitor C4, the other end of the bypass capacitor C4 is grounded, the other end of the resistor R2 is also connected to one end of an external load resistor R3, and one end of the external load resistor R3 is connected to the input terminal of the impedance transformation module 3, and the other end of the external load resistor R3 is grounded.

[0050] Working principle: The specific implementation circuit of the detection module 4 is as Figure 4As shown in the figure, the input end of the detection chip 41 is connected to the RF input RFin after connecting the DC-blocking capacitor C1; one output end of the detection chip 41 is connected to the RF output RFout after connecting the DC-blocking capacitor C2, and the other output end outputs the detection voltage VD to the impedance transformation module 3. Through the DC-blocking capacitor C1 and the DC-blocking capacitor C2, the detection module 4 is isolated from the RF microwave receiving channel, and signal transmission is realized, reducing the influence of the detection module 4 on the RF microwave receiving channel. The capacitance values of the DC-blocking capacitor C1 and the DC-blocking capacitor C2 are related to the sampling frequency, and the value ranges of the DC-blocking capacitor C1 and the DC-blocking capacitor C2 should be from 0.5 pF to 2 pF.

[0051] In the above solution, the AD chip 21 is set as the AD chip LTC2288IUP, the signal processing chip 11 of the signal processing module 1 is set as the FPGA chip XC7Z030-2FFG676I, and the output end of the AD chip LTC2288IUP is docked with the FPGA chip XC7Z030-2FFG676I.

[0052] Working principle: After two analog signals are respectively input into the two AD conversion channels of the AD conversion module 2, the AD chip LTC2288IUP converts the analog signals into digital signals. The output end of the AD chip LTC2288IUP transmits the two digital signals to the signal processing module 1 in a 10-bit data format. The FPGA chip XC7Z030-2FFG676I in the signal processing module 1 processes the digital signals through programming to obtain useful information.

[0053] In the above solution, the detection chip 41 is set as the detection chip VMMK-3213. By setting the detection chip 41 as the detection chip VMMK-3213, the detection effect of the detection module 4 on the RF microwave receiving channel is guaranteed.

[0054] In the above solution, the bias resistor R1 is calculated by the following formula:

[0055]

[0056] It can be known from the formula that the resistance value of the bias resistor R1 is directly proportional to the magnitude of the power supply voltage VB. The resistance value of the bias resistor R1 is adjusted correspondingly with the magnitude of the power supply voltage VB to ensure that the bias resistor R1 works effectively in the circuit.

[0057] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and embodiments. It can be fully applied to various fields suitable for the present invention. For those skilled in the art, additional modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and the examples shown and described herein.

Claims

1. A strong signal comparison system for a data link communication dual-receiving channel, comprising a signal processing module and an AD conversion module. The output end of the AD conversion module is connected to the input end of the signal processing module. It is characterized in that: The AD conversion module is provided with two AD conversion channels with the same specifications; Two impedance transformation modules for adapting the impedance of the AD conversion module, and their output ends are respectively connected to the input ends of the two AD conversion channels; Two detection modules, whose input ends are respectively connected in series on the two radio frequency and microwave receiving channels of the data link communication system, and the output ends of each detection module are respectively connected to the input ends of each impedance transformation module; The AD conversion module includes: An AD chip, and its two signal output ends are both connected to the signal processing module; Two pre-circuits, whose output ends are respectively connected to the signal input ends of the AD chip, and the input ends of each pre-circuit are connected to the output ends of each impedance transformation module; The pre-circuit includes: a DC-blocking capacitor C5, whose input end is connected to the output end of the impedance transformation module, and the output end of the DC-blocking capacitor C5 is connected to the signal input end of the AD chip; the output end of the DC-blocking capacitor C5 is connected in parallel with a pull-up resistor R4 and a pull-up resistor R5. A filter capacitor C6 is connected in series between the pull-up resistor R4 and the pull-up resistor R5, and the output end of the filter capacitor C6 is grounded; an isolation capacitor C7 is also connected in parallel on the connection line between the DC-blocking capacitor C5 and the AD chip. A matching resistor R6 is connected in series at the input end of the isolation capacitor C7, and a matching resistor R7 is connected in series at the input end of the isolation capacitor C7. The output end of the isolation capacitor C7 is connected to the AD chip. A filter capacitor C8 is connected in series between the matching resistor R6 and the matching resistor R7, and the output end of the filter capacitor C8 is grounded; The impedance transformation module includes: a single-power-supply broadband voltage feedback operational amplifier, whose non-inverting input end is connected to one end of a capacitor C13. The other end of the capacitor C13 is connected to one end of a resistor R13, and the other end of the resistor R13 is connected to the output end of the detection module; one end of the resistor R13 is also connected to one end of a resistor R14, and the other end of the resistor R14 is grounded; the inverting input end of the single-power-supply broadband voltage feedback operational amplifier is grounded. The power supply end of the single-power-supply broadband voltage feedback operational amplifier is connected to a resistor R15, and the other end of the resistor R15 is connected to one end of the capacitor C13. The other end of the resistor R15 is also connected to one end of a resistor R16, and the other end of the resistor R16 is grounded. The non-inverting input end and the output end of the single-power-supply broadband voltage feedback operational amplifier are connected, and the output end of the single-power-supply broadband voltage feedback operational amplifier is connected to the input end of the AD conversion channel.

2. The strong signal comparison system for a data link communication dual-receiving channel according to claim 1, wherein The detection module includes: The detection chip, its input end is connected to the RF input RFin of the RF microwave receiving channel through a DC-blocking capacitor C1, and one end of a bias resistor R1 is also connected to the input end of the detection chip. The other end of the bias resistor R1 is connected to a power supply voltage VB. The other end of the bias resistor R1 is also connected to one end of a bypass capacitor C3, and the other end of the bypass capacitor C3 is grounded; The output end of the detection chip is connected to the RF output RFout of the RF microwave receiving channel through a DC-blocking capacitor C2. One end of a detection resistor R2 is connected to the output end of the detection chip. The other end of the resistor R2 is connected to one end of a bypass capacitor C4, and the other end of the bypass capacitor C4 is grounded. The other end of the resistor R2 is also connected to one end of an external load resistor R3, and one end of the external load resistor R3 is connected to the input end of the impedance transformation module, and the other end of the external load resistor R3 is grounded.

3. A strong signal comparison system for a data link communication dual-receiving channel according to claim 1, characterized in that The AD chip is set as the AD chip LTC2288IUP, and the signal processing chip of the signal processing module is set as the FPGA chip XC7Z030-2FFG676I. The output end of the AD chip LTC2288IUP is docked with the FPGA chip XC7Z030-2FFG676I.

4. A strong signal comparison system for a data link communication dual-receiving channel according to claim 2, characterized in that, The detection chip is set as the detection chip VMMK-3213.

5. A strong signal comparison system for a data link communication dual-receiving channel according to claim 2, characterized in that, The bias resistor R1 is calculated by the following formula: .

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