An asynchronous arbitration circuit, an asynchronous arbitration method, and an asynchronous arbitrator
By introducing filtering and a direct request forwarding mechanism into the asynchronous arbitration circuit, the metastability problem of the asynchronous arbitrator is solved, and the system stability and communication performance are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2022-09-13
- Publication Date
- 2026-06-23
AI Technical Summary
Asynchronous arbiters are prone to metastability issues in many-core systems, leading to circuit logic errors and affecting system stability.
Design an asynchronous arbitration circuit, including a request input unit, an arbitration unit, a filtering unit, and a handshake signal generation unit. The circuit eliminates metastable voltages through filtering to ensure circuit stability, and directly outputs a request forward signal during the arbitration process to reduce delay.
It effectively eliminates metastability issues, improves the stability of asynchronous arbitration circuits, reduces latency, and enhances the system's communication performance.
Smart Images
Figure CN115426321B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, and in particular to an asynchronous arbitration circuit, an asynchronous arbitration method, and an asynchronous arbitrator. Background Technology
[0002] Arbitrators are a crucial component of communication architectures. In Network-on-Chip (NoC) systems, multi-core systems, and many-core systems, arbitrators effectively schedule access to shared resources to prevent communication conflicts that occur when multiple hosts simultaneously access shared resources. Therefore, improving arbitrator performance is vital for enhancing the overall communication performance of the system.
[0003] With the development of many-core systems, the number of hosts within these systems is increasing. Compared to synchronous arbitrators, asynchronous arbitrators have advantages in terms of latency and power consumption. However, asynchronous arbitrators are prone to metastability, which can lead to errors in circuit logic and negatively impact system stability. Summary of the Invention
[0004] The purpose of this invention is to provide an asynchronous arbitration circuit, an asynchronous arbitration method, and an asynchronous arbitrator to solve the problem that metastability occurs in existing asynchronous arbitrators, leading to errors in circuit logic and negatively impacting system stability.
[0005] To achieve the above objectives, the present invention provides the following technical solution:
[0006] In a first aspect, the present invention provides an asynchronous arbitration circuit, comprising: a request input unit, an arbitration unit, a filtering unit, and a handshake signal generation unit, wherein:
[0007] The request input unit is connected to the arbitration unit and the handshake signal generation unit respectively; the arbitration unit is connected to the filtering unit.
[0008] The request input unit is used to transmit the request signal to the arbitration unit and the handshake signal generation unit respectively when the received response feedback signal is valid;
[0009] The arbitration unit is used to arbitrate the request signal and determine the target output signal;
[0010] The filtering unit is used to filter the target output signal to eliminate the corresponding metastable voltage in the target output signal and then output the corresponding response signal.
[0011] The handshake signal generation unit is used to output a request forward pass signal based on the request signal.
[0012] Compared with existing technologies, the asynchronous arbitration circuit provided by this invention, when the received response feedback signal is valid, transmits the request signal to both the arbitration unit and the handshake signal generation unit. This prevents new request signals from entering the arbitration unit and handshake signal generation unit before the current arbitration process is completed, thus avoiding circuit logic conflicts and ensuring circuit stability. The arbitration unit processes the request signal to determine the target output signal, and the filtering unit filters the target output signal to eliminate the corresponding metastable voltage before outputting the corresponding response signal. Based on this, after the arbitration unit processes the request signal and determines the target output signal, the filtering unit can filter the target output signal to eliminate the metastable voltage, further reducing the probability of metastable voltage transmission and thus avoiding metastability problems caused by metastable voltage, improving the stability of the asynchronous arbitration circuit. Furthermore, the handshake signal generation unit provided by this invention can directly output a request forwarding signal based on the request signal, without waiting for a round of arbitration to complete before transmitting the request forwarding signal, significantly improving the latency of the asynchronous arbitration circuit.
[0013] Therefore, the asynchronous arbitration circuit provided by the present invention can solve the problem that the asynchronous arbiter in the prior art will have metastability, which will lead to errors in the circuit logic and thus have a negative impact on the stability of the system.
[0014] Secondly, the present invention also provides an asynchronous arbitration method, applied to the asynchronous arbitrator described in the first aspect of the technical solution above, the asynchronous arbitration method comprising:
[0015] If the received response feedback signal is valid, the request input unit will transmit the request signal to the arbitration unit and the handshake signal generation unit respectively.
[0016] The arbitration unit arbitrates the request signal to determine the target output signal;
[0017] The filtering unit filters the target output signal to eliminate the corresponding metastable voltage, and then outputs the corresponding response signal.
[0018] The handshake signal generation unit outputs a request forwarding signal based on the request signal.
[0019] Compared with the prior art, the beneficial effects of the asynchronous arbitration method provided by the present invention are the same as those of the asynchronous arbitration circuit described in the above technical solutions, and will not be repeated here.
[0020] Thirdly, the present invention also provides an asynchronous arbitrator, including at least one asynchronous arbitration circuit as described in the first aspect of the technical solution above;
[0021] In the case where the asynchronous arbitrator includes a single-stage asynchronous arbitration circuit, the request forward signal is the response feedback signal.
[0022] In the case where the asynchronous arbiter includes at least two levels of asynchronous arbitration circuits, the request forward signal output by the handshake signal generation unit of each level is the request signal of the request unit corresponding to the next level of asynchronous arbitration circuit, and the response signal output by the filter unit corresponding to the next level of asynchronous arbitration circuit is the response feedback signal corresponding to the current level of asynchronous arbitration circuit.
[0023] Compared with the prior art, the beneficial effects of the asynchronous arbitrator provided by the present invention are the same as those of the asynchronous arbitration circuit described in the first aspect of the technical solution above, and will not be repeated here. Attached Figure Description
[0024] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:
[0025] Figure 1 A circuit diagram of an asynchronous arbitration circuit provided in an embodiment of the present invention;
[0026] Figure 2 This is a schematic diagram of the structure of a four-input asynchronous arbitrator provided in an embodiment of the present invention.
[0027] Figure label:
[0028] 1-Asynchronous arbitration circuit; 11-Request input unit;
[0029] 12 - Arbitration unit; 13 - Filtering unit;
[0030] 14 - Handshake signal generation unit; 111 - First AND-OR gate;
[0031] 112 - Second AND-OR gate, 121 - First NAND gate;
[0032] 122 - Second NAND gate, 131 - First NOR gate;
[0033] 132 - First AND gate, 133 - Second NOR gate;
[0034] 134 - Second AND gate, 141 - Request signal forwarding module;
[0035] 142 - Response signal feedback module. Detailed Implementation
[0036] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.
[0037] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.
[0038] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.
[0039] like Figure 1 As shown, this embodiment of the invention provides an asynchronous arbitration circuit 1, including a request input unit 11, an arbitration unit 12, a filtering unit 13, and a handshake signal generation unit 14, wherein:
[0040] The request input unit 11 is connected to the arbitration unit 12 and the handshake signal generation unit 14 respectively; the arbitration unit 12 is connected to the filtering unit 13.
[0041] The request input unit 11 is used to transmit the request signal to the arbitration unit 12 and the handshake signal generation unit 14 respectively when the received response feedback signal is in a valid state.
[0042] Arbitration unit 12 is used to arbitrate the request signal and determine the target output signal;
[0043] The filtering unit 13 is used to filter the target output signal to eliminate the corresponding metastable voltage in the target output signal and then output the corresponding response signal.
[0044] The handshake signal generation unit 14 is used to output a request forwarding signal based on the request signal.
[0045] When the above technical solution is adopted: If the received response feedback signal is valid, the request input unit 11 transmits the request signal to the arbitration unit 12 and the handshake signal generation unit 14 respectively. This prevents new request signals from entering the arbitration unit 12 and the handshake signal generation unit 14 before the current arbitration process is completed, thus avoiding circuit logic conflicts and ensuring circuit stability. The arbitration unit 12 is used to arbitrate the request signal and determine the target output signal. The filtering unit 13 is used to filter the target output signal to eliminate the corresponding metastable voltage and output the corresponding response signal. Based on this, after the arbitration unit 12 arbitrates the request signal and determines the target output signal, the filtering unit 13 can filter the target output signal to eliminate the metastable voltage, further reducing the probability of metastable voltage being transmitted, thereby avoiding metastability problems caused by metastable voltage and improving the stability of the asynchronous arbitration circuit 1. Furthermore, the handshake signal generation unit 14 provided in this embodiment of the invention can directly output a request forwarding signal based on the request signal, without waiting for a round of arbitration to be completed before transmitting the request forwarding signal, which can significantly improve the delay of the asynchronous arbitration circuit 1.
[0046] Therefore, the asynchronous arbitration circuit 1 provided in this embodiment of the invention can solve the problem that the asynchronous arbiter in the prior art will have metastability, which will lead to errors in the circuit logic and thus have a negative impact on the stability of the system.
[0047] Specifically, such as Figure 1 As shown, the first request signal receiving end of the request input unit 11 is electrically connected to the corresponding first external request signal end, the second request signal receiving end of the request input unit 11 is electrically connected to the corresponding second external request signal end, the first control signal receiving end and the second control signal receiving end of the request input unit 11 are both electrically connected to the response feedback signal output end of the handshake signal generation unit 14, the first output end of the request input unit 11 is electrically connected to the corresponding first input end of the arbitration unit 12, and the second output end of the request input unit 11 is electrically connected to the corresponding second input end of the arbitration unit 12, which is used to input the first request signal and the second request signal to the arbitration unit 12 when the response feedback signal is valid.
[0048] The first output terminal of the arbitration unit 12 is electrically connected to the corresponding first input terminal of the filter unit 13, and the second output terminal of the arbitration unit 12 is electrically connected to the corresponding second input terminal of the filter unit 13. It is used to determine the target output signal after arbitrating the first request signal and the second request signal, and transmit the corresponding target output signal to the filter unit 13. The target output signal can be the target output signal corresponding to the first request signal or the target output signal corresponding to the second request signal.
[0049] The first output terminal of the filter unit 13 is electrically connected to the first response signal output terminal, and the second output terminal of the filter unit 13 is electrically connected to the second response signal output terminal. The filter unit 13 is used to filter out the metastable voltage in the target output signal after receiving the target output signal, and finally output a voltage-stable response signal.
[0050] Meanwhile, the first and second output terminals of the request input unit 11 are also electrically connected to the request signal input terminal of the handshake signal generation unit 14, so that the handshake signal generation unit 14 can directly generate a request forwarding signal based on the first and second request signals output by the request input unit 11.
[0051] For example, in the asynchronous arbitration circuit 1 described above, if the request forward signal output by the handshake signal generation unit 14 is the response feedback signal of the asynchronous arbitration circuit 1, then the asynchronous arbitration circuit 1 is a two-input asynchronous arbitrator.
[0052] In one possible implementation, after the filtering unit 13 outputs the corresponding response signal, the current request signal corresponding to the response signal is set to an invalid state. The request input unit 11 is also used to sequentially pass the current request signal through the arbitration unit 12 and the filtering unit 13 to set the current response signal corresponding to the current request signal to an invalid state until the response feedback signal is in an valid state.
[0053] Understandably, when two or more request signals simultaneously enter the asynchronous arbitration circuit 1, after the arbitration unit 12 of the asynchronous arbitration circuit 1 determines the target output signal, it means that only the request signal corresponding to the target output signal is currently received. The filtering unit 13 outputs a corresponding response signal based on the target output signal. Upon receiving the response signal, the corresponding current request signal is set to an invalid state. Similarly, when the current request signal is in an invalid state, after passing through the arbitration unit 12 and the filtering unit 13 in sequence, the response signal will also be set to an invalid state. Furthermore, when the current request signal is in an invalid state, regardless of whether the response feedback signal is in a valid state, the current request signal can pass through the request input unit 11 to enter the arbitration unit 12 and the filtering unit 13 in sequence, setting the current response signal to an invalid state.
[0054] It should be noted that although two or more request signals enter the arbitration unit 12 at the same time, all output signals except the target output signal are invalid. The invalid output signals will also output invalid response signals after passing through the filtering unit 13. The invalid response signals will not affect the request signals. Only when a valid response signal is received will the request signal corresponding to the response signal be set to an invalid state.
[0055] In one possible implementation, such as Figure 1 As shown, the request input unit 11 includes a first AND-OR gate 111 and a second AND-OR gate 112, and the request signal includes a first request signal and a second request signal.
[0056] The first input terminal of the first AND-OR gate 111 is electrically connected to the first external request signal terminal, the second input terminal of the first AND-OR gate 111 is electrically connected to the response feedback signal output terminal of the handshake signal generation unit 14, the third input terminal of the first AND-OR gate 111 is electrically connected to the first external request signal terminal, the fourth input terminal of the first AND-OR gate 111 is electrically connected to the output terminal of the first AND-OR gate 111, the output terminal of the first AND-OR gate 111 is electrically connected to the input terminal of the arbitration unit 12, and the output terminal of the first AND-OR gate 111 is also electrically connected to the first input terminal of the handshake signal generation unit 14; the first AND-OR gate 111 is used to receive the first request signal.
[0057] The first input terminal of the second AND-OR gate 112 is electrically connected to the second external request signal terminal, the second input terminal of the second AND-OR gate 112 is electrically connected to the response feedback signal output terminal of the handshake signal generation unit 14, the third input terminal of the second AND-OR gate 112 is electrically connected to the second external request signal terminal, the fourth input terminal of the second AND-OR gate 112 is electrically connected to the output terminal of the second AND-OR gate 112, the output terminal of the second AND-OR gate 112 is electrically connected to the input terminal of the arbitration unit 12, and the output terminal of the second AND-OR gate 112 is also electrically connected to the second input terminal of the handshake signal generation unit 14; the second AND-OR gate 112 is used to receive the second request signal.
[0058] It should be noted that the first AND-OR gate 111 can be composed of two standard AND gates and one standard OR gate. That is, the first and second input terminals of the first AND-OR gate 111 are the two input terminals of an AND gate, and the third and fourth input terminals of the first AND-OR gate 111 are the two input terminals of another AND gate. The output terminals of the two AND gates are the two input terminals of the OR gate. That is, the signals received by the first and second input terminals of the first AND-OR gate 111 are subjected to AND logic operation, and the signals received by the third and fourth input terminals of the first AND-OR gate 111 are also subjected to AND logic operation. Then the output signals of the two AND gates are transmitted to the OR gate for OR logic operation. It can be understood that the second AND-OR gate 112 is the same, which will not be elaborated here.
[0059] Specifically, the first external request signal terminal is used to output the first request signal, and the first input terminal and the third input terminal of the first AND-OR gate 111 are both used to receive the first request signal. The first request signal is logically ANDed with the response feedback signal of the valid state. The first request signal is also logically ANDed with the output signal of the first AND-OR gate 111. The results of the two logical AND operations are then logically ORed and simultaneously output to the first input terminal of the arbitration unit 12 and the handshake signal generation unit 14.
[0060] The second external request signal terminal is used to output the second request signal. The first and third input terminals of the second AND-OR gate 112 are both used to receive the second request signal. The second request signal is ANDed with the response feedback signal of the valid state. The second request signal is also ANDed with the output signal of the second AND-OR gate 112. The results of the two AND operations are then ORed and output to the second input terminal of the arbitration unit 12 and the handshake signal generation unit 14.
[0061] Therefore, according to the operation rules of AND and OR gates, the first and second request signals transmitted by the request input unit 11 are only valid request signals when the response feedback signal received by the request input unit 11 is valid; otherwise, the request input unit 11 can only output invalid request signals. In other words, only when the response feedback signal is valid can a valid request signal pass through the request input unit 11 sequentially into the arbitration unit 12 and the filtering unit 13, thereby outputting a valid response signal. Furthermore, a valid request signal can directly pass through the request input unit 11 into the handshake signal generation unit 14, thereby outputting a valid request forwarding signal.
[0062] In one possible implementation, such as Figure 1 As shown, the arbitration unit 12 includes a first NAND gate 121 and a second NAND gate 122, and the request signal includes a first request signal and a second request signal.
[0063] The first input terminal of the first NAND gate 121 is electrically connected to the first output terminal of the request input unit 11, and the first input terminal is used to receive the first request signal. The second input terminal of the first NAND gate 121 is electrically connected to the output terminal of the second NAND gate 122. The output terminal of the first NAND gate 121 is electrically connected to the corresponding input terminal of the filter unit 13 and the first input terminal of the second NAND gate 122. The second input terminal of the second NAND gate 122 is electrically connected to the second output terminal of the request input unit 11, and the second input terminal is used to receive the second request signal. The output terminal of the second NAND gate 122 is also electrically connected to the corresponding input terminal of the filter unit 13. The first NAND gate 121 and the second NAND gate 122 are used to arbitrate the first request signal and the second request signal according to a preset gating level to determine the target output signal.
[0064] Specifically, the first NAND gate 121 and the second NAND gate 122 are coupled together. The first NAND gate 121 receives the first request signal output from the first output terminal of the request input unit 11, performs a logical AND operation with the output signal of the second NAND gate 122, and then performs a logical OR operation. The second NAND gate 122 receives the second request signal output from the second output terminal of the request input unit 11, performs a logical AND operation with the output signal of the first NAND gate 121, and then performs a logical OR operation. It should be understood that after the input signals of the first NAND gate 121 and the second NAND gate 122 undergo logical operations, the output signals of the first NAND gate 121 and the second NAND gate 122 are output signals with completely opposite levels. If the target level is preset to high level, then the high-level output signal is determined to be the target output signal, and the low-level output signal is the invalid output signal in this round of arbitration. If the target level is preset to low level, then the low-level output signal is determined to be the target output signal, and the high-level output signal is the invalid output signal in this round of arbitration.
[0065] In one possible implementation, such as Figure 1 As shown, the filtering unit 13 includes a first NOR gate 131, a first AND gate 132, a second NOR gate 133, and a second AND gate 134. The request signal includes a first request signal and a second request signal. The target output signal includes a first target output signal corresponding to the first request signal and a second target output signal corresponding to the second request signal.
[0066] The first input terminal of the first NOR gate 131 is electrically connected to the first output terminal of the arbitration unit 12. The second input terminal of the first NOR gate 131 is electrically connected to the response feedback signal output terminal of the handshake signal generation unit 14. The output terminal of the first NOR gate 131 is electrically connected to the first input terminal of the first AND gate 132. The second input terminal of the first AND gate 132 is electrically connected to the second target output signal output terminal of the arbitration unit 12. The output terminal of the first AND gate 132 is used to output a first response signal when the target output signal is the first target output signal.
[0067] The second input terminal of the second NOR gate 133 is electrically connected to the second output terminal of the arbitration unit 12. The second input terminal of the second NOR gate 133 is electrically connected to the response feedback signal output terminal of the handshake signal generation unit 14. The output terminal of the second NOR gate 133 is electrically connected to the first input terminal of the second AND gate 134. The second input terminal of the second AND gate 134 is electrically connected to the first target output signal output terminal of the arbitration unit 12. The output terminal of the second AND gate 134 is used to output a second response signal when the target output signal is the second target output signal.
[0068] Specifically, the first NOR gate 131 first performs a logical OR operation on the received signal, and then performs a logical NOT operation. Similarly, the second NOR gate 133 also first performs a logical OR operation on the received signal, and then performs a logical NOT operation. The first AND gate 132 performs a logical AND operation on the output signal of the first NOR gate 131 and the second target output signal output by the arbitration unit 12, and then outputs a first response signal. The second AND gate 134 performs a logical AND operation on the output signal of the second NOR gate 133 and the first target output signal output by the arbitration unit 12, and then outputs a second response signal.
[0069] Furthermore, NOR gates and AND gates can be logic gates without threshold values. For example, when the target level is set to low, the NOR gate can be set as a low-threshold standard NOR gate, and the AND gate can be set as a high-threshold standard AND gate. In this case, the low-threshold NOR gate can treat the metastable voltage as a high level, and after the high-level signal undergoes logical OR and logical NOT operations, it outputs an invalid low level. The high-threshold AND gate can extend the metastability resolution time and further reduce the probability of metastable voltage propagation, thereby solving the metastability problem.
[0070] In one possible implementation, such as Figure 1 As shown, the handshake signal generation unit 14 includes a request signal forwarding module 141 and a response signal feedback module 142. The input terminal of the request signal forwarding module 141 is electrically connected to the output terminal of the request input unit 11. The request signal forwarding module 141 is used to output a request forwarding signal based on the request signal.
[0071] The output terminal of the response signal feedback module 142 is electrically connected to the input terminal of the request input unit 11 and the input terminal of the filter unit 13, respectively. The response signal feedback module 142 is used to receive the response feedback signal and transmit the response feedback signal to the request input unit 11.
[0072] In some embodiments, such as Figure 1As shown, the request signal forwarding module 141 includes an OR gate, which has a first input, a second input, and an output. The first input of the OR gate is electrically connected to the first output of the request input unit 11, and the second input of the OR gate is electrically connected to the second output of the request input unit 11. The output of the OR gate is used to output a request forwarding signal based on the request signal.
[0073] Specifically, the OR gate performs a logical OR operation on the signals received from the first and second input terminals and outputs a request forwarding signal. The request signal includes a first request signal and a second request signal. Based on this, the request signal forwarding module 141 can directly generate a request forwarding signal based on the first and second request signals, further reducing the delay of the asynchronous arbitration circuit 1.
[0074] For example, the output of the OR gate can be electrically connected to the input of the request input unit 11 of the next-level asynchronous arbitration circuit 1. If the current asynchronous arbitration circuit 1 is the last-level asynchronous arbitration circuit 1, the output of the OR gate can be directly electrically connected to the input of the response signal feedback module 142 of the current-level asynchronous arbitration circuit 1.
[0075] In some embodiments, such as Figure 1 As shown, the response signal feedback module 142 includes a NOT gate, which has an input terminal and an output terminal. The output terminal of the NOT gate is electrically connected to the input terminal of the request input unit 11, and the output terminal of the NOT gate is also electrically connected to the input terminal of the filter unit 13. The input terminal of the NOT gate is used to receive the response feedback signal.
[0076] Specifically, the NOT gate performs a logical NOT operation on the received response feedback signal and outputs the NOT-operated response feedback signal to both the request input unit 11 and the filtering unit 13. For example, if the response feedback signal received by the NOT gate is taken as the first response feedback signal, and the response feedback signal output by the NOT gate is taken as the second response feedback signal, when the first response feedback signal is valid, the second response feedback signal is also valid; when the first response feedback signal is invalid, the second response feedback signal is also invalid. In this embodiment, the first response feedback signal can be set to a low level to be valid.
[0077] For example, the input of the NOT gate can be electrically connected to the output of the filter unit 13 of the next stage asynchronous arbitration circuit 1. If the current asynchronous arbitration circuit 1 is the last stage asynchronous arbitration circuit 1, the input of the NOT gate is directly electrically connected to the output of the request signal forwarding module 141.
[0078] This invention also provides an asynchronous arbitration method applied to the asynchronous arbitration circuit 1 described in the above embodiments, the asynchronous arbitration method comprising:
[0079] If the received response feedback signal is valid, the request input unit 11 will transmit the request signal to the arbitration unit 12 and the handshake signal generation unit 14 respectively.
[0080] Arbitration unit 12 arbitrates the request signal to determine the target output signal;
[0081] After filtering the target output signal to eliminate the corresponding metastable voltage, the filter unit 13 outputs the corresponding response signal.
[0082] The handshake signal generation unit 14 outputs a request forwarding signal based on the request signal.
[0083] Compared with the prior art, the beneficial effects of the asynchronous arbitration method provided in this embodiment of the invention are the same as those of the asynchronous arbitration circuit 1 described in the above embodiments, and will not be repeated here.
[0084] like Figure 1 and Figure 2 As shown, this embodiment of the invention also provides an asynchronous arbitrator, including at least one asynchronous arbitration circuit 1 as described in the above embodiments;
[0085] In the case where the asynchronous arbitrator includes a first-level asynchronous arbitration circuit 1, the request forward signal is the response feedback signal.
[0086] When the asynchronous arbiter includes at least two levels of asynchronous arbitration circuits 1, the request forward signal output by each level handshake signal generation unit 14 is the request signal of the request unit corresponding to the next level asynchronous arbitration circuit 1, and the response signal output by the filter unit 13 corresponding to the next level asynchronous arbitration circuit 1 is the response feedback signal corresponding to the current level asynchronous arbitration circuit 1.
[0087] Compared with the prior art, the beneficial effects of the asynchronous arbitrator provided in the embodiments of the present invention are the same as those of the asynchronous arbitration circuit 1 described in the above embodiments, and will not be repeated here.
[0088] In addition, such as Figure 1 The asynchronous arbitration circuit 1 shown is composed of logic gates from the standard cell library. It can function as a two-input asynchronous arbitrator or be cascaded with other gates to form an N-input tree arbitrator.
[0089] For example, will Figure 1 The asynchronous arbitration circuit 1 shown is connected to the request signal forwarding module 141 and the response signal feedback module 142, forming a two-input asynchronous arbitrator. That is, the request forwarding signal in the current asynchronous arbitrator is the response feedback signal. Its working process is as follows:
[0090] In the initial state, the first request signal req0, the second request signal req1, the first acknowledgment signal ack0, and the second acknowledgment signal ack1 are all low, indicating that there is no request signal input at this time. The first request signal req0 and the second request signal req1 are ORed together to make the request forward signal REQ and the acknowledgment feedback signal ACK also low.
[0091] When the first request signal req0 and / or the second request signal req1 arrive, the first request signal req0 and / or the second request signal req1 become 1. At this time, ACK is 0, the first AND-OR gate 111 and / or the second AND-OR gate 112 of the request input unit 11 are opened, and the first request signal req0 and / or the second request signal req1 enter the arbitration unit 12.
[0092] Arbitration unit 12's first NAND gate 121 and second NAND gate 122 arbitrate the first request signal req0 and the second request signal req1. Based on a preset target level, it determines the target input signal, i.e., selects one of the first request signal req0 and the second request signal req1, and outputs it to filtering unit 13. Simultaneously, the first request signal req0 and the second request signal req1 generate a request forward signal REQ through the OR gate of handshake signal generation unit 14, thereby making the response feedback signal ACK become 1.
[0093] The response feedback signal ACK will, on the one hand, close the first AND-OR gate 111 and the second AND-OR gate 112 of the request input section to prevent the next request from participating in the arbitration process and causing a logical function error. On the other hand, it will open the first NOR gate 131 and the second NOR gate 133 of the filter unit 13 to successfully generate the first response signal ack0 or the second response signal ack1.
[0094] Furthermore, the first response signal ack0 or the second response signal ack1 passes through the first NOR gate 131 or the second NOR gate 133 with a low threshold, and the first AND gate 132 or the second AND gate 134 with a high threshold to filter out the metastable voltage present therein, and finally outputs the first response signal ack0 or the second response signal ack1 without metastable current.
[0095] Upon receiving the first acknowledgment signal ack0 or the second acknowledgment signal ack1, the corresponding first request signal req0 or second request signal req1 is set to a low level. At this point, there is no need to wait for the acknowledgment feedback signal ACK to be set low; the low-level request signal can directly set the received first acknowledgment signal ack0 or second acknowledgment signal ack1 to a low level through the request input unit 11, arbitration unit 12, and filtering unit 13. This completes one arbitration process. The next arbitration process can only begin after the acknowledgment feedback signal ACK is set low.
[0096] When an asynchronous arbitrator includes at least two levels of asynchronous arbitrators, for example, such as Figure 2 The four-input asynchronous arbitrator shown includes three asynchronous arbitration circuits 1. The first-stage asynchronous arbitration circuit 1 includes Cell-1 and Cell-2, and the second-stage asynchronous arbitration circuit 1 includes Cell-3. Cell-1 in the first-stage asynchronous arbitration circuit 1 receives a first request signal req0 and a second request signal req1, while Cell-2 in the first-stage asynchronous arbitration circuit 1 receives a third request signal req2 and a fourth request signal req3. Cell-1 is used to arbitrate the first request signal req0 and the second request signal req1, and Cell-2 is used to arbitrate the third request signal req2 and the fourth request signal req3. Simultaneously, without waiting for the arbitration result, Cell-1 and Cell-2 output request forwarding signals REQ0 and REQ1 respectively to Cell-3 in the second-stage asynchronous arbitration circuit 1. The request forwarding signal REQ0 output by Cell-1 is the first request signal req0 received by Cell-3 in the second-stage asynchronous arbitration circuit 1, and the response feedback signal ACK0 received by Cell-1 is the first response signal ACK0 output by Cell-3. Similarly, the request forwarding signal REQ1 output by Cell-2 is the second request signal req1 received by Cell-3, and the response feedback signal ACK1 received by Cell-2 is the second response signal ACK1 output by Cell-3. Cell-3 is used to arbitrate the received first request signal req0 and second request signal req1, selecting one of the request signals and outputting the corresponding response signal. Cell-1 or Cell-2 receives the response signal ACK0 or ACK1 from Cell-3, thereby generating the response signal ack0 or ack1 or ack2 or ack3 corresponding to the request input. This process is repeated until all input request signals have been processed and the request signals are set to an invalid state. The corresponding response signal does not need to wait for the feedback of the response signal of the next level and can be directly set to an invalid state by the invalid request signal, reducing the delay in the entire arbitration process. Furthermore, since Cell-3 in the second-level asynchronous arbitration circuit 1 is the last-level asynchronous arbitration circuit 1, the output terminal of the request forwarding signal module of Cell-3 is directly electrically connected to the input terminal of the response feedback module.
[0097] Based on this, the embodiments of the present invention utilize fast request forwarding technology. The handshake signal generation unit 14 can directly generate a request forwarding signal based on the request signal, directly transmitting the request of this level to the next level without waiting for the arbitration of this level to be completed, thus significantly improving arbitration latency. Based on fast response feedback technology, the response signal can be directly pulled low by the request signal without waiting for the response feedback signal of the next level, greatly reducing arbitration latency.
[0098] As can be seen from the above, the asynchronous arbitrators provided in this embodiment of the invention are all designed using logic gates from the standard cell library, replacing the use of analog circuits in the prior art to solve the metastability problems that may occur in asynchronous arbitrators. The circuit design can be completed using mainstream Electronic Design Automation (EDA) tools, enabling the asynchronous arbitrator to be implemented using the hardware description language Verilog. This simplifies the entire design process in large-scale digital circuit design and reduces the design difficulty of the circuit. At the same time, the asynchronous arbitrator also has two internal mechanisms: fast request forwarding and fast response feedback, which effectively reduce the latency of multi-input arbitrators and improve the communication performance of digital systems.
[0099] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.
[0100] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.
Claims
1. An asynchronous arbitration circuit, characterized in that, include: The system includes a request input unit, an arbitration unit, a filtering unit, and a handshake signal generation unit, wherein: The request input unit is connected to both the arbitration unit and the handshake signal generation unit; the arbitration unit is connected to the filtering unit. The request input unit is used to transmit the request signal to the arbitration unit and the handshake signal generation unit respectively when the received response feedback signal is valid; The arbitration unit is used to arbitrate the request signal and determine the target output signal; The filtering unit is used to filter the target output signal to eliminate the corresponding metastable voltage in the target output signal and then output a corresponding response signal. The handshake signal generation unit is used to output a request forwarding signal based on the request signal; After the filtering unit outputs the corresponding response signal, the current request signal corresponding to the corresponding response signal is set to an invalid state; The request input unit is further configured to pass the current request signal through the arbitration unit and the filtering unit in sequence, and set the current response signal corresponding to the current request signal to an invalid state until the response feedback signal is in the valid state. The request input unit includes a first AND-OR gate and a second AND-OR gate, and the request signal includes a first request signal and a second request signal, wherein: The first input terminal of the first AND-OR gate is electrically connected to the first external request signal terminal; the second input terminal of the first AND-OR gate is electrically connected to the response feedback signal output terminal of the handshake signal generation unit; the third input terminal of the first AND-OR gate is electrically connected to the first external request signal terminal; the fourth input terminal of the first AND-OR gate is electrically connected to the output terminal of the first AND-OR gate; the output terminal of the first AND-OR gate is electrically connected to the input terminal of the arbitration unit; and the output terminal of the first AND-OR gate is also electrically connected to the first input terminal of the handshake signal generation unit. The first AND-OR gate is used to receive the first request signal. The first input terminal of the second AND-OR gate is electrically connected to the second external request signal terminal; the second input terminal of the second AND-OR gate is electrically connected to the response feedback signal output terminal of the handshake signal generation unit; the third input terminal of the second AND-OR gate is electrically connected to the second external request signal terminal; the fourth input terminal of the second AND-OR gate is electrically connected to the output terminal of the second AND-OR gate; the output terminal of the second AND-OR gate is electrically connected to the input terminal of the arbitration unit; and the output terminal of the second AND-OR gate is also electrically connected to the second input terminal of the handshake signal generation unit. The second AND-OR gate is used to receive the second request signal. The arbitration unit includes a first NAND gate and a second NAND gate, and the request signal includes a first request signal and a second request signal, wherein: The first input terminal of the first NAND gate is electrically connected to the first output terminal of the request input unit. The first input terminal is used to receive the first request signal. The second input terminal of the first NAND gate is electrically connected to the output terminal of the second NAND gate. The output terminal of the first NAND gate is electrically connected to the corresponding input terminal of the filter unit and the first input terminal of the second NAND gate, respectively. The second input terminal of the second NAND gate is electrically connected to the second output terminal of the request input unit. The second input terminal is used to receive the second request signal. The output terminal of the second NAND gate is also electrically connected to the corresponding input terminal of the filter unit. The first NAND gate and the second NAND gate are used to arbitrate the first request signal and the second request signal according to a preset gating level to determine the target output signal.
2. The asynchronous arbitration circuit according to claim 1, characterized in that, The filtering unit includes a first NOR gate, a first AND gate, a second NOR gate, and a second AND gate. The request signal includes a first request signal and a second request signal. The target output signal includes a first target output signal corresponding to the first request signal and a second target output signal corresponding to the second request signal, wherein: The first input terminal of the first NOR gate is electrically connected to the first output terminal of the arbitration unit, the second input terminal of the first NOR gate is electrically connected to the response feedback signal output terminal of the handshake signal generation unit, the output terminal of the first NOR gate is electrically connected to the first input terminal of the first AND gate, the second input terminal of the first AND gate is electrically connected to the second target output signal output terminal of the arbitration unit, and the output terminal of the first AND gate is used to output a first response signal when the target output signal is the first target output signal; The second input terminal of the second NOR gate is electrically connected to the second output terminal of the arbitration unit, the second input terminal of the second NOR gate is electrically connected to the response feedback signal output terminal of the handshake signal generation unit, the output terminal of the second NOR gate is electrically connected to the first input terminal of the second AND gate, the second input terminal of the second AND gate is electrically connected to the first target output signal output terminal of the arbitration unit, and the output terminal of the second AND gate is used to output a second response signal when the target output signal is the second target output signal.
3. The asynchronous arbitration circuit according to claim 1, characterized in that, The handshake signal generation unit includes a request signal forwarding module and a response signal feedback module, wherein: the input terminal of the request signal forwarding module is electrically connected to the output terminal of the request input unit, and the request signal forwarding module is used to output the request forwarding signal based on the request signal; The output terminal of the response signal feedback module is electrically connected to the input terminal of the request input unit and the input terminal of the filtering unit, respectively. The response signal feedback module is used to receive the response feedback signal.
4. The asynchronous arbitration circuit according to claim 3, characterized in that, The request signal forwarding module includes an OR gate, which includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the OR gate is electrically connected to the first output terminal of the request input unit, and the second input terminal of the OR gate is electrically connected to the second output terminal of the request input unit. The output of the OR gate is used to output the request forward signal based on the request signal.
5. The asynchronous arbitration circuit according to claim 3, characterized in that, The response signal feedback module includes a NOT gate, wherein the NOT gate includes an input terminal and an output terminal; The output of the NOT gate is electrically connected to the input of the request input unit, and the output of the NOT gate is also electrically connected to the input of the filter unit. The input terminal of the NOT gate is used to receive the response feedback signal.
6. An asynchronous arbitration method, applied to the asynchronous arbitration circuit according to any one of claims 1-5, characterized in that, The asynchronous arbitration method includes: When the received response feedback signal is valid, the request input unit transmits the request signal to the arbitration unit and the handshake signal generation unit respectively. The arbitration unit performs arbitration processing on the request signal to determine the target output signal; The filtering unit eliminates the corresponding metastable voltage in the target output signal through filtering processing and outputs a corresponding response signal. The handshake signal generation unit outputs a request forwarding signal based on the request signal.
7. An asynchronous arbitrator, characterized in that, Includes at least the asynchronous arbitration circuit described in any one of claims 1 to 5; In the case where the asynchronous arbitrator includes a first-stage asynchronous arbitration circuit, the request forward signal is the response feedback signal; When the asynchronous arbiter includes at least two stages of the asynchronous arbitration circuit, the request forward signal output by the handshake signal generation unit of each stage is the request signal of the request unit corresponding to the next stage of the asynchronous arbitration circuit, and the response signal output by the filter unit corresponding to the next stage of the asynchronous arbitration circuit is the response feedback signal corresponding to the current stage of the asynchronous arbitration circuit.