Write assist scheme using bit lines

Abstract

A method and apparatus with an improved write-assisted scheme are proposed. The apparatus includes: a power node configured to supply power from a power source to a memory cell for storing data; a bit line configured to provide write data to a memory cell during a write operation; and a discharge circuit configured to selectively discharge the power node to the bit line based on the write data. The method of writing to a memory cell using the write-assisted scheme includes: supplying power from a power source to a memory cell via the power node for storing data; providing write data to a memory cell via the bit line during a write operation; and selectively discharging the power node to the bit line based on the write data.

Description

[0001] Priority requirements

[0002] This patent application claims priority to non-provisional application number 16 / 862238 entitled “WRITE ASSIST SCHEME WITHBITLINE”, filed on April 29, 2020, which has been assigned to the assignee of this application and is expressly incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to methods and apparatuses with improved write assistance schemes, and more specifically, to a memory configured to reduce the voltage on a power node to assist a write operation. Background Technology

[0004] Computing devices (such as laptops, mobile phones, etc.) may include one or more processors to perform various functions, such as telephony, wireless data communication, artificial intelligence, and camera / video functions. Memory is a crucial component of computing devices. A processor can be coupled to memory to perform the aforementioned computational functions. For example, a processor can fetch instructions from memory to perform computational functions and / or store temporary data within memory for processing these computational functions. Improvements in memory performance also improve computing devices. Summary of the Invention

[0005] This invention discloses some exemplary features and is not an exclusive or exhaustive description of the subject matter. Additional features and aspects are described, and these will become clear to those skilled in the art after reading the following detailed description and examining the accompanying drawings, which form a part of it.

[0006] An apparatus according to at least one embodiment includes: a plurality of memory cells; a power node configured to supply power from a power source to one or more or all of the plurality of memory cells to store data; a bit line configured to supply write data to a memory cell in a write operation; and a discharge circuit configured to selectively discharge the power node to the bit line based on the write data (e.g., charge moves from the power node to the bit line).

[0007] A method for writing to a memory cell using a write-assisted scheme includes: supplying power from a power source to one of a plurality of memory cells via a power node to store data; in a write operation, supplying write data to a memory cell via a bit line; and, based on the write data, selectively discharging the power node to the bit line.

[0008] Another apparatus according to at least one embodiment includes: a plurality of memory cells; a power node configured to provide power from a power source to one of the memory cells to store data; a pair of bit lines configured to provide write data to one memory cell during a write operation; and a discharge circuit configured to selectively release at least a portion of the charge pulled down from the power node to one of the pair of bit lines during a write operation. Attached Figure Description

[0009] Various aspects of the apparatus and method will now be presented in detail by way of example rather than limitation, with reference to the accompanying drawings, in which:

[0010] Figure 1 The illustration shows an apparatus comprising at least one processor and memory according to certain aspects of the present disclosure.

[0011] Figure 2 The illustrations depict certain aspects of this disclosure. Figure 1 The functional blocks of the memory.

[0012] Figure 3 The illustrations depict certain aspects of this disclosure. Figure 2 Memory units.

[0013] Figure 4 The illustration shows an improved write-assistance scheme according to certain aspects of this disclosure. Figures 1-2 The memory.

[0014] Figure 5 The illustrations depict certain aspects of the use of this disclosure. Figure 4 The waveform of the write operation of the improved write-assisted scheme.

[0015] Figure 6 The illustrations depict certain aspects of the use of this disclosure. Figure 4 and Figure 5 The presented write-assisted scheme is a method for writing into memory cells.

[0016] Figure 7 The illustrations depict certain aspects of the use of this disclosure. Figure 6 The presented write-assistance scheme includes additional operations for writing to memory cells. Detailed Implementation

[0017] The detailed description below, taken in conjunction with the accompanying drawings, is intended to illustrate various configurations and is not intended to present the only configuration in which the concepts described herein can be practiced. The detailed description includes specific details used to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0018] As used herein, the term "coupled to" in various tenses of the verb "couple" can mean that element A is directly connected to element B, or that other elements can be connected between element A and B (i.e., element A is indirectly connected to element B) to perform certain intended functions. For example, the term "coupled" can mean that element A and element B communicate directly or via other elements or have information transmission.

[0019] The term "electrical connection" can mean that current flows between component A and component B, or that current can be configured to flow between component A and component B. In some examples, the term "electrical connection" can mean the transfer of electrical energy between component A and component B to operate some intended function. For example, in addition to wires, traces, or other conductive materials and components, component A and component B can also be connected via resistors, transistors, or inductors.

[0020] The terms "first," "second," "third," etc., are used for ease of reference and may not have substantial meaning. Similarly, the names of components / modules are used for ease of reference and may not be limiting. For example, such non-limiting names may include "discharge" transistors and / or "control" transistors, etc. In some examples, the modules and components presented in this disclosure can be implemented by circuitry. Such circuitry can operate at least partially according to software / firmware instructions.

[0021] The terms "bus system" and / or "signal connection" can specify that the elements coupled thereto can exchange information directly or indirectly between them. In this way, the terms "bus system" and / or "signal connection" can encompass multiple physical connections as well as intermediate stages such as buffers, latches, registers, etc.

[0022] In this disclosure, memory can be embedded on a semiconductor die along with the processor, or it can be part of a semiconductor die separate from the processor. Memory can perform various functions. For example, memory can be used as a cache, register file, or storage device. Memory can be of various types. For example, memory can be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash, or NOR flash, etc.

[0023] As semiconductor processes advance, write operations in memory become increasingly difficult. For example, lower supply voltages reduce write margin. In some examples, write margin can refer to the threshold that allows data to be correctly written to a memory cell (e.g., in terms of signal timing, voltage levels, etc.). Furthermore, in FinFET processes, the ratio of p-type to n-type transistors in a memory cell cannot be adjusted as easily as in previous processes. Write-assist schemes have been developed to improve write margin in advanced semiconductor processes. One such write-assist scheme lowers the voltage at the power node of the memory cell to improve write margin. The lower voltage improves the writing of data to the memory cell. However, lowering the voltage at the power node introduces unnecessary and undesirable power consumption.

[0024] Methods and apparatus utilizing an improved write-assist scheme are proposed. In some examples, the voltage of the power node is discharged (e.g., reduced) to the bit line, which is configured to carry write data to the memory cell, the write data causing the bit line to be pulled up, or configuring the bit line to be pulled up. Therefore, during the write operation, the charge released from the power node can be used to charge the bit line (e.g., pull the bit line up). In this way, power consumption is reduced.

[0025] This disclosure presents methods and apparatuses through non-limiting examples of static random access memory (SRAM) and its write operations to illustrate aspects of improved write-aided schemes. Figure 1 The illustration depicts an apparatus 100 comprising at least one processor 102 and memory 110 according to certain aspects of this disclosure. The apparatus 100 may include, for example, a computing system (e.g., a server, data center, desktop computer), a mobile computing device (e.g., a laptop computer, mobile phone, vehicle, etc.), an Internet of Things device, a virtual reality (VR) system, or an augmented reality (AR) system. The processor 102 may include a collection of processing logic or one or more central processing units. Figure 1 The illustration shows a device 100 that includes at least one processor 102 coupled to a memory 110 via a bus system 104. The at least one processor 102 and the memory 110 may be on the same semiconductor die or on different dies. The at least one processor 102 may be coupled to the memory 110 to perform computational functions, such as data processing, data communication, graphics display, camera, AR or VR rendering, image processing, etc. For example, the memory 110 may store instructions or data for the at least one processor 102 to perform the aforementioned computational functions.

[0026] Figure 2 The illustrations depict certain aspects of this disclosure. Figure 1The memory 110 is a functional block. As an example, the memory 110 is presented as an SRAM having a memory array 212. For illustrative purposes, the memory 110 is shown configured to have 1-bit access (reading or writing one bit on each access). The memory 110 can read or write multiple bits (e.g., x8, x16, x32) on each access. The memory array 212 includes multiple memory cells 214 (e.g., 214_1_1 to 214_2) arranged in multiple rows (labeled "row" for example) and multiple columns (labeled "column" for example). m _2 n Each memory cell 214 can store one data bit (logic 1 or logic 0). As illustrated, the memory array 212 includes 2 n row and 2 m In some examples, "m" and "n" can be integers greater than or equal to 1. To access memory cell 214, memory 110 may include a row decoder 222 and a word line driver circuit 224 (in...). Figure 2 The circuit is shown as WL driver circuit 224), column decoder 226, multiplexer 228, write driver 221 and / or sense amplifier 229. Figure 2 Further illustration shows a data input / output bus 230 for providing data to / receiving data from memory 110. In some examples, the data input / output bus 230 may be coupled to bus system 104. Figure 1 ( ), so as to provide data read from memory 110 to at least one processor 102 (or receive data from at least one processor 102 to be written to memory 110).

[0027] Memory 110 can be configured to receive an address as input to access (e.g., read or write) the memory cell (or multiple memory cells) 214 corresponding to that address. Row decoder 222 can be configured to receive n bits of the address as a row address, decode the row address, and provide the decoded row address 223 to word line driver circuit 224. Word line driver circuit 224 can be configured to output 2... n Bar lines (WL_1 to WL_2) n Word lines WL_1 to WL_2 n Each word line in the memory can be coupled to the corresponding row of memory cell 214 for read or write operations (e.g., to enable access to that row). Column decoder 226 can be configured to receive m bits of the address as the column address, decode the column address, and output the decoded column address 227 to... m Select from the data columns.

[0028] Each memory cell 214 can be configured to be electrically connected or coupled to bit line pairs BL and BLB, and each column of memory cells 214 can be configured to share the same bit line pairs BL and BLB. Therefore, in Figure 2 Among them, there are 2 m Units line pairs (e.g., BL_1 to BL_2) m ;BLB_1 to BLB_2 m During a single access, word line driver circuitry 224 can be configured to provide (e.g., drive or influence) a certain voltage level to WL_1 through WL_2 selected by the row address. n On one of the word lines, to access rows of memory cells 214 coupled to that word line (e.g., to facilitate read or write operations to rows of memory cells 214 coupled to that word line). For read access (e.g., memory 110 in a read operation), the row of memory cells 214 can be configured to provide the stored data to 2 m On the unit bit line pairs BL and BLB. For write access (e.g., memory 110 in a write operation), the write data can be provided to 2 m The bits are written to the pairs BL and BLB and then to the row of memory cell 214.

[0029] Multiplexer 228 can be configured to select a bit line pair BL and BLB based on the decoded column address 227 for read and / or write access. In a read operation, multiplexer 228 can be configured to select a bit line pair BL and BLB and provide the data on the selected bit line pair BL and BLB as read data to sense amplifier 229. Sense amplifier 229 can be configured to amplify and / or store the data read from memory array 212 via multiplexer 228 and output the amplified read data to data input / output bus 230. In a write operation, write driver 221 can be configured to receive input data from data input / output bus 230 and output it as write data to multiplexer 228. Multiplexer 228 can be configured to select a bit line pair BL and BLB (based on the decoded column address 227) and provide write data to the selected bit line pair BL and BLB.

[0030] Figure 3 The illustrations depict certain aspects of this disclosure. Figure 2 Memory unit 214. Figure 3The diagram illustrates a memory cell 214 having p-type transistors 336, 337, n-type transistors 338, 339, and access transistors 346 and 348. The memory cell 214 can be configured to be powered by a supply voltage VDD via a power node 325 and ground. The memory cell 214 can be configured as two cross-coupled inverters 332 and 334 to store data. P-type transistors 336 and 338 can be configured as inverter 332, and p-type transistors 337 and 339 can be configured as inverter 334. Storage node 342 can be configured to be electrically connected or coupled to the output of inverter 332 and the input of inverter 334. Storage node 344 can be configured to be electrically connected or coupled to the output of inverter 334 and the input of inverter 332. Data can be stored by storage nodes 342 and 344 (e.g., logic 0 can be stored at storage node 342, while logic 1 is stored at storage node 344, and vice versa, to represent different stored values ​​of the storage bits). When logic 0 is stored at storage node 342 (and logic 1 is stored at storage node 344), n-type transistor 338 can be configured to hold logic 0 at storage node 342 by keeping storage node 342 discharged. When logic 0 is stored at storage node 344 (and logic 1 is stored at storage node 342), n-type transistor 339 can be configured to hold logic 0 at storage node 344 by keeping storage node 344 discharged.

[0031] Access transistors 346 and 348 can be configured to provide read or write access to or from bit lines BL and BLB to memory nodes 342 and 344. Word line WL can be configured to turn on access transistors 346 and 348 during read or write operations, enabling access to one row of multiple rows of memory cell 214. Figure 2 ).exist Figure 3 In the circuit, access transistors 346 and 348 are n-type transistors and are used as transmission gates. Word line driver circuit 224 ( Figure 2 The word line WL can be configured to drive a voltage level for accessing memory cell 214 (e.g., providing a voltage level to the word line WL to turn on access transistors 346 and 348 and facilitate a read or write operation). The voltage level can be a high voltage, such as VDD, to turn on access transistors 346 and 348 to allow reading or writing of memory cell 214.

[0032] During a read operation, both the bit line pair BL and BLB can be precharged to a high voltage level, such as VDD. (As an example, Figure 4The precharge circuit 450 is shown in the diagram. Memory cell 214 can be configured to selectively pull down one of the bit lines in bit line pairs BL and BLB to provide a stored bit on the bit line pairs BL and BLB. For example, memory node 342 stores logic 0 (e.g., a low voltage level such as ground), and memory node 344 stores logic 1 (e.g., a high voltage level such as VDD). During a read operation, bit line BLB is pulled down by n-type transistor 338 via access transistor 346, while bit line BL remains at a (precharged) high voltage level. Therefore, a voltage difference is generated between bit line pairs BL and BLB to indicate the stored bit of memory cell 214.

[0033] In this way, bits stored in rows of memory cell 214 can be provided to bit line pairs (BL_1, BLB_1 to BL_2). m BLB_2 m On memory cell 214, this row is coupled to word lines (WL_1 to WL_2). n One of them), the word line is driven by word line driver circuit 224 ( Figure 2 The multiplexer 228 is driven high for read operations. Multiplexer 228 can be configured to select a bit line pair BL and BLB based on the decoded column address 227 from column decoder 226, and provide the stored bits from the selected bit line pair BL and BLB (e.g., in the form of a voltage difference across the bit line pair BL and BLB) to sense amplifier 229. Sensing amplifier 229 can be configured to amplify the voltage difference across the bit line pair BL and BLB and output the result to data input / output bus 230 (see...). Figure 2 ) and external systems (e.g., output to at least one processor 102 via bus system 104; see Figure 1 ).

[0034] During the write operation, refer to Figure 2 Write to drive 221 (see Figure 2 It can be configured to be used via bus system 104 (see Figure 1 ) and / or data input / output bus 230 (see Figure 2 The write driver 221 receives input for writing from, for example, at least one processor 102. The write driver 221 can also be configured to drive the input as write data to bit line pairs BL and BLB selected via multiplexer 228. For example, the write driver 221 can be configured to discharge (e.g., pull down) the bit line BL of the selected column to a low voltage level (e.g., ground) and charge (e.g., pull up) the bit line BLB to a high voltage level. In some examples, high voltage level and low voltage level can be relative terms (e.g., compared to each other). Reference Figure 3In the example where memory node 342 stores logic 0 (e.g., a low voltage level such as ground) and memory node 344 stores logic 1 (e.g., a high voltage level such as VDD) before a write access, the bit line BL, driven to a low voltage level, pulls memory node 344 to a low voltage level (e.g., ground or near ground) via access transistor 348. The bits stored by memory cell 214 can correspondingly toggle their states. In this way, different states are written to memory cell 214.

[0035] Figure 4 The illustration shows an improved write-assistance scheme according to certain aspects of this disclosure. Figures 1-2 The memory 110. Figure 4 include Figures 2-3 Memory cell 214 Figure 2 Multiplexer 228, power supply 420, isolation transistor 422, discharge circuit 432, precharge circuit 450 and write driver 221 (see Figure 2 ). Figure 4 It also includes a discharge circuit 432 having a control transistor 430 and discharge transistors 442 and 444. The power supply 420 can be configured to provide power from the supply voltage VDD to the power node 325. For example, the power supply 420 may include a head switch and / or include a transistor (not shown) electrically connecting the supply voltage VDD and the power node 325.

[0036] The isolation transistor 422 can be configured to isolate power node 325 from power supply 420 when discharge circuit 432 discharges power node 325 to bit line BL or BLB, to assist the write operation. Further details of write assistance during the write operation are presented below. The isolation transistor 422 can also be configured to be controlled (e.g., turned on and off) by a write signal or a signal indicating a write operation. In some examples, the isolation transistor 422 may include a p-type transistor having a gate electrically connected to node 423. The write signal (or signal indicating a write operation) may be provided via node 423, and in particular may indicate a state of being in a write operation. In some examples, the isolation transistor 422 isolating power node 325 from power supply 420 can isolate power node 325 from being pulled up (e.g., pulled up to VDD). For example, because the isolation transistor 422 isolates power node 325 from power supply 420, power node 325 may be isolated from all or any pull-up sources.

[0037] Power node 325 can be configured to provide power from power supply 420 to memory cells 214_1_1 to 214_2. m _2 n ( Figure 2The memory cell 214 in the memory array 212 is used to store data. In some examples, the power node 325 can be configured to supply power to the memory array 212 (see memory cell 214). Figure 2 Power is supplied to a portion of the multiple columns of the memory array 212. In some examples, power node 325 may be configured to supply power to one column of the multiple columns of the memory array 212. In some examples, the cross-coupled inverters 332 and 334 of the memory cells 214 may be powered via power node 325, and therefore, the data stored in memory nodes 342 and 344 may be powered via power node 325.

[0038] Bit line pairs BL and BLB can be configured to provide write data (or multiple versions of write data) to memory cell 214 during a write operation. Precharge circuitry 450 can be configured to precharge bit line pairs BL and BLB to a certain level before a write operation. For example, precharge circuitry 450 can be configured to precharge bit lines BL and BLB to VDD before a write operation.

[0039] Write driver 221 can be configured to drive bit line pairs BL and BLB based on write data to be written to memory cell 214. For example, write driver 221 can be configured to discharge the bit line BL of the selected column to a low voltage level (e.g., ground) and charge the bit line BLB to a high voltage level (e.g., pull-up to, for example, VDD) in response to write data being in a first state. Write driver 221 can also be configured to discharge the bit line BLB of the selected column to a low voltage level (e.g., ground) and charge the bit line BL to a high voltage level (e.g., pull-up to, for example, VDD) in response to write data being in a second state. The first state and the second state can be different. In this way, bit line pairs such as BL and BLB can be complementary bit lines. For example, bit line BL can be the complementary bit line of bit line BLB, and vice versa, to carry write data in a write operation. The write driver 221 can be configured to drive (e.g., discharge or pull up) bit line pairs BL and BLB via multiplexer 228 (shown together with the decoded column address 227 that controls multiplexer 228).

[0040] The discharge circuit 432 can be configured to selectively discharge the power node 325 to the bit line BL (or BLB) based on the written data. For example, the discharge circuit 432 can be configured to discharge the power node 325 to the bit line BL (or BLB) in response to the written data being in a state that charges the write driver 221 to the bit line BL (or BLB). For example, the write driver 221 can be configured to output a logic 1 or a high voltage to the selected bit line BL (or BLB) via multiplexer 228 based on the state of the written data to charge the bit line BL (or BLB). Therefore, the discharge circuit 432 can be configured to select one of the bit lines, BL and BLB, to discharge the power node 325 according to the written data.

[0041] In some examples, the discharge circuit 432 may include a control transistor 430, a discharge transistor 442, and a second discharge transistor 444. In some examples, the control transistor 430, the discharge transistor 442, and / or the second discharge transistor 444 may be one or more p-type transistors. The control transistor 430 may be configured to be coupled to the power node 325, the discharge transistor 442, and the second discharge transistor 444. For example, the control transistor 430 may be configured to be electrically connected to the power node 325 and electrically connected to the discharge transistor 442 and the second discharge transistor 444 via node 431. The control transistor 430 may be configured to be turned on based on a signal indicating a write operation, so that the power node 325 can discharge. For example, the control transistor 430 may include a gate electrically connected to node 433. The inversion of the write signal may be provided via node 433 and may in particular indicate a state of write operation. For example, a signal at logic 0 on node 433 may indicate that a write operation is activated.

[0042] In some examples, discharge transistor 442 may be configured to be electrically connected to bit line BLB in response to write data being in a state that charges the write driver to bit line BLB (e.g., a first state), so as to discharge power node 325 to bit line BLB. For example, discharge transistor 442 may include a gate electrically connected to node 443. A signal may be provided via node 443, and in particular may indicate the inversion of write data. For example, in response to write data being logic 1, discharge transistor 442 may be turned on to discharge power node 325 to bit line BLB. Write data of logic 1 may cause write driver 221 to output logic 1 to bit line BLB via multiplexer 228 to charge bit line BLB (e.g., when bit line BLB drops below VDD-Vth—Vth is the threshold voltage of the n-type transistor of multiplexer 228). In this way, control transistor 430 and discharge transistor 442 may be configured in series to discharge power node 325 to bit line BLB.

[0043] The second discharge transistor 444 can be configured to be electrically connected to the bit line BL in response to write data being in a state that charges the write driver to the bit line BL (e.g., a second state), so as to discharge the power node 325 to the bit line BL. For example, the second discharge transistor 444 may include a gate electrically connected to node 445. A signal can be provided via node 445, and in particular, can indicate the write data. For example, in response to write data being logic 0, the second discharge transistor 444 can be turned on to discharge the power node 325 to the bit line BL. Write data of logic 0 can cause the write driver 221 to output logic 1 to the bit line BL via multiplexer 228 to charge the bit line BL (e.g., when the bit line BL drops below VDD-Vth—Vth is the threshold voltage of the n-type transistor of multiplexer 228). In this way, the control transistor 430 and the discharge transistor 444 can be configured in series to discharge the power node 325 to the bit line BL. As mentioned above, bit line BL can be the complementary bit line of bit line BLB, and vice versa, because a low bit line represents a different state of written data for each bit line in BL and BLB.

[0044] Figure 5 The illustrations depict certain aspects of the use of this disclosure. Figure 4 The waveform of the write operation of the improved write-assisted scheme is shown. Time is plotted on the X-axis. Reference Figure 4 Presentation Figure 5 As an example, logic 0 is stored in storage node 342, and logic 1 is stored in storage node 344. Therefore, before a write operation, memory cell 214 holds storage node 342 grounded and storage node 344 held at VDD. The terms "high" and "low" can be relative and can be based on voltage.

[0045] Before the write operation, the precharge circuit 450 precharges bit lines BL and BLB to VDD. At T0, the signal at node 423 goes up to logic 1 or VDD, and the signal at node 433 goes down to logic 0 or ground, indicating that the write operation is enabled. The precharge circuit 450 can be turned off at the start of the write operation. Isolation transistor 422 is turned off (by the signal at node 423 going high), isolating power node 325 from power supply 420. Subsequently, in some examples, power node 325 is isolated from being pulled up (e.g., power node 325 is not electrically connected to any pull-up circuit). Control transistor 430 is turned on by the signal at node 433 going low, electrically connecting power node 325 to node 431.

[0046] At T1, word line WL becomes as high as logic 1 or VDD. Access transistors 346 and 348 within memory cell 214 are turned on, electrically connecting memory node 342 to bit line BLB and memory node 344 to bit line BL. Therefore, bit line BLB is discharged through access transistor 346 and memory node 342 (see...). Figure 5 (P1 in the diagram). Bit line BL does not discharge because the storage node 344, which is electrically connected to it, is at logic 1 or VDD. Therefore, when the discharge circuit 432 discharges the power node 325 to the bit line BLB, the power node 325 is isolated from the power supply 420 through the isolation transistor 422.

[0047] At T2, the signal at node 443 (e.g., the active low indicator for write operations) goes low, turning on discharge transistor 442. The signal at node 445 (e.g., the active high indicator for write data); Figure 5 (Not shown in the image) remains high to keep discharge transistor 444 off. Therefore, power node 325 discharges the bit line BLB via control transistor 430 and discharge transistor 442 (see image). Figure 5 (P2 in the middle). Furthermore, as a result, the bit line BLB is pulled up by the discharged power node 325 via charge sharing between the bit line BLB and the power node 325. Figure 5 The illustration further illustrates that the voltage at power node 325 is pulled down by ΔV 526. The reduction in voltage at power node 325 supplying memory cell 214 and / or the increase in the BLB voltage contributes to write margin when writing to memory 214. For example, by reducing the voltage at power node 325 and / or increasing the voltage of the bit line BLB, the chance of successfully rewriting memory cell 214 with written data is improved because the strength of the pull-down of inverter 334 against the bit line BL is also reduced due to the reduced voltage at power node 325.

[0048] In addition, write driver 221 is enabled to output write data to bit pairs BL and BLB. Figure 5 In the example, via multiplexer 228 (see Figure 4 The write driver 221 outputs the write data to bit line BLB and inverts the write data to bit line BL. In this example, to toggle a bit stored in memory cell 214, the write driver 221 charges (e.g., pulls up) bit line BLB high and pulls bit line BL low by outputting logic 1 to bit line BLB and logic 0 to bit line BL. Figure 5As shown, bit line BL is pulled low to logic 0 or ground. Depending on the BLB voltage level, write driver 221 can hold bit line BLB either at or pulled up to VDD-V. TH (The threshold voltage of the n-type transistor in multiplexer 228). For example, if the BLB voltage level is higher than VDD-V after charge sharing with power node 325 is complete. TH If the write driver 221 does not charge the BLB, then the write driver 221 will not charge the BLB. On the other hand, if the BLB voltage level is below VDD-V after charge sharing... TH Then, writing to driver 221 will pull the bit line BLB up to VDD-V. TH .

[0049] In this way, the discharge circuit 432 (see...) Figure 4 The power node 325 can be configured to discharge the bit line BLB to pull the bit line BLB up to a level higher than that at which the write driver 221 charges the bit line BLB. For example, a discharge circuit 432 that discharges the power node 325 to the bit line BLB can pull the bit line BLB up to a level higher than that at which the individual write driver 221 can pull up the bit line BLB. For example, see reference... Figure 5 When writing to drive 221 via multiplexer 228 (see Figure 4 When logic 1 is output to bit line BLB, write driver 221 is configured to charge bit line BLB or pull it up to VDD-V. TH The discharge circuit 432 that discharges the power supply node 325 to the bit line BLB (see...) Figure 4 Pull the bit line BLB up above VDD-V TH VDD-ΔV 526. Therefore, with the assistance of the reduced voltage on power node 325 and the increased voltage on bit line BLB, the lowered bit line BL can be able to flip the value stored in memory cell 214, thereby inputting write data into memory cell 214.

[0050] Figure 6 The illustrations depict certain aspects of the use of this disclosure. Figure 4 and Figure 5 The presented write-assisted scheme describes a method for writing to memory cells. For example, Figure 6 The operation can be performed by Figures 1-4 The presented memory 110 implementation. Arrows indicate certain relationships in the operation, but not necessarily sequential relationships. At 610, power from the power supply is provided to one of the multiple memory cells to store data via a power node. For example, refer to... Figure 4 Power is supplied by power supply 420 via power node 325 to (memory array 212; see below) Figure 2Memory cell 214 is used to store data. At 620, during a write operation, the write data is provided to the memory cell via bit lines. For example, refer to... Figure 4 Data is provided to (e.g., written to) memory cell 214 via bit line BL and / or bit line BLB.

[0051] At 630, based on the written data, the power node is selectively discharged to the bit line. For example, refer to... Figure 4 The power node 325 can be selected to discharge or not discharge the bit line BLB based on the data being written. For example, when the data being written is logic 0, the inverted signal indicating the data being written at node 443 will be at logic 1 (high voltage or VDD), which will turn off the discharge transistor 442. In this case, during the write operation, based on the data being written being logic 0, power node 325 is selected not to discharge the bit line BLB. The signal indicating the data being written at node 445 will be at logic 0 (low voltage or ground), which will turn on the discharge transistor 444. During the write operation, based on the data being written being logic 0, power node 325 is selected to discharge the bit line BL.

[0052] When the written data is logic 1, the inverted signal indicating the written data at node 443 will be at logic 0 (low voltage or ground), which will turn on discharge transistor 442. In this case, during the write operation, based on the written data being logic 1, power node 325 is selected to discharge the bit line BLB. The signal indicating the written data at node 445 will be at logic 1 (high voltage or VDD), which will turn off discharge transistor 444. Therefore, during the write operation, based on the written data being logic 1, power node 325 is not selected to discharge the bit line BL.

[0053] At 640, the bit line is driven by the write driver based on the written data. For example, refer to... Figure 4 Based on the written data being logic 0, the write driver 221 discharges bit line BLB (e.g., to low voltage or ground) and charges bit line BL (e.g., to high voltage or VDD-V). TH Based on the written data being logic 1, the write driver 221 charges the bit line BLB (e.g., to a high voltage or VDD-V). TH And discharge the bit line BL (e.g., to a low voltage or ground). At 650, in response to the write data being in a state that charges the bit line with the write drive circuitry, the power node discharges the bit line through the discharge circuitry. For example, refer to Figure 4The second discharge transistor 444 includes a gate electrically connected to node 445. Signals are provided via node 445 and specifically indicate written data. For example, in response to a write data of logic 0, the second discharge transistor 444 turns on to discharge power node 325 to bit line BL. A write data of logic 0 causes write driver 221 to output a logic 1 to bit line BL to charge bit line BL via multiplexer 228 (e.g., when bit line BL drops below VDD-V). TH In the case of V; TH It is the threshold voltage of the n-type transistor in the multiplexer 228.

[0054] At 645, the bit line is pulled up to a level higher than the level at which the write driver charges the bit line. For example, refer to... Figure 5 The discharge circuit 432, which discharges the power node 325 to the bit line BLB, can pull the bit line BLB up to a level higher than that that the individual write driver 221 can pull up. For example, in the case of the write driver 221 via multiplexer 228 (see... Figure 4 When logic 1 is output to bit line BLB, the write driver 221 charges bit line BLB or pulls it up to VDD-V. TH The discharge circuit 432 that discharges the power supply node 325 to the bit line BLB (see...) Figure 4 Pull the bit line BLB up above VDD-V TH VDD-ΔV 526.

[0055] At 660, when the discharge circuit discharges the power node to the bit line, the power node is isolated from the power supply via an isolation transistor. For example, see reference... Figure 4 The isolation transistor 422 is controlled by a write signal (e.g., turn on and off). The isolation transistor 422 includes a p-type transistor having a gate electrically connected to node 423. The write signal is provided via node 423 and specifically indicates a write operation state. The isolation transistor 422 isolates power node 325 from power supply 420 and also isolates power node 325 from pull-up sources. For example, due to the isolation transistor 422 isolating power node 325 from power supply 420, power node 325 is isolated from all or any pull-up sources. Reference Figure 5 The isolation transistor 422 is turned off.

[0056] refer to Figure 5 At T0, the start of the write operation turns off isolation transistor 422. At T1, word line WL goes high to logic 1 or VDD. Access transistors 346 and 348 within memory cell 214 are turned on, electrically connecting memory node 342 to bit line BLB and memory node 344 to bit line BL. Therefore, bit line BLB is discharged through access transistor 346 and memory node 342 (see...). Figure 5 (P1 in the diagram). Bit line BL does not discharge because the storage node 344 electrically connected to it is at logic 1 or VDD. Therefore, when the discharge circuit 432 discharges the power node 325 to the bit line BLB, the power node 325 is isolated from the power supply 420 through the isolation transistor 422.

[0057] At position 670, power is supplied from the power source to a portion of multiple columns via a power node to store data. For example, refer to... Figure 4 Power node 325 supplies power from power supply 420 to memory array 212 (see...). Figure 2 One column from multiple columns (and for example, only one column), thus providing a portion. Operations can be performed on... Figure 7 Continue at point 710.

[0058] Figure 7 The illustrations depict certain aspects of the use of this disclosure. Figure 6 The presented write-assisted scheme includes additional operations for writing to memory cells. These operations can originate from... Figure 6 At 670, and at 710, in response to the write data being in a state that charges the bit line with the write drive circuit, the discharge transistor of the discharge circuit is turned on to discharge the power node to the bit line. At 730, in response to the write data being in a second state that charges the complementary bit line with the write drive circuit, the power node discharges to the complementary bit line of the bit line through the second discharge transistor of the discharge circuit. For example, refer to... Figure 4 In response to the write data being in a state that charges the write driver to bit line BLB (e.g., a first state; e.g., logic 1), discharge transistor 442 is electrically connected to bit line BLB to discharge power node 325 to bit line BLB. In response to the write data being in a state that charges the write driver to bit line BL (e.g., a second state; e.g., logic 0), second discharge transistor 444 is electrically connected to bit line BL to discharge power node 325 to bit line BL.

[0059] At 730, based on the signal indicating a write operation, the control transistor of the discharge circuit is turned on to enable the power node to discharge. For example, refer to... Figure 4 Based on a signal indicating a write operation on its gate, control transistor 430 is turned on to allow power node 325 to discharge. Control transistor 430 includes a gate electrically connected to node 433. An inverted write signal is provided via node 433 and specifically indicates a write operation state. For example, a signal at logic 0 on node 433 indicates write operation activity.

[0060] The preceding description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but rather to conform to the full scope consistent with the language of the claims, wherein references to elements in the singular form, unless specifically stated otherwise, are not intended to mean “one and only one,” but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects. Unless otherwise specifically stated, the term “some” means one or more. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C, and may include multiple A, multiple B, or multiple C. Specifically, combinations such as "at least one of A, B, or C", "one or more of A, B, or C", "at least one of A, B, and C", "one or more of A, B, and C", and "A, B, C, or any combination thereof" can be A only, B only, C only, A and B, A and C, B and C, or A and B and C, wherein any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements of the aspects described in this disclosure that are known to or will be known hereafter by those skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be exclusive to the public, whether or not such disclosure is expressly referenced in the claims. Terms such as "module", "mechanism", "element", "device", etc., may not replace the word "component". Therefore, no claim element should be construed as a component plus function unless the element is explicitly described using the phrase "component for...".

Claims

1. An apparatus for improving memory write operations, comprising: Multiple memory units; A power node is configured to supply power from a power source to one of the plurality of memory cells to store data; An isolation transistor is coupled between the power supply and the power node, the isolation transistor being configured to be turned off during a write operation to isolate the power node from the power supply; Bit lines are configured to provide write data to one of the memory cells during the write operation; as well as A discharge circuit is configured to couple the power node to the bit line when the written data is in a first state.

2. The apparatus according to claim 1, further comprising: A write driver is configured to drive the bit line based on the write data, and the discharge circuit is further configured to discharge the power node to the bit line in response to the write data being in a state that causes the write driver circuit to charge the bit line.

3. The apparatus of claim 2, wherein the discharge circuit is configured to discharge the power node to the bit line to pull the bit line up to a level higher than that at which the write driver charges the bit line.

4. The apparatus of claim 1, wherein the isolation transistor that isolates the power node from the power supply isolates the power node from being pulled up.

5. The apparatus of claim 1, wherein the plurality of memory cells are arranged in a plurality of columns, and the power node is configured to provide power to a portion of the plurality of columns.

6. The apparatus of claim 5, wherein a portion of the plurality of columns is a single column.

7. The apparatus according to claim 5, further comprising: A device selected from one of the following: a computing system, a mobile computing system, an Internet of Things (IoT) device, a virtual reality (VR) system, or an augmented reality (AR) system. The device includes the plurality of memory cells, the power node, the bit line, and the discharge circuit.

8. The apparatus of claim 7, wherein the discharge circuit includes a discharge transistor configured to turn on in response to the write data being in the state that causes the write drive circuit to charge the bit line, so as to cause the power node to discharge the bit line.

9. The apparatus of claim 8, wherein the discharge transistor comprises a p-type transistor.

10. The apparatus according to claim 8, wherein the discharge circuit further comprises: A control transistor is configured to turn on based on a signal indicating the write operation, so that the power node can discharge.

11. The apparatus of claim 10, wherein the control transistor and the discharge transistor are configured in series to discharge the power node.

12. The apparatus of claim 11, wherein the control transistor and the discharge transistor are p-type transistors.

13. The apparatus of claim 10, wherein the discharge circuit includes a second discharge transistor. The control transistor is coupled to the power node, the discharge transistor, and the second discharge transistor. In response to the written data being in the state that causes the write drive circuit to charge the bit line, the discharge transistor is electrically connected to the bit line to cause the power node to discharge the bit line. In response to the written data being in a second state that causes the write drive circuit to charge the complementary bit line, the second discharge transistor is electrically connected to the complementary bit line of the bit line to cause the power node to discharge the complementary bit line.

14. The apparatus of claim 13, wherein the control transistor, the discharge transistor, and the second discharge transistor are p-type transistors.

15. A method for writing to a memory cell using a write-assisted scheme, comprising: Power is supplied from a power source to one of a plurality of memory cells via a power node to store data; By using an isolation transistor coupled between the power source and the power node, the power node is isolated from the power source during a write operation by turning off the isolation transistor. In the write operation, write data is provided to the memory cell via a bit line; as well as When the written data is in the first state, the power node discharges to the bit line.

16. The method of claim 15, further comprising: The bit line is driven by the write driver based on the written data; In response to the write data being in a state that causes the write drive circuit to charge the bit line, the power node is discharged to the bit line through the discharge circuit.

17. The method of claim 16, wherein discharging the power node to the bit line via the discharge circuit comprises: Pull the bit line up to a level higher than the level at which the write driver charges the bit line.

18. The method of claim 16, wherein the isolation transistor that isolates the power node from the power supply isolates the power node from being pulled up.

19. The method of claim 16, wherein the plurality of memory cells are arranged in a plurality of columns, the method further comprising: Power is supplied from the power source to a portion of the plurality of columns via the power node to store data.

20. The method of claim 19, wherein a portion of the plurality of columns is a single column.

21. The method of claim 19, further comprising: In response to the written data being in the state that causes the write drive circuit to charge the bit line, the discharge transistor of the discharge circuit is turned on to cause the power node to discharge the bit line.

22. The method of claim 21, wherein the discharge transistor comprises a p-type transistor.

23. The method of claim 21, further comprising: Based on the signal indicating the write operation, the control transistor of the discharge circuit is turned on so that the power node can discharge.

24. The method of claim 23, wherein the power node is discharged by the control transistor and the discharge transistor connected in series.

25. The method according to claim 24, wherein the control transistor and the discharge transistor are p-type transistors.

26. The method of claim 23, further comprising: In response to the written data being in a second state that causes the write drive circuit to charge the complementary bit line, the power node discharges the complementary bit line of the bit line through the second discharge transistor of the discharge circuit.

27. The method of claim 26, wherein the control transistor, the discharge transistor, and the second discharge transistor are p-type transistors.

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