Semiconductor device, reservoir computing system, and method of manufacturing semiconductor device

Abstract

The present application provides a semiconductor device, comprising: a plurality of tunnel diodes, each comprising a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type disposed on the first semiconductor region and having a shape of a nanowire; an insulating film covering side surfaces of the second semiconductor regions; a plurality of first electrodes each connected to the first semiconductor region; and a plurality of second electrodes each connected to the second semiconductor region, the second electrode having a first surface, the first surface opposing the side surface of the second semiconductor region via the insulating film, and the diameters of the second semiconductor regions being different between the plurality of tunnel diodes.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, reservoir computing systems, and methods for manufacturing semiconductor devices. Background Technology

[0002] To provide advanced information processing services utilizing artificial intelligence, an AI-oriented computing system is being developed. This system is being developed using neural modal computing inspired by biological neural models. Reservoir computing, in particular, is expected to enhance AI technologies such as animation recognition and prediction due to its ability to process time-series information. The reservoir computing system utilizes a network-type circuit, called a reservoir circuit, which comprises multiple nonlinear elements with varying nonlinear characteristics.

[0003] Patent Document 1: Japanese Patent Application Publication No. 8-213561

[0004] Patent Document 2: Japanese Patent Application Publication No. 2011-238909

[0005] Patent Document 3: Japanese Patent Publication No. 2015-529006

[0006] Non-patent literature 1: Extended Abstracts of the 2019 International Conference on Solid State Devices and Materials, Nagoya, 2019, pp. 195-196

[0007] It is difficult to configure multiple nonlinear components with different nonlinear characteristics with a high degree of integration. Summary of the Invention

[0008] The purpose of this disclosure is to provide a semiconductor device, a reservoir computing system, and a method for manufacturing a semiconductor device that can be configured with multiple nonlinear elements with different nonlinear characteristics at a high degree of integration.

[0009] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a plurality of tunnel diodes, each having a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type disposed on the first semiconductor region and having a nanowire shape; an insulating film covering the side surface of the second semiconductor region; a plurality of first electrodes respectively connected to the first semiconductor region; and a plurality of second electrodes respectively connected to the second semiconductor region, wherein each second electrode has a first surface, the first surface being opposed to the side surface of the second semiconductor region through the insulating film, and the diameters of the second semiconductor regions are different among the plurality of tunnel diodes.

[0010] According to this disclosure, it is possible to configure multiple nonlinear elements with different nonlinear characteristics with a high degree of integration. Attached Figure Description

[0011] Figure 1 This is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0012] Figure 2 This is a cross-sectional view of a semiconductor device in its first embodiment during operation.

[0013] Figure 3 This is a graph representing the voltage-current characteristics of nanowires.

[0014] Figure 4 This is a cross-sectional view (1) showing a method for manufacturing a semiconductor device according to the first embodiment.

[0015] Figure 5 This is a cross-sectional view (2) showing a method for manufacturing a semiconductor device according to the first embodiment.

[0016] Figure 6 This is a cross-sectional view (3) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0017] Figure 7 This is a cross-sectional view (4) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0018] Figure 8 This is a cross-sectional view (5) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0019] Figure 9 This is a cross-sectional view (6) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0020] Figure 10 This is a cross-sectional view (7) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0021] Figure 11 This is a cross-sectional view (8) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0022] Figure 12 This is a cross-sectional view (9) showing the manufacturing method of the semiconductor device according to the first embodiment.

[0023] Figure 13 This is a diagram showing the voltage-current characteristics of nanowires with various second semiconductor regions of different diameters.

[0024] Figure 14This is a graph showing the voltage-current characteristics of nanowires with various second semiconductor regions having different doping concentrations.

[0025] Figure 15 This is a circuit diagram illustrating the reservoir circuit of the second embodiment.

[0026] Figure 16 This is a cross-sectional view showing the reservoir circuit of the second embodiment.

[0027] Figure 17 This is a circuit diagram showing a modified example of the reservoir circuit of the second embodiment.

[0028] Figure 18 This is a circuit diagram illustrating the reservoir circuit of the third embodiment.

[0029] Figure 19 This is a cross-sectional view showing the reservoir circuit of the third embodiment.

[0030] Figure 20 This is a block diagram illustrating the reservoir calculation system of the fourth embodiment. Detailed Implementation

[0031] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, in this specification and the accompanying drawings, repeated descriptions are omitted by using the same reference numerals for constituent elements having substantially the same functional structure.

[0032] (First Implementation)

[0033] The first embodiment will be described. The first embodiment relates to a semiconductor device having semiconductor regions having the shape of nanowires. Figure 1 This is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0034] like Figure 1 As shown, in the semiconductor device 100 of the first embodiment, an n-type semiconductor layer 102 is formed on a substrate 101, and an insulating film 103 is formed on the n-type semiconductor layer 102. Openings 21 and 22 extending to the n-type semiconductor layer 102 are formed on the insulating film 103. For example, the substrate 101 is a semi-insulating (SI)-GaAs(111)B substrate, and the n-type semiconductor layer 102 is an n-type GaAs layer with a thickness of 100 nm to 300 nm. For example, the insulating film 103 is a silicon nitride film with a thickness of 40 nm to 60 nm, and the diameters of the openings 21 and 22 are 40 nm to 200 nm. The diameter of the opening 21 is larger than the diameter of the opening 22.

[0035] The semiconductor device 100 has a first nanowire 11 grown above a substrate 101 through an opening 21 and a second nanowire 12 grown above the substrate 101 through an opening 22. For example, the diameters of the first nanowire 11 and the second nanowire 12 are 40 nm to 200 nm. The first nanowire 11 is thicker than the second nanowire 12. The n-type semiconductor layer 102 is separated into a region connected to the first nanowire 11 and a region connected to the second nanowire 12 by an element separation trench 109.

[0036] The first nanowire 11 has an n-type first semiconductor region 111 and a p-type second semiconductor region 112. The first semiconductor region 111 is disposed on the n-type semiconductor layer 102 and extends upward. The second semiconductor region 112 is disposed on the first semiconductor region 111 and extends upward. A metal film 31 is formed on the second semiconductor region 112. The metal film 31 is, for example, a gold (Au) film with a diameter of 40 nm to 200 nm.

[0037] The second nanowire 12 has an n-type first semiconductor region 121 and a p-type second semiconductor region 122. The first semiconductor region 121 is disposed on the n-type semiconductor layer 102 and extends upward. The second semiconductor region 122 is disposed on the first semiconductor region 121 and extends upward. A metal film 32 is formed on the second semiconductor region 122. The metal film 32 is, for example, a gold (Au) film with a diameter of 40 nm to 200 nm.

[0038] The second semiconductor region 112 and the second semiconductor region 122 have a nanowire shape. The first semiconductor region 111 and the first semiconductor region 121 can also have a nanowire shape. For example, the first semiconductor region 111 and the first semiconductor region 121 are n-type InAs nanowires, and the second semiconductor region 112 and the second semiconductor region 122 are p-type GaAs nanowires. 1－x Sb x Nanowires made of GaAs. 1－x Sb x The Sb composition ratio x is preferably 0.8 or higher, but it can also be 1.0. The n-type first semiconductor region 111 and the p-type second semiconductor region 112 are tunnel bonded to each other, and the n-type first semiconductor region 121 and the p-type second semiconductor region 122 are tunnel bonded to each other. The first nanowire 11 and the second nanowire 12 are an example of a tunnel diode.

[0039] The height (length) of the first semiconductor region 111 and the first semiconductor region 121 is, for example, 0.5 μm to 0.7 μm, and the heights of the first semiconductor region 111 and the first semiconductor region 121 can also be equal. The height (length) of the second semiconductor region 112 and the second semiconductor region 122 is, for example, 1.0 μm to 1.5 μm, and the heights of the second semiconductor region 112 and the second semiconductor region 122 can also be equal. The height (length) of the first nanowire 11 and the second nanowire 12 is, for example, 1.5 μm to 2.0 μm, and the heights of the first nanowire 11 and the second nanowire 12 can also be equal.

[0040] An insulating film 104 is formed covering the sides of the first nanowire 11 and the sides of the second nanowire 12. The insulating film 104 is, for example, an aluminum oxide film or a hafnium oxide film with a thickness of 10 nm to 30 nm. The thickness referred to here is the thickness in the direction perpendicular to the sides 112A and 122A of the second semiconductor regions 112 and 122. The insulating film 104 is also formed on the insulating film 103.

[0041] An organic insulating film 105 is formed on the insulating film 104. The organic insulating film 105 is, for example, a benzocyclobutene (BCB) film. The upper surface of the organic insulating film 105 is located above the interface 113 between the first semiconductor region 111 and the second semiconductor region 112 and the interface 123 between the first semiconductor region 121 and the second semiconductor region 122.

[0042] Metal film 41, which is in contact with metal film 31, and metal film 42, which is in contact with metal film 32, are formed on organic insulating film 105. Metal film 41 and metal film 42 are, for example, a stack of platinum (Pt) film and gold (Au) film on platinum (Pt) film. Metal film 41 has a surface 41A that faces the side 112A of the second semiconductor region 112 through insulating film 104. Metal film 42 has a surface 42A that faces the side 122A of the second semiconductor region 122 through insulating film 104. For example, the lower surface 41B of metal film 41 and the lower surface 42B of metal film 42 are located above the interface 113 of the first semiconductor region 111 and the second semiconductor region 112 and the interface 123 of the first semiconductor region 121 and the second semiconductor region 122. Metal film 31 and metal film 41 are included in anode electrode 51, which is in ohmic contact with the second semiconductor region 112. Metal films 32 and 42 are included in anode electrode 52, which is in 122-ohm contact with the second semiconductor region 1. Anode electrodes 51 and 52 are examples of the second electrode. Surfaces 41A and 42A are examples of the first surface.

[0043] Openings 71 and 72 are formed in the organic insulating films 105, 104, and 103, respectively. Opening 71 extends to a region connected to the first semiconductor region 111 of the n-type semiconductor layer 102, and opening 72 extends to a region connected to the first semiconductor region 121 of the n-type semiconductor layer 102. A cathode electrode 61 and a cathode electrode 62, both in contact with the n-type semiconductor layer 102 through opening 71 and opening 72, are formed on the organic insulating film 105. Metal films 41 and 42 are, for example, laminates of gold-germanium (AuGe) films and gold (Au) films on gold-germanium films. Cathode electrodes 61 and 62 are examples of the first electrode.

[0044] Here, the function of the semiconductor device 100 will be explained. Figure 2 This is a cross-sectional view of the semiconductor device 100 in its first embodiment during operation. Figure 3 This is a diagram showing the voltage-current characteristics of the first nanowire 11 and the second nanowire 12.

[0045] If a positive voltage is applied between the anode electrode 51 and the cathode electrode 61, then as Figure 2 As shown, due to the influence of the electric field from the metal film 41, a depletion layer 114 is formed near the side surface 112A of the second semiconductor region 112. Similarly, if a positive voltage is applied between the anode electrode 52 and the cathode electrode 62, then as... Figure 2 As shown, due to the influence of the electric field from the metal film 42, a depletion layer 124 is formed near the side 122A of the second semiconductor region 122. If the magnitude of the forward voltage is the same, the thicknesses of the depletion layers 114 and 124 are the same. In the semiconductor device 100, the diameter of the second semiconductor region 112 is larger than the diameter of the second semiconductor region 122. Therefore, if the thicknesses of the depletion layers 114 and 124 are the same, the proportion of the depletion layer 114 occupying the second semiconductor region 112 in the radial direction is smaller than the proportion of the depletion layer 124 occupying the second semiconductor region 122 in the radial direction. Therefore, as... Figure 3 As shown, the voltage-current characteristics of the first nanowire 11 and the second nanowire 12 are different. In other words, the nonlinear characteristics differ between the first nanowire 11 and the second nanowire 12. For example, the first nanowire 11 functions as an Esaki diode, exhibiting an S-shaped characteristic that includes a negative resistive component, while the second nanowire 12 exhibits a simple rectifying characteristic.

[0046] The thickness of the insulating film 104 is preferably 10 nm or more and 30 nm or less, more preferably 10 nm or more and 20 nm or less. If the insulating film 104 is too thin, there is a concern that the insulation between the second semiconductor region 112 and the metal film 41, and between the second semiconductor region 122 and the metal film 42, cannot be sufficiently ensured. If the insulating film 104 is too thick, there is a concern that the depletion layers 114 and 124 cannot be sufficiently formed.

[0047] Next, the manufacturing method of the semiconductor device 100 will be described. Figures 4 to 12 This is a cross-sectional view showing a method for manufacturing the semiconductor device 100 according to the first embodiment.

[0048] First, such as Figure 4 As shown, an n-type semiconductor layer 102 is formed on the substrate 101. The n-type semiconductor layer 102 can be grown, for example, by metal-organic chemical vapor deposition (MOCVD). Next, an insulating film 103 is formed on the n-type semiconductor layer 102.

[0049] After that, as Figure 5 As shown, openings 21 and 22 are formed on the insulating film 103. Openings 21 and 22 can be formed, for example, by forming a mask using photolithography and etching the insulating film 103 using the mask. The diameters of openings 21 and 22 are 40 nm to 200 nm, with the diameter of opening 21 being larger than that of opening 22. Next, as a catalyst for the nanowires, a metal film 31, for example, in a disc shape, is formed within opening 21, and a metal film 32, for example, in a disc shape, is formed within opening 22. Gold (Au) is used as a material for metal films 31 and 32, for example. In this way, a substrate for crystal growth comprising a substrate 101, an n-type semiconductor layer 102, an insulating film 103, metal films 31 and 32 is obtained. The insulating film 103 with openings 21 and 22 is an example of a growth mask.

[0050] Next, as Figure 6As shown, a first semiconductor region 111 and a first semiconductor region 121, both composed of n-type GaAs and having a nanowire shape, are grown above a substrate 101. The first semiconductor region 111 is grown from the inside of opening 21, and the first semiconductor region 121 is grown from the inside of opening 22. The first semiconductor regions 111 and 121 can be grown, for example, by MOCVD. For example, the growth temperature is 400°C to 450°C, and the height (length) of the first semiconductor regions 111 and 121 is 0.5 μm to 0.7 μm. For example, triethylgallium (TEGa) is used as the Ga raw material, and arsine (AsH3) is used as the As raw material. Additionally, hydrogen sulfide (H2S) is used as the n-type impurity raw material, and sulfur (S) is used as the n-type impurity dopant. The S concentration is, for example, 1 × 10⁻⁶. 18 cm －3 ~1×10 20 cm －3 The first semiconductor region 111 and the first semiconductor region 121 have the same composition, and the concentrations of n-type impurities contained in the first semiconductor region 111 and the first semiconductor region 121 are also the same.

[0051] Furthermore, similarly Figure 6 As shown, a second semiconductor region 112 and a second semiconductor region 122, composed of p-type GaAsSb and having a nanowire shape, are grown above a substrate 101. The second semiconductor region 112 is grown on the first semiconductor region 111, and the second semiconductor region 122 is grown on the first semiconductor region 121. The second semiconductor regions 112 and 122 can be grown using the same MOCVD method as the first semiconductor regions 111 and 121. For example, the growth temperature is 400°C to 450°C, and the height (length) of the second semiconductor regions 112 and 122 is 1.0 μm to 1.5 μm. For example, triethylgallium (TEGa) is used as the raw material for Ga, arsine (AsH3) is used as the raw material for As, and trimethylantimony (TMSb) is used as the raw material for Sb. Additionally, diethylzinc (DEZn) is used as the raw material for the p-type impurity, with Zn doped as a p-type impurity. The Zn concentration is, for example, 1 × 10⁻⁶. 18 cm －3 ~1×10 20 cm －3 The second semiconductor region 112 and the second semiconductor region 122 have the same composition, and the concentrations of p-type impurities contained in the second semiconductor region 112 and the second semiconductor region 122 are also the same.

[0052] As a result, a first nanowire 11 having a first semiconductor region 111 and a second semiconductor region 112, and a second nanowire 12 having a first semiconductor region 121 and a second semiconductor region 122 are obtained. The diameter of the first nanowire 11 is larger than the diameter of the second nanowire 12.

[0053] Next, as Figure 7 As shown, an insulating film 104 is formed, which covers the first nanowire 11, the second nanowire 12, and the insulating film 103. The insulating film 104 is, for example, an alumina film or a hafnium oxide film with a thickness of 10 nm to 30 nm, preferably 10 nm to 20 nm. The insulating film 104 can be formed, for example, by atomic layer deposition (ALD).

[0054] After that, as Figure 8 As shown, a device separation trench 109 is formed on the insulating film 104, the insulating film 103, and the n-type semiconductor layer 102. The device separation trench 109 is formed to separate the n-type semiconductor layer 102 into a region connected to the first nanowire 11 and a region connected to the second nanowire 12. The device separation trench 109 can be formed, for example, by forming a mask using photolithography and etching the insulating film 104, the insulating film 103, and the n-type semiconductor layer 102 using the mask.

[0055] Next, as Figure 9 As shown, a separation groove 109 for the buried element is formed, and an organic insulating film 105 is formed on the insulating film 104. The organic insulating film 105 is preferably formed with a thickness such that the entire upper surface is located above the top of the metal film 31 and the metal film 32. For example, a BCB film is formed as the organic insulating film 105.

[0056] Next, as Figure 10 As shown, the organic insulating film 105 is dry etched to a thickness approximately 300 nm below the tops of the first nanowire 11 and the second nanowire 12. In the dry etching, a mixture of carbon tetrafluoride (CF4) and oxygen (O2) can be used, for example. The portion of the insulating film 104 covering the metal film 31 and metal film 32 is also removed by utilizing the difference in etching rates between the organic insulating film 105 and the insulating film 104. If the portion of the insulating film 104 covering the metal film 31 and metal film 32 cannot be sufficiently removed during dry etching of the organic insulating film 105, the portion of the insulating film 104 covering the metal film 31 and metal film 32 can be removed by, for example, ion sputtering using argon (Ar) ions after dry etching of the organic insulating film 105.

[0057] After that, as Figure 11As shown, a metal film 41 in contact with a metal film 31 and a metal film 42 in contact with a metal film 32 are formed on an organic insulating film 105. For example, metal films 31 and 32 are laminated films consisting of a platinum (Pt) film and a gold (Au) film on the platinum film. Metal films 31 and 41 are included in an anode electrode 51, and metal films 32 and 42 are included in an anode electrode 52.

[0058] Next, as Figure 12 As shown, openings 71 and 72 are formed in the organic insulating films 105, 104, and 103, respectively. Opening 71 extends to the region of the n-type semiconductor layer 102 connected to the first semiconductor region 111, and opening 72 extends to the region of the n-type semiconductor layer 102 connected to the first semiconductor region 121. Openings 71 and 72 can be formed, for example, by forming a photolithography mask and etching the organic insulating films 105, 104, and 103 using the mask. The insulating films 104 and 103 can also be removed, for example, by ion sputtering using argon (Ar) ions. After forming openings 71 and 72, a cathode electrode 61 that contacts the n-type semiconductor layer 102 through opening 71 and a cathode electrode 62 that contacts the n-type semiconductor layer 102 through opening 72 are formed on the organic insulating film 105. As metal films 41 and 42, for example, are laminated films forming a gold-germanium (AuGe) film and a gold (Au) film on the gold-germanium film.

[0059] In this way, the semiconductor device 100 of the first embodiment can be manufactured.

[0060] According to this method, a semiconductor device 100 can be easily manufactured by configuring multiple nanowires (first nanowire 11 and second nanowire 12) with different voltage-current characteristics with a high degree of integration. Therefore, multiple nonlinear elements with different nonlinear characteristics can be configured with a high degree of integration.

[0061] In the first embodiment, only the first nanowire 11 and the second nanowire 12 are disposed on the substrate 101, but more nanowires may also be disposed.

[0062] The first semiconductor region 111 and the first semiconductor region 121 do not need to have a nanowire shape, but the first semiconductor region 111 and the first semiconductor region 121 having a nanowire shape can easily form a second semiconductor region 112 and a second semiconductor region 122 having a nanowire shape.

[0063] As described above, the voltage-current characteristics of the first nanowire 11 and the second nanowire 12 vary depending on the diameters of the second semiconductor region 112 and the second semiconductor region 122. Here, the relationship between the diameter of the second semiconductor region and the voltage-current characteristics will be explained. Figure 13 This is a graph showing the voltage-current characteristics of nanowires with various second semiconductor regions of different diameters. Figure 13 In the middle, it is shown that with 5×10 17 cm －3 The nanowires, doped with p-type impurities at high concentrations and possessing a second semiconductor region d with a diameter of 20 nm to 200 nm, exhibit voltage-current characteristics. By utilizing a diameter region where the forward current migrates from the micro-ampere level to the nano-ampere level, the forward tunneling current can be varied significantly, enabling the concentrated fabrication of various nonlinear components. From this perspective, in Figure 13 In the example shown, the preferred diameter is around 60nm to 200nm.

[0064] The voltage-current characteristics of the first nanowire 11 and the second nanowire 12 vary not only according to the diameters of the second semiconductor region 112 and the second semiconductor region 122, but also according to the doping concentration (hereinafter referred to as doping concentration) of the p-type impurities contained in the second semiconductor region 112 and the second semiconductor region 122. Here, the relationship between doping concentration and voltage-current characteristics will be explained. Figure 14 This is a graph showing the voltage-current characteristics of nanowires with various second semiconductor regions possessing different doping concentrations. Figure 14 The image shows a diameter of 60 nm and a 1×10⁻⁶ Ω·cm. 17 cm －3 ~5×10 18 cm －3 The voltage-current characteristics of nanowires in the second semiconductor region with a doping concentration ρ. As described above, by using a diameter region where the forward current migrates from the microampere level to the nanoampere level, the forward tunneling current can be varied significantly, enabling the concentrated fabrication of various nonlinear elements. From this perspective, in Figure 14 In the example shown, the preferred doping concentration is 5 × 10⁻⁶. 17 cm －3 ~5×10 18 cm －3 about.

[0065] The inventors of this application, in order to... Figure 13 as well as Figure 14 The relationships shown were further generalized and investigated in greater depth. As a result, the diameter d (cm) and doping concentration ρ (cm²) of the second semiconductor region were discovered. －3 When the following equation (1) is satisfied, a variety of nonlinear elements can be effectively obtained by using multiple nanowires with second semiconductor regions of different diameters.

[0066] 1.8×10 7 ≤d 2 ×ρ≤2×108 ...Equation (1)

[0067] Furthermore, when the diameter of the second semiconductor region varies in the height direction, for example, when the diameter of the second semiconductor region is larger closer to the substrate side, the diameter d in equation (1) is the diameter of the upper surface of the second semiconductor region.

[0068] (Second Implementation)

[0069] The second embodiment will be described. The second embodiment relates to a reservoir circuit having multiple nanowires with different nonlinear characteristics. The reservoir circuit is an example of a semiconductor device. Figure 15 as well as Figure 16 This is a diagram illustrating the reservoir circuit of the second embodiment. Figure 15 It is a circuit diagram showing the connection relationship of multiple nanowires. Figure 16 This is a cross-sectional view showing the interconnections of multiple nanowires. Figure 16 In the original text, some structural elements, such as the insulating film, were omitted.

[0070] like Figure 16 As shown, the reservoir circuit 200 of the second embodiment has a substrate 101, an n-type semiconductor layer 102, a plurality of nanowires 20, wiring 233, wiring 234, wiring 235, wiring 236, an input terminal 231, and an output terminal 232.

[0071] The nanowire 20 has an n-type first semiconductor region 201 and a p-type second semiconductor region 202. The first semiconductor region 201 is disposed on the n-type semiconductor layer 102 and extends upward. The second semiconductor region 202 is disposed on the first semiconductor region 201 and extends upward. The diameters of the nanowires 20 vary. However, it is not necessary for all nanowires 20 to have different diameters; they can also contain nanowires 20 with equal diameters. The n-type semiconductor layer 102 is separated for each nanowire element.

[0072] like Figure 15As shown, for example, multiple nanowires 20 are arranged at equal intervals in two mutually orthogonal directions (X direction and Y direction). That is, when viewed from above, the multiple nanowires 20 are arranged in a lattice pattern above the substrate 101. For example, the input terminals 231 and the output terminals 232 are provided in the same number as the number of rows formed by the multiple nanowires 20 arranged in the X direction. Wiring 233 connects the input terminals 231 to the second semiconductor region 202 of one end of the multiple nanowires 20 arranged in the X direction. Wiring 234 connects the output terminals 232 to the n-type semiconductor layer 102 connected to the first semiconductor region 201 of the multiple nanowires 20 arranged in the X direction at the other end. Wiring 235 connects the n-type semiconductor layer 102 connected to one first semiconductor region 201 and another second semiconductor region 202 between two adjacent nanowires 20 in the X direction. Wiring 236 connects one second semiconductor region 202 and another second semiconductor region 202 between two adjacent nanowires 20 in the Y direction.

[0073] A portion of wiring 233 and a portion of wiring 236 function as an anode electrode, and a portion of wiring 234 functions as a cathode electrode. A portion of wiring 235 functions as an anode electrode, and the remaining portion functions as a cathode electrode. The portions of wirings 233, 235, and 236 that function as anode electrodes are the same as those of metal films 41 and 42 in the first embodiment, and are configured to have surfaces facing the side of the second semiconductor region 202 separated by an insulating film 204.

[0074] According to the second embodiment, multiple nanowires 20 with different nonlinear characteristics are connected in a network. Therefore, a reservoir circuit 200 is obtained that integrates multiple nonlinear elements possessing various nonlinear characteristics with a high degree of integration. Furthermore, since the nonlinear characteristics differ even among the multiple nanowires 20 if their diameters are different, even if the materials and compositions are the same, they can be manufactured without complex processing.

[0075] exist Figure 15 The middle figure shows 36 nanowires 20 in a 6×6 configuration, but it is preferable to have more nanowires 20.

[0076] (A variation of the second embodiment)

[0077] A variation of the second embodiment will be described. The connection points between the plurality of nanowires 20 in the variation differ from those in the second embodiment. Figure 17 This is a diagram showing a modified example of the reservoir circuit of the second embodiment. Figure 17 It is a circuit diagram showing the connection relationship of multiple nanowires.

[0078] like Figure 17As shown, in the modified reservoir circuit 200A, a portion of the pair of adjacent nanowires 20 in the X direction is not provided with wiring 235. Additionally, a portion of the pair of adjacent nanowires 20 in the Y direction is not provided with wiring 236.

[0079] The other structures are the same as in the second embodiment.

[0080] According to the modified reservoir circuit 200A, compared with the reservoir circuit 200 of the second embodiment, the irregularity of the network of nonlinear elements can be improved.

[0081] In the second embodiment or its variations, multiple second semiconductor regions are connected via wiring, or the first semiconductor region is connected to the second semiconductor region, but multiple first semiconductor regions can also be connected via wiring.

[0082] (Third Implementation)

[0083] A third embodiment will be described. This third embodiment relates to a reservoir circuit comprising multiple nanowires with different nonlinear characteristics and including a variable weighting circuit. The reservoir circuit is an example of a semiconductor device. Figure 18 as well as Figure 19 This is a diagram illustrating the reservoir circuit of the third embodiment. Figure 18 It is a circuit diagram showing the connection relationship of multiple nanowires. Figure 19 This is a cross-sectional view showing the interconnections of multiple nanowires. Figure 19 The insulating film and other structural components are omitted in the text.

[0084] like Figure 19 As shown, the reservoir circuit 300 of the third embodiment includes a substrate 101, an n-type semiconductor layer 102, a plurality of nanowires 20, wiring 233, wiring 234, wiring 235, wiring 236, wiring 237, a variable weighting circuit 238, an input terminal 231, and an output terminal 232. The substrate 101, the n-type semiconductor layer 102, the plurality of nanowires 20, wiring 233, wiring 235, and wiring 236 are configured in the same manner as in the second embodiment.

[0085] The variable weighting circuit 238 includes oxide memristors 239 arranged in rows of a plurality of nanowires 20 arranged in the X direction. Wiring 234 connects one end of the oxide memristor 239 to an n-type semiconductor layer 102, wherein the n-type semiconductor layer 102 is connected to a first semiconductor region 201 of one of the nanowires 20 arranged in the X direction at the other end. Wiring 237 connects an output terminal 232 to the n-type semiconductor layer 102, wherein the n-type semiconductor layer 102 is connected to the other end of the oxide memristor 239. The oxide memristor 239 is an example of an analog memory.

[0086] The other structures are the same as in the second embodiment.

[0087] In the reservoir circuit 300 of the third embodiment, the resistance of the oxide memristor 239 varies according to the current (signal strength) output from the plurality of nanowires 20 through wiring 234, and the variable weighting circuit 238 maintains the weighting information. The reservoir circuit 300 of the third embodiment is equivalent to a device integrated into linear readout in a reservoir computing system.

[0088] (Fourth Implementation)

[0089] The fourth embodiment will be described. The fourth embodiment relates to a reservoir computing system equipped with reservoir circuitry. Figure 20 This is a block diagram illustrating the reservoir calculation system of the fourth embodiment.

[0090] like Figure 20 As shown, the reservoir computing system 400 of the fourth embodiment includes an input circuit 401, a reservoir circuit 402, and an output circuit 403. The reservoir circuit 402 includes a readout weighting unit 404. The reservoir computing system 400 may also include a learning data circuit 405. The reservoir circuit 402 may also be either the reservoir circuit 200 or the reservoir circuit 300.

[0091] When learning the reservoir calculation system 400, learning data (teacher data) is input from the learning data circuit 405 to the readout weighting unit 404, and the readout weighting unit 404 is adjusted to perform appropriate weighting. The readout weighting unit 404 is an example of an analog memory.

[0092] When using the reservoir computing system 400, the learning data circuit 405 is disconnected from the reservoir circuit 402. Furthermore, data is input from the input circuit 401 to the reservoir circuit 402, where the readout weighting unit 404 performs weighted and other computational processing on the input data. The results of the computational processing in the reservoir circuit 402 are output from the output circuit 403.

[0093] According to the fourth embodiment, nanowires can be configured as multiple nonlinear elements included in the reservoir computing system 400 with a high degree of integration.

[0094] The preferred embodiments have been described in detail above, but are not limited to the embodiments described above. Various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims.

[0095] Explanation of reference numerals in the attached figures

[0096] 11, 12, 20… nanowires; 21, 22… openings; 31, 32, 41, 42… metal films; 41A, 42A… surfaces; 51, 52… anode electrodes; 61, 62… cathode electrodes; 100… semiconductor device; 103, 104, 204… insulating films; 111, 112, 121, 122, 201, 202… semiconductor regions; 112A, 122A… sides; 113, 123… bonding interfaces ; 114, 124… Depletion layer; 200, 200A, 300… Reservoir circuit; 231… Input terminal; 232… Output terminal; 233, 234, 235, 236, 237… Wiring; 238… Variable weighting circuit; 239… Oxide memristor; 400… Reservoir calculation system; 401… Input circuit; 402… Reservoir circuit; 403… Output circuit; 404… Readout weighting unit; 405… Learning data circuit.

Claims

1. A semiconductor device, characterized in that, have: Multiple tunnel diodes each have a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type disposed on the first semiconductor region and having a nanowire shape; An insulating film is disposed around the side of the aforementioned second semiconductor region; Multiple first electrodes are respectively connected to the aforementioned first semiconductor region; and Multiple second electrodes are respectively connected to the aforementioned second semiconductor region. The second electrode has a first surface, which faces the side of the second semiconductor region across the insulating film. The diameter of the upper surface of the second semiconductor region of the first tunnel diode in the plurality of tunnel diodes is different from the diameter of the upper surface of the second semiconductor region of the second tunnel diode in the plurality of tunnel diodes. The lower surface of the second electrode is located above the interface between the first semiconductor region and the second semiconductor region.

2. The semiconductor device according to claim 1, characterized in that, The diameter of the impurity of the second conductivity type contained in the upper surface of the second semiconductor region is d (cm), and the concentration of the impurity of the second conductivity type contained in the second semiconductor region is ρ (cm³). -3 When ), the relationship in equation (1) holds. 1.8×10 7 ≤d 2 ×ρ≤2×10 8 ...Formula (1).

3. The semiconductor device according to claim 1, characterized in that, The thickness of the aforementioned insulating film is greater than 10 nm and less than 30 nm.

4. The semiconductor device according to claim 1, characterized in that, The first portion of the plurality of first electrodes is connected to the second portion of the plurality of first electrodes or one of the plurality of second electrodes.

5. The semiconductor device according to claim 1, characterized in that, The first semiconductor region described above has the shape of a nanowire.

6. The semiconductor device according to claim 1, characterized in that, Among the plurality of tunnel diodes, the concentration of impurities of the second conductivity type contained in the second semiconductor region is equal.

7. A reservoir computing system, characterized in that, have: Input circuit; Output circuit; as well as The reservoir circuit is connected between the input circuit and the output circuit. The aforementioned reservoir circuit includes a semiconductor device, the semiconductor device having: Multiple tunnel diodes each have a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type disposed on the first semiconductor region and having a nanowire shape; An insulating film is disposed around the side of the aforementioned second semiconductor region; Multiple first electrodes are respectively connected to the aforementioned first semiconductor region; and Multiple second electrodes are respectively connected to the aforementioned second semiconductor region. The second electrode has a first surface, which faces the side of the second semiconductor region across the insulating film. The diameter of the upper surface of the second semiconductor region of the first tunnel diode in the plurality of tunnel diodes is different from the diameter of the upper surface of the second semiconductor region of the second tunnel diode in the plurality of tunnel diodes. The lower surface of the second electrode is located above the interface between the first semiconductor region and the second semiconductor region.

8. The reservoir computing system according to claim 7, characterized in that, The aforementioned reservoir circuit has an analog memory. It has a learning data circuit, which inputs teacher data into the analog memory.

9. A method for manufacturing a semiconductor device, characterized in that, have: A process for forming multiple tunnel diodes, wherein each of the multiple tunnel diodes has a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type disposed on the first semiconductor region and having a nanowire shape; The process of forming an insulating film, wherein the insulating film is disposed around the side surface of the second semiconductor region; The process of forming a plurality of first electrodes, wherein the plurality of first electrodes are respectively connected to the first semiconductor region; and The process of forming a plurality of second electrodes, wherein the plurality of second electrodes are respectively connected to the second semiconductor region. The process of forming the above-mentioned multiple tunnel diodes includes: A process of forming a growth mask with multiple openings of different diameters on top of a substrate; The process of growing multiple first semiconductor regions through the aforementioned multiple openings; and The process of growing the second semiconductor region on each of the aforementioned first semiconductor regions. The second electrode has a first surface, which faces the side of the second semiconductor region across the insulating film. The diameter of the upper surface of the second semiconductor region of the first tunnel diode in the plurality of tunnel diodes is different from the diameter of the upper surface of the second semiconductor region of the second tunnel diode in the plurality of tunnel diodes. The lower surface of the second electrode is located above the interface between the first semiconductor region and the second semiconductor region.

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