Microprocessor, method for a microprocessor and data processing system

Abstract

A microprocessor is disclosed that includes a shared functional unit, a first execution queue, and a second execution queue. The first execution queue includes a plurality of entries, where each entry of the first execution queue includes a first count value that is decremented until the first count value reaches zero. When the first count value reaches zero, the first execution queue dispatches a first type of instruction to the shared functional unit. The second execution queue includes a plurality of entries, where each entry of the second execution queue includes a second count value that is decremented until the second count value reaches zero. When the second count value reaches zero, the second execution queue dispatches a second type of instruction to the shared functional unit. A dispatch unit resolves all data dependencies and resource conflicts such that the first count value and the second count value are preset for the first type of instruction and the second type of instruction to be executed by the shared functional unit at exact times in the future relative to each other.

Description

Technical Field

[0001] This disclosure generally relates to a microprocessor, and more specifically, to a microprocessor having a shared functional unit for executing multiple types of instructions, methods suitable for the microprocessor, and a data processing system. Background Technology

[0002] Superscalar microprocessors achieve high performance by executing multiple instructions per clock cycle and through out-of-order instruction execution. Instructions must be written back to the register set in an ordered manner to avoid control hazards such as branch misprediction, interrupts, and precise exceptions. Temporary storage devices, such as reorder buffers and register renaming, are used for result data until it can be returned to the register set in an ordered manner. Furthermore, storage devices are needed to hold source operand data in the execution queue until the instruction is available for execution by a functional unit. These storage devices are typically several times the size of the architecture's register set, and reading / writing these storage devices consumes significantly more power.

[0003] When a microprocessor contains independent, multi-type processing units (such as a scalar floating-point unit (FPU) and a vector processing unit (VPU), achieving performance, power, and area (PPA) metrics becomes difficult. A VPU consists of both integer and floating-point (FP) arithmetic functions. FP execution units are significantly larger than integer execution units. Sharing execution units between different instruction types can be extremely complex, especially in out-of-order execution microprocessors that handle different register sets, data dependencies, and result forwarding. Microprocessors can share execution units by serializing instruction types, meaning scalar FP instructions must be completed and the execution unit must be cleaned up before vector instructions can be sent to it. However, when instructions from two multi-type processing units are allowed to reside in the microprocessor's execution pipeline, the microprocessor's performance is limited. Summary of the Invention

[0004] This disclosure describes a microprocessor, method, and data processing system that can improve the performance of a microprocessor with shared functional units.

[0005] In some embodiments, the microprocessor includes a shared functional unit, a first execution queue, a second execution queue, a first type dispatch unit, and a second type dispatch unit. The first execution queue contains multiple entries, each entry recording a first type instruction. Each entry in the first execution queue contains a first count value corresponding to the first type instruction, and the first count value is decremented until it reaches 0. When the first count value corresponding to the first type instruction reaches 0, the first execution queue dispatches the first type instruction to the shared functional unit. The second execution queue contains multiple entries, each entry recording a second type instruction. Each entry in the second execution queue contains a second count value corresponding to the second type instruction, and the second count value is decremented until it reaches 0. When the second count value reaches 0, the second execution queue dispatches the second type instruction to the shared functional unit. The shared functional unit executes the first type instruction and the second type instruction, wherein the first type instruction from the first execution queue and the second type instruction from the second execution queue are dispatched to the shared functional unit mutually exclusively. A key difference from existing techniques that dynamically select different types of instructions for execution by a shared function unit is that, by using preset counters (a first count value and a second count value), instructions are scheduled for execution by the shared function unit at a precise future time. Reads and writes of data from the register set are preset to be synchronized for the precise future execution time of either type I or type II instructions within the shared function unit. As with existing techniques, dynamic conflict resolution, dynamic data dependency resolution, and dynamic read / write port resolution are not required. Dynamic resolution is the most power-intensive aspect of microprocessor design.

[0006] In some embodiments, the method is applicable to a microprocessor including a first execution queue, a second execution queue, and a shared functional unit. The method includes the steps of: dispatching a first type of instruction recorded in an entry of the first execution queue to the shared functional unit in response to determining that a first counter in an entry of the first execution queue reaches 0; dispatching a second type of instruction recorded in an entry of the second execution queue to the shared functional unit in response to determining that a second counter in an entry of the second execution queue reaches 0; and executing the first type of instruction and the second type of instruction by the shared functional unit.

[0007] In some embodiments, the data processing system includes a memory and a microprocessor, wherein the memory is configured to store first type instructions and second type instructions. The microprocessor includes a shared functional unit, a first execution queue, a second execution queue, a first type dispatch unit, and a second type dispatch unit. The first execution queue contains multiple entries, each entry of which records a first type instruction. Each entry of the first execution queue contains a first count value corresponding to the first type instruction, and the first count value is decremented until a first counter reaches 0. When the first count value corresponding to the first type instruction reaches 0, the first execution queue dispatches the first type instruction to the shared functional unit. The second execution queue contains multiple entries, each entry of which records a second type instruction. Each entry of the second execution queue contains a second count value corresponding to the second type instruction, and the second count value is decremented until a second counter reaches 0. When the second counter reaches 0, the second execution queue dispatches the second type instruction to the shared functional unit. The shared functional unit executes the first type instructions and the second type instructions, wherein the first type instructions from the first execution queue and the second type instructions from the second execution queue are mutually dispatched to the shared functional unit. In another embodiment, the first and second execution queues can be merged into a single queue with a label of the type of instruction used to indicate each entry in the queue. A single execution queue is more efficient, but two execution queues are easier to configure. Attached Figure Description

[0008] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figure 1 This is a block diagram illustrating a data processing system according to some embodiments;

[0010] Figure 2 This is a diagram illustrating a scoreboard and register set according to some embodiments;

[0011] Figures 3A to 3B This is a diagram illustrating various structures of scoreboard entries according to some embodiments;

[0012] Figure 4 This is a diagram illustrating a read shifter associated with a read port of a register set according to some embodiments;

[0013] Figure 5 This is a diagram illustrating a write shifter associated with a write port of a register set according to some embodiments;

[0014] Figure 6 This is a diagram illustrating the execution queue according to some embodiments;

[0015] Figures 7A to 7B These are diagrams illustrating various structures of a microprocessor according to some embodiments;

[0016] Figure 8 This is a diagram illustrating the execution queue according to some embodiments;

[0017] Figure 9 This is a flowchart illustrating the process of issuing instructions according to some embodiments;

[0018] Figure 10 This is a flowchart illustrating a method suitable for a microprocessor according to some embodiments.

[0019] Explanation of icon numbers

[0020] 1: Data processing system;

[0021] 10: Microprocessor;

[0022] 11: Instruction cache;

[0023] 12: Branch prediction unit;

[0024] 13, 13b, 13c: Decoding / Publishing Unit;

[0025] 14, 14b, 14c: Register set;

[0026] 15, 15b, 15c: Scoreboard;

[0027] 16, 16b, 16c: Read / write control unit;

[0028] 17: Load / store unit;

[0029] 18: Data caching;

[0030] 19, 19A, 19B, 19C, 19D, 19E, 291A, 291B, 291C, 292A, 292B, 292C: Execution queue;

[0031] 19s: Shared execution queue;

[0032] 20, 20A, 20B, 20C, 160, 201A, 201B, 202A, 202B: Functional units;

[0033] 20s: Shared functional unit;

[0034] 22: Tag array;

[0035] 163: Write to the shifter;

[0036] 24: Data array / data cache;

[0037] 30: Memory;

[0038] 31, 31b, 31c: Read the bus;

[0039] 32, 32b, 32c: Result bus;

[0040] 100, 100A, 100B, 100C: Execution blocks;

[0041] 150(0), 150(N), 190(0), 190(1), 190(2), 190(Q), 1510(0), 1510(N), 1610(1), 1610(M), 1630(1), 1630(P): Entries;

[0042] 151: First Scoreboard;

[0043] 152: Second Scoreboard;

[0044] 161: Read the shifter / shift register;

[0045] 171: Address generation unit;

[0046] 191: Valid field;

[0047] 192: Micro-operation count field;

[0048] 193: Execution control data field;

[0049] 194: Throughput count field;

[0050] 195: Data field;

[0051] 197: Read the count field;

[0052] 199: Accumulator counter;

[0053] 199b: Vector cumulative throughput counter;

[0054] 199c: FP cumulative throughput counter;

[0055] 200A, 200B, 200C, 200D: Execution Units;

[0056] 300, 302_1, 302_2, 330: Multiplexing;

[0057] 303: Micro-operation counter;

[0058] 305: Throughput counter;

[0059] 501, 502, 503b, 503c, 510, 511b, 511c: Blocks;

[0060] 1511, 1521: Unknown fields;

[0061] 1531, 1523: Count fields;

[0062] 1551: Functional unit field;

[0063] 1520(0), 1520(N): Scoreboard entries;

[0064] 1611, 1611(X): Read valid fields;

[0065] 1613: Address field / register address;

[0066] 1631, 1631(Y): Write back valid fields;

[0067] 1633: Write address field / register address;

[0068] 1635: Functional unit field;

[0069] f_active: FP active bit;

[0070] f_inst: FP instruction;

[0071] inst: Valid instruction;

[0072] R(0), R(N): Registers;

[0073] rd_cnt: Read count;

[0074] v_active: Vector active bit;

[0075] v_inst: Vector instruction. Detailed Implementation

[0076] The following disclosure provides several different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first feature is formed in direct contact with the second feature, and may also include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0077] This disclosure describes a microprocessor that schedules instructions to a future time for execution rather than suspending the pipeline. This processor may also be referred to as a future scheduling execution (FSE) microprocessor. Conventionally, if a register or functional unit specified by an instruction is not ready (e.g., resource conflicts such as data dependencies, availability of register read and write ports, availability of functional units, etc.), the decode / issue unit will suspend the execution pipeline or set aside the instruction until the availability of the register or functional unit is resolved. In an FSE microprocessor, based on the resolution of data dependencies and the availability of register and functional unit read and write ports in the future time, the decode / issue unit will still issue these instructions and schedule them to a future time for execution.

[0078] refer to Figure 1 A schematic diagram of a data processing system 1 comprising a microprocessor 10 and a memory 30 is shown according to some embodiments. The microprocessor 10 is configured to perform various data processing functions by executing instructions stored in the memory 30. The memory 30 may include a level 2 (L2) cache and a level 3 (L3) cache, as well as the main memory of the data processing system 1, wherein the L2 cache and L3 cache have faster access times than the main memory. The memory may include at least one of random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), programmable read-only memory (PROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory.

[0079] Microprocessor 10 can be a superscalar microprocessor that implements instruction-level parallelism within a single microprocessor. Superscalar microprocessors achieve high performance by executing multiple instructions per clock cycle. Multiple instructions are dispatched to different functional units for parallel execution. Superscalar microprocessors can employ out-of-order (OOO) execution, where a second instruction that has no dependency on the first instruction can be executed before the first instruction. In conventional out-of-order microprocessor designs, instructions can be executed out of order, but due to control hazards such as branch misprediction, interrupts, and precise exceptions, the instructions must be out-of-ordered to the microprocessor's register set. Temporary storage such as reorder buffers and register renaming is used for the result data until the instructions are out-of-ordered from the execution pipeline. In this invention, as long as the instructions do not have data dependencies or control hazards, microprocessor 10 can execute and out-of-order instructions by writing the result data out of order back to the register set. In embodiments, no temporary registers are used for this FSE microprocessor 10 because microprocessor 10 is configured to issue instructions with data dependencies or control hazards by scheduling instructions to future times. However, this disclosure is not intended to be limited thereto. In some other embodiments, temporary registers may also be used.

[0080] refer to Figure 1The microprocessor 10 may include an instruction cache 11, a branch prediction unit (BPU) 12, a decode / release unit 13, a register set 14, a scoreboard 15, a read / write control unit 16, a load / store unit 17, a data cache 18, multiple execution queues (EQ) 19A to 19E, wherein the execution queues may be used for dedicated purposes (such as a tag execution queue TEQ 19D and a data execution queue DEQ 19E), and multiple functional units (FUNT) 20A to 20C. The microprocessor 10 also includes a read bus 31 and a result bus 32. The read bus 31 is coupled to the load / store unit 17, functional units 20A to 20C, and the register set 14 for transferring operand data from registers in the register set 14 to the load / store unit 17 and functional units 20A to 20C, which may also be referred to as the operation of reading operation data from the register set 14 (or storing data in the case of stored instructions). The result bus 32 is coupled to data cache 18, functional units 20A to 20C, and register group 14 for transferring data from data cache 18 or functional units 20A to 20C to registers in register group 14. This can also be referred to as writing result data back to register group 14 (or loading data in the case of load instructions). Elements referred to by specific reference numerals followed by letters herein will be collectively referred to by separate reference numerals. For example, unless otherwise specified, execution queues 19A to 19E will be collectively referred to as execution queue 19. Decode / release unit 13, scoreboard 15, read / write control unit 16, register group 14, multiple execution queues 19, and multiple functional units 20 are grouped together in execution block 100A for one type of instruction that performs data access through the same register group. In some embodiments, microprocessor 10 may also execute other types of instructions, such as vector instructions or floating-point instructions shown in execution blocks 100B and 100C, which are collectively referred to herein as execution block 100. In some embodiments, instructions may comprise different types of instructions. For example, instructions may include at least one of vector instructions, scalar FP instructions, single instruction / multiple data (SIMD) instructions, digital signal processing (DSP) instructions, or any other type of instruction. The definitions of vector instructions, scalar FP instructions, SIMD instructions, and DSP instructions are well known in the related art, and therefore detailed descriptions of those instruction types are omitted below. Some embodiments of this disclosure may use... Figure 1 The components shown may be more, fewer, or different.

[0081] In some embodiments, instruction cache 11 is coupled (not shown) to memory 30 and decode / deploy unit 13, and configured to store instructions fetched from memory 30 and dispatch the instructions to decode / deploy unit 13. Instruction cache 11 contains a plurality of cache lines for consecutive instruction bytes from memory 30. Cache lines are organized as direct mapping, fully associative mapping, or set-associative mapping, etc. Direct mapping, fully associative mapping, and set-associative mapping are well known in the related art, and therefore detailed descriptions of the above mappings are omitted below.

[0082] Instruction cache 11 may include a tag array (not shown) and a data array (not shown) for storing portions of the addresses of frequently used instructions used by microprocessor 10 and data, respectively. Each tag in the tag array corresponds to a cache line in the data array. When microprocessor 10 needs to execute an instruction, it first checks the presence of the instruction in instruction cache 11 by comparing the address of the instruction with the tags stored in the tag array. If the instruction address matches one of the tags in the tag array (i.e., a cache hit), the corresponding cache line is retrieved from the data array. If the instruction address does not match any entry in the tag array, it is a cache miss, and microprocessor 10 can access memory 30 to find the instruction. In some embodiments, microprocessor 10 also includes an instruction queue (not shown) coupled to instruction cache 11 and a decoding / deploying unit 13 for storing instructions from instruction cache 11 or memory 30 before sending instructions to decoding / deploying unit 13.

[0083] BPU 12 is coupled to instruction cache 11 and configured to speculatively fetch instructions following branch instructions. BPU 12 may provide a prediction of the branch direction (taken or not taken) of a branch instruction based on past behavior of the branch instruction, and provides the predicted branch target address of the taken branch instruction. A branch direction may be "taken," where subsequent instructions are fetched from the branch target address of the taken branch instruction. A branch direction may be "not taken," where subsequent instructions are fetched from a memory location contiguous with the branch instruction. In some embodiments, BPU 12 implements basic block branch prediction for predicting the end of a basic block from the start address of the basic block. The start address of the basic block (e.g., the address of the first instruction of the basic block) may be the target address of a previously taken branch instruction. The end address of the basic block is the address of the instruction following the last instruction of the basic block, which may be the start address of another basic block. A basic block may contain multiple instructions, and the basic block ends when a branch in the basic block jumps to another basic block.

[0084] The functional unit may include a branch execution unit (BEU) (which may be one of the functional units 20) that executes branch instructions and determines whether the predicted branch direction is incorrect (mispredicted). For example, the BEU may compare the predicted branch direction (taken or not taken) with the actual branch executed to determine whether the predicted branch direction is correct. Instructions following the mispredicted branch are discarded from various units in the microprocessor. Branch misprediction may also come from the decode / release unit 13 to decode unconditional branch instructions (always taken branches) that were not predicted by the BPU 12. The decode / release unit 13 and the BPU 12 may provide update information to the BPU 12. In the microprocessor 10, instructions following a branch instruction must not be written back to register set 14 until after the branch instruction has been executed.

[0085] Decoding / Releasing Unit 13 can decode instructions received from Instruction Cache 11. Instructions may contain the following fields: operation code (or opcode), operands (e.g., source operand and destination operand), and immediate data. The opcode may specify the operation to be performed (e.g., ADD, SUBTRACT, SHIFT, STORE, LOAD, etc.). Operands may specify the index or address of a register in Register Set 14, where the source operand indicates the register from which the operation will be read, and the destination operand indicates the register from which the result data of the operation in Register Set will be written back. It should be noted that the source operand and destination operand may also be referred to as source register and destination register, and are used interchangeably below. In some embodiments, operands will require a 5-bit index to identify a register in Register Set 14 with 32 registers. Some instructions may use immediate data instead of register data as specified in the instruction. Each operation will be executed in Function Unit 20 or Load / Store Unit 17. Each instruction will have an execution latency and throughput time based on the operation type specified by the opcode and the availability of resources (e.g., registers, function units, etc.). Execution wait time (or wait period) refers to the amount of time (i.e., clock cycles) required to execute the operation specified by the instruction to complete and write back the result data. Throughput time refers to the amount of time (i.e., clock cycles) required for the next instruction to enter functional unit 20.

[0086] In this embodiment, instructions are decoded in the decoding / issuing unit 13 based on the opcode, execution wait time, throughput time, and instruction type. Instructions are dispatched to execution queue 19 for execution by functional unit 20 or load / store unit 17. Multiple instructions can be issued to an execution queue 19 in which the throughput time is accumulated. The accumulated time indicates the time when the next instruction can enter functional unit 20 for execution, based on previously issued instructions in execution queue 19. The time when an instruction can be sent to functional unit 20 is called the read time (from the register set), and the time when the instruction is completed by functional unit 20 is called the write time (to the register set). Instructions are issued to execution queue 19, where each issued instruction has a scheduled read time to be dispatched to functional unit 20 or load / store unit 17 for execution. The accumulated throughput time is the read time of the issued instruction. When an instruction is issued to the next available entry in execution queue 19, the instruction wait time of the instruction is added to the accumulated throughput to produce the write time. The accumulated time modifies the wait time and start time of the issued instruction. The modified execution wait time will be referred to herein as the write time of the most recently issued instruction, and the modified start time will be referred to herein as the read time of the issued instruction. The write time and read time can also be referred to as access time, which describes the specific point in time when the issued instruction is written to or read from the registers of register group 14. For parallel issuance of more than one instruction, the write time and read time of the second instruction can be further adjusted based on the first instruction issued before the second instruction. The decode / issue unit 13 can decode the load / store instruction into two micro-operations, including a tag micro-operation and a data micro-operation.

[0087] In some embodiments, before issuing an instruction, the decoding / issuing unit 13 checks and resolves all possible conflicts. Instructions may have four basic types of conflicts: (1) data dependencies, including write-after-read (WAR), read-after-write (RAW), and write-after-write (WAW) dependencies; (2) availability of read ports for reading data from the register set to the functional unit; (3) availability of write ports for writing data back from the functional unit to the register set; and (4) availability of the functional unit 20 for executing data. The decoding / issuing unit 13 may access the scoreboard 15 to check data dependencies before the instruction can be dispatched to the execution queue 19. The register set 14 has a finite number of read and write ports, wherein the issued instruction must arbitrate or reserve read and write ports for future access to the register set 14. The read / write control unit 16 maintains the scheduled read time for each source operand of the instruction and the scheduled write time for each destination operand of the instruction. The decoding / publishing unit 13 can access the read / write control unit 16 to check the availability of the read ports of register set 14 in order to schedule the access time (i.e., read time and write time) of instructions. In other embodiments, one of the write ports may be dedicated to instructions with unknown execution wait times to write back to register set 14 without using write port control, and one of the read ports may be reserved for instructions with unknown read times to read data from register set 14 without using read port control. The number of read ports of register set 14 may be dynamically reserved (not dedicated) for unknown read operations. In this case, functional unit 20 or load / store unit 17 must ensure that the read ports are not busy when attempting to read data from register set 14. In an embodiment, the availability of functional unit 20 can be resolved by coordinating with execution queue 19, in which the throughput time of queued instructions (i.e., previously published to the execution queue) is accumulated. Based on the accumulated throughput time in the execution queue, instructions may be dispatched to execution queue 19, where instructions may be scheduled to be published to functional unit 20 at a specific time in the future when functional unit 20 is available.

[0088] Figure 2This is a block diagram illustrating register 14 and scoreboard 15 according to some embodiments of the present disclosure. Register set 14 may include multiple registers R(0) to R(N), read ports, and write ports (not shown), where N is an integer greater than 1. In embodiments, register set 14 may include scalar register sets and vector register sets. The present disclosure does not intend to limit the number of registers, read ports, and write ports in register set 14. Scoreboard 15 includes multiple entries 150(0) to 150(N), and each scoreboard entry corresponds to a register in register set 14 and records information associated with the corresponding register. In some embodiments, scoreboard 15 has the same number of entries as register set 14 (i.e., N entries), but the present disclosure does not intend to limit the number of entries in scoreboard 15.

[0089] Figures 3A to 3B This is a diagram illustrating various structures of scoreboard entries according to some embodiments of the present disclosure. In an embodiment, scoreboard 15 may include a first scoreboard 151 for handling write-back operations to register set 14 and a second scoreboard 152 for handling read operations from register set 14. The first scoreboard 151 and the second scoreboard 152 may or may not coexist in the microprocessor 10. The present disclosure is not intended to be limited thereto. In other embodiments, the first scoreboard 151 and the second scoreboard 152 may be implemented as or considered as a single scoreboard 15 handling both read and write operations. Figure 3A The first scoreboard 151 for the destination register of the issued instructions is shown. Figure 3B The second scoreboard 152 is shown, used for the source registers of the issued instructions. (Reference) Figure 3A Each entry 1510(0) to 1510(N) of the first scoreboard 151 contains an Unknown field (“Unknown”) 1511, a count field (“cnt”) 1531, and a functional unit field (“funit”) 1551. Each of these fields records information related to the corresponding destination register to be written by the issued instruction. These fields of the scoreboard entry can be set when the instruction is issued.

[0090] Unknown field 1511 contains bit values ​​indicating whether the write time of the register corresponding to the scoreboard entry is known or unknown. For example, unknown field 1511 may contain one bit where a non-zero value indicates the register has an unknown write time, and a zero value indicates the register has a known write time as indicated by count field 1531. In some embodiments, unknown field 1511 may contain any number of bits to indicate that one or more issued instructions with unknown write times are scheduled to write to the register. Unknown field 1511 may be set or modified at the time of instruction issuance and reset after resolving the unknown register write time. The reset operation can be performed by decoding / issuing unit 13, loading / storing unit 17 (e.g., after a data hit), or functional unit 20 (e.g., after an INT DIV operation resolves the number of numbers to be divided), and other units in the microprocessor involved in executing instructions with unknown write times. In some embodiments, unknown field 1511 may contain two bits, which would have four different states recording the presence of three other issued instructions scheduled to write to the register with unknown write times. In some other embodiments, the unknown field 1511 may include three bits, four bits, etc., to record multiple published instructions with unknown write times.

[0091] Count field 1531 records a count value indicating the number of clock cycles before the register can be written to (issued) by the next instruction; it may also be referred to as the write count field. In other words, count field 1531 records the number of clock cycles it will take for a previously issued instruction to complete its operation and write the result data back to the register. The count value of count field 1531 is set based on the execution wait time at the instruction's issuance time. The count value is then counted down (i.e., decremented by one) for each clock cycle until it reaches zero (i.e., a self-reset counter). For example, the execution wait time for an ADD instruction is 2 clock cycles, and the count value in count field 1531 will be set to 2 at the issuance time of the ADD instruction in the destination register and will self-reset when the count field reaches 0. A count value of 3 indicates that the result data will be written back to the register corresponding to the scoreboard entry after 3 clock cycles, a count value of 1 indicates that the result data will be written back to the register in the next clock cycle, and a count value of 0 indicates that there is no data dependency for accessing the register. In an embodiment, the issued instruction can be written to or read from the register. When writing to a register, the value of counter field 1531 can be referred to as the write (or wait) count value. When reading from a register, the value of counter field 1531 can be referred to as the read-to-read count value. Figure 3B The read count value is discussed in the text. In other words, in some other embodiments, the count value field may record the write time or read time of the register depending on the operation specified by the issued instruction.

[0092] The function unit field 1551 of the scoreboard entry specifies the function unit 20 to be written back to the register (as specified by the issued instruction). For example, the function unit field 1551 for recording the ALU indicates that result data will be written back to the register from the ALU function unit. In some embodiments, the function unit recorded in the function unit field 1551 can be used to forward result data from the recorded function unit to another function unit specified by the next instruction when the count field 1531 reaches a value of 1.

[0093] Figure 3B This is a diagram illustrating the structure of scoreboard entries according to some embodiments of the present disclosure. A second scoreboard 152, having the structure of scoreboard entries 1520(0) to 1520(N), is designed to resolve conflicts written to the register corresponding to the scoreboard entry before reading a issued instruction from the register. The second scoreboard may also be referred to as a WAR scoreboard for resolving WAR data dependencies. Each of scoreboard entries 1520(0) to 1520(N) includes an unknown field (“Unknown”) 1521 and a count field (also referred to as a count field) (“read_cnt”) 1523. Functional unit fields may be omitted in embodiments of the WAR scoreboard. The unknown field 1521 contains a bit value indicating whether the read time of the register corresponding to the scoreboard entry is known or unknown. The operation and functionality of the unknown field 1521 are similar to that of the unknown field 1511; therefore, its details are omitted for brevity. The count field 1523 records a read count value indicating the number of clock cycles that will be spent reading a previously issued instruction from the corresponding register. The count field 1523 can also be referred to as the read count field that stores the read count value. Similar to the write count value of the (write) count field 1531, the read count value counts down by one per clock cycle until the read count value reaches 0. Unless otherwise specified, the operation and functionality of the (read) count field 1523 are similar to those of the (write) count field 1531, therefore its details are omitted.

[0094] The read / write control unit 16 is configured to record the availability of the read and / or write ports of register group 14 at multiple clock cycles in the future for scheduling access to instructions to be issued. Upon issuing an instruction, the decoding / issuing unit 13 accesses the read / write control unit 16 to check the availability of the read and / or write ports of register group 14 based on the access time specified by the instruction. Specifically, the read / write control unit 16 selects an available read port in the future as the scheduled read time to read the source operand into functional unit 20, and selects an available write port in the future as the scheduled write time to write back the result data from functional unit 20. In an embodiment, the read / write control unit 16 may include a read shifter 161 and a write shifter 163 for scheduling the read and write ports as described above.

[0095] Figure 4 This is a diagram illustrating a read shifter 161 associated with a read port of a register set according to some embodiments of the present disclosure. Figure 5 This is a diagram illustrating a write shifter 163 associated with a write port of a register set according to some embodiments of the present disclosure. Each read port of the register set 14 may be associated with a read shifter 161, and each write port of the register set 14 may be associated with a write shifter 163. In embodiments, the read shifter 161 and the write shifter 163 may be included in a read / write control unit 16. However, the present disclosure is not limited thereto. In some other embodiments, the read shifter 161 and the write shifter 163 may be external to the read / write control unit 16, wherein the read / write control unit 16 may be communicatively coupled to the read shifter 161 and the write shifter 163, respectively, for controlling the use of the read and write ports of the register set 14.

[0096] refer to Figure 4 The read shifter 161 includes multiple entries 1610(1) to 1610(M), each of which may include a read validity field 1611 and an address field 1613, where M is an integer greater than 1. Each of entries 1610(1) to 1610(M) is associated with a future clock cycle and records the availability of the corresponding read port in said clock cycle. For example, entry 1610(1) indicates the availability of the read port in the first upcoming clock cycle (i.e., the immediate next clock cycle), and entry 1610(M) indicates the availability of the read port in the Mth future clock cycle. (See reference...) Figure 4The bottom entries from 1610(1) to 1610(M) are shifted out each clock cycle, and a new entry can be added as 1610(M). For example, the bottom entry 1610(1) will be shifted out in the next clock cycle immediately. In an embodiment, the read validity field (“rd”) 1611 records a read validity value indicating the availability of the read port in the corresponding clock cycle. For example, a non-zero value in the read validity field 1611(X) of the Xth entry indicates that the read port will be busy in the Xth clock cycle in the future, where X is greater than 1 and less than M. A zero value in the read validity field 1611(X) of the Xth entry indicates that the corresponding read port will be free to access in the Xth clock cycle in the future. The read address field (“rd_addr”) 1613 records the address of the register from which data is to be read. For example, entry 1610(1) indicates that the corresponding read port will be busy in the next clock cycle immediately for reading data from register 7 (i.e., address “r7”). In some alternative embodiments, each entry of the read shifter 161 contains more or fewer fields for recording other information.

[0097] Before issuing an instruction, the decoding / issuing unit 13 checks the read / write control unit 16 for the availability of the read ports of register group 14 at the read time of the instruction. For example, the read time is X clock cycles. The read / write control unit 16 checks the Xth entry of the read shifter 161 to determine if the read port is idle at the Xth future clock cycle. If the number of available read ports at the read time is greater than or equal to the number of read ports required by the instruction, then the decoding / issuing unit 13 can issue and schedule the instruction for execution at the Xth clock cycle (i.e., the scheduled read time). The read validity field 1611 and read address 1613 are set for each valid source register of the issued instruction. If the number of available read ports is less than the required number of read ports, then the decoding / issuing unit 13 can pause the instruction and recheck the read shifter in the next clock cycle. At the scheduled read time, the read shifter provides the read validity field 1611 and register address 1613 to the corresponding functional unit for reading data from register group 14. In one embodiment, shift register 161 may be implemented by rotating a read pointer, wherein the read pointer indicates the bottom of shift register 161 to read valid field 1611 and register address 1613 in each clock cycle, and the read pointer increments in each clock cycle.

[0098] refer to Figure 5The write shifter 163 (which may be referred to as the wait-time shifter) contains multiple entries 1630(1) to 1630(P), each of which contains a write-back valid field (“wr”) 1631, a write address field (“wr_addr”) 1633, and a functional unit field (“funit”) 1635, where P is an integer greater than 1. Each of entries 1630(1) to 1630(P) is associated with a future clock cycle and records the availability of the corresponding write port in said clock cycle. For example, entry 1630(1) indicates the availability of the write port in the first upcoming clock cycle (i.e., the immediately following clock cycle), and entry 1630(P) indicates the state of the write port in the Nth future clock cycle. Reference Figure 5 The bottom entries from 1630(1) to 1630(P) are shifted out in each clock cycle. For example, the bottom entry 1630(1) will be shifted out immediately in the next clock cycle, and a new entry can be added as 1630(P). In an embodiment, the write-back valid field (“wr”) 1631 records the write-back valid value, which indicates the availability of the write port at the clock cycle corresponding to the entry. For example, a non-zero value in the write-back valid field 1631(Y) of the Yth entry indicates that the write port will be busy in the Yth clock cycle in the future, where Y is greater than 1 and less than P. A zero value in the read value field 1631(Y) of the Yth entry indicates that the write port will be free to access in the Yth clock cycle in the future. The write address field (“wr_addr”) 1633 indicates the address of a register in register set 14, which the functional unit writes the resulting data back to. The function unit field (“funit”) 1635 specifies the function unit 20 or load / store unit 17 that writes the result data back to the write port. For example, the first entry 1630(1) of the write shifter 163 indicates that the write port will be busy in the first upcoming clock cycle, where alu 0 recorded in the function field 1635 will write the result data back to register 22 (“r22”) recorded in the write address field 1633.

[0099] Before issuing an instruction, the decoding / issuing unit 13 checks the availability of the write ports of register group 14 at the instruction's write time against the read / write control unit. For example, the write time is Y clock cycles. The read / write control unit 16 checks the Yth entry of the write shifter 163 to determine if the write port is idle at the future Yth clock cycle. If the number of available write ports at the write time is greater than or equal to the number of write ports required by the instruction, then the decoding / issuing unit 13 can issue and schedule the instruction for completion at the Yth clock cycle (i.e., the scheduled write time). The write-back valid field 1631, function unit 1635, and destination address 1633 are set for each valid destination register of the issued instruction. If the number of available write ports is less than the required number of write ports, then the decoding / issuing unit 13 can pause the instruction and recheck the write shifter in the next clock cycle. At the scheduled write time, the read / write port control retrieves the result data from functional unit 20, as recorded in functional unit field 1635, and writes the result data to the register specified in write address field 1633. In an embodiment, write shifter 163 can be implemented by rotating a read pointer, wherein the read pointer indicates the bottom of write shifter 163 to read the valid bit 1631, register address 1633, and functional unit 1635 in each clock cycle, and the read pointer increments in each clock cycle.

[0100] refer to Figure 1 Execution queue 19 is configured to hold issued instructions scheduled to be dispatched to functional unit 20. Functional unit 20 may include, but is not limited to, integer multiplication, integer division, arithmetic logic unit (ALU), floating-point unit (FPU), branch execution unit (BEU), and units that receive decoded instructions and perform operations. In an embodiment, each of execution queues 19 is coupled to or dedicated to one of the functional units 20. For example, execution queue 19A is coupled between decoding / issuing unit 13 and the corresponding functional unit 20A to queue and dispatch instructions that specify the operation that the corresponding functional unit 20A is designed to perform. Similarly, execution queue 19B is coupled between decoding / issuing unit 13 and the corresponding functional unit 20B, and execution queue 19C is coupled between decoding / issuing unit 13 and the corresponding functional unit 20C. In an embodiment, execution queues 19D and 19E are coupled between decoding / issuing unit 13 and loading / issuing unit 17 to handle load / store instructions. Execution queues 19D and 19E can also be referred to as the Tag-Execution Queue (TEQ) 19D and the Data-Execution Queue (DEQ) 19E, respectively.

[0101] Figure 6 This is a diagram illustrating an execution queue 19 according to some embodiments. EQ 19 may contain a plurality of entries 190(0) to 190(Q) for recording information about instructions issued from the decoding / issuing unit 13 in the order they will be sent to the functional unit 20, where Q is an integer greater than 0. In this example, each entry of the execution queue 19 contains... Figure 6 The valid fields 191, execution control data field 193, data field 195, and read count field 197 are respectively labeled as "v", "ex_ctrl", "data", and "rd_cnt". In other embodiments, there may be more or fewer fields recorded in each EQ, and data field 195 may have other data instead of immediate data.

[0102] The valid field 191 indicates whether an entry is valid (e.g., a valid entry is indicated by "1" and an invalid entry by "0"). The execution control data field 193 and data field 195 indicate the execution control information of functional unit 20 and the immediate data of instructions derived from instructions. The read count field 197 records the read count rd_cnt used to indicate the read time of an instruction. The read time stored in the read count field 197 counts down by one every clock cycle until the read count rd_cnt becomes zero. When the read time in the read count field 197 is 0, the execution queue 19 dispatches a valid instruction to functional unit 20.

[0103] Execution queue 19 may include or be coupled to an accumulation counter 199 for storing an accumulation count value acc_cnt, which counts down by one each clock cycle until the count value becomes zero. An accumulation count of zero indicates that EQ19 is empty. The accumulation count value acc_cnt of accumulation counter 199 indicates the time when the next instruction in decode / release unit 13 can be dispatched to functional unit 20 or load / store unit 17. The next instruction in decode / release unit 13 can be dispatched to functional unit 20 or load / store unit 17 according to the scheduled dispatch time based on the accumulation count value of accumulation counter 199. In some embodiments, the instruction read time is the accumulation count value, and the accumulation count value is set according to the sum of the current acc_cnt of the next instruction and the instruction throughput time (acc_cnt = acc_cnt + inst_xput_time). In some other embodiments, the read time is modified (where the read time is greater than the current cumulative count), and for the next instruction, the cumulative count value acc_cnt is set based on the sum of the instruction's read time (rd_cnt) and the instruction's throughput time (acc_cnt = rd_cnt + inst_xput_time). The read shifter 161 and write shifter 163 are designed to be synchronized with the execution queue 19, such that the execution queue 19 can dispatch instructions to the functional unit 20 or the load / store unit 17 while simultaneously reading source registers from register bank 14 according to the read shifter 161, and write the result data from the functional unit 20 or the load / store unit 17 back to register bank 14 according to the write shifter 163.

[0104] refer to Figure 1 The load / store unit 17 is coupled to the decode / publish unit 13 to handle load instructions and store instructions. In an embodiment, the decode / publish unit 13 publishes the load / store instruction as two micro-operations, including a tag micro-operation and a data micro-operation. The tag micro-operation is sent to the tag execution queue (TEQ) 19D, and the data micro-operation is sent to the data execution queue (DEQ) 19E. In some embodiments, the throughput time of the micro-operations of the load / store instruction is one cycle; TEQ 19D and DEQ 19E are independently processed load / store operations; and TEQ 19D must publish the tag operation before DEQ 19E publishes the data operation.

[0105] Data cache 18 is coupled to memory 30 and load / store unit 17 and configured to store data fetched from memory 30 and accessed by load / store unit 17 for load / store data. Data cache 18 contains a number of cache lines for consecutive data bytes from memory 30. The cache lines of data cache 18 are organized in a manner similar to direct mapping, fully associative mapping, or set-associative mapping of instruction cache 11, but do not require the same mapping as instruction cache 11.

[0106] Data cache 18 may include a tag array (TA) 22 and a data array (DA) 24 for storing portions of the addresses and data of frequently used data used by microprocessor 10, respectively. Similar to instruction cache 11, each tag in tag array 22 corresponds to a cache line in data array 24. When microprocessor 10 needs to execute a load / store instruction, it first checks the presence of load / store data in data cache 18 by comparing the load / store address with the tags stored in tag array 22. If the load / store address matches one of the tags in tag array (cache hit), the corresponding cache line in data array 24 is accessed for the load / store data. In some embodiments, a load instruction fetches data from a cache line in data array 24 to write to a destination register in register set 14, while a store instruction writes data from a source register in register set 14 to a cache line in data array 24. If a load / store address does not match any entry in tag array 22, it is a cache miss, and microprocessor 10 can access memory 30 to find the data. When a cache hit occurs, the execution latency of a load / store instruction is known (e.g., 2, 3, 6, or any number of clock cycles). When a cache miss occurs, the execution latency of a load / store instruction is 15 clock cycles or more. The execution latency of a load instruction is essentially unknown, depending on the cache hit and memory 30 latency.

[0107] Tag operations involve calculating an address using the address generation unit (AGU) 171 in load / store unit 17, and using the calculated address to access tag array 22 and translation look-aside buffer (TLB) (not shown) for virtual address to physical address translation. The address is calculated from the source register in register set 14 and from... Figure 6 Addition operation on the immediate data ("immdata") of data field 195. Figure 4The read shifter 161 is scheduled to read source registers from register bank 14 to match the dispatch of tag operations from TEQ 19D to AGU 171. In some embodiments, the virtual address and physical address are the same if a data TLB is not required. TEQ 19D dispatches tag operations to address generation unit (AGU) 171 of load / store unit 17 to compute load / store addresses. Load / store addresses are used to access the tag array (TA) 22 of data cache 18. Cache hit / miss and hit routes (set-associative mapping) are maintained for access by DEQ 19E, where data operations access cache lines of hit routes in DA 24. For load instructions, if DA 24 is accessed simultaneously with TA 22, then all routes of the set-associative mapping in DA 24 are read. In this embodiment, serial access to DA 24 after TA 22 allows reading a single route of DA 24, thus saving considerable power and reducing database conflicts.

[0108] For load instructions, when a cache hit occurs, data is retrieved from the destination register DA 24 of register set 14 via write control of the write shifter. For cache misses, the state of the destination register in scoreboard 15 is changed to unknown, and load data is retrieved from memory 30. Cache miss load data from memory 30 is written back to the destination register of register set 14 via a reserved write port. In one implementation, load data from memory 30 is written to a data miss buffer (not shown), which then writes back to the destination register of register set 14 and ultimately writes the cache line data to data cache 24.

[0109] For store instructions, when a cache hit occurs, the store data is scheduled to be read immediately from register set 14 and written to DA 24 by the read shifter. For cache misses, the store data is sent to a store miss buffer (not shown) in load / store unit 17. During normal execution of a store instruction, the source register for the tag address and the source register for the store data can be read simultaneously from register set 14; in this case, a store buffer is needed to hold the store data until it is written to DA 24. In this invention, the time to write the store data to DA 24 (assuming a cache hit) is known; therefore, the read port control is scheduled to read the source register for the store data from register set 14 "just-in-time" and write it to DA 24, thus eliminating the need for a store buffer. For cache misses, the source register for the store data is not read from register set 14 until the store data is ready to be written to the data cache, which is a "just-in-time" read of the source register.

[0110] For cache misses, load / store unit 17 may allow multiple pending cache miss requests to memory 30. Multiple pending miss requests are maintained in a miss request queue (not shown) in load / store unit 17. A new cache line is fetched from memory 30 into a miss data buffer (not shown) in data cache 18. The miss data buffer may consist of multiple cache lines. Additionally, replacement cache lines in data cache 18 may be dirty, where dirty cache lines must be written back to memory 30 before new cache lines from memory 30 can be written to data cache 18. Dirty cache lines are fetched from data cache 18 into an evict buffer before being evicted from memory 30. The evict buffer may be implemented as part of the miss data buffer. The evict buffer, the miss request queue, and the miss data buffer must be checked by subsequent load / store instructions used for data matching and forwarding.

[0111] Load / store instructions may have exact exceptions, where all subsequent instructions must be discarded from the execution pipeline. Similar to branch instructions, all subsequent instructions following a load / store instruction cannot be written back to register set 14 until the execution of the load / store instruction has finished. Load / store instructions with cache misses may have data error exceptions, which are inaccurate exceptions and are taken by preventing the decode / publish unit 13 from publishing any further instructions and after all instructions in the execution pipeline have completed. Interrupts are similar to inaccurate exceptions, where interruption is taken by preventing the decode / publish unit 13 from publishing any further instructions and after all instructions in the execution pipeline have completed.

[0112] Figure 7A This diagram illustrates execution blocks 100B and 100C according to some embodiments. For simplicity, execution block 100B is also referred to as vector execution block 100B dedicated to processing vector instructions; and execution block 100C is also referred to as FP execution block 100C dedicated to processing FP instructions. However, each of execution blocks 100B and 100C can be configured to process any other type of instruction. Each of execution blocks 100B and 100C may contain the same elements as execution block 100A. For example, each of execution blocks 100B and 100C may include a decoding / issuing unit, a scoring board, a read / write control unit, a register set, an execution queue, and a functional unit. Execution blocks 100B and 100C are also referred to as a first type issuing unit and a second type issuing unit.

[0113] In some embodiments, different types of instructions can be decoded in parallel by decoding / publishing units 13b and 13c in execution block 100B and execution block 100C. In the parallel decoding of instructions, each of decoding / publishing units 13b and 13c can verify an instruction in one of execution blocks 100B and execution block 100C, and an instruction can only be valid in one of execution blocks 100B and execution block 100C at a time.

[0114] In some embodiments, each of the decoding / publishing units 13b and 13c in execution blocks 100B and 100C checks and resolves all possible conflicts between different types of instructions before publishing the instruction. The same mechanism as in execution block 100A can be used to resolve data dependencies and control the read / write ports in execution blocks 100B and 100C. Elements referred to by specific letter reference numerals herein will be collectively referred to by separate reference numerals. For example, unless otherwise specified, execution queues 291A to 291C will be collectively referred to as execution queue 291 of execution block 100B, and execution queues 292A to 292C will be collectively referred to as execution queue 292 of execution block 100C. Therefore, a detailed description of decoding / publishing units 13b and 13c is omitted below.

[0115] The register groups 14b and 14c, scoreboards 15b and 15c, read / write control units 16b and 16c, execution queues 291 and 292, and functional units 201 and 202 in execution blocks 100B and 100C may be similar to the register group 14, scoreboard 15, read / write control unit 16, execution queue 19, and functional unit 20 in execution block 100A. Register group 14, scoreboard 15, read / write control unit 16, execution queue 19, and function unit 20 in execution block 100A are used for scalar integer instructions, while register group 14b, scoreboard 15b, read / write control unit 16b, execution queue 291, and function unit 201 in execution block 100B are dedicated to vector instructions, and register group 14c, scoreboard 15c, read / write control unit 16c, execution queue 292, and function unit 202 in execution block 100C are dedicated to FP instructions. The structure and functionality of these elements in execution blocks 100B and 100C can be inferred from the corresponding elements in execution block 100A; therefore, detailed descriptions of execution blocks 100B and 100C are omitted below.

[0116] In some embodiments, the microprocessor 10 may further include a multiplexer (MUX) 300 and a shared functional unit 20s, wherein the shared functional unit 20s is shared by execution blocks 100B and 100C. The shared functional unit 20s can execute vector instructions dispatched from execution block 100B and FP instructions dispatched from execution block 100C. The shared functional unit 20s can receive vector instructions and FP instructions from the multiplexer 300 and execute the received instructions. In some embodiments, a vector execution queue 291C and an FP execution queue 292C are constructed such that only one of the execution queues 291C or 292C can send a valid instruction to the shared functional unit 20s at a time via the multiplexer 300. In other words, the multiplexer 300 can provide only one of the vector instructions or FP instructions to the shared functional unit 20s at a time, and the shared functional unit 20s executes only one of the vector instructions or FP instructions at a time. In some embodiments, the shared functional unit 20s is coupled to the register group 14b and register group 14c of the execution block 100B and the execution block 100C via multiplexing 300 and read bus 31b and read bus 31c, and the result data from the shared functional unit 20s is written back to the register group 14b or register group 14c via the result bus 32b and result bus 32c.

[0117] In some embodiments, the shared functional unit 20s may include multiple execution units 200A to 200D configured to execute multiple elements of vector instructions. Vector instructions differ from scalar-integer instructions and FP instructions in two ways: (1) vector instructions operate on many elements, while scalar-integer instructions or FP instructions operate on a single element; (2) the many elements of a vector instruction can be grouped into smaller sets of elements so that they can be executed sequentially as micro-operations. For example, a vector instruction may be programmed to execute on 32 elements, which can be executed in hardware as eight micro-operations of four elements; where each element is 32 bits of data. Figure 7A Execution units 200A to 200D perform the execution of four elements. In some embodiments, some functional units of the shared functional unit 20s are shared by both VEQ 291C and FPEQ 292C; and some functional units of the shared functional unit 20s are dedicated to executing multiple elements of vector instructions. In an example, functional unit 200D is shared for executing both vector instructions and FP instructions; and functional units 200A to 200C are dedicated to executing some elements of vector instructions. The number of shared execution units in the shared functional unit 20s is not limited in this disclosure.

[0118] In one embodiment, multiplexing 300 is coupled to VEQ 291C of execution block 100B and FPEQ 292C of execution block 100C, and configured to select vector instructions from VEQ 291C or FP instructions from FPEQ 292C and dispatch them to shared functional unit 20s for execution. In an alternative embodiment, execution block 100B and execution block 100C include multiple VEQ 291s and multiple FPEQ 292s, and multiplexing 300 is coupled to the multiple VEQ 291s and multiple FPEQ 292s to select valid instructions from VEQ 291s and FPEQ 292s and provide them to shared functional unit 20s for execution. In some embodiments, VEQ 291C and FPEQ 292C may provide a valid indication of a valid instruction (i.e., a vector instruction or an FP instruction) to multiplexing 300. The multiplexer 300 can select either a vector instruction or an FP instruction based on valid indications from the VEQ 291C and FPEQ 292C. In some embodiments, only one of the vector instruction and the FP instruction is valid at a time, so only one of the vector instruction or the FP instruction is sent to the shared functional unit for execution.

[0119] In some embodiments, multiplexing 300 is coupled to register sets 14b and 14c of execution blocks 100B and 100C via read buses 31b and 31c to receive operand data associated with vector instructions and FP instructions. Operand data associated with vector instructions or FP instructions can be sent to shared functional unit 20s via multiplexing 300, as illustrated by the connections from register set read buses 31b and 31c to multiplexing 300.

[0120] In some embodiments, operand data from register sets 14b and 14c is sent to the shared functional unit 20s synchronously with VEQ 291C and FPEQ 292C via multiplexing 300. For example, VEQ 291C and FPEQ 292C can dispatch instructions to the shared functional unit 20s via multiplexing 300 while simultaneously reading operand data from register sets 14b and 14c. In some embodiments, read / write control units 16b and 16c schedule the read and write times of instructions such that operand data from register sets 14b and 14c is sent to the shared functional unit 20s synchronously with the operations of VEQ 291C and FPEQ 292C. Because only one of VEQ 291C and FPEQ 292C is allowed to send a valid instruction to the shared functional unit 20s at a time, the choice of multiplexing 300 via VEQ 291C or FPEQ 292C is mutually exclusive.

[0121] In some embodiments, execution block 100B includes functional units for integer, permutation, masking, and floating-point operations, and execution block 100C includes functional units for floating-point operations only. In some embodiments, the floating-point functional units include an FP multiply-accumulate (FP MACC) functional unit, an FP divide (FP DIV) functional unit, and an FP miscellaneous (FP MISC) functional unit, wherein the FP MACC is configured to execute FP multiplication instructions, FP addition / subtraction instructions, and FP multiply-accumulate instructions; the FP DIV functional unit is configured to execute FP division instructions; and the FP MISC functional unit is configured to execute other instructions such as integer FP conversion, FP comparison, FP minimum, and FP maximum instructions. In some embodiments, the FP MACC functional unit is more critical than other FP functional units; therefore, a dedicated FP MACC functional unit is designed for each of execution blocks 100B and 100C, and other FP functional units are shared by both execution blocks 100B and 100C. In this example, the FP MACC functional unit is dedicated to executing the FP instructions of execution block 100C, and the vector FP MACC functional unit is dedicated to executing the vector FP instructions of execution block 100B. In some alternative embodiments, execution block 100B has multiple vector FPMACC functional units, one of which is shared with execution block 100C while another vector FP MACC functional unit is dedicated to execution block 100B.

[0122] Figure 7B A diagram showing execution block 100B and execution block 100C according to some embodiments is provided. Figure 7A The diagram shown is Figure 7B The difference between the diagrams shown is that... Figure 7BThe diagram shows a shared execution queue 19s and multiplexing 330 instead of multiplexing 300. The shared execution queue 19s is coupled to the decoding / distribution units 13b and 13c of execution blocks 100B and 100C, and is configured to receive vector instructions dispatched by decoding / distribution unit 13b or FP instructions dispatched by decoding / distribution unit 13c. In some embodiments, decoding / distribution units 13b and 13c are constructed such that only one of them can send a valid instruction to the shared execution queue 19s. In other words, only one of the vector instructions or FP instructions is written to one of a plurality of entries in the shared execution queue 19s at a time. In another embodiment, if the instructions from execution blocks 100B and 100C are directed to shared functional unit 20s, then decoding / publishing units 13b and 13c have a stopping mechanism that can stop one of them based on the sequence of instructions. In another embodiment, vector instructions and FP instructions use instruction order priority to allow either decoding / publishing unit 13b or decoding / publishing unit 13c to dispatch only one instruction to the shared execution queue 19s at a time. However, in another embodiment, decoding / publishing units 13b and 13c can dispatch both vector instructions and FP instructions to the shared execution queue 19s simultaneously, and write the instructions into two entries according to the instruction order in the shared execution queue 19s. Register operand data from register sets 14b and 14c are synchronized with the shared execution queue 19s via read / write control units 16b and 16c, respectively, to be sent to multiplexer 330 for execution by shared function unit 20s. In other words, multiplexer 330 selects register operand data from register set 14b synchronously with vector instructions to be issued by shared execution queue 19s, or selects register operand data from register set 14c synchronously with FP instructions to be issued by shared execution queue 19s. For example, shared execution queue 19s can dispatch instructions to shared function unit 20s while simultaneously reading operand data from register set 14b or register set 14c. Read / write control units 16b and 16c can schedule the read and write times of instructions so that operand data from register sets 14b and 14c is sent to shared function unit 20s synchronously with the operations of shared execution queue 19s.

[0123] The shared execution queue 19s can contain, for example, Figure 6 The multiple fields of EQ 19 shown are illustrated. Some embodiments of this disclosure may use a comparison... Figure 6The fields shown are more, fewer, or different in the shared execution queue 19s. In an embodiment, the shared execution queue 19s has a tag bit field (not shown) that records the tag bit of each entry in the shared execution queue 19s to indicate the instruction type (e.g., vector or FP) of the instruction recorded in each entry of the shared execution queue 19s. The tag bit recorded in the shared execution queue 19s can be used to select operand data from register sets 14b and 14c of execution block 100B or execution block 100C. For example, when the tag bit in an entry of the shared execution queue 19s indicates that the recorded instruction is a vector instruction, operand data associated with the vector instruction is selected from register set 14b of execution block 100B. Vector instructions and FP instructions stored in the shared execution queue 19s can be dispatched to the shared functional unit 20s in a dispatch order. The read count field 197 recorded in the functional unit 20s (i.e., Figure 6 The read count value in the read count field 197 of the execution queue 10 shown determines the dispatch order of the shared functional unit 20s.

[0124] Figure 8 A diagram of a VEQ 291 according to some embodiments is shown. The VEQ 291 may contain a plurality of entries 190(0) to 190(Q), wherein each entry of the VEQ 291 is configured to record information about a vector instruction. In some embodiments, each entry of the VEQ 291 contains information that can be used with... Figure 6 The example shows multiple fields that are the same or different in EQ 19. For example, Figure 8 The valid field 191, execution control data field 193, data field 195, and read count field 197 shown in VEQ 291 are... Figure 6 The corresponding fields shown in EQ 19 are the same. Additionally, Figure 8 The cumulative throughput counter 199 shown is Figure 6 The cumulative throughput counter 199 shown is the same. (Omitted regarding...) Figure 8 VEQ 291 and Figure 6 A detailed description of the same element as execution queue 19 in the [section / section].

[0125] VEQ 291 may also include a micro-operation count field 192 and a throughput count field (xput_cnt) 194, wherein the micro-operation count field 192 represents multiple micro-operations in a vector instruction. For example, the vector instructions in entries 190(0) and 190(2) have 4 micro-operations; and the vector instruction in entry 190(1) has 8 micro-operations. The throughput count field 194 is configured to represent the throughput time (e.g., multiple clock cycles) of each micro-operation in the vector instruction.

[0126] In some embodiments, VEQ 291 includes or is coupled to micro-operation counter 303 for tracking the number of micro-operations performed. Micro-operation counter 303 may receive the value of micro-operation count field 192 of a first entry 190(0) and decrement the value by one for each micro-operation assigned to functional unit 201 or functional unit 20s. In some embodiments, micro-operation counter 303 decrements the value of micro-operation count field 192 to 0 before invalidating the corresponding entry by resetting valid field 191. In an example, the vector instruction in the first entry 190(0) has four micro-operations with a throughput time of one clock cycle. Therefore, the value of micro-operation count field 192 decrements by one every clock cycle. The throughput count field 194 of micro-operations with a throughput wait time of one clock cycle is set to "0". The throughput time in throughput count field 194 is always one less than the actual throughput time.

[0127] In some embodiments, VEQ 291 further includes a throughput counter 305 for tracking the throughput time of micro-operations assigned to functional unit 201 or functional unit 20s. The throughput counter 305 receives the value of the throughput count field 194 corresponding to the first micro-operation from a first entry 190(0), and decrements the value by one each clock cycle until the value of the throughput count field 194 corresponding to the first micro-operation reaches 0. When the value of the throughput count field 194 corresponding to the first micro-operation reaches 0, the throughput counter 305 is reloaded with the value of the throughput count field 194 corresponding to the next micro-operation, and if the micro-operation count field 192 is greater than 1, the down-counting process is repeated. In some embodiments, the valid field 191 of the VEQ 291 entries remains valid until the values ​​of both the micro-operation counter 303 and the throughput counter 305 reach 0.

[0128] In some embodiments, the FPEQ 292 of the execution block 100C may have the same characteristics as... Figure 6 The execution queue 19 of execution block 100A shown has a substantially the same structure. Therefore, a detailed description of FPEQ 292 for execution block 100C is omitted below.

[0129] refer to Figure 9 The process for issuing different types of instructions in a microprocessor is illustrated according to some embodiments. Figure 9The microprocessor shown may include a vector cumulative throughput counter 199b and an FP cumulative throughput counter 199c, wherein the vector cumulative throughput counter 199b is used to track the cumulative throughput count of valid entries in VEQ 291 and VEQ 291C, and the FP cumulative throughput counter 199c is used to track the cumulative throughput count of valid entries in FPEQ 292 and FPEQ 292C.

[0130] Figure 9 The microprocessor shown also includes multiplexed MUX 302_1 and multiplexed MUX 302_2 coupled to the vector cumulative throughput counter 199b and the FP cumulative throughput counter 199c. Multiplexed MUX 302_1 is configured to select either the vector cumulative throughput counter 199b or the FP cumulative throughput counter 199c as... Figure 8 The read time (or read count rd_cnt) in field 197 is used to post vector instructions to the VEQ 291C. The multiplexed MUX 302_2 is configured to select either the vector cumulative throughput counter 199b or the FP cumulative throughput counter 199c as... Figure 8 The count rd_cnt in field 197 is read to issue scalar FP instructions to FPEQ 292C. In some embodiments, multiplexed MUX 302_1 and multiplexed MUX 302_2 are selected based on the vector active bit v_active and the FP active bit f_active. For example, multiplexed MUX 302_1 and multiplexed MUX 302_2 select vector cumulative throughput counter 199b to issue instructions when the vector active bit v_active is set and the FP active bit f_active is cleared; and multiplexed MUX 302_1 and multiplexed MUX 302_2 select FP cumulative throughput counter 199c to issue instructions when the vector active bit v_active is cleared and the FP active bit f_active is set. In some embodiments, the active bit is set by the type of the last instruction to be issued. For example, when the last instruction to be issued is a vector instruction, the active bit v_active is set; and when the last instruction to be issued is an FP instruction, the active bit f_active is set. In another embodiment, if both the vector instruction and the FP instruction are valid simultaneously and the vector instruction has a higher priority than the FP instruction, then the read time of the vector instruction follows the procedure described above, while the read time of the FP instruction is the sum of the throughput time and read time of the vector instruction. The vector instruction and the FP instruction can be simultaneously issued to execution queue 291C and execution queue 292C, respectively. In some embodiments, the vector cumulative throughput counter 199b, the multiplexing MUX 302_1, and the VEQ 291 are included in... Figure 1The execution block 100B shown is included; and the FP cumulative throughput counter 199c, multiplexed MUX 302_2, and FPEQ 292C are contained within it. Figure 1 In the execution block 100C shown.

[0131] In an embodiment, Figure 7B The shared execution queue 19s contains a single cumulative throughput counter (not shown) that tracks the cumulative throughput count of valid entries in the shared execution queue 19s. Reference Figure 7B and Figure 9 A single cumulative throughput counter can be represented as Figure 9 The cumulative throughput counters 199b and 199c are shown as a combination. In this embodiment, a single cumulative throughput counter is updated according to the instruction order of the instructions recorded in the shared execution queue 19s. For example, a single cumulative throughput counter may be updated according to the last instruction indicated by the instruction order of the shared execution queue 19s. As mentioned above, if both vector instructions and FP instructions are simultaneously issued to... Figure 7B If the shared execution queue 19s is used, then vector instructions and FP instructions are recorded in two entries according to the instruction order of the shared execution queue 19s. The instruction priorities of vector instructions and FP instructions determine the order in which they are issued to the shared execution queue 19s. The value of a single cumulative throughput counter is used as the read time (or...) of the instructions recorded in the shared execution queue 19s. Figure 6 The read count (rd_cnt) in field 197.

[0132] Figure 10 This diagram illustrates a flowchart, according to some embodiments, for issuing instructions to a shared functional unit based on the active bits v_active and f_active. It assumes a valid instruction is sent... Figure 1 The decoding / publishing units in execution blocks 100B and 100C. Execution blocks 100B and 100C are designed such that only one of them decodes the valid instruction as mentioned in block 501. In block 501, if the valid instruction inst is determined to be the vector instruction v_inst, then execution block 100B publishes the valid instruction. Block 502 determines whether the FP active bit f_active is set or cleared. If the FP active bit f_active is cleared (f_active = 0), then in block 503b, the vector cumulative throughput counter 199b of execution block 100B publishes the vector instruction v_inst to the vector execution queue (i.e., Figure 8 VEQ 291), and will correspond to the read count value of the issued instruction (i.e., Figure 8The read count (rd_cnt) in field 197 is set to the value of the vector cumulative throughput counter (v_acc_cnt) in block 503c. Otherwise, if the FP active bit f_active is set (f_active = 1), then in block 503c, the FP cumulative throughput counter 199c in block 100C is used to post the vector instruction v_inst to the vector execution queue (i.e., Figure 8 VEQ 291), and will correspond to the read count value of the issued instruction (i.e., Figure 8 The read count (rd_cnt) in field 197 is set to the value of the FP cumulative throughput counter 199c (f_acc_cnt). It should be further noted that the vector instruction v_inst can be published to the vector execution queue (i.e., ...) as long as the read time of the vector instruction v_inst is equal to or greater than the cumulative time selected by block 502 (i.e., the value of the vector cumulative throughput counter 199b or the FP cumulative throughput counter 199c). Figure 8 VEQ 291), and set the selected cumulative time to the vector instruction read time (i.e., Figure 8 The sum of the read count (rd_cnt value in field 197) and the throughput time of the issued vector instruction. Due to read / write port conflicts or data dependencies in the vector source register and / or destination register, the read time of the vector instruction may be greater than the selected cumulative time.

[0133] Returning to block 501, if the valid instruction `inst` is determined to be the FP instruction `f_inst`, then block 100C is executed to issue the valid instruction. Block 510 determines whether the vector activity bit `v_active` is set or cleared. If the vector activity bit `v_active` is cleared (`v_active = 0`), then in block 511c, the FP cumulative throughput counter 199c of block 100C is executed to issue the FP instruction `f_inst` to the FP execution queue (i.e., Figure 8 FPEQ 291 and Figure 6 EQ 19 in the code, and the corresponding read count value of the issued instruction (i.e., Figure 6 The read count (rd_cnt) in field 197 is the value of the FP cumulative throughput counter 199c (f_acc_cnt). Otherwise, if the vector active bit v_active is set (v_active = 1), then in block 511b, the vector cumulative throughput counter 199b of block 100B is used to publish the FP instruction f_inst to the FP execution queue (i.e., Figure 8 FPEQ 291 or Figure 6 EQ 19), and will correspond to the read count value of the issued instruction (i.e., Figure 6The read count (rd_cnt) in field 197 is set to the value of the vector cumulative throughput counter (v_acc_cnt) in 199b. It should be further noted that the FP instruction f_inst can be published to the FP execution queue (i.e., ...) as long as the read time of the FP instruction f_inst is equal to or greater than the cumulative time selected in block 510 (i.e., the value of the vector cumulative throughput counter 199b or the FP cumulative throughput counter 199c). Figure 8 In FPEQ 291), the selected FP cumulative time is set to the FP instruction read time (i.e., Figure 6 The sum of the read count (rd_cnt value in field 197) and the throughput time of the issued FP instruction. Due to read / write port conflicts or data dependencies in the FP source register and / or destination register, the read time of the FP instruction may be greater than the selected cumulative time.

[0134] According to one embodiment, a microprocessor is disclosed comprising a shared functional unit, a first execution queue, a second execution queue, a first type dispatch unit, and a second type dispatch unit. The first execution queue contains multiple entries, each entry of which records a first type instruction. Each entry of the first execution queue contains a first count value corresponding to the first type instruction, and the first count value is decremented until it reaches 0. When the first count value corresponding to the first type instruction reaches 0, the first execution queue dispatches the first type instruction to the shared functional unit. The second execution queue contains multiple entries, each entry of which records a second type instruction. Each entry of the second execution queue contains a second count value corresponding to the second type instruction, and the second count value is decremented until it reaches 0. When the second count value corresponding to the second type instruction reaches 0, the second execution queue dispatches the second type instruction to the shared functional unit. The shared functional unit executes the first type instruction and the second type instruction. Reading and writing data from the register set are preset to be synchronized for the exact future execution time of the first type instruction or the second type instruction in the shared functional unit. Similar to the prior art, dynamic conflict resolution, dynamic data dependency resolution, and dynamic read / write port resolution are not required. Dynamic parsing is the most power-intensive operation in microprocessor design. The microprocessor is configured to dispatch first-type instructions from a first execution queue and second-type instructions from a second execution queue to shared functional units. A first-type issuing unit issues first-type instructions to the first execution queue, schedules the read and write times of the first-type instructions, and sets a first count value recorded in each entry of the first execution queue. A second-type issuing unit issues second-type instructions to the second execution queue, schedules the read and write times of the second-type instructions, and sets a second count value recorded in each entry of the second execution queue.

[0135] According to one of the embodiments, a method applicable to a first execution queue, a second execution queue, a shared functional unit, a first type of publishing unit, and a second type of publishing unit is described. The method includes the following steps: a first type issuing unit issues a first type instruction to a first execution queue; the first type issuing unit schedules the read and write times of the first type instruction; the first type issuing unit sets a first count value in each entry of the first execution queue, wherein the first count value is decremented until it reaches 0; in response to determining that the first count value in an entry of the first execution queue reaches 0, the first execution queue dispatches the first type instruction in the entry of the first execution queue to a shared function unit; a second type issuing unit issues a second type instruction to a second execution queue; the second type issuing unit schedules the read and write times of the second type instruction; the second type issuing unit sets a second count value in each entry of the second execution queue, wherein the second count value is decremented until it reaches 0; in response to determining that the second count value in an entry of the second execution queue reaches 0, the second execution queue dispatches the second type instruction in the entry of the second execution queue to a shared function unit; and the shared function unit executes the first type instruction and the second type instruction. First-type instructions from the first execution queue and second-type instructions from the second execution queue are mutually dispatched to shared functional units.

[0136] According to one embodiment, a data processing system including a memory and a microprocessor is provided. The memory is configured to store first type instructions and second type instructions. The microprocessor includes a shared functional unit, a first execution queue, a second execution queue, a first type dispatch unit, and a second type dispatch unit. The first execution queue contains multiple entries, wherein each entry of the first execution queue records a first type instruction, and each entry of the first execution queue contains a first count value corresponding to the first type instruction, the first count value being decremented until it reaches 0. When the first count value corresponding to the first type instruction reaches 0, the first execution queue dispatches the first type instruction to the shared functional unit. The second execution queue contains multiple entries, wherein each entry of the second execution queue records a second type instruction, and each entry of the second execution queue contains a second count value corresponding to the second type instruction, the second count value being decremented until it reaches 0. When the second count value corresponding to the second type instruction reaches 0, the second execution queue dispatches the second type instruction to the shared functional unit. The shared functional unit executes the first type instructions and the second type instructions, wherein the first type instructions from the first execution queue and the second type instructions from the second execution queue are mutually dispatched to the shared functional unit. The first type issuing unit issues first type instructions to the first execution queue, schedules the read and write times of the first type instructions, and sets a first count value recorded in each entry of the first execution queue. The second type issuing unit issues second type instructions to the second execution queue, schedules the read and write times of the second type instructions, and sets a second count value recorded in each entry of the second execution queue.

[0137] The features of several embodiments have been outlined above to enable those skilled in the art to better understand the following detailed description. Those skilled in the art will understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A microprocessor, comprising: A first execution queue includes multiple entries, wherein each entry of the first execution queue records a first type of instruction, each entry of the first execution queue includes a first count value corresponding to the first type of instruction, the first count value is decremented until the first count value reaches 0, and when the first count value corresponding to the first type of instruction reaches 0, the first execution queue dispatches the first type of instruction to a shared functional unit. The second execution queue includes multiple entries, wherein each entry of the second execution queue records a second type of instruction, each entry of the second execution queue includes a second count value corresponding to the second type of instruction, the second count value is decremented until the second count value reaches 0, and when the second count value corresponding to the second type of instruction reaches 0, the second execution queue dispatches the second type of instruction to the shared functional unit. A shared functional unit executes a first type of instruction and a second type of instruction, wherein the first type of instruction from the first execution queue and the second type of instruction from the second execution queue are mutually exclusively dispatched to the shared functional unit; The first type of publishing unit publishes the first type of instruction to the first execution queue, schedules the reading time and writing time of the first type of instruction, and sets the first count value recorded in each entry of the first execution queue. as well as The second type of publishing unit publishes the second type of instruction to the second execution queue, schedules the reading and writing times of the second type of instruction, and sets the second count value recorded in each entry of the second execution queue.

2. The microprocessor according to claim 1, wherein The first count value in each entry of the first execution queue represents the read time of the first type of instruction. The first count value in each entry of the first execution queue is decremented by one every clock cycle until the first count value reaches 0. When the first count value corresponding to the first type of instruction reaches 0, the first type of instruction recorded in the first execution queue is dispatched to the shared functional unit.

3. The microprocessor according to claim 1, wherein The first type of publishing unit includes a first type of decoding / publishing unit, a first type of register group, a first type of scoring board, a first type of read / write control unit for the first type of register group, and a first execution queue. The second type of publishing unit includes a second type of decoding / publishing unit, a second type of register group, a second type of scoreboard, a second type of read / write control unit for the second type of register group, and a second execution queue.

4. The microprocessor according to claim 3, wherein The first type of issuing unit and the execution of the first type of instruction in the shared function unit synchronously schedule the read time of the first type of instruction to read the operand data of the first type of instruction from the first type of register group, and schedule the write time of the first type of instruction to write the result data from the shared function unit to the first type of register. The second type of issuing unit synchronously schedules the read time of the second type of instruction with the execution of the second type of instruction in the shared function unit to read the operand data of the second type of instruction from the second type of register group, and schedules the write time of the second type of instruction to write the result data from the shared function unit to the second type of register. The first type of issuing unit parses the data dependencies and resource conflicts of the first type of instruction to set the first count value recorded in each entry of the first execution queue, and The second type of issuing unit parses the data dependencies and resource conflicts of the second type of instruction to set the second count value in each entry recorded in the second execution queue.

5. The microprocessor according to claim 3, further comprising: A first multiplexing, coupled to the first execution queue, the second execution queue, and the shared functional unit, is configured to mutually exclusively dispatch first-type instructions from the first execution queue or second-type instructions from the second execution queue to the shared functional unit, wherein... The first multiplexing is further coupled to the first type of register group and the second type of register group through the first read bus and the second read bus respectively, and the first multiplexing mutually excludes operand data from the first type of register group or operand data from the second type of register group from the shared functional unit.

6. The microprocessor according to claim 5, wherein The first execution queue also includes a first cumulative throughput counter that decrements by one every clock cycle. The first cumulative throughput counter indicates in which clock cycle the first type of issuing unit is allowed to issue the next first type of instruction to the first execution queue. The second execution queue also includes a second cumulative throughput counter that decrements by one every clock cycle. The second cumulative throughput counter indicates in which clock cycle the second type of issuing unit is allowed to issue the next second type instruction to the second execution queue.

7. The microprocessor according to claim 6, wherein The first type of publishing unit, based on the first active bit of the first execution queue and the second active bit of the second execution queue, uses the first cumulative throughput counter or the second cumulative throughput counter to publish the first type of instruction to the first execution queue as the read time of the published first type of instruction; and The second type of publishing unit, based on the first active bit of the first execution queue and the second active bit of the second execution queue, uses the first cumulative throughput counter or the second cumulative throughput counter to publish the second type of instruction to the second execution queue as the read time of the published second type of instruction, wherein... When the first type of issuing unit issues the first type of instruction, the first active bit is set. When the second type of issuing unit issues the second type of instruction, the first active bit is cleared. When the first cumulative throughput counter is zero, the first active bit is cleared. When the second type of issuing unit issues the second type of instruction, the second active bit is set. When the first type of issuing unit issues the first type of instruction, the second active bit is cleared, and When the second cumulative throughput counter is zero, the second active bit is cleared.

8. The microprocessor according to claim 3, further comprising: A shared execution queue is used by the first type of publishing unit and the second type of publishing unit to receive the first type of instruction and the second type of instruction, record the first type of instruction and the second type of instruction in the entries of the shared execution queue, and sequentially dispatch the first type of instruction and the second type of instruction recorded in the entries of the shared execution queue. as well as The second multiplexing is coupled to the first type of register group and the second type of register group via a first read bus and a second read bus, respectively. It receives operand data of the first type of instruction via the first read bus or operand data of the second type of instruction via the second read bus, and dispatches the operand data of the first type of instruction and the operand data of the second type of instruction to the shared functional unit in a mutually exclusive manner. The second multiplexing and the shared execution queue synchronously dispatch the operand data of the first type of instruction and the operand data of the second type of instruction for the dispatch of the first type of instruction and the second type of instruction.

9. The microprocessor according to claim 8, wherein The shared execution queue includes a cumulative throughput counter that tracks the cumulative throughput count of valid entries in the shared execution queue. The cumulative throughput counter is updated based on the last instruction published to the shared execution queue from either the first type of publishing unit or the second type of publishing unit. The cumulative throughput counter decrements by one every clock cycle, and the cumulative throughput counter indicates in which clock cycle the issuing unit is allowed to issue the next instruction to the shared execution queue.

10. The microprocessor according to claim 1, further comprising: A non-shared functional unit has the same functionality as the shared functional unit, wherein the non-shared functional unit is dedicated to executing the first type of instruction or the second type of instruction.

11. The microprocessor of claim 1, wherein the shared functional unit comprises: The first execution unit is shared for executing the first type of instructions and the second type of instructions; as well as The second execution unit is dedicated to executing either the first type of instruction or the second type of instruction.

12. A method suitable for a microprocessor, the microprocessor comprising a first execution queue, a second execution queue, a shared functional unit, a first type release unit, and a second type release unit, the method comprising: The first type of instruction is published to the first execution queue by the first type of publishing unit; The first type of issuing unit schedules the read and write times of the first type of instruction; The first type of publishing unit sets a first count value in each entry of the first execution queue, wherein the first count value is decremented until the first count value reaches 0; In response to determining that the first count value in the entry contained in the first execution queue reaches 0, the first execution queue dispatches the first type of instruction in the entry recorded in the first execution queue to the shared functional unit; The second type of instruction is issued to the second execution queue by the second type of issuing unit; The second type of issuing unit schedules the read and write times of the second type of instructions; The second type of publishing unit sets a second count value in each entry of the second execution queue, wherein the second count value is decremented until the second count value reaches 0; In response to determining that the second count value in the entry contained in the second execution queue reaches 0, the second type of instruction recorded in the entry of the second execution queue is dispatched by the second execution queue to the shared functional unit; as well as The shared functional unit executes the first type of instruction and the second type of instruction, wherein the first type of instruction from the first execution queue and the second type of instruction from the second execution queue are mutually exclusively dispatched to the shared functional unit.

13. The method of claim 12, wherein The first count value in each of the first execution queues represents the read time of the first type of instruction. The first count value in each entry of the first execution queue is decremented by one every clock cycle until the first count value reaches 0. When the first count value corresponding to the first type of instruction reaches 0, the first type of instruction recorded in the first execution queue is dispatched to the shared functional unit.

14. The method of claim 12, wherein The first type of publishing unit includes a first type of decoding / publishing unit, a first type of register group, a first type of scoring board, a first type of read / write control unit for the first type of register group, and a first execution queue. The second type of publishing unit includes a second type of decoding / publishing unit, a second type of register group, a second type of scoreboard, a second type of read / write control unit for the second type of register group, and a second execution queue.

15. The method of claim 14, wherein The first type of issuing unit and the execution of the first type of instruction in the shared function unit synchronously schedule the read time of the first type of instruction to read the operand data of the first type of instruction from the first type of register group, and schedule the write time of the first type of instruction to write the result data from the shared function unit to the first type of register. The second type of issuing unit synchronously schedules the read time of the second type of instruction with the execution of the second type of instruction in the shared function unit to read the operand data of the second type of instruction from the second type of register group, and schedules the write time of the second type of instruction to write the result data from the shared function unit to the second type of register. The first type of issuing unit parses the data dependencies and resource conflicts of the first type of instruction to set the first count value recorded in each entry of the first execution queue, and The second type of issuing unit parses the data dependencies and resource conflicts of the second type of instruction to set the second count value in each entry recorded in the second execution queue.

16. The method of claim 14, wherein The first execution queue also includes a first cumulative throughput counter that decrements by one every clock cycle. The first cumulative throughput counter indicates in which clock cycle the first type of issuing unit is allowed to issue the next first type of instruction to the first execution queue. The second execution queue also includes a second cumulative throughput counter that decrements by one every clock cycle. The second cumulative throughput counter indicates in which clock cycle the second type of issuing unit is allowed to issue the next second type of instruction to the second execution queue. The first type of issuing unit, based on the first active bit of the first execution queue and the second active bit of the second execution queue, uses the first cumulative throughput counter or the second cumulative throughput counter to issue the first type of instruction to the first execution queue as the read time of the issued first type of instruction; and The second type of issuing unit, based on the first active bit of the first execution queue and the second active bit of the second execution queue, uses either the first cumulative throughput counter or the second cumulative throughput counter to issue the second type of instruction to the second execution queue as the read time of the issued second type of instruction, wherein... When the first type of issuing unit issues the first type of instruction, the first active bit is set. When the second type of issuing unit issues the second type of instruction, the first active bit is cleared. When the first cumulative throughput counter is zero, the first active bit is cleared. When the second type of issuing unit issues the second type of instruction, the second active bit is set. When the first type of issuing unit issues the first type of instruction, the second active bit is cleared, and When the second cumulative throughput counter is zero, the second active bit is cleared.

17. The method of claim 14, wherein the microprocessor further comprises: A first multiplexing, coupled to the first execution queue, the second execution queue, and the shared functional unit, is configured to mutually exclusively dispatch first-type instructions from the first execution queue or second-type instructions from the second execution queue to the shared functional unit, wherein... The first multiplexing is further coupled to the first type of register group and the second type of register group through the first read bus and the second read bus respectively, and the first multiplexing mutually excludes operand data from the first type of register group or operand data from the second type of register group from the shared functional unit.

18. The method of claim 14, wherein the microprocessor further comprises: A shared execution queue is used by the first type of publishing unit and the second type of publishing unit to receive the first type of instruction and the second type of instruction, record the first type of instruction and the second type of instruction in the entries of the shared execution queue, and sequentially dispatch the first type of instruction and the second type of instruction recorded in the entries of the shared execution queue. as well as The second multiplexing is coupled to the first type of register group and the second type of register group via a first read bus and a second read bus, respectively. It receives operand data of the first type of instruction via the first read bus or operand data of the second type of instruction via the second read bus, and dispatches the operand data of the first type of instruction and the operand data of the second type of instruction to the shared functional unit in a mutually exclusive manner. The second multiplexing and the shared execution queue synchronously dispatch the operand data of the first type of instruction and the operand data of the second type of instruction for the dispatch of the first type of instruction and the second type of instruction.

19. The method of claim 18, wherein The shared execution queue includes a cumulative throughput counter that tracks the cumulative throughput count of valid entries in the shared execution queue, and The cumulative throughput counter is updated based on the last instruction published to the shared execution queue from either the first type of publishing unit or the second type of publishing unit. The cumulative throughput counter decrements by one every clock cycle, and the cumulative throughput counter indicates in which clock cycle the issuing unit is allowed to issue the next instruction to the shared execution queue.

20. A data processing system, comprising: The memory is configured to store first-type instructions and second-type instructions; as well as Microprocessors, including: A first execution queue includes multiple entries, wherein each entry of the first execution queue records a first type of instruction, each entry of the first execution queue includes a first count value corresponding to the first type of instruction, the first count value is decremented until the first count value reaches 0, and when the first count value corresponding to the first type of instruction reaches 0, the first execution queue dispatches the first type of instruction to a shared functional unit. The second execution queue includes multiple entries, wherein each entry of the second execution queue records a second type of instruction, each entry of the second execution queue includes a second count value corresponding to the second type of instruction, the second count value is decremented until the second count value reaches 0, and when the second count value corresponding to the second type of instruction reaches 0, the second execution queue dispatches the second type of instruction to the shared functional unit. A shared functional unit executes a first type of instruction and a second type of instruction, wherein the first type of instruction from the first execution queue and the second type of instruction from the second execution queue are mutually exclusively dispatched to the shared functional unit; The first type of publishing unit publishes the first type of instruction to the first execution queue, schedules the read and write times of the first type of instruction, and sets the first count value recorded in each entry of the first execution queue; and The second type of publishing unit publishes the second type of instruction to the second execution queue, schedules the reading and writing times of the second type of instruction, and sets the second count value recorded in each entry of the second execution queue.

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