Control Method, Device, and Readable Medium for Compatibility with External Plug-in Cards in a Storage System

Abstract

The present invention discloses a control method, device and readable medium for compatible external plug-in cards in a storage system. The method includes: the CPLD identifies the type of the external plug-in card by detecting the id of the external plug-in card inserted into the slot of the main board; during the system startup process, the Bios obtains the external plug-in card type through the GPIO of the PCH and then performs PCIE bandwidth allocation. The PCH notifies the CPU to perform PCIE communication link by loading the bandwidth information provided by the bios through SPI; the CPLD controls the power-on of the external plug-in card by detecting the external plug-in card presence signal, and; after the external plug-in card is powered on, it feeds back the card power good signal to the CPLD, and the CPLD controls the external plug-in card to de-reset. This control method can achieve the compatibility of the control logic of standard and non-standard external plug-in cards in the storage system, enabling the product to be flexibly configured, with a flexible design scheme, and one design can be compatible with multiple products.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and in particular, to a control method, device, and readable medium for a storage system to be compatible with external plug-in cards. Background Art

[0002] At present, when designing the main control system of a storage unit, many external plug-in card slots are provided to connect various service cards to meet various service requirements. Generally speaking, the external plug-in card slots provided on the storage motherboard are all standard slots, which are used to connect standard external plug-in cards and execute a unified design specification, with strong versatility and can be flexibly configured according to different requirements. However, some powerful service cards are restricted by space layout and design specification requirements and cannot be designed in the form of a unified standard card. Such a card is required by the storage system and needs to be used in combination with standard cards at the same time. This requires that when designing the storage motherboard, the external plug-in card slots can be compatible with both standard cards and non-standard cards. This case provides a design interface and an external plug-in card control solution that can connect both standard cards and non-standard cards. Summary of the Invention

[0003] In view of this, an object of an embodiment of the present invention is to provide a control method for a storage system to be compatible with external plug-in cards. The control method for a storage system to be compatible with external plug-in cards can achieve the compatibility of the control logics of external standard cards and non-standard cards in the storage system, enabling the product to be flexibly configured, with a flexible design scheme, and one design can be compatible with multiple products.

[0004] Based on the above object, on the one hand, an embodiment of the present invention provides a control method for a storage system to be compatible with external plug-in cards. In the storage system, a CPLD, a CPU, and multiple slots are provided on the motherboard and are communicatively connected to each other. Each slot can directly plug in a non-standard card and can plug in a standard card through an adapter board. The CPU is communicatively connected to the PCH through the DMI bus. The CPLD enables the eFuse module through control. The non-standard card includes two main control chips, and the standard card includes one main control chip. The control method includes: the CPLD identifies the type of the external plug-in card by detecting the id of the external plug-in card inserted into the slot on the motherboard; during the system startup process, the bios obtains the external plug-in card type through the GPIO of the PCH and then performs PCIE bandwidth allocation. The PCH notifies the CPU to perform PCIE communication link by loading the bandwidth information provided by the bios through SPI; the CPLD controls the power-on of the external plug-in card by detecting the external plug-in card presence signal, and; after the external plug-in card is powered on, it feeds back the card power good signal to the CPLD, and the CPLD controls the external plug-in card to be de-reset.

[0005] In some embodiments, the external plug-in card includes a standard card and a non-standard card. The non-standard card includes two main control chips, the standard card includes one main control chip, and 14 slots are provided on the motherboard.

[0006] In some embodiments, the CPLD identifies the type of the external card by detecting the ID of the external card inserted into the slot on the main board, including: when the external card is inserted into the slot, the CPLD on the main board detects the value of the slot id[1:0] of the slot. When the value is 10, the external card is identified as a non-standard card. When the value is 01, the external card is identified as a standard card inserted through an adapter board.

[0007] In some embodiments, during the system startup process, the BIOS obtains the type of the external card through the GPIO of the PCH and then allocates the PCIE bandwidth. The PCH loads the bandwidth information provided by the BIOS through SPI and notifies the CPU to establish a PCIE communication link, including: the CPLD feeds back the detected type of the external card to the PCH. If the external card is a non-standard card, the CPU notifies the BIOS to provide 2 lanes of PCIE-X4 bandwidth. If the external card is a standard card, the CPU notifies the BIOS to provide 1 lane of PCIE-X8 bandwidth.

[0008] In some embodiments, the CPLD controls the power-on of the external card by detecting the card presence signal of the external card, including: when an external card is inserted into the slot, the CPLD detects that the card presence signal of the slot is valid, and the CPLD enables the eFuse module to supply power to the slot. Among them, the power supply is 12V.

[0009] In some embodiments, the CPLD conveys the power enable control signal to the non-standard card through the slot and conveys it to the adapter board through the slot and then to the standard card. The power enable control signals of the standard card and the non-standard card include three control signals: Power enable1, Power enable2, and Power enable3. Among them,

[0010] For the standard card, the CPLD conveys Power enable1 to the standard card to control the enabling of the standby power on the standard card during the system startup process. The CPLD conveys Power enable2 to the standard card to control the enabling of the main power on the standard card after the system startup.

[0011] For a non-standard card, the CPLD delivers Power enable2 to the non-standard card to control the power-on enabling of the first main control chip and the second main control chip on the non-standard card after the system starts. After the FirmWare of the first main control chip is upgraded and the CPLD receives the power-down instruction sent by the system through the I2C / LPC / ESPI interface of the PCH, it delivers Power enable1 to the non-standard card to control the power-down enabling of the first main control chip. After the FirmWare of the second main control chip is upgraded and the CPLD receives the power-down instruction sent by the system through the I2C / LPC / ESPI interface of the PCH, it delivers Power enable3 to the non-standard card to control the power-down enabling of the second main control chip.

[0012] In some embodiments, after the external plug-in card is powered on, it feeds back the card power good signal to the CPLD. The CPLD controls the de-resetting of the external plug-in card, including:

[0013] After the non-standard card is powered on, after the CPLD receives the card powergood1 signal returned by the first main control chip or the card power good2 signal returned by the second main control chip, it delays for a period of time to de-reset the non-standard card;

[0014] After the standard card is powered on, after the CPLD receives the card powergood signal returned by the chip of the standard card, it delays for a period of time to de-reset the standard card.

[0015] In some embodiments, a first AND gate chip communicatively connected to each other and a first main control chip, and a second AND gate chip communicatively connected to each other and a second main control chip are provided on the non-standard card:

[0016] After the non-standard card receives the reset signal sent by the CPLD, it controls the first main control chip through the first AND gate chip and the second main control chip through the second AND gate chip to respectively control the de-resetting of the first main control chip and the second main control chip.

[0017] In another aspect of the embodiments of the present invention, a computer device is further provided, including: at least one processor; and a memory storing computer instructions that can run on the processor. When the instructions are executed by the processor, the steps of the method include: the CPLD identifies the type of the external plug-in card by detecting the id of the external plug-in card inserted into the slot on the motherboard; during the system startup process, the bios obtains the type of the external plug-in card through the GPIO of the PCH and then performs PCIE bandwidth allocation. The PCH loads the bandwidth information provided by the bios through SPI and notifies the CPU to perform PCIE communication link; the CPLD controls the power-on of the external plug-in card by detecting the in-position signal of the external plug-in card; and after the external plug-in card is powered on, it feeds back the card power good signal to the CPLD, and the CPLD controls the external plug-in card to be reset.

[0018] In some embodiments, the external plug-in card includes a standard card and a non-standard card. The non-standard card includes 2 main control chips, the standard card includes 1 main control chip, and 14 slots are provided on the motherboard.

[0019] In some embodiments, the CPLD identifies the type of the external plug-in card by detecting the id of the external plug-in card inserted into the slot on the motherboard, including: when the external plug-in card is inserted into the slot, the CPLD on the motherboard detects the value of the slot id[1:0] of the slot. When the value is 10, the external plug-in card is identified as a non-standard card. When the value is 01, the external plug-in card is identified as a standard card plugged in through an adapter board.

[0020] In some embodiments, during the system startup process, the bios obtains the type of the external plug-in card through the GPIO of the PCH and then performs PCIE bandwidth allocation. The PCH loads the bandwidth information provided by the bios through SPI and notifies the CPU to perform PCIE communication link, including: the CPLD feeds back the detected type of the external plug-in card to the PCH. If the external plug-in card is a non-standard card, the CPU notifies the bios to provide 2-way PCIE-X4 bandwidth. If the external plug-in card is a standard card, the CPU notifies the bios to provide 1-way PCIE-X8 bandwidth.

[0021] In some embodiments, the CPLD controls the power-on of the external plug-in card by detecting the in-position signal of the external plug-in card, including: when an external plug-in card is inserted into the slot, the CPLD detects that the card in-position signal of the slot is valid, and the CPLD enables the eFuse module to supply power to the slot, where the power supply is 12V.

[0022] In some embodiments, the CPLD conveys the power enable control signal to the non-standard card through the slot and conveys it to the adapter board through the slot and then to the standard card. The power enable control signals of the standard card and the non-standard card include three control signals: Power enable1, Power enable2, and Power enable3. Among them,

[0023] For the standard card, the CPLD delivers Power enable1 to the standard card to control the standby power enable on the standard card during system startup, and the CPLD delivers Power enable2 to the standard card to control the main power enable on the standard card after system startup;

[0024] For the non-standard card, the CPLD delivers Power enable2 to the non-standard card to control the power-on enable of the first main control chip and the second main control chip on the non-standard card after system startup. After the FirmWare of the first main control chip is upgraded and the CPLD receives the power-off instruction sent by the system through the I2C / LPC / ESPI interface of the PCH, the CPLD delivers Power enable1 to the non-standard card to control the power-off enable of the first main control chip. After the FirmWare of the second main control chip is upgraded and the CPLD receives the power-off instruction sent by the system through the I2C / LPC / ESPI interface of the PCH, the CPLD delivers Power enable3 to the non-standard card to control the power-off enable of the second main control chip.

[0025] In some embodiments, after the external plug-in card is powered on, it feeds back the card power good signal to the CPLD. The CPLD controls the de-reset of the external plug-in card, including:

[0026] After the non-standard card is powered on, after the CPLD receives the card power good1 signal returned by the first main control chip or the card power good2 signal returned by the second main control chip, it delays for a period of time to perform de-reset on the non-standard card;

[0027] After the standard card is powered on, after the CPLD receives the card power good signal returned by the chip of the standard card, it delays for a period of time to perform de-reset on the standard card.

[0028] In some embodiments, a first AND gate chip and a first main control chip that communicate with each other, and a second AND gate chip and a second main control chip that communicate with each other are provided on the non-standard card;

[0029] After the non-standard card receives the reset signal sent by the CPLD, it controls the first main control chip through the first AND gate chip and the second main control chip through the second AND gate chip to respectively control the de-reset of the first main control chip and the second main control chip.

[0030] In another aspect of the embodiments of the present invention, a computer-readable storage medium is further provided. The computer-readable storage medium stores a computer program that implements the method steps of the present invention when executed by a processor.

[0031] The present invention has at least the following beneficial technical effects:

[0032] In the storage system of the present invention, the control method for compatible external cards can achieve the compatibility of the control logics of standard cards and non-standard cards externally inserted into the storage system, enabling the product to be flexibly configured. With a flexible design scheme, one design can be compatible with multiple products. The same external card slot in the storage system can support both non-standard cards and standard cards. Standard cards and non-standard cards have both common signals and independent signals. After the motherboard CPLD identifies the card type, it outputs the corresponding control logic; there are 2 main control chips on the non-standard card, which is equivalent to connecting 2 standard cards to 1 slot. The motherboard CPLD and the non-standard card cooperate to complete the normal power-on working logic control of the non-standard card; there are 2 main control chips on the non-standard card, and the power-off of the 2 main control chips is separately controlled by the motherboard CPLD. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following-described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other embodiments can be obtained based on these drawings.

[0034] Figure 1 It is a schematic diagram of an embodiment of the control method for compatible external cards in the storage system provided by the present invention;

[0035] Figure 2 It is a schematic diagram of an embodiment of the control logic for compatible external cards in the storage system provided by the present invention.

[0036] Figure 3 It is a schematic diagram of an embodiment of the control logic of the non-standard card provided by the present invention.

[0037] Figure 4 It is a schematic diagram of an embodiment of the control logic of the standard card provided by the present invention.

[0038] Figure 5 It is a schematic diagram of an embodiment of the control logic of the first main control chip and the second main control chip of the non-standard card provided by the present invention.

[0039] Figure 6 It is a schematic diagram of an embodiment of the computer device provided by the present invention;

[0040] Figure 7 It is a schematic diagram of an embodiment of the computer-readable storage medium provided by the present invention. Detailed Embodiments

[0041] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the following further elaborates on the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0042] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for distinguishing two entities or parameters with the same name but different identities. It can be seen that "first" and "second" are only for the convenience of expression and should not be construed as limitations on the embodiments of the present invention. This will not be elaborated one by one in the subsequent embodiments.

[0043] Based on the above objectives, in the first aspect of the embodiments of the present invention, a control method for compatible external plug-in cards in a storage system is proposed. Figure 1 The figure shows a schematic diagram of an embodiment of the control method for compatible external plug-in cards in the storage system provided by the present invention. Figure 2 The figure shows a schematic diagram of an embodiment of the control logic for compatible external plug-in cards in the storage system provided by the present invention. Figure 3 The figure shows a schematic diagram of an embodiment of the control logic for non-standard cards provided by the present invention. Figure 4 The figure shows a schematic diagram of an embodiment of the control logic for standard cards provided by the present invention. Figure 5 The figure shows a schematic diagram of an embodiment of the control logic for the first main control chip and the second main control chip of non-standard cards provided by the present invention. As Figures 1 to 5 shown, in the storage system of the embodiments of the present invention, a CPLD, a CPU, and multiple slots are provided on the main board and are communicatively connected to each other. Each slot can directly plug in a non-standard card and can plug in a standard card through an adapter board. The CPU is communicatively connected to the PCH through the DMI bus. The CPLD enables the eFuse module through control. The control method for compatible external plug-in cards in the storage system includes the following steps:

[0044] 001. The CPLD identifies the type of the external plug-in card by detecting the id of the external plug-in card inserted into the slot on the main board;

[0045] 002. During the system startup process, the bios obtains the external plug-in card type through the GPIO of the PCH and then performs PCIE bandwidth allocation. The PCH loads the bandwidth information provided by the bios through SPI and notifies the CPU to perform PCIE communication link;

[0046] 003. The CPLD controls the power-on of the external plug-in card by detecting the external plug-in card presence signal;

[0047] 004. After the external plug-in card is powered on, it feeds back the card power good signal to the CPLD, and the CPLD controls the external plug-in card to be de-reset.

[0048] In this embodiment, each slot on the main board provides only one non-standard interface, which can be directly docked with a non-standard card. If a standard card is to be connected, it needs to be docked with the standard card through an adapter board. The CPLD (Complex Programmable Logic Device) is included in the controller module, that is, on the main board, as an external card control module. It means that various logical controls for the external card are carried out inside the CPLD to enable it to operate normally. The main board, that is, the controller module, is the core module in the storage system and can provide 14 external card slots. The CPU module is included in the main board and mainly provides the PCIE high-speed signals required by the external card.

[0049] In some embodiments of the present invention, the external cards include standard cards and non-standard cards. The non-standard card includes 2 main control chips, and the standard card includes 1 main control chip. There are 14 slots provided on the main board.

[0050] In this embodiment, the non-standard card, that is, the non-standard service card, is mainly used to connect to the EBOF, that is, the hard disk expansion cabinet of the storage system, to expand the storage capacity of the storage system. There is one interface at each end of the adapter board. The interface at one end is the same as the interface of the non-standard card and is directly docked with the slot on the main board. The interface at the other end is a standard OCP slot to connect to the standard card. The standard card is the OCP3.0 service card to expand various functions.

[0051] In some embodiments of the present invention, the CPLD identifies the type of the external card inserted into the slot on the main board by detecting the id of the external card, including: when the external card is connected to the slot, the CPLD on the main board detects the value of the slot id[1:0] of the slot. When the value is 10, the external card is identified as a non-standard card. When the value is 01, the external card is identified as a standard card plugged in through the adapter board.

[0052] In this embodiment, when an external card is connected, the main board CPLD first detects the value of the slot id[1:0] to distinguish between a standard card and a non-standard card. The slot id[1:0] is defaulted to a 2-bit value. The slot id of the non-standard card is set to ok on the non-standard card and is 10. Since the standard card does not support the output of the slot id, the slot id of the standard card is designed on the adapter board and is 01.

[0053] In some embodiments of the present invention, during the system startup process, the BIOS obtains the type of the externally inserted card through the GPIO of the PCH and then allocates the PCIe bandwidth. The PCH loads the bandwidth information provided by the BIOS through SPI and notifies the CPU to establish a PCIe communication link, including: the CPLD feeds back the detected type of the externally inserted card to the PCH. If the externally inserted card is a non-standard card, the CPU notifies the BIOS to provide 2 lanes of PCIe-X4 bandwidth; if the externally inserted card is a standard card, the CPU notifies the BIOS to provide 1 lane of PCIe-X8 bandwidth.

[0054] In this embodiment, after the CPLD on the motherboard detects the type of the externally inserted card, during the system startup process, it will notify the BIOS to provide different PCIe bandwidths. There are 2 main control chips on the non-standard card, and the BIOS will provide 2 lanes of PCIe-X4; 1 lane of PCIe-X8 bandwidth is provided on the standard card.

[0055] In some embodiments of the present invention, the CPLD controls the power-on of the externally inserted card by detecting the card presence signal of the externally inserted card, including: when the externally inserted card is inserted into the slot, the CPLD detects that the card presence signal of the slot is valid, and the CPLD enables the eFuse module to supply power to the slot. Here, the power supply is 12V.

[0056] In this embodiment, when the CPLD on the motherboard detects that the card presence signal, i.e., card present, is valid, it will turn on the 12V eFuse enable on the motherboard to supply 12V power to the slot.

[0057] In some embodiments of the present invention, the CPLD conveys the power enable control signal to the non-standard card through the slot and then to the adapter board through the slot and further to the standard card. The power enable control signals for the standard card and the non-standard card include three control signals: Power enable1, Power enable2, and Power enable3. Among them,

[0058] For the standard card, the CPLD conveys Power enable1 to the standard card to control the standby power enable on the standard card during the system startup process, and the CPLD conveys Power enable2 to the standard card to control the main power enable on the standard card after the system startup;

[0059] For non-standard cards, the CPLD delivers Power enable2 to the non-standard card to control the power-on enabling of the first master chip and the second master chip on the non-standard card after the system starts up. After the FirmWare of the first master chip is upgraded and the CPLD receives the power-off instruction sent by the system through the I2C / LPC / ESPI interface of the PCH, the CPLD delivers Power enable1 to the non-standard card to control the power-off enabling of the first master chip. After the FirmWare of the second master chip is upgraded and the CPLD receives the power-off instruction sent by the system through the I2C / LPC / ESPI interface of the PCH, the CPLD delivers Power enable3 to the non-standard card to control the power-off enabling of the second master chip.

[0060] In this embodiment, the control of power enabling for non-standard cards and standard cards is different, specifically manifested as follows: Powerenable1: A signal shared by non-standard cards and standard cards, which controls the standby power enabling of the standard card and is turned on after a delay after the 12V eFuse is turned on, controls the power-off of the first master chip on the non-standard card, and is only operated after the CPLD receives the power-off instruction sent by the system after the FirmWare of the first master chip is upgraded. The CPLD will perform different operations on powerenable1 according to the card type; Power enable2: A signal shared by non-standard cards and standard cards, which controls the main power enabling of the standard card and the power-on enabling of the first master chip and the second master chip of the non-standard card, and performs the power-on enabling operation on the large standard card after the system starts up; Power enable3: A signal unique to non-standard cards and not used by standard cards, which controls the power-off of the second master chip on the non-standard card and is only operated after the CPLD receives the power-off instruction sent by the system after the FirmWare of the second master chip is upgraded.

[0061] In some embodiments of the present invention, after the external plug-in card is powered on, it feeds back the card power good signal to the CPLD. The CPLD controls the de-resetting of the external plug-in card, including:

[0062] After the non-standard card is powered on, after the CPLD receives the card power good1 signal returned by the first master chip or the card power good2 signal returned by the second master chip, it delays for a period of time to de-reset the non-standard card;

[0063] After the standard card is powered on, after the CPLD receives the card power good signal returned by the chip of the standard card, it delays for a period of time to de-reset the standard card.

[0064] In this embodiment, after all the power supplies are turned on, the CPLD will receive the power card power good signal fed back from the card:

[0065] Non-standard card: There are 2 main control chips on the non-standard card. After the power supply of the first main control chip is okay, it returns card powergood1. After the power supply of the second main control chip is okay, it returns card power good2;

[0066] Standard card: According to the standard specification of the standard card, the standard card only uses the card power good1 signal and returns card power good1 after the power supply of the standard card is okay.

[0067] In some embodiments of the present invention, a first AND gate chip and a first main control chip that are communicatively connected to each other, and a second AND gate chip and a second main control chip that are communicatively connected to each other are provided on the non-standard card:

[0068] After receiving the reset signal sent by the CPLD, the non-standard card controls the first main control chip through the first AND gate chip and controls the second main control chip through the second AND gate chip to respectively control the first main control chip and the second main control chip to release the reset.

[0069] In this embodiment, after receiving the card power good signals of the non-standard card and the standard card, the CPLD delays for a period of time to release the reset of the non-standard card and the standard card to make them work normally:

[0070] Non-standard card: Due to the tight number of pins PIN, only 1 path of reset can be provided for the non-standard card. After receiving the reset signal sent by the CPLD, the non-standard card further controls the first main control chip and the second main control chip to release the reset separately on the non-standard card, and separates the release of the reset of the 2 chips;

[0071] Standard card: After receiving the reset release signal from the CPLD, it can start to work normally.

[0072] For the above purpose, in the second aspect of the embodiments of the present invention, a computer device is proposed. Figure 6 The following shows a schematic diagram of the embodiment of the computer device provided by the present invention. As Figure 6 shown, the computer device of the embodiment of the present invention includes the following devices: at least one processor 021; and a memory 022, and the memory 022 stores computer instructions 023 that can run on the processor. When the instructions are executed by the processor, the steps of the method include:

[0073] The CPLD identifies the type of the external plug-in card by detecting the id of the external plug-in card inserted into the slot on the motherboard;

[0074] During the system startup process, the BIOS obtains the type of the externally inserted card through the GPIO of the PCH and then allocates the PCIe bandwidth. The PCH loads the bandwidth information provided by the BIOS through SPI and notifies the CPU to establish a PCIe communication link;

[0075] The CPLD controls the power-on of the externally inserted card by detecting the card-present signal of the externally inserted card, and;

[0076] After the externally inserted card is powered on, it feeds back the card power good signal to the CPLD, and the CPLD controls the de-reset of the externally inserted card.

[0077] Among them, a CPLD, a CPU, and multiple slots that communicate with each other are provided on the motherboard. Each slot can directly plug in a non-standard card and can plug in a standard card through an adapter board. The CPU is communicatively connected to the PCH through the DMI bus, and the CPLD enables through controlling the eFuse module. The externally inserted card includes a standard card and a non-standard card. The non-standard card includes 2 main control chips, the standard card includes 1 main control chip, and 14 slots are provided on the motherboard.

[0078] The CPLD identifies the type of the externally inserted card by detecting the id of the externally inserted card inserted into the slot on the motherboard, including: when the externally inserted card is inserted into the slot, the CPLD on the motherboard detects the value of the slot id[1:0] of the slot. When the value is 10, the externally inserted card is identified as a non-standard card. When the value is 01, the externally inserted card is identified as a standard card plugged in through an adapter board.

[0079] During the system startup process, the BIOS obtains the type of the externally inserted card through the GPIO of the PCH and then allocates the PCIe bandwidth. The PCH loads the bandwidth information provided by the BIOS through SPI and notifies the CPU to establish a PCIe communication link, including: the CPLD feeds back the detected type of the externally inserted card to the PCH. If the externally inserted card is a non-standard card, the CPU notifies the BIOS to provide 2 lanes of PCIe-X4 bandwidth. If the externally inserted card is a standard card, the CPU notifies the BIOS to provide 1 lane of PCIe-X8 bandwidth.

[0080] The CPLD controls the power-on of the externally inserted card by detecting the card-present signal of the externally inserted card, including: after the externally inserted card is inserted into the slot, the CPLD detects that the card-present signal of the slot is valid, and the CPLD enables the eFuse module to supply power to the slot. Among them, the power supply is 12V.

[0081] The CPLD conveys the power enable control signal to the non-standard card through the slot and conveys it to the adapter board through the slot and then to the standard card. The power enable control signals of the standard card and the non-standard card include three control signals: Power enable1, Power enable2, and Power enable3. Among them,

[0082] For the standard card, the CPLD delivers Power enable1 to the standard card to control the standby power enable on the standard card during system startup, and the CPLD delivers Power enable2 to the standard card to control the main power enable on the standard card after system startup;

[0083] For the non-standard card, the CPLD delivers Power enable2 to the non-standard card to control the power-on enable of the first main control chip and the second main control chip on the non-standard card after system startup. After the FirmWare of the first main control chip is upgraded and the CPLD receives the power-off instruction sent by the system through the I2C / LPC / ESPI interface of the PCH, the CPLD delivers Power enable1 to the non-standard card to control the power-off enable of the first main control chip. After the FirmWare of the second main control chip is upgraded and the CPLD receives the power-off instruction sent by the system through the I2C / LPC / ESPI interface of the PCH, the CPLD delivers Power enable3 to the non-standard card to control the power-off enable of the second main control chip.

[0084] After the external plug-in card is powered on, it feeds back the card power good signal to the CPLD. The CPLD controls the de-reset of the external plug-in card, including:

[0085] After the non-standard card is powered on, after the CPLD receives the card powergood1 signal returned by the first main control chip or the card power good2 signal returned by the second main control chip, it delays for a period of time to perform de-reset on the non-standard card;

[0086] After the standard card is powered on, after the CPLD receives the card powergood signal returned by the chip of the standard card, it delays for a period of time to perform de-reset on the standard card.

[0087] On the non-standard card, there are a first AND gate chip (for example, Figure 5 the AND gate chip 1 in Figure 5 ) and the first main control chip, which are communicatively connected to each other, and a second AND gate chip (for example,

[0088] the AND gate chip 2 in

[0089] The present invention also provides a computer-readable storage medium. Figure 7 Shown is a schematic diagram of an embodiment of the computer-readable storage medium provided by the present invention. AsFigure 7 As shown, the computer-readable storage medium 031 stores a computer program 032 that, when executed by a processor, executes the method described in the present invention.

[0090] Finally, it should be noted that those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program of the method for centralized testing by the server can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium of the program can be a magnetic disk, an optical disc, a read-only memory (ROM), or a random access memory (RAM), etc. The embodiments of the above computer programs can achieve the same or similar effects as the corresponding foregoing method embodiments.

[0091] In addition, the method disclosed according to the embodiments of the present invention can also be implemented as a computer program executed by a processor, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the above functions defined in the method disclosed in the embodiments of the present invention are executed.

[0092] In addition, the above method steps and system units can also be implemented by using a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the above step or unit functions.

[0093] Those skilled in the art will also understand that the various exemplary logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, a general description has been given of the functions of the various illustrative components, blocks, modules, circuits, and steps. Whether this function is implemented as software or hardware depends on the specific application and the design constraints imposed on the overall system. The functions that those skilled in the art can implement in various ways for each specific application, but this implementation decision should not be construed as causing a departure from the scope of the disclosure of the embodiments of the present invention.

[0094] In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. The storage media may be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example, and not limitation, the computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. In addition, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0095] The above are exemplary embodiments disclosed by the present invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present invention as defined by the claims. The functions, steps, and / or actions of the method claims according to the disclosed embodiments herein need not be performed in any particular order. In addition, although the elements disclosed by the embodiments of the present invention may be described or claimed in individual form, they may also be understood as plural unless explicitly limited to the singular.

[0096] It should be understood that, as used herein, unless the context clearly supports exceptions, the singular forms "a" and "an" are intended to also include the plural forms. It should also be understood that the phrase "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0097] The serial numbers of the disclosed embodiments of the present invention above are only for description and do not represent the superiority or inferiority of the embodiments.

[0098] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware, or can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium, and the above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disk, etc.

[0099] Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope (including the claims) of the disclosure of the embodiments of the present invention is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the embodiments of the present invention as described above, and they are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included in the protection scope of the embodiments of the present invention.

Claims

1. A control method for compatible external plug-in cards in a storage system, characterized in that On the main board, a CPLD, a CPU, and multiple slots are set up to communicate with each other. Each slot can directly plug in a non-standard card and can plug in a standard card through an adapter board. The CPU is communicatively connected to the PCH through the DMI bus, and the CPLD enables the eFuse module through control. The control method includes: The CPLD identifies the type of the externally plugged card by detecting the id of the externally plugged card in the slot inserted into the main board; During the system startup process, the bios obtains the type of the externally plugged card through the GPIO of the PCH and then performs PCIE bandwidth allocation. The PCH loads the bandwidth information provided by the bios through SPI and notifies the CPU to perform PCIE communication link; The CPLD controls the power-on of the externally plugged card by detecting the card presence signal; and After the externally plugged card is powered on, it feeds back the card power good signal to the CPLD, and the CPLD controls the de-reset of the externally plugged card; The externally plugged card includes a standard card and a non-standard card. The non-standard card includes 2 main control chips, the standard card includes 1 main control chip, and 14 slots are set up on the main board; The "During the system startup process, the bios obtains the type of the externally plugged card through the GPIO of the PCH and then performs PCIE bandwidth allocation. The PCH loads the bandwidth information provided by the bios through SPI and notifies the CPU to perform PCIE communication link" includes: The CPLD feeds back the detected type of the externally plugged card to the PCH. If the externally plugged card is a non-standard card, the CPU notifies the bios to provide 2-way PCIE-X4 bandwidth. If the externally plugged card is a standard card, the CPU notifies the bios to provide 1-way PCIE-X8 bandwidth.

2. The control method for compatible external plug-in cards in the storage system according to claim 1, characterized in that, The "The CPLD identifies the type of the externally plugged card by detecting the id of the externally plugged card in the slot inserted into the main board" includes: When the externally plugged card is inserted into the slot, the CPLD on the main board detects the value of the slot id[1:0] of the slot. When the value is 10, the externally plugged card is identified as a non-standard card. When the value is 01, the externally plugged card is identified as a standard card plugged in through an adapter board.

3. The control method for compatible external plug-in cards in the storage system according to claim 1, characterized in that, The "The CPLD controls the power-on of the externally plugged card by detecting the card presence signal" includes: After the externally plugged card is inserted into the slot, the CPLD detects that the card presence signal of the slot is valid, and the CPLD enables the eFuse module to supply power to the slot. Among them, the power supply is 12V.

4. The control method for compatible external plug-in cards in the storage system according to claim 3, characterized in that, The CPLD transports the power enable control signal to the non-standard card through the slot and transports it to the adapter board through the slot and then transports it to the standard card. The power enable control signals of the standard card and the non-standard card include three control signals: Power enable1, Powerenable2, and Power enable3. Among them, For the standard card, the CPLD transports Power enable1 to the standard card to control the enabling of the standby power on the standard card during the system startup process. The CPLD transports Power enable2 to the standard card to control the enabling of the main power on the standard card after the system startup; For a non-standard card, the CPLD delivers Power enable2 to the non-standard card to control the power-on enabling of the first master chip and the second master chip on the non-standard card after the system starts up. After the FirmWare upgrade of the first master chip is completed and the CPLD receives a power-down instruction sent by the system through the I2C / LPC / ESPI interface of the PCH, the CPLD delivers Power enable1 to the non-standard card to control the power-down enabling of the first master chip. After the FirmWare upgrade of the second master chip is completed and the CPLD receives a power-down instruction sent by the system through the I2C / LPC / ESPI interface of the PCH, the CPLD delivers Power enable3 to the non-standard card to control the power-down enabling of the second master chip.

5. The control method for compatible external plug-in cards in the storage system according to claim 1, characterized in that, After the external plug-in card is powered on, it feeds back the card power good signal to the CPLD. The CPLD controls the de-resetting of the external plug-in card, including: After the non-standard card is powered on, after the CPLD receives the card power good1 signal returned by the first master chip or the card power good2 signal returned by the second master chip, it delays for a period of time to de-reset the non-standard card; After the standard card is powered on, after the CPLD receives the card power good signal returned by the chip of the standard card, it delays for a period of time to de-reset the standard card.

6. The control method for compatible external plug-in cards in the storage system according to claim 5, wherein, On the non-standard card, there are a first AND gate chip and a first master chip that communicate with each other, and a second AND gate chip and a second master chip that communicate with each other; After the non-standard card receives the reset signal sent by the CPLD, it controls the first master chip through the first AND gate chip and the second master chip through the second AND gate chip to respectively control the de-resetting of the first master chip and the second master chip.

7. A computer device, characterized in that, Including: At least one processor; And A memory that stores computer instructions executable on the processor. When the instructions are executed by the processor, the steps of the method according to any one of claims 1-6 are implemented.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1-6 are implemented.

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