Memory circuit, write driver and method of operating the same

Abstract

Systems and methods for limiting negative bit line voltage in SRAM cells are provided. A voltage limiter circuit can be implemented in a write driver to control the magnitude of negative voltage applied on a bit line. The voltage limiter circuit can generate a negative bit line voltage of a desired magnitude at a lower operating voltage level. The voltage limiter circuit can also limit the magnitude of the negative bit line voltage to not exceed a predetermined value. The reduction in the negative bit line voltage magnitude can reduce the effective power supply of the SRAM cell. Embodiments of the present application also provide memory circuits, write drivers, and methods of operating the same.

Description

Technical Field

[0001] The techniques described in this disclosure generally relate to SRAM cells, specific memory circuits, write drivers, and methods of operation thereof. Background Technology

[0002] For a given memory cell supply voltage, a write operation can be performed using the minimum voltage amplitude on the bit line. For some SRAM cells, including dual-port SRAM cells and high-density single SRAM cells, this voltage requirement is negative. Summary of the Invention

[0003] According to one aspect of an embodiment of this application, a write driver is provided, the write driver being configured to receive a data signal, a write signal, and a negative bit line input signal and to generate a negative bit line voltage for one of two bit lines of a memory cell, the write driver comprising: a capacitor, responsive to a first node, configured to provide a transition of the negative bit line voltage over a period of time; and a voltage limiter circuit, configured to control the voltage at the first node, the voltage limiter circuit being configured to limit the amplitude of the negative bit line voltage on one of the two bit lines of the memory cell such that the amplitude does not exceed a predetermined threshold.

[0004] According to another aspect of the embodiments of this application, a method for operating a write driver is provided, comprising: receiving a data signal; generating a negative bit line voltage, wherein the amplitude of the negative bit line voltage is limited to not exceeding a predetermined value and is allowed to reach a write operation threshold level; and applying the negative bit line voltage to one of two bit lines based on the data signal.

[0005] According to another aspect of the embodiments of this application, a memory circuit is provided, comprising: a memory array including a plurality of transistors and a plurality of bit lines forming a plurality of memory cells, the memory array being configured to receive one or more write operation data signals and perform a write operation on a memory location; and a write driver configured to receive a data signal, a write signal, and a negative bit line input signal and generate one or more write operation data signals including a negative bit line voltage to one of two bit lines of a particular memory cell, the write driver including a capacitor configured to provide a transition of the negative bit line voltage over a period of time and a voltage limiter circuit configured to limit the amplitude of the negative bit line voltage on one of the two bit lines of the memory cell. Attached Figure Description

[0006] Figure 1 This is a diagram of an exemplary memory architecture in an SRAM cell according to an embodiment.

[0007] Figure 2 This is a detailed diagram of the memory architecture in an SRAM cell according to an embodiment.

[0008] Figure 3 FIG. 1 is a diagram of a voltage limiter circuit implemented in a write driver and a memory array according to an embodiment.

[0009] Figure 4 FIG. 2 is a diagram of a diode voltage limiter circuit implemented in a write driver according to an embodiment.

[0010] Figure 5 FIG. 3 is a timing diagram of waveforms of various signals within the diode voltage limiter circuit according to an embodiment.

[0011] Figure 6 FIG. 4 is a flowchart for deciding components within the diode voltage limiter circuit according to an embodiment.

[0012] Figure 7 FIG. 5 is a detailed diagram of a memory architecture in an SRAM cell according to an embodiment.

[0013] Figure 8 FIG. 6 is a diagram of a PMOS voltage limiter circuit implemented in a write driver according to an embodiment.

[0014] Figure 9 FIG. 7 is a detailed diagram of an embodiment of the PMOS voltage limiter circuit according to an embodiment.

[0015] Figure 10 FIG. 8 is a timing diagram of various signals within the PMOS voltage limiter circuit according to an embodiment.

[0016] Figure 11 FIG. 9 is a timing diagram of operation of the PMOS voltage limiter circuit during a low operating voltage mode according to an embodiment.

[0017] Figure 12 FIG. 10 is a table showing a relationship between a voltage threshold selection signal and voltages at nodes within the PMOS voltage limiter circuit according to an embodiment.

[0018] Figure 13 FIG. 11 is a diagram of one embodiment of a voltage limiter circuit (i.e., an NMOS voltage limiter circuit) according to an embodiment.

[0019] Figure 14 FIG. 12 is a detailed diagram of the NMOS voltage limiter circuit according to an embodiment.

[0020] Figure 15 FIG. 13 is a timing diagram showing a relationship between various signals within the NMOS voltage limiter circuit according to an embodiment.

[0021] Figure 16 FIG. 14 is a table showing a relationship between various signals within the NMOS voltage limiter circuit according to an embodiment.

[0022] Figure 17 is a flowchart of a method of operating a write driver according to an embodiment.

[0023] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless context dictates otherwise. The figures are drawn in simplified form and are not necessarily to scale. Individual embodiments are discussed in the description below. DETAILED DESCRIPTION

[0024] The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific embodiments or examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, the formation of a first part over or on a second part can include embodiments where the first part and the second part are formed in direct contact, and where additional parts can be formed between the first part and the second part, such that the first part and the second part can not be in direct contact. Moreover, the application can be practiced with additional components not expressly described herein. Additionally, the application can be practiced in various examples with reference to different numbers of components and / or different component configurations. The repeated use of reference characters in the description and the drawings is intended to represent the same, or similar, elements or features in the description and drawings. Although processes are described with regard to particular operational flows, many of the steps described as discrete steps in operational

[0025] Furthermore, spatial relationship terms between components (such as "beneath", "below", "lower", "above", "upper", etc.) can be used herein for ease of describing one element or component's relationship to another element(s) or component(s) as drawn or illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, and the apparatus can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Some embodiments of the present disclosure are described. Additional operations can be provided before, during, and / or after the described stages. Some stages can be modified or eliminated. Additional components can be added to the apparatus. Some stages can be performed simultaneously. Some stages can be performed or implemented differently, or in an order that is different than that described. Some stages can be performed or implemented at least in part by different components. The apparatus can be used in different ways than that described. Although the present application has been described in detail with reference to certain illustrative embodiments, those skilled in the art will recognize that the application can be practiced without those specific details. In other instances, well-known methods, structures and techniques have not been described in detail in order to avoid obscuring the application. The following claims are intended to cover all such alternatives and modifications as can fall within the scope of the present application.

[0026] At a given memory cell supply voltage, the minimum amplitude voltage on the bit line is required to perform a write operation. For some SRAM (Static Random Access Memory) cells, including dual-port SRAM cells and high-density single SRAM cells, this voltage requirement is negative. Under certain operating conditions, negative bit line voltages can cause device reliability issues, such as negative bias temperature instability. For example, a high amplitude of negative bit line voltage combined with a high memory cell supply voltage can cause negative bias temperature instability. In some cases, such as a high amplitude of negative voltage on the bit line, a high electric field is created for unselected SRAM cells in a column between the source and gate. This can lead to reliability issues in the device, such as negative bias temperature instability. Prolonged negative bias temperature instability can shorten the device's lifetime.

[0027] Some circuits function well to generate the required negative bitline voltage at low voltages. However, some circuits can also generate high amplitude negative bitline voltages at high voltages, where such high amplitude may be unnecessary for a successful write operation. For example, when the memory operates at 0.6V, the generated negative bitline voltage can be -150mV, which may be suitable for the operation of the memory circuitry. However, when the memory supply voltage is 1.3V (e.g., during periods of high demand), the negative bitline voltage can be -300mV, which could lead to reliability issues within the device.

[0028] In embodiments, the systems and methods described herein can reduce the magnitude of negative bit line voltages when high memory cell supply voltages are present. Due to this negative voltage, the systems and methods described herein can also reduce the effective power supply of SRAM cells. The subject matter of this document discloses several embodiments for reducing the magnitude of negative bit line voltages under high operating voltages.

[0029] Figure 1 This is a diagram of an exemplary memory architecture in an SRAM cell according to an embodiment. In one embodiment, the memory architecture includes control circuitry 106 that generates a write signal 105 and a negative bit line input signal 104. The memory circuitry also includes a write driver 102 configured to receive the write signal 105, the negative bit line input signal 104, and a data signal 103 from a data latch 107. During a write operation, depending on whether a "0" or a "1" is written to the memory cell, the write driver 102 is configured to apply a high voltage to one of the two bit lines 108, 109 and a low voltage to the other bit line. The write driver includes a voltage limiter circuitry 101 configured to control the voltage at a first node of the negative bit line (see...). Figure 3For example, the voltage limiter circuit can be configured to limit the magnitude of the negative bit line voltage applied to one of the two bit lines (108, 109) of the memory array 110. As shown in Figure 1 the memory array 110 is configured to receive the negative bit line voltage on one of the lines 108, 109 and perform a write operation to one or more of the memory cells in the memory array 110.

[0030] Figure 2 is a detailed diagram of a memory architecture in an SRAM cell according to an embodiment. The memory architecture can include a latch 204, a clock 201, a data latch 107, a control circuit 106, a write driver 102, and a memory array 110. In one embodiment, the control circuit 106 is configured to receive a clock signal 202 from the clock 201, an address signal 203 from the latch 204, and generate a negative bit line input signal NBL 104 and write signals (105, 111). The clock signal 201 is used for timing coordination within the control circuit 106, and the address signal 203 from the latch 204 is used to determine where in the memory cell the data will be written. A write decoder within the control circuit 106 can be configured to decode the address signal 203 and generate one or more write signals 105. In one example, one write signal WRITEB_T 105 is enabled to access the top memory array 110, and another write signal WRITEB_B 111 is enabled to access the bottom memory array 113. Each write driver 102 can be configured to receive the negative bit line input signal NBL 104, the write signals (105, 106), and a data signal LDATA 103 from the data latch 107, and generate a negative bit line voltage to one of the two bit lines (108, 109) of the corresponding memory array (110, 113). The data signal LDATA 103 from the data latch 107 can determine the data (i.e., “0” or “1”) to be written to the memory cell. The write driver 102 includes a voltage limiter circuit 101, which can be configured to control the voltage at the first node of the negative bit line (108, 109). For example, the voltage limiter circuit 101 can be configured to limit the magnitude of the negative bit line voltage on one of the two bit lines (108, 109) of the memory cell such that the magnitude does not exceed a predetermined threshold.

[0031] Figure 3 is a diagram of a memory architecture according to an embodiment including an implementation of the voltage limiter circuit 101. In this example, the voltage limiter circuit 101 is implemented as a voltage limiter circuit 101 A, which is configured to limit the magnitude of the negative bit line voltage on one of the two bit lines (108, 109) of the memory array 110 such that the magnitude does not exceed a predetermined threshold. In one embodiment, the voltage limiter circuit 101 A is implemented as a voltage limiter circuit 101 A that includes a first transistor 1011, a second transistor 1012, and a third transistor 1013. The first transistor 1011 is configured to receive a first input signal 1014 and a second input signal 1015, and generate a first output signal 1016. The second transistor 1012 is configured to receive the first output signal 1016 and a third input signal 1017, and generate a second output signal 1018. The third transistor 1013 is configured to receive the second output signal 1018 and a fourth input signal 1019, and generate a third output signal 1020. The first input signal 1014 can be a voltage signal, and the second input signal 1015 can be a current signal. The third input signal 1017 can be a voltage signal, and the fourth input signal 1019 can be a current signal. The first output signal 1016 can be a voltage signal, and the second output signal 1018 can be a current signal. The third output signal 1020 can be a voltage signal. Figure 3In the illustrated example, the voltage limiter circuit 101 is implemented within the write driver 102 and is coupled as a first node of the low active negative bit line NBLB C 302. The write driver 102 also includes a capacitor 301 configured to provide a transition of the negative bit line voltage over a period of time. The voltage limiter circuit 101 can control the magnitude of the negative bit line voltage such that the magnitude does not exceed a predetermined threshold, but is not limited to being below a magnitude necessary to perform a write operation in a memory cell, such as an SRAM cell. Several different embodiments of the voltage limiter circuit 101 are disclosed in this example, all of which are within the scope of the present invention.

[0032] The example can be further understood in connection with a discussion of a write operation Figure 3 After the clock signal 202 rises, the WRITEB T 105 can become a logic low (“0”). If the data to be written, LDATA, is at a logic high (“1”) at this time, the A LD 310 will also be at a logic high (“1”). Conversely, the A LDB will be at a logic low (“0”). As a result, the output of the logic (NOR (not OR)) gate 312 will be at a logic low (“0”), and the transistor MN1 307 will be disabled. However, the output of the logic (NOR) gate 313 will be at a logic high (“1”), and the transistor MN2 308 will be enabled. As a result, the second low active negative bit line BLB 109 will be at a logic low (“0”), as the second low active negative bit line BLB 109 will be coupled to the ground source node NVSS 306. In some cases, a negative voltage is applied to this node NVSS 306 to increase the gate-to-source voltage of the pass gate transistors (314, 315) to perform a write operation. The negative voltage can be generated using the negative bit line input signal NBL 104. As the NBL 104 becomes a logic high (“1”), the first node NBLB C 302 on the low active negative bit line will drop to a logic low (“0”). As a result, the negative voltage will be coupled to the ground source node NVSS 306. The magnitude of the negative voltage coupled to the ground source node NVSS 306 can depend on the value of the capacitor 301.

[0033] During some operations, a memory can operate at a high voltage level. For example, the memory can be used in a microprocessor. As understood by one of skill in the art, during some operations, a processor can have increased processing demands. This can be the case when the processor is operating in an application that involves many calculations, such as the operation of a video game. During such increased demands, the processor can operate at a high frequency. As understood by one of skill in the art, this can result in an increase in voltage to various components of the processor, such as the memory. Conversely, the processor can have low processing demands. For example, there can be low processing demands when the processor is operating in an application that performs administrative tasks. Such low processing demands can result in a decrease in voltage to components of the processor, such as the memory. A high operating voltage can be, for example, above 0.9 V. A low operating voltage can be, for example, below 0.9 V. Throughout the disclosure, a low operating voltage refers to a memory operating voltage that is below a predetermined value, while throughout the disclosure, a high operating voltage refers to a memory operating voltage that is above a predetermined value. The specific predetermined value can vary depending on the embodiment of the invention being implemented.

[0034] At a high operating voltage, the gate-to-source voltage of the pass gate transistors (314, 315) can be at a level sufficient to perform a write operation. However, the high gate-to-source voltage of the pass gate transistors (314, 315) can decrease the reliability of the memory device. For example, as described above, a long high gate-to-source voltage can result in negative bias temperature instability. The voltage limiter circuit 101 can reduce the magnitude of the negative voltage at the source node NVSS 306 at a high operating voltage of the memory, while not significantly affecting the negative voltage at the source node NVSS 306 at a low operating voltage of the memory. In addition to mitigating reliability issues in the memory device, due to this lower voltage at the higher operating voltage mode, the voltage limiter circuit 101 can also reduce the effective power supply of the SRAM cell.

[0035] Figure 4is a schematic diagram of one embodiment of a voltage limiter circuit 101 according to embodiments. In this embodiment, the voltage limiter circuit 101 includes a diode circuit 401 that can be enabled during a high operating voltage mode of the memory and disabled during a low voltage mode of the memory. In one example, the diode circuit is coupled to a first node NBLB C 302 on a low active negative bit line. This node 302 can be configured to provide a transition of the negative bit line voltage to the negative bit line for a period of time. In one embodiment, the diode circuit 401 includes a transistor 402. A source terminal of this transistor 402 can be coupled to a supply voltage node VDD 111, while a drain terminal of the transistor 402 is coupled to the first low active negative bit line node 302. The diode circuit 401 can be configured to clamp the first node NBLB C 302 at a predetermined threshold voltage. For example, a negative bit line input signal NBL 104 can increase to a logic high ("1") during the beginning of a write operation. Since this negative bit line input signal NBL 104 is coupled to the first node NBLB C 302 through a transistor with an inverting gate terminal, as shown in Figure 4 , this will cause the voltage at the first node NBLB C 302 to decrease. When the voltage at the node NBLB C 302 decreases to a level that generates a differential voltage across the transistor 402 in the diode circuit 401 that satisfies the threshold of the transistor 402, the diode circuit 401 couples the supply voltage VDD 111 to the first node NBLB C 302. In this way, the voltage at the first node NBLB C 302 will be prevented from decreasing below a certain constant value.

[0036] In embodiments of this disclosure, diode circuit 401 is configured to clamp node NBLB_C 302 on the low effective negative bit line at a predetermined voltage level in a high operating voltage mode. In this way, a lower amplitude negative voltage is coupled at ground source node NVSS 306 in the high operating voltage mode. The value of this predetermined voltage level may depend on the size and threshold voltage of transistor 402 within diode circuit 401 and a second separate transistor 403 also coupled to the first node 302 on the low effective negative bit line. With the voltage clamped at the first node NBLB_C 302, the amplitude of the negative voltage at ground source node NVSS 306 is reduced. This is because the voltage at the anode of capacitor 301 will be clamped at a higher level, and therefore the voltage drop across capacitor 301 will result in a higher voltage at the cathode of capacitor 301 than would be without diode circuit 401. Because the cathode of capacitor 301 is directly coupled to the ground source node NVSS 306, the voltage at the ground source node will be at a higher level, or the amplitude of the negative voltage at the ground source node NVSS 306 will be lower in the presence of diode circuit 401. The amount by which the amplitude of the negative voltage at the ground source node NVSS 306 can be reduced by diode circuit 401 can be determined by many factors, such as the characteristics of capacitor 301, transistor 402, and transistor 403. The appropriate characteristics of these components can be determined using simulation and calculation, such as in... Figure 6 As further described in the discussion. For example, at a high operating voltage of 1.2V, the magnitude of the negative voltage at the ground source node NVSS306 can be reduced to approximately -150mV. However, at a low operating voltage, such as 0.6V, diode circuit 401 can be disabled, and the voltage at node NBLB_C can be at a voltage level of approximately -100mV.

[0037] Figure 5 This is a timing diagram of the waveforms of the negative bit line input signal NBL 104, the voltage at the first negative bit line node NBLB_C 302, the voltage at the second negative bit line node 303, and the voltage at the ground source node NVSS 306, according to an embodiment. Figure 5 In the example shown, the negative bit line input signal NBL 104 begins to rise. For example, the negative bit line input signal NBL 104 may begin to rise after the control circuit 106 indicates the start of a write operation. For example, the write operation may be initiated by a signal from a user device with implemented memory circuitry, or it may be automatically initiated depending on the application. After the negative bit line input signal begins to rise, the voltage of the first negative bit line node NBLB_C 302 begins to decrease. This is because the negative bit line signal NBL 104 is coupled to the inverting gate terminal of transistor 404, which is also coupled to the first negative bit line node NBLB_C 302, as... Figure 4is shown. Thus, when the negative bit line input signal NBL 104 increases to a logic high ("1"), the transistor 404 stops coupling voltage from the supply voltage VDD 111 to the first node NBLB_C 302, causing the voltage at this first node NBLB_C 302 to decrease. The voltage at the first negative bit line node NBLB_C 302 can decrease for a longer period of time than the negative bit line input signal rises due to the influence of the capacitor 301. The voltage at the second negative bit line node NBLB_N 303 can also decrease after the negative bit line input signal NBL 104 rises because this second node 303 is coupled to a transistor whose gate terminal is coupled to the inverted negative bit line input signal NBL 104. Thus, when the negative bit line input signal NBL 104 increases to a logic high ("1"), the transistor stops coupling voltage from the supply voltage VDD 111 to the second negative bit line node NBLB_N 303, causing the voltage at this second node NBLB_N 303 to decrease. The ground source node NVSS 306 is also shown in Figure 5 Because the diode voltage limiter circuit 401 clamps the node of the low effective negative bit line NBLB_C 302 at a predetermined voltage level, the magnitude of the voltage at the ground source node NVSS 306 is limited as a result. In one example, the magnitude of the voltage at the ground source node NVSS 306 is limited because the diode circuit 401 is configured to clamp the magnitude of the voltage at the node NBLB_C 302, as described above. Thus, the voltage drop from this node 302 caused by the capacitor 301 can also cause the voltage at the ground source node NVSS 306 to be limited. In this example, the voltage at NVSS 306 is limited to not decrease below -150 mV at a memory operating voltage of 1.2 V.

[0038] Figure 6 is a flowchart of determining appropriate sizes of the individual transistors MN-a 403 and MPD transistor 402 according to embodiments. The first step 601 of determining appropriate sizes of the MN-a 403 and MPD 402 transistors is determining the negative voltage at the bit line required for a successful write operation. These can be determined by Monte Carlo simulation, as understood by one skilled in the art. The second step 602 of determining appropriate sizes of the MN-a 403 and MPD 402 transistors is determining the voltage drop across the resistance 304 of the first bit line 108 and the voltage drop across the resistance 305 of the second low effective negative bit line 109. The second step 602 also includes determining the voltage drop across the MN1 transistor 307, and the voltage drop across the MN2 transistor 308. The third step 603 is determining the value of the capacitor 301 to use based on the negative voltage required at the ground source voltage node NVSS 306. This determination involves the equation V NVSS = Vneg +V1+V2, where V1 and V2 are determined by the second step. The fourth step 604 involves determining the dimensions and threshold voltages of the MPD 402 and MN-a 403 transistors. This can be achieved using simulation to obtain the desired low and high voltages at NVSS 306.

[0039] Figure 7 This is a detailed diagram of a memory architecture embodiment in an SRAM cell according to an embodiment. The memory architecture may include latch 204, clock 201, data latch 107, control circuitry 106, write driver 102, and memory array 110. For example... Figure 7 As shown, control circuitry 106 is configured to receive clock signal 202 from clock 201, address signal 203 from latch 204, and generate negative bit-line input signal NBL 104 and one or more write signals (105, 111). Each write driver (102, 112) can be configured to receive negative bit-line input signal NBL 104 and write signals (105, 111), and generate a negative bit-line voltage to one of the two bit lines (108, 109) of the corresponding memory array 110. Write driver 102 can also be configured to receive data signal 103 from data latch 107, high voltage signal HV 705, and multiple voltage threshold selection signals 702. Figure 7 In this embodiment, the high voltage signal HV 705 is used to indicate whether the SRAM cell is operating in a high operating voltage mode or a low operating voltage mode. For example, the high voltage signal HV 705 can be set to logic high ("1") when the operating voltage of the SRAM cell is higher than a predetermined value, and set to logic low ("0") when the operating voltage of the SRAM cell is lower than the predetermined value. Multiple voltage threshold selection signals 702 can be used to set the voltage level at the negative bit line node, as in... Figure 9 As described in the discussion.

[0040] A write decoder within the control circuit 106 can be configured to decode the address signal 203 and generate one or more write signals 105. In one example, one write signal, WRITEB_T 105, is enabled to access the top memory array 110, and another write signal, WRITEB_B 111, is enabled to access the bottom memory array 113. A data signal, LDATA 103, from the data latch 107 can determine the data (i.e., “0” or “1”) to be written to the memory cell. The write driver 102 includes a voltage limiter circuit 701 that can be configured to control the voltage at the first node of the negative bit line (108, 109). For example, the voltage limiter circuit 701 can be configured to limit the amplitude of the negative bit line voltage on one of the two bit lines (108, 109) of the memory cell such that the amplitude does not exceed a predetermined threshold, as discussed in the discussion of the example of Figure 8 .

[0041] Figure 8 is a diagram of an embodiment of a memory architecture according to an embodiment in which the voltage limiter circuit is a PMOS voltage limiter circuit 701. The PMOS voltage limiter circuit 701 can limit the amplitude of the negative bit line voltage on one of the two bit lines (108, 109) by first limiting the amplitude of the voltage at the first node NBLB_C 302. When the voltage at the first node NBLB_C 302 is limited, this will also limit the voltage at the ground source node 306 after the voltage drop across the capacitor 301. The ground source node NVSS 306 can be coupled to one of the two bit lines (108, 109), as shown in Figure 8 , and thus also limits that voltage. The PMOS voltage limiter circuit 701 can be coupled to the negative bit line that is configured to clamp the NBLB_C 302 voltage at a voltage lower than the supply voltage VDD 111. The voltage limiter circuit 701 can also be coupled to the supply voltage node VDD 111 and receive a high voltage signal HV 705 and a plurality of voltage threshold selection signals 702.

[0042] can be further understood in conjunction with the discussion of the example of a write operation Figure 8After the clock signal 202 rises, WRITEB_T 105 can become logic low (“0”). If the data to be written, LDATA, is at logic high (“1”) at this time, A_LD 310 will also be at logic high (“1”). Conversely, A_LDB will be at logic low (“0”), because LDATA 103 is coupled to a buffer, and A_LDB is the inverted output of that buffer. Thus, the output of logic (NOR) gate 312 will be at logic low (“0”), and transistor MN1 307 will be disabled. However, the output of logic (NOR) gate 313 will be at logic high (“1”), and transistor MN2 308 will be enabled. Thus, the second low- effective negative bit line BLB 109 will be at logic low (“0”), because it will be coupled to ground source node NVSS 306. In some cases, a negative voltage is applied to this node NVSS 306 to increase the gate-to-source voltage of the pass-gate transistors (314, 315) to perform a write operation. This negative voltage can be generated using negative bit line input signal NBL 104. As NBL 104 becomes logic high (“1”), the first node NBLB_C 302 on the low- effective negative bit line will drop to logic low (“0”). Thus, a negative voltage will be coupled to ground source node NVSS 306. The magnitude of the negative voltage coupled to ground source node NVSS 306 can depend on the value of capacitor 301.

[0043] During some operations, the memory can operate at a high voltage level. For example, there can be a high operating voltage when the memory performs many operations at a high frequency. At a high operating voltage, the gate-to-source voltage of the pass-gate transistors (314, 315) can be at a level sufficient to perform a write operation. For example, because the source terminal of pass-gate transistor 314 is coupled to negative bit line 109, which can be at a high magnitude of negative voltage, the gate-to-source voltage of pass-gate transistor 314 can be sufficient, causing the voltage between the gate terminal and the source terminal of pass-gate transistor 314 to also be at a high level. However, the high gate-to-source voltage of pass-gate transistor 314 can reduce the reliability of the memory device, as further discussed in the description of Figure 3 PMOS voltage limiter circuit 701 can reduce the magnitude of the negative voltage at ground source node NVSS 306 at high operating voltages of the memory, without significantly affecting the negative voltage at source node NVSS 306 at low operating voltages of the memory. In addition to mitigating reliability issues in the memory device, the voltage limiter circuit 101 can also reduce the effective power supply of the SRAM cell as a result of the reduced voltage on the corresponding bit line (108, 109). For example, the effective power supply can be reduced by reducing the power consumed by the bit line resistances (304, 305) as a result of the reduced voltage on the corresponding bit line (108, 109).

[0044] Figure 9 is a detailed diagram of an embodiment of the PMOS voltage limiter circuit 701 according to an embodiment. In Figure 9 In an embodiment, the PMOS voltage limiter 701 circuit includes an array of transistors. In one embodiment, the array of transistors includes a first column of transistors 903, a second column of transistors 904, and a third column of transistors 905. The PMOS voltage limiter circuit can receive a plurality of voltage threshold select signals (906, 907). For example, voltage threshold select signals SEL[0] 906 and SEL[1] 907 can be used as inputs to a logic (AND) gate 917. The output of the logic (AND) gate 917 can be inverted and used as an inverted gate terminal to a transistor 908 in the first column of transistors 903. In an embodiment of the disclosure, the first column of transistors 903 further includes a metal resistor 902 coupled in series with the transistor 908. The voltage threshold select signal SEL[0] 906 can also be used as an inverted input to a transistor gate terminal within the second column of transistors 904. The source terminal of the transistor receiving SEL[0] 906 can be coupled to the drain terminal of another transistor in the second column of transistors 904. In the third column of transistors 905, SEL[1] 907 can be received at the gate terminal of another transistor. The source terminal of the transistor receiving SEL[1] 907 can be coupled to the drain terminal of a second transistor within the third column of transistors 905. The source terminal of the second transistor can be coupled to an inverted input to the gate terminal of the same transistor. The source terminal of the transistor can be coupled to the drain terminal of a third transistor within the third column of transistors 905. The source terminal of the third transistor can be coupled to an inverted input to the gate terminal of the same transistor. The source terminal of the third transistor within the third column of transistors 905 can also be coupled to a VAST voltage node 909. In Figure 9 In the example shown, the VAST voltage node 909 is also coupled to a second transistor within the second column of transistors 904 and to the metal resistor 902 within the first column of transistors 903.

[0045] In examples of the present disclosure, the PMOS voltage limiter circuit 701 behaves differently based on the high voltage signal HV 705 and the voltage threshold selection signal (906, 907). For example, during low voltage memory operation conditions (e.g., memory operation voltages less than or equal to 0.9V), the high voltage signal HV 705 is set to low (“0”) and the circuit behaves as if no voltage limiter circuit is present. This is because the high voltage signal HV 705 is coupled to the inverting gate input at transistor 910 which is directly coupled to the VAST node 909. However, during high voltage memory operation conditions (e.g., memory operation voltages greater than 0.9V), the high voltage signal HV 705 is set to high (“1”). In this case, the transistor 911 coupled to the high voltage signal HV 705 through a buffer will be enabled and will determine the voltage at the VAST node 909 based on the setting of the voltage threshold selection signal SEL[1:0], as further described in the discussion of Figure 12 .

[0046] Figure 10 is a timing diagram of waveforms of the negative bit line input signal NBL 104, the voltage of the first negative bit line node NBLB_C 302, the voltage at the second negative bit line node NBLB_N 303, and the voltage at the ground source node NVSS 306 according to an embodiment. In the example shown in Figure 10 , the negative bit line input signal NBL 104 begins to rise. For example, the negative bit line input signal NBL 104 can begin to rise after the control circuit 106 indicates the start of a write operation. After the negative bit line input signal NBL 104 begins to rise, the voltage of the first negative bit line node NBLB_C 302 begins to decrease. This is because the negative bit line input signal NBL 104 is coupled to the inverting gate terminal of the transistor 404, which is also coupled to the first negative bit line node NBLB_C 302, as further described in the discussion of Figure 4as shown. Thus, when the negative bit line input signal NBL 104 increases to a logic high ("1"), the transistor 404 stops coupling voltage from the supply voltage VDD 111 to the first node NBLB_C 302, causing the voltage at the first node NBLB_C 302 to decrease. The voltage at the first negative bit line node NBLB_C 302 decreases over a longer period of time than the negative bit line input signal NBL 104 increases due to the action of the capacitor 301. The voltage at the second negative bit line node NBLB_N 303 also decreases after the negative bit line input signal NBL 104 increases because the second node NBLB_N 303 is coupled to a transistor whose gate terminal is coupled to the inverted negative bit line input signal NBL 104. This is because when the negative bit line input signal NBL 104 increases to a logic high ("1"), the transistor stops coupling voltage from the supply voltage VDD 111 to the second negative bit line node NBLB_N 303, causing the voltage at the second node NBLB_N 303 to decrease. The ground source node NVSS 306 is also shown in Figure 10 Because the PMOS voltage limiter circuit 701 clamps the first node NBLB_C 302 of the low- effective negative bit line at a predetermined voltage level, the magnitude of the ground source node voltage NVSS is limited as a result. This is because the ground source node NVSS 306 is coupled to the first node NBLB_C 302 through the capacitor 301, and there can be a constant voltage drop across the capacitor 301. In this example, the ground source node NVSS voltage is limited to not decrease below -200 mV at a memory operating voltage of 1.2 V. In this example, a memory operating voltage of 1.2 V represents a high memory operating voltage.

[0047] Figure 11is a timing diagram of the operation of the PMOS voltage limiter circuit 701 during the low operating voltage mode according to an embodiment. During the low operating voltage mode, the high voltage signal HV 705 is set to “0” and the voltage at the ground source node NVSS is the same as when the voltage limiter circuit is not present. This is because the VAST voltage is equal to the voltage at the supply voltage node VDD 111. When the negative bit line input signal NBL 104 rises, the VAST voltage node 902 will fall to a logic low (“0”). This is because the high voltage signal HV 705 is coupled to the inverting gate terminal of the transistor 910. Thus, when the high voltage signal HV 705 is at a logic low (“0”), the transistor 910 will conduct and effectively short the circuit to the VAST voltage node 909. Due to the influence of the capacitor 301, the VAST voltage node 909 will fall slower than the second negative bit line node NBLB N. When the high voltage signal HV 705 becomes a logic low, the capacitor 301 will start to discharge and thus the VAST voltage node coupled to the capacitor 301 will decrease at a rate dependent on the time constant of the capacitor 301, as understood by those skilled in the art. This is demonstrated in Figure 8 .

[0048] Figure 12 is a table 1200 showing the relationship between the voltage threshold select signal 702 and the VAST voltage of the PMOS voltage limiter circuit 701 when the HV 705 is set to a value of 1 according to one embodiment of the disclosure. In one example, when SEL[0] is 0 and SEL[1] is also 0, the VAST voltage can be between 0.8 and 1 V. In another example, when SEL[0] is 0 and SEL[1] is 1, the output of the inverting logic (AND) gate of the PMOS voltage limiter circuit is enabled and thus the first column of transistors 903 with the metal resistor 902 is disabled. The second column of transistors 904 is enabled due to receiving SEL[0] at the inverting gate terminal of the transistors in the second column of transistors 904. However, in this example, the third column of transistors 905 is disabled due to receiving SEL[1] at the inverting gate terminal of the transistors at a high value. In Figure 12In the example shown, in the case where SEL[0] is 0 and SEL[1] is 1, the VAST voltage can be 1.0 V. In another example of operation of the PMOS voltage limiter circuit 701, SEL[0] can be set to 1 and SEL[1] can be set to 0. In this case, the VAST voltage can be 0.8 V. In another example, when SEL[0] is 1 and SEL[1] is also 1, the VAST voltage can be determined by the resistance value. This is because the second column of transistors 904 and the third column of transistors 905 receive the respective voltage threshold selection signals 702 as inverted inputs to the gate terminals of the transistors in each column. However, SEL[0] and SEL[1] are both set to 1, which disables the output of the inverting AND gate, which is received as an inverted input at the gate terminal within the first column of transistors 903, which is coupled in series with the metal resistor 902. In one example, when both voltage threshold selection signals are set to 1, the VAST voltage can be 1.1 V.

[0049] The size of each PMOS and the number of PMOS in the PMOS voltage limiter circuit 701 can be modified based on the selected design. For example, the size of each PMOS can be the same in one embodiment and different in another embodiment. In another embodiment, the columns of the PMOS voltage limiter circuit 701 can all include metal resistors. For example, the middle column that can be enabled when SEL[0] is set to 0 can include one or more PMOS. The right column that can be enabled when SEL[1] is set to 0 can include one or more PMOS.

[0050] Figure 13This is a diagram of one embodiment of a voltage limiter circuit (NMOS voltage limiter circuit 1301) according to an embodiment of the present disclosure. In one embodiment of the present disclosure, the NMOS voltage limiter circuit 1301 is coupled to a first negative bitline input node NBLB_C 302. The NMOS voltage limiter circuit 1301 can be configured to receive a plurality of voltage threshold selection signals 1303 and a high voltage signal HV 1302, which is enabled during high-voltage operating mode. The NMOS voltage limiter circuit 1301 can be implemented in a write driver 102 to clamp the first node NBLB_C 302 at a predetermined voltage level. Node 302 can be configured to provide a transition of negative bitline voltage over a period of time. In one example, the predetermined voltage level is a level less than the supply voltage VDD 111. For example, in high operating voltage mode, the supply voltage VDD 111 can be 1.2V. However, the NMOS voltage limiter circuit 1301 can be configured to provide a voltage drop between the supply voltage VDD 111 and the first node NBLB_C 302. In one example, this voltage drop can be 200mV. Therefore, the voltage at the first node NBLB_C 302 can be 1.0V. This value is obtained by subtracting the 200mV voltage drop from the 1.2V supply voltage VDD 111. Therefore, when the voltage at the first node 302 decreases as the negative bit input signal NBL 104 rises, the voltage at the first node 302 will only decrease by 1.0V from 1.0V to 0V. This reduction in the magnitude of the voltage drop at the first node 302 can cause a lower magnitude of the negative voltage at the ground source node 306. For example, in the above example where the supply voltage VDD 111 is 1.2V and the voltage drop across the NMOS voltage limiter circuit 1301 is 200mV, the voltage at the ground source node NVSS 306 can have a magnitude of -100mV. In contrast, when the first node NBLB_C 302 is not clamped to a voltage lower than the supply voltage VDD 111 and the first node NBLB_C 302 is at 1.2V, the voltage at the ground source node NVSS 306 can have a magnitude of -200mV. As those skilled in the art will understand, the exact value of the voltage at the ground source node NVSS 306 can also be a function of the capacitance of capacitor 301.

[0051] Figure 14 According to the embodiments Figure 13A detailed diagram of the NMOS voltage limiter circuit 1301 is shown. In embodiments of the present disclosure, the NMOS voltage limiter circuit 1301 includes a first column of transistors 1406 and a second column of transistors 1407. In one example, the high voltage signal HV 1302 can be used as an input to a logic (AND) gate 1401. The negative bit line input signal NBL 104 can be coupled to a buffer 1409, and the output of the buffer 1409 can be inverted and used as another input to the logic (AND) gate 1401. The output of the logic (AND) gate 1401 can be coupled to a gate terminal of a first transistor MN1 1408. In Figure 14 In the example shown, the transistor MN1 1408 is coupled to the drain terminals of the transistors in the first column of transistors 1406 and the second column of transistors 1407. A voltage threshold selection signal SEL[0] 1404 can be received at the gate terminals of the transistors within the first column of transistors 1406. Similarly, a voltage threshold selection signal SEL[1] 1405 can be received at the gate terminals of the transistors within the second column of transistors 1407. In Figure 14 In the example shown, the source terminals of each of these transistors can be coupled to the VAST voltage node 1402. The drain terminals of these transistors can be coupled to the source terminals of additional transistors within the respective columns (1406, 1407).

[0052] Figure 14The operation of the voltage limiter circuit 1301 shown in FIG. 13 can be as follows. During a low voltage mode of operation, the high voltage signal HV 1302 is set to low (“0”), and the MN1 transistor 1408 is disabled. Thus, the circuit behaves the same as without the voltage limiter circuit. During a high voltage mode of operation, the high voltage signal HV 1302 is set to high (“1”). As the high voltage signal HV 1302 is set to 1, the MN1 transistor 1408 is enabled when the negative bit line input signal NBL 104 is set to logic low (“0”). In this case, based on the voltage threshold selection signals SEL[0] 1404 and SEL[1] 1405, the voltage value of the VAST node 1402 is determined by the ratio of the size of the MP1 1403 to the diode size. In embodiments of the disclosure, the size and number of NMOS transistors can vary depending on the design. The size of each NMOS transistor can be different or the same depending on the particular design and application of the circuit. Further, the number of NMOS transistors in each path can be different or the same. For example, there can be more transistors or larger transistors in the third column of transistors 905 when the design requires a relatively lower voltage at the VAST node 1402 when SEL[1] is at logic low (“0”). In contrast, there can be fewer transistors or smaller transistors in the third column of transistors 905 when the design requires a relatively higher voltage at the VAST node 1402 when SEL[1] is at logic low (“0”).

[0053] Figure 15 is a timing diagram showing the relationship between the negative bit line input signal 104, the voltage at the first node 302 configured to provide a transition of the negative bit line for a period of time, the voltage at the second node NBLB_N 303 of the low effective negative bit line, and the ground source node 306 according to an embodiment. In Figure 15 In the example shown, the negative bit line input signal rises. For example, the negative bit line input signal NBL 104 can begin to rise after the control circuit 106 indicates the start of a write operation. After the negative bit line input signal begins to rise, the voltage at the first node 302 configured to provide a transition of the negative bit line for a period of time begins to decrease. This is because the negative bit line input signal NBL 104 is coupled to the inverting gate terminal of the transistor 1403, which is also coupled to the first negative bit line node NBLB_C 302, as shown in FIG. 13. As the negative bit line input signal NBL 104 rises, the voltage at the first node 302 configured to provide a transition of the negative bit line for a period of time decreases. Figure 14The first node NBLB_C 302 is coupled to the supply voltage VDD 111 through transistor 1403. The second node NBLB_N 303 is coupled to ground through transistor 1404. The NMOS voltage limiter circuit 1301 is enabled when the negative bit line input signal NBL 104 is at a logic low (“0”). When the negative bit line input signal NBL 104 is at a logic low, the NMOS voltage limiter circuit 1301 is disabled. When the NMOS voltage limiter circuit 1301 is disabled, the first node NBLB_C 302 is coupled to the supply voltage VDD 111 through transistor 1403. The second node NBLB_N 303 is coupled to ground through transistor 1404. Thus, when the negative bit line input signal NBL 104 increases to a logic high (“1”), the transistor 1403 stops coupling the voltage from the supply voltage VDD 111 to the first node NBLB_C 302, causing the voltage at the first node NBLB_C 302 to decrease. Thereafter, the voltage at the second node NBLB_N 303 of the low active negative bit line begins to decrease. The ground source node NVSS subsequently decreases, but in this example, the NMOS voltage limiter circuit 1301 is limited at -200 mV due to the voltage limiter circuit 1301. Figure 15 The operating voltage shown in the middle is 1.2V, which is considered as a high operating voltage mode in this disclosure.

[0054] Figure 16 Table 1600 according to one embodiment of the disclosure, which shows the relationship between the voltage threshold selection signal 1303 of the NMOS voltage limiter circuit 1301 and the VAST voltage when HV is set to 1. In one example, when SEL[0] is 0 and SEL[1] is also 0, the first and second column transistors in the NMOS voltage limiter circuit are disabled. Thus, the VAST voltage is 1.2V, which is the same as the operating voltage of the present invention. In another example, when SEL[0] is 0 and SEL[1] is 1, the second column transistor 1407 is enabled, and the VAST voltage can be clamped at a voltage of 1.0V. In another example, when SEL[0] is 1 and SEL[1] is 0, the first column transistor 1406 is enabled, and the VAST voltage node 1402 can be 0.8V. In another example, when SEL[0] is 1 and SEL[1] is also 1, the VAST voltage can be between 0.8V and 1.0V.

[0055] Figure 17 is a flowchart 1700 of a method of operating a write driver according to one embodiment of the disclosure. In examples of the disclosure, the first step 1701 of operating a write driver is receiving a data signal. The data signal can be, for example, the LDATA 103. The data signal LDATA 103 can be received by the write driver. The second step 1702 is generating a negative bit line voltage. The negative bit line voltage can be generated by, for example, the negative bit line input signal NBL 104. The amplitude of the negative bit line voltage can be limited to not exceed a predetermined value while being allowed to reach a write operation threshold level. The limitation of the amplitude of the negative bit line voltage can be implemented by a voltage limiting circuit, such as the voltage limiter circuit 101 of the present invention. After the negative bit line voltage is generated, the negative bit line voltage can be applied to one of the two bit lines, as shown in the third step 1703.

[0056] The foregoing detailed description discloses a write driver configured to receive a data signal, a write signal, and a negative bit line input signal, and generate a negative bit line voltage for one of two bit lines of a memory cell. The write driver can include a capacitor configured to provide a transition of the negative bit line voltage over a period of time in response to a first node. The write driver can also include a voltage limiter circuit configured to control a voltage at the first node, the voltage limiter circuit configured to limit an amplitude of the negative bit line voltage on the one of the two bit lines of the memory cell such that the amplitude does not exceed a predetermined threshold.

[0057] The voltage limiter circuit can also be configured to limit the amplitude of the negative bit line voltage while allowing the negative bit line voltage to reach a write operation threshold level. The voltage limiter circuit can also be configured to reduce an effective power supply of an SRAM cell in a high operating voltage mode. In one example, the write driver can be coupled to a memory array configured to receive the negative bit line voltage and perform a write operation on the memory cell. The memory array can include one or more transistors and the two bit lines. The write driver can also be coupled to a control circuit configured to generate the negative bit line input signal and the write signal, and a data latch configured to generate a data signal. Each of the two bit lines can also include a pass gate MOSFET (metal oxide semiconductor field effect transistor) configured to transfer the one or more write operation data signals from the write driver to the memory array. The negative bit line voltage increases a gate-to-source voltage of the pass gate MOSFET.

[0058] In one example of the disclosure, the voltage limiter circuit of the write driver includes a diode circuit configured to clamp the first node at a predetermined voltage level. The diode circuit can include a transistor. A source terminal of the transistor is coupled to a supply voltage node. A drain terminal of the transistor is coupled to the low active negative bit line, and the low active negative bit line is coupled to the first node.

[0059] In another example of the disclosure, the voltage limiter circuit of the write driver can include a transistor array configured to receive a plurality of voltage threshold selection signals and clamp a node of a low active negative bit line at one of a plurality of predetermined voltage levels based on the plurality of voltage threshold selection signals, the plurality of predetermined voltage levels each being lower than an operating voltage of an SRAM cell. In one example, the plurality of voltage threshold selection signals can be received at the gate terminals of one or more transistors within the transistor array. The transistor array can be coupled to the low active negative bit line, and the low active negative bit line can be coupled to the first node.

[0060] The foregoing detailed description also discloses a method of operating a write driver in embodiments. In one example, the first step of operating a write driver is receiving a data signal. The next step is generating a negative bit line voltage. The amplitude of the negative bit line voltage is limited to not exceed a predetermined value and to allow reaching a write operation threshold level. The next step in this example is applying the negative bit line voltage to one of two bit lines based on the data signal. The step of limiting the negative bit line voltage amplitude can be done during a high operating voltage mode of an SRAM cell. An additional step of the method can include determining the amplitude of the negative bit line voltage required to perform a successful write operation. The method can result in an effective power reduction of an SRAM cell.

[0061] The foregoing detailed description also discloses a memory circuit. In an example embodiment, the memory circuit includes a memory array including a plurality of transistors and a plurality of bit lines forming a plurality of memory cells. The memory array can be configured to receive one or more write operation data signals and perform a write operation to a memory location. The memory circuit can also include a write driver configured to receive a data signal, a write signal, and a negative bit line input signal and generate one or more write operation data signals including a negative bit line voltage to one of two bit lines of a particular memory cell, the write driver including a capacitor configured to provide a transition of a negative bit line voltage over a period of time and a voltage limiter circuit configured to limit an amplitude of the negative bit line voltage on the one of the two bit lines of the memory cell.

[0062] In one example, each of the foregoing bit lines can also include a pass gate MOSFET configured to transfer the one or more write operation data signals from the write driver to the memory array. The memory circuit can also include a control circuit configured to receive a clock signal and an address signal and generate the negative bit line input signal and the write signal, and a data latch configured to generate the data signal.

[0063] In one embodiment of the disclosure, the voltage limiter circuit can include a diode circuit configured to clamp a node of a low active negative bit line at a predetermined voltage level, thereby limiting the amplitude of the negative voltage coupled to one of the two bit lines not to exceed a predetermined threshold.

[0064] In another embodiment of the disclosure, the voltage limiter circuit can include a transistor array configured to clamp a node of a low significant negative bit line at one of a plurality of predetermined voltage levels, each of the plurality of predetermined voltage levels being lower than an operating voltage of the SRAM cell. In one example, the transistor array is configured to receive a plurality of voltage threshold selection signals and to clamp the node of the low significant negative bit line at one of the plurality of predetermined voltage levels based on the plurality of voltage threshold selection signals.

[0065] The foregoing summarizes features of several embodiments in order that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art will readily understand that they can readily employ the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same results in a manner that involves no more than a modest exercise of their skilled abilities and resources. Those skilled in the art will further appreciate that the concept of equivalence in the disclosure is intended to apply to process steps as well as to structures. Those skilled in the art will also recognize or be able to ascertain using no more than routine experimentation such other processes and structures that they can use for carrying out the embodiments described herein without departing from the spirit and scope of the disclosure.

Claims

1. A write driver configured to receive a data signal, a write signal, and a negative bit line input signal and generate a negative bit line voltage for one of two bit lines of a memory cell, the write driver comprising: A capacitor, in response to a first node, is configured to provide the transition of the negative bit line voltage over a period of time; as well as A voltage limiter circuit is configured to control the voltage at the first node, the voltage limiter circuit being configured to limit the amplitude of the negative bit line voltage on one of the two bit lines of the memory cell, such that the amplitude does not exceed a predetermined threshold. The voltage limiter circuit includes a diode circuit configured to clamp the first node at a predetermined voltage level, or The voltage limiter circuit includes a transistor array configured to receive a plurality of voltage threshold selection signals and clamp nodes of low active negative bit lines at one of a plurality of predetermined voltage levels based on the plurality of voltage threshold selection signals. The amplitude of the restricted negative bit line voltage is not proportional to the operating voltage of the SRAM cell.

2. The write driver according to claim 1, wherein, The voltage limiter circuit is also configured to limit the amplitude of the negative bit line voltage while allowing the negative bit line voltage to reach a write operation threshold level.

3. The write driver according to claim 1, wherein, The voltage limiter circuit is also configured to reduce the effective power supply of the SRAM cell in high operating voltage mode.

4. The write driver according to claim 1, wherein the write driver is coupled to: A memory array configured to receive the negative bit line voltage and perform write operations on the memory cells, the memory array including one or more transistors and the two bit lines; The control circuit is configured to generate the negative bit line input signal and the write signal; as well as A data latch is configured to generate the data signal.

5. The write driver according to claim 4, wherein, Each of the two bit lines also includes a transmission gate MOSFET configured to transmit one or more write operation data signals from the write driver to the memory array.

6. The write driver according to claim 5, wherein, The negative line voltage increases the gate-to-source voltage of the transmission gate MOSFET.

7. The write driver according to claim 1, wherein, When the voltage limiter circuit includes the diode circuit, the diode circuit is enabled in high operating voltage mode and disabled in low operating voltage mode.

8. The write driver according to claim 1, wherein, In the case where the diode circuit includes a transistor array: The source terminal of the transistor is coupled to the supply voltage node; The drain terminal of the transistor is coupled to the low effective negative bit line; and The low effective negative bit line is coupled to the first node.

9. The write driver according to claim 1, wherein, When the voltage limiter circuit includes the transistor array, each of the plurality of predetermined voltage levels is lower than the operating voltage of the SRAM cell.

10. The write driver according to claim 9, wherein: The plurality of voltage threshold selection signals are received at the gate terminals of one or more transistors in the transistor array; The transistor array is coupled to the low effective negative bit line; and The low effective negative bit line is coupled to the first node.

11. A method for operating a write drive, comprising: Receive data signals; Generate a negative bit line voltage, wherein the amplitude of the negative bit line voltage is limited to not exceeding a predetermined value and is allowed to reach a write operation threshold level; and The negative bit line voltage is applied to one of the two bit lines based on the data signal. The amplitude of the restricted negative bit line voltage is not proportional to the operating voltage of the SRAM cell.

12. The method according to claim 11, wherein, The step of limiting the amplitude of the negative bit line voltage is performed during the high operating voltage mode of the SRAM cell.

13. The method of claim 11, further comprising determining the magnitude of the negative bit line voltage required to perform a successful write operation.

14. The method of claim 12, wherein the method reduces the effective power supply of the SRAM cell.

15. A memory circuit, comprising: A memory array, comprising a plurality of transistors and a plurality of bit lines forming a plurality of memory cells, the memory array being configured to receive one or more write operation data signals and perform write operations on memory locations; as well as A write driver is configured to receive a data signal, a write signal, and a negative bit line input signal, and to generate one or more write operation data signals including a negative bit line voltage to one of the two bit lines of a specific memory cell. The write driver includes a capacitor configured to provide a transition of the negative bit line voltage over a time period and a voltage limiter circuit configured to limit the amplitude of the negative bit line voltage on one of the two bit lines of the memory cell. The voltage limiter circuit includes a diode circuit configured to clamp the node of the low effective negative bit line at a predetermined voltage level, thereby limiting the amplitude of the negative voltage coupled to one of the two bit lines to not exceed a predetermined threshold. The voltage limiter circuit includes a transistor array configured to clamp a node of a low effective negative bit line at one of a plurality of predetermined voltage levels. The amplitude of the restricted negative bit line voltage is not proportional to the operating voltage of the SRAM cell.

16. The memory circuit according to claim 15, wherein, Each of the one or more bit lines further includes a transmission gate MOSFET configured to transmit the one or more write operation data signals from the write driver to the memory array.

17. The memory circuit according to claim 15, wherein the memory circuit further comprises: The control circuit is configured to receive a clock signal and an address signal and generate the negative bit input signal and the write signal; as well as A data latch is configured to generate the data signal.

18. The memory circuit of claim 15, wherein, when the voltage limiter circuit includes the diode circuit, the diode circuit is enabled in a high operating voltage mode and disabled in a low operating voltage mode.

19. The memory circuit according to claim 15, wherein, When the voltage limiter circuit includes the transistor array, each of the plurality of predetermined voltage levels is lower than the operating voltage of the SRAM cell.

20. The memory circuit according to claim 19, wherein, In the case where the voltage limiter circuit includes a transistor array, the transistor array is configured to receive a plurality of voltage threshold selection signals and clamp the node of the low effective negative bit line at one of the plurality of predetermined voltage levels based on the plurality of voltage threshold selection signals.

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