Control circuit of a memory device

Abstract

The present disclosure relates to control circuitry for memory devices. A circuit includes a tracking word line, a power switch, a tracking bit line, a sense circuit. The power switch is coupled between the tracking word line and a first node. The power switch is configured to discharge a voltage level on the first node in response to a clock pulse signal sent to the power switch through the tracking word line. The tracking bit line is coupled between the first node and a plurality of tracking cells in a memory array. The sense circuit is coupled between the first node and a second node. The sense circuit is configured to generate a negative bit line enable signal in response to the voltage level on the first node being below a threshold voltage value of the sense circuit.

Description

Technical Field

[0001] This disclosure generally relates to control circuits for memory devices. Background Technology

[0002] Static random access memory (SRAM) is commonly used in integrated circuits. Embedded SRAM is particularly popular in high-speed communications, image processing, and system-on-a-chip (SoC) applications. SRAM cells have the advantage of storing data without needing to be refreshed. Typically, an SRAM cell includes two transmission gate transistors, through which bits can be read from or written to the SRAM cell.

[0003] The lowest VDD voltage (high supply voltage) at which an SRAM bit cell can function is called Vccmin. A low cell VDD near Vccmin reduces leakage current and also reduces the probability of read flip-flops. On the other hand, a high cell VDD increases the probability of a successful write operation. Therefore, Vccmin is limited by write operations. Summary of the Invention

[0004] According to one embodiment of this disclosure, a circuit is provided, comprising: a tracking word line; a power switch coupled between the tracking word line and a first node, the power switch being configured to discharge a voltage level on the first node in response to a clock pulse signal transmitted to the power switch via the tracking word line; a tracking bit line coupled between the first node and a plurality of tracking cells in a memory array; and a sensing circuit coupled between the first node and a second node, the sensing circuit being configured to generate a negative bit line enable signal in response to a voltage level on the first node being lower than a threshold voltage value of the sensing circuit.

[0005] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a write driver configured to provide bit line voltages and two's complement bit line voltages to a memory array; a write auxiliary circuit coupled to the write driver, the write auxiliary circuit being configured to pull down a voltage level on a bit line or a two's complement bit line to a transient negative voltage level in response to a negative bit line trigger signal; and a timing control circuit coupled to the write auxiliary circuit, wherein the timing control circuit includes a tracking word line related to a first delay on a word line in the memory array and a tracking bit line related to a second delay on a bit line in the memory array, the timing control circuit being configured to generate the negative bit line trigger signal in response to a clock pulse signal, with reference to the first delay and the second delay.

[0006] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: transmitting a clock pulse signal via a tracking word line; discharging a voltage level on a first node coupled to a tracking bit line in response to the clock pulse signal; generating a negative bit line enable signal in response to a voltage level on the first node being lower than a threshold voltage value of a sensing circuit; and generating a negative bit line trigger signal based on the negative bit line enable signal. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a schematic diagram illustrating a memory device according to various embodiments of the present disclosure.

[0009] Figure 2 This illustrates some embodiments. Figure 1 Example diagram of the structure of the bit cell, write driver, selection circuit and write auxiliary circuit.

[0010] Figure 3 This illustrates some embodiments. Figure 1 Example diagram of the structure of timing control circuit and related components.

[0011] Figure 4 This illustrates some embodiments. Figure 3 The signal waveform diagram showing the relationship between time and voltage levels on relative signals in a timing control circuit.

[0012] Figure 5 This is a waveform diagram illustrating the relationship between time and voltage levels on a relative signal in another example of a write operation failure according to some embodiments.

[0013] Figure 6A This illustrates some embodiments. Figure 1 A layout diagram of the memory device.

[0014] Figure 6B This is another layout diagram illustrating another layout of a memory device according to some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. The use of examples in this specification (including examples of any terms discussed herein) is merely illustrative and in no way limits the scope and meaning of this disclosure or any exemplary terminology. Similarly, this disclosure is not limited to the various embodiments given in this specification.

[0017] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of the embodiments, and similarly, a second element may be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed entries.

[0018] As used herein, the terms “including,” “contains,” “have,” “includes,” “involves,” etc., should be understood as open-ended, meaning including but not limited to.

[0019] Throughout this specification, references to "an embodiment," "an embodiment," or "some embodiments" indicate that a particular feature, structure, implementation, or characteristic described in connection with one or more embodiments is included in at least one embodiment of this disclosure. Therefore, the use of the phrases "in one embodiment," "in an embodiment," or "in some embodiments" in various places throughout the specification does not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, implementations, or characteristics may be combined in any suitable manner.

[0020] Figure 1This is a schematic diagram illustrating a memory device 100 according to various embodiments of the present disclosure. In some embodiments, digital data is written to bit cells BC11 to BCmn in a memory array CA1 using the memory device 100. This digital data can be stored in bit cells BC11 to BCmn and can be read or accessed by the memory device 100 from bit cells BC11 to BCmn in the memory array CA1.

[0021] like Figure 1 As shown, in some embodiments, the memory array CA1 may include M*N bit cells BC11 to BCmn arranged along M columns and N rows. Bit cells in the same column are connected to the same bit line and the same two's complement bit line. For example, bit cells BC11, BC12...BC1n in the same column are connected to bit line BL1 and two's complement bit line BLB1; bit cells BCm1, BCm2...BCmn in the same column are connected to bit line BLm and two's complement bit line BLBm. Bit cells in the same row are connected to the same word line. For example, bit cells BC11 and BCm1 in the same row are connected to word line WL1; bit cells BC12 and BCm2 in the same row are connected to word line WL2; bit cells BC1n and BCmn in the same row are connected to word line WLn.

[0022] In some embodiments, the write driver 120 is configured to set the bit line voltage VBL and the complement bit line voltage VBLB to predetermined voltage levels based on the digital data to be written into one of the bit cells BC11 to BCmn.

[0023] like Figure 1 As shown, in some embodiments, the selection circuit 170 is configured to connect the bit line voltage VBL and the two's complement bit line voltage VBLB to one of the bit lines BL1-BLm and the two's complement bit lines BLB1-BLBm on a selected column in the memory array CA1. The word line driver 180 is configured to provide word line signals on word lines WL1-WLn on different rows in the memory array CA1.

[0024] For example, when the digital data "0" is to be written into one of the bit cells BC11 to BCmn, the write driver 120 is configured to set the bit line voltage VBL to a low supply voltage (VSS) and the two's complement bit line voltage VBLB to a high supply voltage (VDD). When the digital data "1" is to be written into one of the bit cells BC11 to BCmn, the write driver 120 is configured to set the bit line voltage VBL to VDD and the two's complement bit line voltage VBLB to VSS.

[0025] To reduce leakage current in bit cells BC11-BCmn, it is desirable to set VDD to a low level (or close to Vccmin). When the level of VDD decreases, the voltage difference between VDD and VSS is insufficient to cover the digital data stored in bit cells BC11-BCmn, increasing the probability of write failure. In some embodiments, to achieve a lower VDD and also reduce the probability of write failure, during the write operation, the write assist circuit 140 pulls the low VSS to a transient negative voltage level NVSS. In other words, one of the bit line voltage VBL and the two's complement bit line voltage VBLB is temporarily pulled below ground level by the write assist circuit 140 to the transient negative voltage level NVSS (i.e., NVSS < 0V), thereby ensuring that digital data can be successfully written to the target bit cell.

[0026] Further reference Figure 2 . Figure 2 This illustrates some embodiments. Figure 1 An example diagram of the structure of bit cell BC11, write driver 120, select circuit 170, and write auxiliary circuit 140. (Relative to...) Figure 1 Implementation examples, Figure 2 The same components are labeled with the same reference numerals for easy understanding.

[0027] like Figure 2 As shown, in some embodiments, bit cell BC11 is a static random access memory (SRAM) cell formed by six transistors (6T-SRAM). Note that... Figure 2 The bit cell BC11 shown is an exemplary example, and bit cells BC11 to BCmn are not limited to 6T-SRAM, and bit cells BC11 to BCmn can be formed from other equivalent SRAM bit cells. For the sake of brevity, Figure 2 The write driver 120, selection circuit 170, and write auxiliary circuit 140 shown illustrate a structure related to setting the voltage level on bit line BL1. In some embodiments, the write driver 120, selection circuit 170, and write auxiliary circuit 140 also include similar structures corresponding to the two's complement bit line BLB1 and other bit lines and two's complement bit lines on different columns, and these similar structures are not shown in Figure 2 As shown in the image.

[0028] refer to Figure 1 and Figure 2 The following paragraphs discuss an exemplary write operation of the bit cell BC11 for demonstration purposes. In the exemplary write operation, it is assumed that the memory device 100 is configured to write the digital data "0" to a bit cell such as... Figure 2The storage node BL_in is located in bit cell BC11. During a write operation, word line WL1 is pulled high to turn on transistors Ta and Tb in bit cell BC11, allowing the voltage level on bit line BL1 to reach storage node BL_in. Simultaneously, bit selection transistor 171 in selection circuit 170 is turned on by bit selection signal Ysel to transfer the bit line voltage VBL (provided by write driver 120) to bit line BL1. In this case, to write the digital data "0" into bit cell BC11, write driver 120 is configured to set the bit line voltage VBL to a low level, such as GND or VSS. Figure 2 As shown, the pull-down transistor 122 in the write driver 120 is turned on by the high-level write control signal GW, thereby setting the bit line voltage VBL to a lower level. On the other hand, the pull-up transistor 121 in the write driver 120 is turned off by the write control signal GW. Figure 2 As shown, the write auxiliary circuit 140 is connected to the pull-down transistor 122 of the write driver 120.

[0029] In another exemplary write operation, assume that memory device 100 is configured to write the digital data "1" into the memory node BL_in in bit cell BC11. In such an embodiment, to write the digital data "1" into bit cell BC11, write driver 120 is configured to set the bit line voltage VBL to VDD and the two's complement bit line voltage VBLB to VSS. Bit selection transistor 171 in selection circuit 170 is turned on by bit selection signal Ysel to transfer the bit line voltage VBL (provided by write driver 120) to bit line BL1. Word line WL1 is pulled high to turn on transistors Ta and Tb in bit cell BC1, allowing the voltage on bit line BL1 to be transferred to memory node BL_in.

[0030] As described above, the write assist circuit 140 pulls the bit line voltage VBL to a transient negative voltage level NVSS (NVSS < 0V) to ensure that digital data can be successfully written to the target bit cell. In some embodiments, the write assist circuit 140 is triggered by the falling edge of the negative bit line trigger signal NBLK provided by the timing control circuit 160. Before the falling edge of the negative bit line trigger signal NBLK, the negative bit line trigger signal NBLK is at a high level, and the pull-down transistor switch 141 of the write assist circuit 140 is turned on to couple node NV and the bit line voltage VBL to the 0V ground terminal. When the falling edge of the negative bit line trigger signal NBLK arrives, the write assist circuit 140 is turned off, and the bit line voltage VBL is now floating. The negative bit line trigger signal NBLK is delayed by a delay unit including inverters 142 and 143 to a delayed negative bit line trigger signal NBLKd. A coupling capacitor 144 is disposed between inverter 143 and node NV. In response to the falling edge of the delayed negative bit line trigger signal NBLKd, the coupling capacitor 144 is configured to couple the voltage difference of the falling edge to node NV and pull down the bit line voltage VBL to the transient negative voltage level NVSS.

[0031] Note that in some embodiments, the falling edge of the negative bit-line trigger signal NBLK (and the delayed negative bit-line trigger signal NBLKd) needs to arrive at the correct timing. If the falling edge of the negative bit-line trigger signal NBLK arrives too early or too late, the write assist circuit 140 will not be able to properly pull down the bit line voltage VBL to the transient negative voltage level NVSS, and the write operation may fail. For example, if the falling edge of the negative bit-line trigger signal NBLK arrives too early before the word line WL1 is fully pulled high, the bit line voltage VBL on bit line BL1 will not reach the memory node BL_in in bit cell BC11, and the write operation may fail. If the falling edge of the negative bit-line trigger signal NBLK arrives too late after the word line WL1 is turned off, the bit line voltage VBL on bit line BL1 will also not reach the memory node BL_in in bit cell BC11. If the falling edge of the negative bit line trigger signal NBLK arrives too early before the bit line voltage VBL is fully discharged to ground (i.e., 0V) or sufficiently close to ground, the voltage difference that delays the falling edge of the negative bit line trigger signal NBLKd will not be sufficient to pull the bit line voltage VBL down to the transient negative voltage level NVSS.

[0032] Note that the parameters of memory cell CA1 (such as the number of columns, number of rows, array size, or bit cell size) will differ on each different memory device. It is difficult to apply a fixed timing to provide the negative bit line trigger signal NBLK.

[0033] In some embodiments, timing control circuitry 160 is configured to provide a negative bit line trigger signal NBLK to write auxiliary circuitry 140 at the correct timing, thereby triggering write auxiliary circuitry 140 to provide a transient negative voltage level NVSS.

[0034] Further reference Figure 3 and Figure 4 . Figure 3 This illustrates some embodiments. Figure 1 An example diagram of the structure of the timing control circuit 160 and related components. Figure 4 This illustrates some embodiments. Figure 3 The signal waveform diagram showing the relationship between time and voltage level on the relative signal in the timing control circuit 160. Figure 1 and Figure 2 Implementation examples, Figure 3 and Figure 4 The same components are labeled with the same reference numerals for easy understanding.

[0035] like Figure 3 As shown, the timing control circuit 160 includes word lines in the memory array CA1 ( Figure 1 The tracking word line tWL associated with the first delay on WL1~WLn shown, and the bit line (in memory array CA1) Figure 1 The tracking bit line tBL is associated with the second delay on BL1 to BLm. The timing control circuit 160 is configured to generate a negative bit line trigger signal NBLK in response to the clock pulse signal CKP, with reference to the first and second delays.

[0036] like Figure 3 As shown, in some embodiments, the timing control circuit 160 includes a tracking word line tWL, a power switch 162, a tracking bit line tBL, a sensing circuit 163, and an inverter 164.

[0037] The input terminal of the tracking word line tWL receives the clock pulse signal CKP. In some embodiments, such as Figure 3 and Figure 4 As shown, the clock pulse signal CKP can indicate the start of a write operation, and the clock pulse signal CKP is used by the word line driver 180 to... Figure 1 Word line voltages are provided on the word lines WL1 to WLn shown. For example... Figure 3As shown, in some embodiments, the tracking word line tWL includes a first line segment tWLa, a second line segment tWLb, and a third line segment tWLc connected in series. The second line segment tWLb is connected between the first line segment tWLa and the third line segment tWLc. In some embodiments, the total length of the tracking word line tWL (including the first line segment tWLa, the second line segment tWLb, and the third line segment tWLc) is configured to be similar to the width of M columns in the memory array CA1. In such an embodiment, the signal transmitted through the tracking word line tWL is delayed by the bit cell BCm1, BCm2...BCmn transmitted from the word line driver 180 across the memory array CA1 to one of the bit cells BCm1, BCm2...BCmn on the m-th column (e.g., ...). Figure 1 The signal has a similar delay time as shown in the figure.

[0038] In some embodiments, the length of the first segment tWLa is substantially equal to half the width of the memory array CA1 (i.e., M / 2 columns of the memory array CA1). In some embodiments, the length of the third segment tWLc is also substantially equal to half the width of the memory array. For example, if the memory array CA1 has 32 columns, the length of the first segment tWLa (and the length of the third segment tWLc) is configured to be substantially equal to the width of 16 columns in the memory array CA1. For example, if the memory array CA1 has 128 columns, the length of the first segment tWLa (and the length of the third segment tWLc) is configured to be substantially equal to the width of 64 columns in the memory array CA1. In other words, the length of the first segment tWLa (and the length of the third segment tWLc) is adaptive according to the size of the memory array CA1. The total length of the tracking word lines tWL will be similar to the word lines in the memory array CA1 ( Figure 1 One of the WL1-WLn shown.

[0039] like Figure 3 As shown, the tracking word line signal WLTK can be supplied to the power switch 162 by the tracking word line tWL. This is because the resistive-capacitive (RC) load on the tracking word line tWL is similar to that in the memory array CA1. Figure 1 The word line WL1 in the signal, therefore the tracking word line signal WLTK will be similar to... Figure 4 The signal on word line WL1 is shown.

[0040] Power switch 162 is coupled between the track word line tWL and node N1. Power switch 162 is configured to discharge the voltage level on node N1 according to the track word line signal WLTK. The track word line signal WLTK is generated based on the clock pulse signal CKP transmitted to power switch 162 via the track word line tWL.

[0041] like Figure 3As shown, in some embodiments, the power switch 162 includes a P-type transistor T1 and N-type transistors T2, T3, and T4. All gate terminals of transistors T1-T4 are coupled together to the track word line tWL. Figure 3 and Figure 4 As shown, transistors T1-T4 in power switch 162 are controlled by tracking word line signal WLTK. For example... Figure 4 As shown, when the tracking word line signal WLTK reaches a relatively high level sufficient to turn on transistors T2, T3 and T4 and also sufficient to turn off transistor T1, the tracking bit line signal BLTK on node N1 begins to be discharged by transistors T2, T3 and T4 in power switch 162.

[0042] Note that in some embodiments... Figure 3 The number of transistors T2, T3, and T4 in the power switch 162 is approximately equal to the number of transistors located in the power switch 162. Figure 2 The number of transistors on the discharge path DCP from bit cell BC11 in memory array CA1 to the ground terminal. In other words, transistors T2, T3, and T4 in power switch 162 can be replicated (or simulated). Figure 2 The discharge path DCP in the middle. Figure 3 The number of transistors T2, T3, and T4 in the power switch 162 shown is not limited to three. In other embodiments, if the discharge path DCP from bit cell BC11 in the memory array CA1 to the ground terminal includes more transistors (e.g., four, five, or more) or fewer transistors (e.g., one or two), the power switch 162 may be adjusted accordingly to include the same number of N-type transistors.

[0043] like Figure 3 As shown, in some embodiments, the tracking bit line tBL is coupled between node N1 and tracking cells BCt in the memory array CA1. In some embodiments, the number of tracking cells BCt coupled to the tracking bit line tBL is substantially equal to the number of cell rows in the memory array CA1. For example, if the memory array CA1 comprises 256 rows of bit cells, then the tracking bit line tBL is coupled to a total of 256 tracking cells BCt. In some embodiments, the tracking cells BCt may comprise the same or similar internal structure of the bit cells (see reference). Figure 2 In the bit cell BC11), the tracking bit line tBL coupled to the tracking cell BCt will have a resistive-capacitive (RC) load similar to one of the bit lines BL1 to BLm in the memory array CA1. In this case, as Figure 4 As shown, the discharge rate of the tracking bit line signal BLTK on node N1 can be similar to that of the signals on bit lines BL1-BLm in memory array CA1.

[0044] like Figure 3 As shown, in some embodiments, sensing circuit 163 is coupled between node N1 and node N2. Sensing circuit 163 is configured to generate a negative bit-line enable signal NBLENB at node N2 in response to a voltage level at node N1 falling below a threshold voltage value Vt1 of sensing circuit 163. In some embodiments, such as Figure 3 As shown, the sensing circuit 163 includes a Schmitt trigger. In some embodiments, the Schmitt trigger includes three P-type transistors T5, T6, and T8 and one N-type transistor T7. Figure 3 The Schmitt trigger shown is an exemplary structure of a Schmitt trigger. The sensing circuit 163 is not limited to... Figure 3 The structure of the Schmitt trigger shown is illustrated. The Schmitt trigger includes two threshold voltages (a high threshold voltage and a low threshold voltage). At time TS1, the Schmitt trigger, in response to the voltage level at node N1 falling below the low threshold voltage value Vt1 of the Schmitt trigger, raises the negative bit line enable signal NBLENB (at node N2) from a low level to a high level. In some exemplary embodiments, the low threshold voltage value Vt1 of the sensing circuit 163 is configured to be approximately 15% of the total voltage gap Vd between the high and low levels on the tracking bit line signal BLTK. In other words, when the tracking bit line signal BLTK is below 15% of the total voltage gap Vd, the sensing circuit 163 begins to raise the negative bit line enable signal NBLENB (at node N2).

[0045] like Figure 3 and Figure 4 As shown, in some embodiments, inverter 164 is configured to convert the negative bit line enable signal NBLENB into a negative bit line trigger signal NBLK, and the negative bit line trigger signal NBLK is sent to write auxiliary circuit 140.

[0046] In some embodiments, the timing of the negative bit-line trigger signal NBLK provided by the timing control circuit 160 is adapted to the memory array CA1 because the tracking word line tWL and the tracking bit line tBL vary corresponding to the memory array CA1. As described above, since the negative bit-line trigger signal NBLK is generated with reference to the tracking word line signal WLTK, and the tracking word line signal WLTK is generated by the tracking word line tWL to simulate the time delay of the signal on word line WL1, the negative bit-line trigger signal NBLK can track the time delay of the signal on word line WL1. In addition, since the negative bit-line trigger signal NBLK is generated with reference to the tracking bit line signal BLTK on node N1, the negative bit-line trigger signal NBLK begins to discharge after the tracking bit line signal BLTK falls below the low threshold voltage Vt1 of the Schmitt trigger in the sensing circuit 163. The tracking bit line signal BLTK on node N1 is coupled to the tracking bit line tBL to simulate the resistive-capacitive (RC) load on one of the bit lines BL1 to BLm in the memory array CA1. Therefore, the negative bit-line trigger signal NBLK can track the resistive-capacitive (RC) load on one of the bit lines BL1 to BLm in the memory array CA1. In this case, as... Figure 4 As shown, the falling edge FE1 of the delayed negative bit line trigger signal NBLKd will arrive when the bit line BL1 discharges close to the ground level GND.

[0047] like Figure 2 and Figure 4 As shown, bit line BL1 is discharged to ground level GND via pull-down transistor 122 in write driver 120 and pull-down transistor switch 141 in write auxiliary circuit 140. When the signal on bit line BL1 reaches ground level GND, the falling edge FE1 of the delayed negative bit line trigger signal NBLKd will (through coupling capacitor 144) pull down the voltage difference dNBL of bit line BL1 below ground level GND. In this case, write auxiliary circuit 140 is able to pull bit line BL1 to transient negative voltage level NVSS (i.e., 0V-dNBL) at the correct timing, which occurs after the signal on word line WL1 is fully activated and after bit line BL1 is discharged to ground level GND. In some embodiments, since bit line BL1 is pulled down to a transient negative voltage level NVSS below ground level GND, the transient negative voltage level NVSS helps ensure that the signal on bit line BL1 (i.e., the transient negative voltage level NVSS) covers the storage node BL_in in bit cell BC11, causing the storage node BL_in to flip from high to low and be configured to store data "0", such as... Figure 4 As shown. In such an embodiment, the storage node BL_in is written to have the voltage level required in the write operation.

[0048] In some other cases, if bit line BL1 is pulled to a voltage level that is not low enough, the voltage level on bit line BL1 may not cover the voltage level on memory node BL_in latched in bit cell BC11, causing memory node BL_in to return to a high level. Further references Figure 5 . Figure 5 This is a waveform diagram illustrating the relationship between time and voltage levels on a relative signal in another example of a write operation failure. Relative to Figure 4 Implementation examples, Figure 5 The same components are labeled with the same reference numerals for ease of understanding. In some cases, if the sensing circuit 163 in the timing control circuit 160 has a threshold voltage Vt2, which is higher than the low threshold voltage Vt1 of the Schmitt trigger in the aforementioned embodiment, then when the voltage level of the tracking bit line signal BLTK is lower than the threshold voltage Vt2, the sensing circuit 163 with the threshold voltage Vt2 begins to raise the negative bit line enable signal NBLENB (at node N2). In some cases, if the threshold voltage value Vt2 of the sensing circuit 163 (e.g., the sensing circuit 163 may be an inverter) is configured to be approximately 50% of the total voltage gap Vd, then in Figure 5 In the case shown, Figure 5 At time TS2, when the tracking bit line signal BLTK is below 50% of the total voltage gap Vd, the sensing circuit 163 begins to raise the negative bit line enable signal NBLENB. Since the threshold voltage Vt2 is higher than the low threshold voltage Vt1, the negative bit line enable signal NBLENB... Figure 5 The time TS2 in the middle rises, and this time TS2 is earlier than Figure 4 The time in TS1.

[0049] like Figure 5 As shown, because the negative bit line enable signal NBLENB is pulled high earlier, the falling edge FE2 of the delayed negative bit line trigger signal NBLKd will also arrive earlier, meaning that the falling edge FE2 may arrive before the voltage level of bit line BL1 is completely discharged to ground. Figure 5 In the example shown, because the falling edge FE2 of the delayed negative bit line trigger signal NBLKd arrives too early, the voltage level on bit line BL1 cannot fall below ground level GND even if bit line BL1 is pulled down after time TS3, making it impossible for the voltage level on bit line BL1 to fall below ground level GND. Figure 5 In the example shown, write operations to storage nodes BL_in and BLB_in failed.

[0050] In other words, in some embodiments, in Figure 3 The Schmitt trigger used in the sensing circuit 163 of the timing control circuit 160 shown, and Figure 4The signal waveforms shown help ensure a high probability of successful write operations. In some embodiments, the Schmitt trigger raises the negative bit-line enable signal NBLENB in ​​response to the voltage level on the first node N1 falling below the low threshold voltage Vt1 of the Schmitt trigger. Therefore, the negative bit-line enable signal NBLENB is raised in the appropriate timing to trigger a signal including the negative bit-line trigger signal NBLK and a delayed negative bit-line trigger signal NBLKd. Thus, the falling edge FE1 of the delayed negative bit-line trigger signal NBLKd arrives in the appropriate timing to (through coupling capacitor 144) pull down the voltage difference dNBL on bit line BL1 below ground level GND, as... Figure 4 As shown.

[0051] Further reference Figure 6A . Figure 6A This illustrates, according to some embodiments, including Figure 1 A layout diagram of the memory device 100 in the image. (See diagram below.) Figure 6A As shown, Figure 6A Exemplary layout configurations associated with the physical arrangement of components in memory device 100, according to some embodiments, are shown, including, for example... Figure 3 The tracking word line tWL, tracking bit line tBL, power switch 162, sensing circuit 163, and inverter 164, and Figure 1 The write auxiliary circuit 140, write driver 120, and selection circuit 170. In other words, Figure 6A The spatial relationship of the above components in the semiconductor layout is shown. For example... Figure 6A As shown, the components of memory device 100 are arranged around memory array CA1. Figure 6A As shown, in some embodiments, the tracking word line tWL can be set on the main input / output area MIO on one side of the memory array CA1, and the clock pulse signal CKP can be controlled by a time controller set in the main controller area MCNT. Figure 6A (Not shown) is provided to the tracking word line tWL. In some embodiments, a power switch 162 and a sensing circuit 163 are also provided in the main controller region MCNT. In some embodiments, the tracking bit line tBL is provided in the vertical word line driver region WLDV. In some embodiments, an inverter 164 is provided in the local controller region LCTRL. In some embodiments, a write assist circuit 140, a write driver 120, and a selection circuit 170 are provided in the local input / output region LIO on the other side of the memory array CA1. In some embodiments, the memory device 100 is not limited to having a memory array CA1.

[0052] Further reference Figure 6B . Figure 6BThis is another layout diagram illustrating another layout of a memory device 200 according to some embodiments. Figure 6B Exemplary layout configurations associated with the physical arrangement of components in a memory device 200, according to some embodiments, are shown, including, for example... Figure 3 The circuit includes a tracking word line tWL and a tracking bit line tBL, a power switch 262, a sensing circuit 263, an inverter 264, a write auxiliary circuit 240a, a write auxiliary circuit 240b, a write driver 220a, a write driver 220b, and selection circuits 270a and 270b. For illustration, the power switch 262 corresponds to... Figure 3 The power switch 162 and the sensing circuit 263 correspond to Figure 3 The power switch 162 and inverter 264 correspond to Figure 3 Inverter 164. Used to drive Figure 6B The write auxiliary circuit 240a, write driver 220a, and selection circuit 270a of the memory array CA1 correspond to Figure 3 The system includes a write auxiliary circuit 140, a write driver 120, and a selection circuit 170. These are used for driving... Figure 6B The write auxiliary circuit 240b, write driver 220b, and selection circuit 270b of the other memory array CA2 correspond to Figure 3 The write auxiliary circuit 140, write driver 120, and selection circuit 170. In other words, Figure 6B This illustrates the spatial relationship of the components in the semiconductor layout. Figure 6A Compared to the embodiment with a memory array CA1, Figure 6B The memory device 200 has two memory arrays, CA1 and CA2. For example... Figure 6B As shown, the tracking word line tWL can be disposed on the main input / output region MIO on one side of the memory array CA1, and the clock pulse signal CKP can be provided to the tracking word line tWL by a time controller (not shown) disposed in the main controller region MCNT. In some embodiments, a power switch 262 and a sensing circuit 263 are also disposed in the main controller region MCNT. In some embodiments, the tracking bit line tBL is disposed in the vertical word line driver region WLDV, which is located between the two memory arrays CA1 and CA2. In some embodiments, an inverter 264 is disposed in the local controller region LCTRL. In some embodiments, there are two write auxiliary circuits 240a / 240b, two write drivers 220a / 220b, and two selection circuits 270a / 270b respectively disposed in the local input / output region LIO along the top side of the memory arrays CA1 / CA2. Figure 6BAs shown, the negative bit line trigger signal NBLK is distributed from the center point to the two write auxiliary circuits 240a / 240b, so that the arrival timing of the negative bit line trigger signal NBLK to the write auxiliary circuits 240a / 240b is approximately the same.

[0053] Figure 6B The internal structure and behavior of the power switch 262, sensing circuit 263, write auxiliary circuit 240a / 240b, write driver 220a / 220b, and selection circuit 270a / 270b are similar to those of the power switch 262, sensing circuit 263, write auxiliary circuit 240a / 240b, write driver 220a / 220b, and selection circuit 270a / 270b. Figures 1 to 3 The power switch 162, sensing circuit 163, write auxiliary circuit 140, write driver 120, and selection circuit 170 are described in detail here.

[0054] In some embodiments, the memory device described above can provide a transient negative voltage level NVSS to the bit lines or two's complement bit lines connected to the bit cells at appropriate timing. The timing of the transient negative voltage level NVSS is adapted to the parameters of the memory array so that the transient negative voltage level NVSS arrives at the correct time, ensuring that write operations can succeed even if VDD used to operate the memory array is set to a relatively low value. By providing the transient negative voltage level NVSS at appropriate timing, the memory device can further reduce the level of VDD to achieve lower leakage current on the memory array, thereby reducing the power consumption of the memory device in this case.

[0055] In some embodiments, a circuit includes a tracking word line, a power switch, a tracking bit line, and sensing circuitry. The power switch is coupled between the tracking word line and a first node. The power switch is configured to discharge a voltage level on the first node in response to a clock pulse signal sent to the power switch via the tracking word line. The tracking bit line is coupled between the first node and a plurality of tracking cells in a memory array. The sensing circuitry is coupled between the first node and a second node. The sensing circuitry is configured to generate a negative bit line enable signal in response to a voltage level on the first node falling below a threshold voltage value of the sensing circuitry.

[0056] In some embodiments, the circuit further includes an inverter. The inverter is coupled to a sensing circuit to convert a negative bit-line enable signal into a negative bit-line trigger signal. The negative bit-line trigger signal is sent to a write assist circuit. The write assist circuit is triggered by the negative bit-line trigger signal to pull down the bit-line voltage or two's complement bit-line voltage to a transient negative voltage level.

[0057] In some embodiments, the sensing circuit includes a Schmitt trigger. The threshold voltage value of the sensing circuit is the low threshold voltage value of the Schmitt trigger. The Schmitt trigger generates a negative bit-line enable signal in response to a voltage level at the first node moving downwards past the low threshold voltage value of the Schmitt trigger.

[0058] In some embodiments, the trace word line includes a first segment, a second segment, and a third segment connected in series. The first segment and the third segment are parallel to each other. The length of the first segment is substantially equal to half the width of the memory array. The length of the third segment is substantially equal to half the width of the memory array.

[0059] In some embodiments, the number of tracking cells coupled to the tracking bit lines is substantially equal to the number of cell rows in the memory array.

[0060] In some embodiments, the power switch includes a first transistor of a first conductivity type and a plurality of second transistors of a second conductivity type, the gate terminals of the first transistor and the second transistors being coupled together to a trace word line.

[0061] In some embodiments, the number of second transistors in the power switch is substantially equal to the number of transistors located on the discharge path from the bit cell in the memory array to the ground terminal.

[0062] In some embodiments, a device includes a write driver, a write auxiliary circuit, and timing control circuitry. The write driver is configured to provide bit line voltages and two's complement bit line voltages to a memory array. The write auxiliary circuitry is coupled to the write driver. The write auxiliary circuitry is configured to pull down a voltage level on a bit line or two's complement bit line to a transient negative voltage level in response to a negative bit line trigger signal. The timing control circuitry is coupled to the write auxiliary circuitry. The timing control circuitry includes a tracking word line associated with a first delay on a word line in the memory array and a tracking bit line associated with a second delay on a bit line in the memory array. The timing control circuitry is configured to generate a negative bit line trigger signal in response to a clock pulse signal, referencing the first and second delays.

[0063] In some embodiments, the write auxiliary circuitry includes a transistor switch, a delay unit, and a capacitor. The transistor switch is coupled between a ground terminal and an output node to the write driver. The capacitor is coupled between the delay unit and the output node. The capacitor is configured to couple the voltage level of the output node to a transient negative voltage level in response to a falling edge of a negative bit-line trigger signal.

[0064] In some embodiments, the timing control circuitry further includes a power switch and a sensing circuit. The power switch is coupled between a trace word line and a first node. The power switch is configured to discharge the voltage level on the first node in response to a clock pulse signal sent to the power switch via the trace word line. The sensing circuit is coupled between the first node and a second node. The sensing circuit is configured to generate a negative bit-line enable signal in response to a voltage level on the first node falling below a threshold voltage value of the sensing circuit.

[0065] In some embodiments, the tracking bit line is coupled between the first node and a plurality of tracking cells in the memory array. The number of tracking cells coupled to the tracking bit line is substantially equal to the number of cell rows in the memory array.

[0066] In some embodiments, the trace word line includes a first segment, a second segment, and a third segment connected in series. The first segment and the third segment are parallel to each other. The length of the first segment is substantially equal to half the width of the memory array. The length of the third segment is substantially equal to half the width of the memory array.

[0067] In some embodiments, the timing control circuit further includes an inverter coupled to the sensing circuit for converting the negative bit line enable signal into a negative bit line trigger signal.

[0068] In some embodiments, the sensing circuit includes a Schmitt trigger. The threshold voltage value of the sensing circuit is the low threshold voltage value of the Schmitt trigger. The Schmitt trigger generates a negative bit-line enable signal in response to a voltage level at the first node moving downwards past the low threshold voltage value of the Schmitt trigger.

[0069] In some embodiments, the power switch includes a first transistor of a first conductivity type and a plurality of second transistors of a second conductivity type. The gate terminals of the first and second transistors are coupled together to a trace word line.

[0070] In some embodiments, the number of second transistors in the power switch is substantially equal to the number of transistors located on the discharge path from the bit cell in the memory array to the ground terminal.

[0071] In some embodiments, a method includes the steps of: transmitting a clock pulse signal via a tracking word line; discharging a voltage level on a first node coupled to the tracking bit line in response to the clock pulse signal; generating a negative bit line enable signal in response to the voltage level on the first node being lower than a threshold voltage value of a sensing circuit; and generating a negative bit line trigger signal based on the negative bit line enable signal.

[0072] In some embodiments, the method further includes the step of: pulling down the bit line voltage or complement bit line voltage to a transient negative voltage level in response to the falling edge of the negative bit line trigger signal.

[0073] In some embodiments, the tracking bit line is coupled between the first node and a plurality of tracking cells in the memory array.

[0074] In some embodiments, the trace word line includes a first segment, a second segment, and a third segment connected in series. The first segment and the third segment are parallel to each other. The length of the first segment is substantially equal to half the width of the memory array. The length of the third segment is substantially equal to half the width of the memory array.

[0075] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0076] Example 1 is a circuit comprising: a tracking word line; a power switch coupled between the tracking word line and a first node, the power switch being configured to discharge a voltage level on the first node in response to a clock pulse signal transmitted to the power switch via the tracking word line; a tracking bit line coupled between the first node and a plurality of tracking cells in a memory array; and a sensing circuit coupled between the first node and a second node, the sensing circuit being configured to generate a negative bit line enable signal in response to a voltage level on the first node being lower than a threshold voltage value of the sensing circuit.

[0077] Example 2 is the circuit described in Example 1, further comprising: an inverter coupled to the sensing circuit for converting the negative bit line enable signal into a negative bit line trigger signal, wherein the negative bit line trigger signal is sent to a write auxiliary circuit, the write auxiliary circuit being triggered by the negative bit line trigger signal to pull down the bit line voltage or two's complement bit line voltage to a transient negative voltage level.

[0078] Example 3 is the circuit described in Example 1, wherein the sensing circuit includes a Schmitt trigger, the threshold voltage value of the sensing circuit is the low threshold voltage value of the Schmitt trigger, and the Schmitt trigger generates the negative bit enable signal in response to a voltage level at the first node moving downwards past the low threshold voltage value of the Schmitt trigger.

[0079] Example 4 is the circuit described in Example 1, wherein the tracking word line includes a first segment, a second segment, and a third segment connected in series, the first segment and the third segment being parallel to each other, the length of the first segment being substantially equal to half the width of the memory array, and the length of the third segment being substantially equal to half the width of the memory array.

[0080] Example 5 is the circuit described in Example 1, wherein the number of tracking cells coupled to the tracking bit line is substantially equal to the number of cell rows in the memory array.

[0081] Example 6 is the circuit described in Example 1, wherein the power switch includes a first transistor of a first conductivity type and a plurality of second transistors of a second conductivity type, the gate terminals of the first transistor and the second transistors being coupled together to the trace word line.

[0082] Example 7 is the circuit described in Example 6, wherein the number of the second transistors in the power switch is substantially equal to the number of transistors located on the discharge path from the bit cell in the memory array to the ground terminal.

[0083] Example 8 is a semiconductor device comprising: a write driver configured to provide bit line voltages and two's complement bit line voltages to a memory array; a write auxiliary circuit coupled to the write driver, the write auxiliary circuit being configured to pull down a voltage level on a bit line or two's complement bit line to a transient negative voltage level in response to a negative bit line trigger signal; and a timing control circuit coupled to the write auxiliary circuit, wherein the timing control circuit includes a tracking word line relating to a first delay on a word line in the memory array and a tracking bit line relating to a second delay on a bit line in the memory array, the timing control circuit being configured to generate the negative bit line trigger signal in response to a clock pulse signal, with reference to the first delay and the second delay.

[0084] Example 9 is the device described in Example 8, wherein the write assist circuitry includes: a transistor switch coupled between a ground terminal and an output node of the write driver; a delay unit; and a capacitor coupled between the delay unit and the output node, the capacitor being configured to couple the voltage level of the output node to a transient negative voltage level in response to a falling edge of the negative bit line trigger signal.

[0085] Example 10 is the device described in Example 8, wherein the timing control circuitry further includes: a power switch coupled between the trace word line and the first node, the power switch being configured to discharge a voltage level on the first node in response to a clock pulse signal transmitted to the power switch via the trace word line; and a sensing circuit coupled between the first node and the second node, the sensing circuit being configured to generate a negative bit line enable signal in response to a voltage level on the first node being lower than a threshold voltage value of the sensing circuit.

[0086] Example 11 is the device described in Example 10, wherein the tracking bit line is coupled between the first node and a plurality of tracking cells in the memory array, and the number of tracking cells coupled to the tracking bit line is substantially equal to the number of cell rows in the memory array.

[0087] Example 12 is the device described in Example 10, wherein the tracking word line includes a first segment, a second segment, and a third segment connected in series, the first segment and the third segment being parallel to each other, the length of the first segment being substantially equal to half the width of the memory array, and the length of the third segment being substantially equal to half the width of the memory array.

[0088] Example 13 is the device described in Example 10, wherein the timing control circuit further includes: an inverter coupled to the sensing circuit for converting the negative bit line enable signal into the negative bit line trigger signal.

[0089] Example 14 is the device described in Example 10, wherein the sensing circuit includes a Schmitt trigger, the threshold voltage value of the sensing circuit is the low threshold voltage value of the Schmitt trigger, and the Schmitt trigger generates the negative bit enable signal in response to a voltage level at the first node moving downwards past the low threshold voltage value of the Schmitt trigger.

[0090] Example 15 is the device described in Example 10, wherein the power switch includes a first transistor of a first conductivity type and a plurality of second transistors of a second conductivity type, the gate terminals of the first transistor and the second transistors being coupled together to the trace word line.

[0091] Example 16 is the device described in Example 15, wherein the number of the second transistors in the power switch is substantially equal to the number of transistors located on the discharge path from the bit cell in the memory array to the ground terminal.

[0092] Example 17 is a method for forming a semiconductor device, comprising: transmitting a clock pulse signal via a tracking word line; discharging a voltage level on a first node coupled to a tracking bit line in response to the clock pulse signal; generating a negative bit line enable signal in response to the voltage level on the first node being lower than a threshold voltage value of a sensing circuit; and generating a negative bit line trigger signal based on the negative bit line enable signal.

[0093] Example 18 is the method of Example 17, further comprising: pulling down the bit line voltage or complement bit line voltage to a transient negative voltage level in response to a falling edge of the negative bit line trigger signal.

[0094] Example 19 is the method described in Example 17, wherein the tracking bit line is coupled between the first node and a plurality of tracking cells in the memory array.

[0095] Example 20 is the method described in Example 17, wherein the trace word line includes a first segment, a second segment, and a third segment connected in series, the first segment and the third segment being parallel to each other, the length of the first segment being substantially equal to half the width of the memory array, and the length of the third segment being substantially equal to half the width of the memory array.

Claims

1. A circuit for controlling a memory device, comprising: Follow the word lines; A power switch, coupled between the trace word line and the first node, is configured to discharge the voltage level on the first node in response to a clock pulse signal transmitted to the power switch via the trace word line. A tracking bit line is coupled between the first node and multiple tracking cells in the memory array; as well as A sensing circuit, coupled between the first node and the second node, is configured to generate a negative bit line enable signal in response to a voltage level on the first node being lower than a threshold voltage value of the sensing circuit.

2. The circuit according to claim 1 further includes: An inverter, coupled to the sensing circuit, is used to convert the negative bit line enable signal into a negative bit line trigger signal, wherein the negative bit line trigger signal is sent to a write auxiliary circuit, which is triggered by the negative bit line trigger signal to pull down the bit line voltage or the two's complement bit line voltage to a transient negative voltage level.

3. The circuit of claim 1, wherein, The sensing circuit includes a Schmitt trigger, the threshold voltage value of the sensing circuit is the low threshold voltage value of the Schmitt trigger, and the Schmitt trigger generates the negative bit enable signal in response to the voltage level at the first node moving downwards past the low threshold voltage value of the Schmitt trigger.

4. The circuit of claim 1, wherein, The tracking word line includes a first segment, a second segment, and a third segment connected in series, the first segment and the third segment being parallel to each other, the length of the first segment being substantially equal to half the width of the memory array, and the length of the third segment being substantially equal to half the width of the memory array.

5. The circuit of claim 1, wherein, The number of tracking cells coupled to the tracking bit line is substantially equal to the number of cell rows in the memory array.

6. The circuit of claim 1, wherein, The power switch includes a first transistor of a first conductivity type and a plurality of second transistors of a second conductivity type, the gate terminals of the first transistor and the second transistors being coupled together to the trace word line.

7. The circuit of claim 6, wherein, The number of the second transistors in the power switch is substantially equal to the number of transistors located on the discharge path from the bit cell in the memory array to the ground terminal.

8. A semiconductor device, comprising: The write driver is configured to provide bit line voltages and complement bit line voltages to the memory array; A write auxiliary circuit, coupled to the write driver, is configured to pull down a voltage level on a bit line or two's complement bit line to a transient negative voltage level in response to a negative bit line trigger signal. as well as A timing control circuit, coupled to the write auxiliary circuit, wherein the timing control circuit includes a tracking word line related to a first delay on a word line in the memory array and a tracking bit line related to a second delay on a bit line in the memory array, the timing control circuit being configured to generate the negative bit line trigger signal in response to a clock pulse signal, with reference to the first delay and the second delay.

9. The device of claim 8, wherein, The writing assistance circuit includes: A transistor switch is coupled between a ground terminal and an output node to the write driver; Delay unit; and a capacitor coupled between the delay cell and the output node, the capacitor configured to couple a voltage level of the output node to a transient negative voltage level in response to a falling edge of the negative bit line trigger signal.

10. The device of claim 8, wherein, The timing control circuit further includes: a power switch coupled between the tracking word line and a first node, the power switch configured to discharge a voltage level on the first node in response to a clock pulse signal sent to the power switch through the tracking word line; and a sense circuit coupled between the first node and a second node, the sense circuit configured to generate a negative bit line enable signal in response to a voltage level on the first node being below a threshold voltage value of the sense circuit.

11. The device of claim 10, wherein, The tracking bit line is coupled between the first node and a plurality of tracking cells in the memory array, a number of the tracking cells coupled to the tracking bit line substantially equal to a number of cell rows in the memory array.

12. The device of claim 10, wherein, The tracking word line includes a first segment, a second segment, and a third segment connected in series, the first segment and the third segment parallel to each other, a length of the first segment substantially equal to one half of a width of the memory array, and a length of the third segment substantially equal to one half of the width of the memory array.

13. The device of claim 10, wherein, The timing control circuit further includes: an inverter coupled to the sense circuit for converting the negative bit line enable signal to the negative bit line trigger signal.

14. The device of claim 10, wherein, The sense circuit includes a Schmitt trigger, the threshold voltage value of the sense circuit being a low threshold voltage value of the Schmitt trigger, the Schmitt trigger generating the negative bit line enable signal in response to a voltage level on the first node falling below the low threshold voltage value of the Schmitt trigger.

15. The device of claim 10, wherein, The power switch includes a first transistor of a first conductivity type and a plurality of second transistors of a second conductivity type, gate terminals of the first transistor and the second transistors coupled together to the tracking word line.

16. The device of claim 15, wherein, A number of the second transistors in the power switch is substantially equal to a number of transistors in a discharge path from a bit cell in the memory array to a ground terminal.

17. A method for controlling a memory device, comprising: sending a clock pulse signal through a tracking word line; discharging a voltage level on a first node in response to the clock pulse signal, the first node coupled to a tracking bit line; generating a negative bit line enable signal in response to the voltage level on the first node being below a threshold voltage value of a sense circuit; and generating a negative bit line trigger signal from the negative bit line enable signal.

18. The method of claim 17, further comprising: pulling down a bit line voltage or a complement bit line voltage to a transient negative voltage level in response to a falling edge of the negative bit line trigger signal. The tracking bit line is coupled between the first node and a plurality of tracking cells in the memory array.

19. The method of claim 17, wherein, ​ 20. The method of claim 17, wherein, The tracking word line includes a first segment, a second segment, and a third segment connected in series, the first segment and the third segment are parallel to each other, a length of the first segment is substantially equal to half of a width of a memory array, and a length of the third segment is substantially equal to half of the width of the memory array.

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