Semiconductor structure and method of forming the same

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate, a metal bit line on the substrate, a bit line spacer on sidewalls of the metal bit line, and a contact adjacent to the metal bit line. The semiconductor structure includes a cap layer covering the metal bit line, the bit line spacer, and the contact, wherein the cap layer includes a first portion covering sidewalls of the bit line spacer, a second portion covering sidewalls of the contact, and a third portion covering a top surface of the contact. The semiconductor structure includes an air gap between the first portion and the second portion of the cap layer, wherein a top portion of the air gap is tilted toward the bit line spacer, and the first portion and the third portion are in contact with each other above the air gap. The cap layer in the semiconductor structure of the present disclosure forms the air gap by self-encapsulation, such that the structure of the air gap is complete, thereby effectively reducing the parasitic capacitance in the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor structures and methods for their formation, and in particular to semiconductor structures with air gaps and methods for their formation. Background Technology

[0002] As the minimum feature width, or critical dimension (CD), within semiconductor devices continues to shrink, the device density increases and the device size decreases. However, the reduced spacing between closely packed components can lead to an increase in parasitic capacitance between them. Therefore, creating structurally sound air gaps between components to effectively reduce parasitic capacitance is a crucial development project for semiconductor devices. Summary of the Invention

[0003] According to one embodiment of this disclosure, a semiconductor structure is provided, including a substrate, metal bit lines on the substrate, a bit line spacer layer on the sidewalls of the metal bit lines, and contacts adjacent to the metal bit lines. The semiconductor structure includes a capping layer covering the metal bit lines, the bit line spacer layer, and the contacts, wherein the capping layer includes a first portion covering the sidewalls of the bit line spacer layer, a second portion covering the sidewalls of the contacts, and a third portion covering the top surface of the contacts. The semiconductor structure includes an air gap between the first and second portions of the capping layer, wherein the top portion of the air gap is inclined toward the bit line spacer layer, and the first and third portions of the capping layer are in contact with each other above the air gap.

[0004] In one embodiment of this disclosure, the bottom width of the air gap is greater than the top width.

[0005] In one embodiment of this disclosure, the bottom width of the air gap is between 1 nm and 10 nm.

[0006] In one embodiment of this disclosure, the upper width of the contact member is greater than the lower width.

[0007] In one embodiment of this disclosure, the top surface of the contact has a first width, and the portion of the contact that is coplanar with the top surface of the substrate has a second width, the difference between the first width and the second width being between 5 nm and 20 nm.

[0008] In one embodiment of this disclosure, the metal bit line includes a gate metal layer, and the top surface of the contact is located between the top surface of the metal bit line and the top surface of the gate metal layer.

[0009] In one embodiment of this disclosure, the thickness of the cover layer is between 3 nm and 5 nm.

[0010] According to one embodiment of this disclosure, a method for forming a semiconductor structure is provided, comprising forming a plurality of metal bit lines on a substrate, forming a plurality of bit line spacer layers on the sidewalls of each metal bit line, forming a first sacrificial layer on the sidewalls of each bit line spacer layer, etching the first sacrificial layer to form a second sacrificial layer with a lower width greater than an upper width, forming contacts that contact the second sacrificial layer between adjacent metal bit lines, removing the second sacrificial layer to form a gap between each bit line spacer layer and the contacts, and depositing a capping layer covering the metal bit lines, the bit line spacer layers, and the contacts to form an air gap in the gap, wherein the capping layer includes a first portion covering the sidewalls of the bit line spacer layers, a second portion covering the sidewalls of the contacts, and a third portion covering the top surface of the contacts, the first portion and the third portion being in contact with each other.

[0011] In one embodiment of this disclosure, the lower width of the second sacrificial layer is between 10 nm and 15 nm.

[0012] In one embodiment of this disclosure, forming a contact between adjacent metal bit lines further includes forming a contact material layer covering a second sacrificial layer between adjacent metal bit lines, and etching the contact material layer to form a contact such that the top surface of the contact is lower than the top surface of the metal bit line. Attached Figure Description

[0013] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0014] Figure 1 A flowchart illustrating a method for forming a semiconductor structure is shown according to one embodiment of the present disclosure.

[0015] Figures 2 to 9 Cross-sectional views of various intermediate stages in forming a semiconductor device are shown according to one embodiment of the present disclosure. Detailed Implementation

[0016] To achieve the various features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, values, operations, materials, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0018] This disclosure provides a semiconductor structure and a method for forming the same, wherein the semiconductor structure includes a capping layer covering metal bit lines, bit line spacers, and contacts. Because the capping layer forms a structurally complete air gap between the bit line spacers and the contacts, the parasitic capacitance between the metal bit lines and the contacts is effectively reduced, thereby increasing the stability of a device including the semiconductor structure.

[0019] Figure 1 A flowchart illustrating a method 1000 for forming a semiconductor structure is shown according to some embodiments of this disclosure. Method 1000 includes steps 1002, 1004, 1006, 1008, 1010, 1012, 1014, and 1016. In some embodiments, additional steps may be added before, during, or after method 1000. In other embodiments, some steps of method 1000 described below may be replaced, reduced, or moved.

[0020] Figures 2 to 9The following are cross-sectional views of a semiconductor structure 10 at various stages of its formation, according to some embodiments disclosed herein. The semiconductor structure 10 can be applied to components of an integrated circuit (IC) or a portion thereof, such as logic circuits, resistors, capacitors, inductors, memory (e.g., Dynamic Random Access Memory (DRAM)), etc. It should be understood that some elements of the semiconductor structure 10 are not shown in the diagram. Figures 2 to 9 The figures are shown for simplification, and additional elements may be included in other embodiments of the semiconductor structure 10.

[0021] refer to Figure 1 Combination Figure 2 In step 1002, a metal bit line 130 is formed on the substrate 100 of the semiconductor structure 10, and a bit line spacer layer 140 is formed covering the metal bit line 130. Specifically, the bit line spacer layer 140 conformally covers the metal bit line 130 to isolate the sidewalls of the metal bit line 130 from the outside, so that the bit line spacer layer 140 can protect the metal bit line 130 from damage in subsequent processes, thereby increasing the reliability of the semiconductor structure 10.

[0022] In some embodiments, substrate 100 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., wherein the insulator may be a buried oxide (BOX) layer, a silicon oxide layer, etc. In some embodiments, substrate 100 may be doped (e.g., containing p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of semiconductor substrate 100 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors, or combinations thereof. Substrate 100 may also be formed of other materials, such as sapphire, indium tin oxide, etc.

[0023] In some embodiments, the substrate 100 may include polysilicon bit lines 110 and 120 for electrically connecting to other elements of the semiconductor structure 10, thereby forming a circuit of the semiconductor structure 10. Specifically, the polysilicon bit lines 110 and 120 may be disposed below the metal bit line 130 to conduct current to the metal bit line 130. In some embodiments, the polysilicon bit line 110 may be disposed in the substrate 100 not covered by the metal bit line 130, thereby acting as a conductor to conduct current to elements above it (e.g., Figure 7 Contact 162 shown.

[0024] In some implementations, the metal bit line 130 may be along a first direction D1 (e.g., Figure 2 As shown, the metal bit line 130 extends on the substrate 100 in a direction perpendicular to the plane of the paper. In some embodiments, the metal bit line 130 may include a stack of multiple material layers, thereby having the function of reading and writing electronic signals. Figure 2 As shown, the metal bit line 130 may include a stack formed of a first conductive layer 134 and a second conductive layer 136, serving as the gate structure of the metal bit line 130. In some embodiments, the first conductive layer 134 and the second conductive layer 136 may include different wire materials. For example, the first conductive layer 134 may include doped polysilicon, and the second conductive layer 136 may include a metal or a metal nitride. In the above example, the first conductive layer 134 may be referred to as a gate polysilicon layer, and the second conductive layer 136 may be referred to as a gate metal layer. In other examples, the first conductive layer 134 may include a metal or a metal nitride, and the second conductive layer 136 may include polysilicon. In some other embodiments, the metal bit line 130 may include an additional conductive layer, such as a metal silicide layer between the first conductive layer 134 and the second conductive layer 136.

[0025] In some embodiments, the metal bit line 130 may further include a dielectric layer 132 to isolate the first conductive layer 134 and underlying structures, such as polysilicon bit line 110 or polysilicon bit line 120. For example, the material forming the dielectric layer 132 may include silicon oxide, silicon nitride, a high-dielectric-constant dielectric material, other suitable materials, or combinations thereof. In some embodiments, the metal bit line 130 may further have a dielectric layer 138 formed on the second conductive layer 136 to isolate the second conductive layer 136 from other features subsequently formed on the metal bit line 130. For example, the material forming the dielectric layer 138 may include silicon oxide, silicon nitride, other dielectric materials, or combinations thereof.

[0026] In some embodiments, the bit-line spacer layer 140 covering the metal bit line 130 may have an appropriate thickness to protect the structure of the metal bit line 130. For example, the bit-line spacer layer 140 may have a thickness between 1 nm and 2 nm and uniformly cover the sidewalls of the dielectric layer 132, the first conductive layer 134, the second conductive layer 136, and the dielectric layer 138, as well as the top surface of the dielectric layer 138. In some embodiments, the bit-line spacer layer 140 may further extend into the substrate 100 such that the bit-line spacer layer 140 contacts the polysilicon bit line 120, thereby separating multiple regions of the semiconductor structure 10. In some embodiments, the material forming the bit-line spacer layer 140 may be a suitable dielectric material, such as silicon nitride, a low dielectric constant dielectric material, or a combination thereof. For example, the bit-line spacer layer 140 may be a single-layer, double-layer, or multi-layer dielectric material, and its multilayer materials may each include different compositions. In some embodiments, suitable deposition processes can be used to form the bit line spacer layer 140, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0027] refer to Figure 1 Combination Figure 3 In step 1004, a portion of the bit-line spacer layer 140 located on the substrate 100 and the metal bit line 130 is removed. Specifically, the bit-line spacer layer 140 on the top surface of the substrate 100 and the top surface of the metal bit line 130 is selectively removed, while the bit-line spacer layer 140 remains on the sidewalls of the metal bit line 130. This is because the uppermost dielectric layer (e.g., in the metal bit line 130) is removed. Figure 2 The dielectric layer 138 shown can protect other material layers underneath, thus allowing the removal of the bit line spacer layer 140 on the top surface of the metal bit line 130, thereby reducing the thickness of the semiconductor structure 10. In some embodiments, removing part of the bit line spacer layer 140 may include forming a photoresist over the substrate 100 and the metal bit line 130 using a patterning process, etching the bit line spacer layer 140 exposed by the photoresist on the substrate 100 and the metal bit line 130, and retaining the bit line spacer layer 140 on the sidewalls of the metal bit line 130.

[0028] refer to Figure 1 Combination Figure 4In step 1006, a first sacrificial layer 150 is formed on the sidewall of the bit line spacer layer 140. Specifically, the first sacrificial layer 150 can be formed using steps similar to those used to form the bit line spacer layer 140. For example, after forming a sacrificial material layer that conformally covers the metal bit lines 130, the bit line spacer layer 140, and the substrate 100, the horizontal portions of the sacrificial material layer on the substrate 100 and the metal bit lines 130 are selectively removed to form the first sacrificial layer 150. The first sacrificial layer 150 is formed on the outer sidewall of the bit line spacer layer 140, so that when other components (e.g., contacts) are subsequently formed between adjacent metal bit lines 130, an air gap (e.g., between the metal bit lines 130 and other components) can be maintained. Figure 9 The space shown is the air gap 190.

[0029] In some embodiments, the first sacrificial layer 150 may have a width W1 in the second direction D2, wherein the second direction D2 is different from the first direction D1. In some embodiments, the first sacrificial layer 150 may have an appropriate width W1 such that the first sacrificial layer 150 can reserve sufficient space for subsequently formed air gaps. For example, the width W1 of the first sacrificial layer 150 may be between 10 nm and 15 nm. In some embodiments, the material forming the first sacrificial layer 150 may include a dielectric material different from the bit line spacer layer 140, such that the first sacrificial layer 150 undergoes selective etching processes (e.g., ...) in subsequent steps. Figure 8 When (as shown), the bit line spacer layer 140 is unaffected. For example, if the bit line spacer layer 140 is silicon nitride, the first sacrificial layer 150 may be, for example, silicon oxide.

[0030] In some embodiments, a suitable deposition process can be used to form the sacrificial material layer of the first sacrificial layer 150, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, etc. In some embodiments, selective removal of the horizontal portion of the sacrificial material layer on the substrate 100 and the metal bit line 130 may include forming a photoresist over the substrate 100 and the metal bit line 130 using a patterning process, etching the sacrificial material layer exposed by the photoresist on the substrate 100 and the metal bit line 130 to retain the sacrificial material layer on the sidewall of the metal bit line 130, such that the top surface of the first sacrificial layer 150 and the top surface of the metal bit line 130 are coplanar.

[0031] refer to Figure 1 Combination Figure 5In step 1008, the first sacrificial layer 150 is etched to form the second sacrificial layer 152, such that the width W1 of the lower portion of the second sacrificial layer 152 is greater than the width W2 of the upper portion. In this document, "upper portion" refers to the location above the work function region (e.g., the gate metal layer) of the metal bit line 130. Conversely, "lower portion" refers to the location below the work function region of the metal bit line 130. Specifically, the upper portion of the first sacrificial layer 150 may be etched, such that the upper portion of the second sacrificial layer 152 has a structure with an upwardly tapering width. Therefore, the lower portion of the second sacrificial layer 152 (e.g., the position near the bottom surface of the second sacrificial layer 152) has a width W1 in the second direction D2 to reserve sufficient space for the subsequently formed air gap; while the etched upper portion of the second sacrificial layer 152 has a width W2 in the second direction D2 that is smaller than the width W1.

[0032] In some embodiments, the upper portion of the second sacrificial layer 152 may be etched to have a continuously smooth arcuate surface, thereby forming a tapered structure that rests against the bit line spacer layer 140. In some embodiments where the second conductive layer 136 is a gate metal layer, the width of the second sacrificial layer 152 may begin to taper above the top surface of the second conductive layer 136; that is, the width W2 of the second sacrificial layer 152 is located above the top surface of the second conductive layer 136.

[0033] refer to Figure 1 Combination Figure 6 In step 1010, a contact material layer 160 is formed between adjacent metal bit lines 130, wherein the contact material layer 160 covers the second sacrificial layer 152. Specifically, a suitable deposition process (e.g., chemical vapor deposition) can be used to form the contact material layer 160, which fills the gaps between adjacent metal bit lines 130 and covers the second sacrificial layer 152. Next, a planarization process can be performed such that the top surface of the contact material layer 160 and the top surface of the metal bit lines 130 are coplanar. Figure 6 As shown, since the second sacrificial layer 152 has a lower width W1 greater than its upper width W2 in the second direction D2, the contact material layer 160 has an upper width W4 greater than its lower width W3 in the second direction D2. It should be understood that, although... Figure 6 The illustration shows a combination of three metal bit lines 130 and two contact material layers 160. The semiconductor structure 10 may include other numbers of metal bit lines 130 and contact material layers 160, for example, two metal bit lines 130 and three contact material layers 160 may be arranged alternately on the substrate 100.

[0034] In some embodiments, the contact material layer 160 may extend into the substrate 100 or further into the polysilicon bit line 120, thereby forming a vertically oriented conductive path that allows the semiconductor structure 10 to connect to conductive features on its upper or lower layers. In some embodiments, the material forming the contact material layer 160 may include a conductive material, such as doped polysilicon, a metal, a metal silicide, a metal nitride, a suitable material, or a combination thereof. In some embodiments, the contact material layer 160 may further include a barrier layer (not shown) formed on the side and bottom surfaces of the contact material layer 160, allowing the contact material layer 160 to contact the substrate 100 via the barrier layer.

[0035] refer to Figure 1 Combination Figure 7 In step 1012, the contact material layer 160 is etched to form the contact 162. Specifically, the contact material layer 160 is selectively etched to recess it such that the top surface of the contact material layer 160 is lower than the top surface of the metal bit line 130, thereby forming the contact 162. More specifically, the etching process of the contact material layer 160 may stop above the second sacrificial layer 152, such that the top surface of the contact 162 contacts the upper portion of the second sacrificial layer 152, which has a tapered width. In other words, the contact 162 is similar to the contact material layer 160, having an upper width greater than a lower width in the second direction D2.

[0036] In some embodiments, the top surface of the contact 162 may have a width W6 in the second direction D2, and the portion of the top surface of the contact 162 and the substrate 100 that are coplanar may have a width W5 in the second direction D2. For example... Figure 7 As shown, the difference between the widths W5 and W6 of the contact 162 depends on the tapered structure of the second sacrificial layer 152. For example, the difference between the widths W5 and W6 of the contact 162 can be between 5 nm and 20 nm. In some embodiments where the second conductive layer 136 is a gate metal layer, the top surface of the contact 162 contacts the upper part of the second sacrificial layer 152, and the upper part of the second sacrificial layer 152 can be higher than the top surface of the second conductive layer 136. Therefore, the top surface of the contact 162 can be located between the top surface of the metal bit line 130 and the top surface of the second conductive layer 136. In some embodiments where the first conductive layer 134 is a gate metal layer, the top surface of the contact 162 can be located between the top surface of the metal bit line 130 and the top surface of the first conductive layer 134, and can be lower than the top surface of the second conductive layer 136.

[0037] refer to Figure 1 Combination Figure 8In step 1014, a second sacrificial layer 152 is removed between the metal bit line 130 and the contact 162 to form a gap 170. Specifically, the second sacrificial layer 152 is removed using a selective etching process (e.g., wet etching) to form the gap 170 between the bit line spacer layer 140 and the contact 162. Figure 8 As shown, the gap 170 formed by removing the second sacrificial layer 152 has a profile similar to the second sacrificial layer 152, such that the distance between the upper part of the contact 162 and the bit line spacer layer 140 is smaller than the distance between the lower part of the contact 162 and the bit line spacer layer 140. Because the second sacrificial layer 152 has a sufficient width W1 (as shown in the image), Figure 5 As shown, this allows the selective etching process to completely remove the second sacrificial layer 152. Therefore, in a semiconductor structure 10 having multiple second sacrificial layers 152, removing the second sacrificial layers 152 can form multiple gaps 170 with the same depth, thereby forming air gaps of uniform depth and complete structure in subsequent processes.

[0038] refer to Figure 1 Combination Figure 9 In step 1016, a capping layer 180 is deposited covering the metal bit line 130, the bit line spacer layer 140, and the contact 162, thereby forming an air gap 190. Specifically, it is possible to... Figure 8 A conformally formed capping layer 180 is formed on the structure shown, such that the capping layer 180 forms an air gap 190 in the gap 170 between the bit line spacer layer 140 and the contact 162. The air gap 190 formed in the gap 170 has a profile similar to the gap 170, such that the top portion of the air gap 190 is inclined toward the bit line spacer layer 140. The air gap 190 can reduce the parasitic capacitance between the metal bit line 130 and the contact 162, thereby increasing the reliability of the semiconductor structure 10.

[0039] like Figure 9As shown, the cover layer 180 includes a first portion 182 covering the sidewalls of the bit line spacer layer 140, a second portion 184 covering the sidewalls of the contact 162, and a third portion 186 covering the top surface of the contact 162. When the cover layer 180 is conformally formed on the bit line spacer layer 140 and the contact 162, since the distance between the upper part of the contact 162 and the bit line spacer layer 140 is smaller than the distance between the lower part of the contact 162 and the bit line spacer layer 140, the third portion 186 and the first portion 182 are in contact with each other, while the second portion 184 and the first portion 182 remain separated. In other words, the cover layer 180 forms an air gap 190 in the gap 170 between the first portion 182 and the second portion 184 in a self-seal manner. It is worth noting that since the cover layer 180 forms the air gap 190 through self-encapsulation, it avoids the use of additional material layers for encapsulation, which would cause material to seep into the air gap 190, thereby maintaining the integrity of the air gap 190 structure and effectively reducing the parasitic capacitance of the semiconductor structure 10.

[0040] In some embodiments, the capping layer 180 may have an appropriate thickness such that when the first portion 182 and the third portion 186 of the capping layer 180 are in contact with each other, the first portion 182 and the second portion 184 of the capping layer 180 remain separated. For example, the thickness of the capping layer 180 may be between 3 nm and 5 nm. However, it should be understood that the thickness of the capping layer 180 may be beyond the range described above, depending on the width of the gap 170 and the design of the semiconductor structure 10. In some embodiments, the material forming the capping layer 180 may include silicon nitride, silicon oxide, silicon oxynitride, metal, metal nitride, or other suitable materials. In some embodiments, the capping layer 180 and the bit line spacer layer 140 may include the same material to increase the adhesion between the capping layer 180 and the bit line spacer layer 140. In some embodiments, the capping layer 180 may be formed using a suitable deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, etc.

[0041] In some embodiments, the bottom width of the air gap 190 may be greater than the top width. For example, the bottom width of the air gap 190 in the second direction D2 may be between 1 nm and 10 nm. In some embodiments, the air gap 190 does not need to be filled with air; it may be filled with other types of gas, or it may be a vacuum.

[0042] According to the embodiments described above, this disclosure provides a semiconductor structure and a method for forming the same. In the process of forming the semiconductor structure, a sacrificial layer of sufficient width is used to retain the air gap space within the semiconductor structure, enabling the formation of a uniformly deep and structurally complete air gap between the metal bit lines and the contacts. Furthermore, a capping layer in the semiconductor structure forms the air gap through self-encapsulation, further maintaining the structural integrity of the air gap. Therefore, the air gap in the semiconductor structure effectively reduces the parasitic capacitance between the metal bit lines and the contacts, thereby increasing the stability of the device including the semiconductor structure.

[0043] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas disclosed herein. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0044] [Symbol Explanation]

[0045] 10: Semiconductor Structure

[0046] 100:Substrate

[0047] 110, 120: Polycrystalline silicon bit lines

[0048] 130: Metal Bit Line

[0049] 132: Dielectric layer

[0050] 134: First conductive layer

[0051] 136: Second conductive layer

[0052] 138: Dielectric layer

[0053] 140: Bit line spacer layer

[0054] 150: First Sacrifice Layer

[0055] 152: Second Sacrificial Layer

[0056] 160: Contact material layer

[0057] 162: Contact element

[0058] 170: Gap

[0059] 180: Overlay

[0060] 182: Part One

[0061] 184: Part Two

[0062] 186: Part Three

[0063] 190: Air gap

[0064] 1000: Method

[0065] 1002, 1004, 1006, 1008, 1010, 1012, 1014, 1016: Steps

[0066] D1: First Direction

[0067] D2: Second Direction

[0068] W1, W2, W3, W4, W5, W6: Width.

Claims

1. A semiconductor structure, characterized in that, include: substrate; Metal bit lines are located on the substrate; Bit line spacer layer, located on the sidewall of the metal bit line; A contact element, adjacent to the metal bit line, wherein the upper width of the contact element is greater than the lower width; A cover layer covers the metal bit line, the bit line spacer layer, and the contact, wherein the cover layer includes a first portion covering the sidewall of the bit line spacer layer, a second portion covering the sidewall of the contact, and a third portion covering the top surface of the contact. as well as An air gap is located between the first and second portions of the cover layer, wherein the top portion of the air gap is inclined toward the bit line spacer layer, and the first and third portions of the cover layer are in contact with each other above the air gap.

2. The semiconductor structure according to claim 1, characterized in that, The bottom width of the air gap is greater than the top width.

3. The semiconductor structure according to claim 2, characterized in that, The bottom width of the air gap is between 1 nm and 10 nm.

4. The semiconductor structure according to claim 1, characterized in that, The top surface of the contact has a first width, and the portion of the contact that is coplanar with the top surface of the substrate has a second width. The difference between the first width and the second width is between 5 nm and 20 nm.

5. The semiconductor structure according to claim 1, characterized in that, The metal bit line includes a gate metal layer, and the top surface of the contact is located between the top surface of the metal bit line and the top surface of the gate metal layer.

6. The semiconductor structure according to claim 1, characterized in that, The thickness of the coating layer is between 3nm and 5nm.

7. A method for forming a semiconductor structure, characterized in that, include: A plurality of metal bit lines are formed on the substrate; A plurality of bit-line spacer layers are formed on the sidewalls of each of the metal bit lines; The first sacrificial layer is formed on the sidewall of each of the bit line spacers; The first sacrificial layer is etched to form a second sacrificial layer, wherein the lower width of the second sacrificial layer is greater than the upper width; Contacts are formed between adjacent metal bit lines, wherein the contact contacts the second sacrificial layer; Remove the second sacrificial layer to form a gap between the bit line spacers and the contact; as well as A cover layer is deposited covering the metal bit lines, the bit line spacers, and the contact to form an air gap in the gap, wherein the cover layer includes a first portion covering the sidewalls of the bit line spacers, a second portion covering the sidewalls of the contact, and a third portion covering the top surface of the contact, the first portion and the third portion being in contact with each other.

8. The method according to claim 7, characterized in that, The width of the lower part of the second sacrificial layer is between 10nm and 15nm.

9. The method according to claim 7, characterized in that, The formation of the contact between adjacent metal bit lines further includes: A contact material layer is formed between adjacent metal bit lines, wherein the contact material layer covers the second sacrificial layer; and The contact material layer is etched to form the contact, such that the top surface of the contact is lower than the top surface of the metal bit lines.

Images