Thin film transistor and manufacturing method thereof, array substrate, and display device

Abstract

The present application discloses a thin film transistor, a manufacturing method, an array substrate, and a display device, comprising: an active layer disposed on a substrate, the active layer including a channel region; a gate insulating layer disposed on the active layer, the gate insulating layer defining an ion implantation region, the ion implantation region including a first implantation region located in the middle and second implantation regions located on either side of the first implantation region, the orthographic projections of the ion implantation regions on the substrate overlapping the orthographic projections of the channel region on the substrate; the distance from the first upper surface of the first implantation region to the upper surface of the active layer is shorter than the distance from the second upper surface of the second implantation region to the upper surface of the active layer. This improves the uniformity of the threshold voltage, the hysteresis characteristics of the thin film transistor, and the display effect; simplifies the manufacturing process of the thin film transistor, avoids damage to the polysilicon film layer in the channel region, and improves the film quality of the active layer channel region.

Description

Technical Field

[0001] The present application generally relates to the field of display technology, and specifically relates to a thin film transistor and a preparation method thereof, an array substrate, and a display device. Background Art

[0002] LTPS (Low Temperature Poly-Silicon) thin film transistors (TFTs) are widely used in display products such as mobile phones, watches, and tablet computers. LTPS technology can form a high-mobility polysilicon semiconductor layer by doping the polysilicon semiconductor layer, giving displays advantages such as high resolution, high aperture ratio, high response speed, and low power consumption.

[0003] The presence and uneven distribution of defects at grain boundaries in polysilicon thin films results in poorly uniform threshold voltage (Vth) across thin-film transistors. This problem becomes more severe as transistor size decreases. Fluctuations in threshold voltage can cause light and dark spots or stripes to appear on OLED flat-panel displays.

[0004] In the existing technology, although the hydrogenation process can fill the inter-grain boundary state to a certain extent, thereby improving the threshold voltage uniformity of the TFT, when the device temperature is higher than 300°C, hydrogen is easy to break bonds and escape, and excessive hydrogenation will produce too many Si-H bonds, resulting in a decrease in mobility.

[0005] Therefore, providing a more stable and reliable method for improving the uniformity of the threshold voltage to ensure that the device has better display characteristics has become an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0006] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a thin film transistor, a method for manufacturing the same, and a display device, which can improve the uniformity of the threshold voltage of the thin film crystal and simplify the manufacturing process.

[0007] In a first aspect, the present application provides a thin film transistor, comprising:

[0008] An active layer disposed on a substrate, the active layer comprising a channel region;

[0009] A gate insulating layer is arranged on the active layer, and the gate insulating layer defines an ion injection region, wherein the ion injection region includes a first injection region located in the middle and second injection regions located on both sides of the first injection region, and the orthographic projection of the ion injection region on the substrate overlaps with the orthographic projection of the channel region on the substrate; the distance from the first upper surface of the first injection region to the upper surface of the active layer is less than the distance from the second upper surface of the second injection region to the upper surface of the active layer.

[0010] Optionally, the active layer is a low-temperature polysilicon semiconductor layer, and the gate insulating layer is any one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0011] Optionally, along the width direction of the channel region, the distances from various positions on the upper surface of the first injection region to the upper surface of the active layer are equal or nearly equal.

[0012] Optionally, along the width direction of the channel region, the channel region includes a high-doping region located in the middle and low-doping regions located on both sides of the high-doping region, and the ion concentration of the high-doping region is greater than the ion concentration of the low-doping region.

[0013] Optionally, the orthographic projection of the first implantation region on the substrate at least covers the orthographic projection of the highly doped region on the substrate.

[0014] Optionally, along the length direction of the channel region, the active layer includes a source region and a drain region respectively arranged on one side of the channel region;

[0015] The thin film transistor further includes:

[0016] A gate layer, an interlayer dielectric layer, and a source-drain metal layer are stacked on the gate insulating layer. The source-drain metal layer contacts the active layer in the source region and the drain region respectively to form a source electrode and a drain electrode.

[0017] Optionally, a difference between a distance from a first upper surface of the first injection region to an upper surface of the active layer and a distance from a second upper surface of the second injection region to an upper surface of the active layer ranges from 30 nm to 120 nm.

[0018] Optionally, the width of the second injection region along the width direction of the channel region is 1 / 20 to 1 / 3 of the width of the channel region.

[0019] In a second aspect, the present application provides a method for preparing a thin film transistor, for preparing any of the above thin film transistors, the method comprising:

[0020] forming an active layer on a substrate and patterning the active layer;

[0021] forming a gate insulating layer on the active layer, and patterning the first implantation region and the second implantation region;

[0022] Through an ion implantation process, ions are implanted into the active layer through the gate insulating layer to form a high-doping region corresponding to the first implantation region and a low-doping region corresponding to the second implantation region.

[0023] Optionally, the implanted ions in the ion implantation process are boron ions, so as to form the thin film crystal with a positive threshold voltage.

[0024] Optionally, the implanted ions in the ion implantation process are phosphorus ions, so as to form the thin film crystal with a negative threshold voltage.

[0025] In a third aspect, the present application provides an array substrate, comprising an array substrate and a plurality of thin film transistors as described above arranged in an array on the array substrate.

[0026] In a fourth aspect, the present application provides a display device comprising any array substrate as described above.

[0027] The technical solutions provided by the embodiments of the present application may have the following beneficial effects:

[0028] The embodiments of the present application provide a thin film transistor. By forming gate insulating layers of different thicknesses on the channel region of the corresponding active layer, the threshold voltage of the thin film transistor is adjusted by adopting the same doping process, so as to achieve high doping in the central region of the channel region and low doping in the edge region of the channel region, thereby improving the uniformity of the threshold voltage; improving the hysteresis characteristics of the thin film transistor and enhancing the display effect; simplifying the manufacturing process of the thin film transistor, and avoiding damage to the polysilicon film layer in the channel region, thereby improving the film layer quality of the channel region of the active layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0030] Figure 1 A top view of a thin film transistor provided in an embodiment of the present application;

[0031] Figure 2 for Figure 1 Schematic diagram of the cross section at AA in the middle;

[0032] Figure 3 for Figure 1 Schematic diagram of the cross section at the middle BB;

[0033] Figure 4A schematic diagram of the arrangement of a channel region provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of another arrangement of channel regions provided in an embodiment of the present application;

[0035] Figure 6 A schematic structural diagram of a channel region provided in an embodiment of the present application;

[0036] Figure 7 A top view of a gate insulating layer provided in an embodiment of the present application;

[0037] Figure 8 A flow chart of a method for manufacturing a thin film transistor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. It should also be noted that, for ease of description, only the portions relevant to the invention are shown in the accompanying drawings.

[0039] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0040] The driving transistor in the pixel drive circuit generates a driving current, and the light-emitting element emits light in response to this driving current. The driving current generated by the driving transistor is directly related to its characteristics, and the stability of the TFT device is crucial to the quality of the panel display. However, in the actual manufacturing process, the presence of charge centers and defect states in the TFT device can cause the threshold voltage to drift during operation, which in turn can negatively affect the image quality on the display.

[0041] For example, the subthreshold swing is the slope of the curve from the off state (cut-off state) to the on state (conduction state) in the semiconductor output characteristic curve. The smaller the slope, the faster the response speed of the thin film transistor from the off state to the on state. Correspondingly, the better the subthreshold swing characteristics, the better the performance of the thin film transistor; the larger the slope, the slower the response speed of the thin film transistor from the off state to the on state. Correspondingly, the worse the subthreshold swing characteristics, the worse the performance of the thin film transistor.

[0042] Through research, this application found that the subthreshold region mainly depends on the central region of the transistor channel region T. In order to improve the characteristics of the central region, please refer to Figure 1-3 , the present application provides a thin film transistor, comprising:

[0043] Base substrate 100;

[0044] An active layer 200 is provided on the base substrate 100 , wherein the active layer 200 includes a channel region T;

[0045] A gate insulating layer 300 is provided on the active layer 200, and the gate insulating layer 300 defines an ion implantation region, wherein the ion implantation region includes a first implantation region P1 located in the middle and second implantation regions P2 located on both sides of the first implantation region P1, and the orthographic projection of the ion implantation region on the base substrate 100 overlaps with the orthographic projection of the channel region T on the base substrate 100; the distance from the first upper surface of the first implantation region P1 to the upper surface of the active layer 200 is less than the distance from the second upper surface of the second implantation region P2 to the upper surface of the active layer 200.

[0046] In the present application, gate insulating layers 300 of different thicknesses are formed on the channel region T corresponding to the active layer 200, and the threshold voltage (Vth) of the thin film transistor is adjusted by using the same doping process, thereby achieving high doping in the central region of the channel region T and low doping in the edge region of the channel region T. The doping process for adjusting the threshold voltage can be a process of doping the thin film transistor with boron ions or phosphorus ions, which varies depending on the type of transistor or application scenario. The doping methods for different transistor types will be described in detail below.

[0047] It should be noted that in the ion implantation process in the embodiment of the present application, the ion doping method in the corresponding channel region T can be controlled by implanting the entire surface of the gate insulating layer 300. The entire surface implantation method can simplify the preparation process and prevent the complexity of the thin film transistor preparation process caused by multiple implantations or process control. In the implementation of the present application, the ion implantation area is only the area corresponding to the active layer 200, and is not the actual control area in the actual ion implantation process. Of course, in different embodiments, the actual implantation area of ​​the ion implantation process can be controlled as needed.

[0048] Based on their semiconductor properties, transistors can be classified as N-type transistors (NMOS) and P-type transistors (PMOS). For example, for a P-type TFT, when the voltage applied to the gate 400 is less than the threshold voltage (Vth < 0), the source 610 and the drain 620 are conductive. Therefore, the threshold voltage is an important parameter that determines TFT performance.

[0049] Optionally, the active layer 200 is a low-temperature polysilicon semiconductor layer, and the gate insulating layer 300 is any one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0050] It should be noted that the present application does not limit the type of thin film transistor 20, and different configurations can be used depending on the device or application scenario. The types of thin film transistors in the present application include but are not limited to low-temperature polysilicon thin film transistors (LTPS), and the active layer 200 is formed by polysilicon deposition.

[0051] Ion implantation is achieved by ionizing the atoms (molecules) to be implanted. After the ions are accelerated and shot into the solid material, a series of collisions will occur with the atomic nuclei and electrons in the material. After a tortuous path of movement, the energy of the incident ions gradually loses, and finally they stay in the material, causing changes in the surface composition, structure and properties of the material.

[0052] Through research in this application, it was found that gate insulating layers 300 of different thicknesses have different ion blocking capabilities. When the thickness is too high, ion injection is completely blocked when passing through the gate insulating layer 300 and cannot enter the active layer 200. Within a certain gate insulating layer 300 thickness range, the thinner the gate insulating layer 300, the smaller the ion blocking capability. When the appropriate injection energy is selected, the ion doping concentration in the active layer 200 can be higher.

[0053] In the embodiment of the present application, along the width W of the channel region T, the distance from each position on the upper surface of the first injection region P1 to the upper surface of the active layer 200 is equal or nearly equal. By maintaining the same thickness of the gate insulation layer 300 at each position corresponding to the first injection region P1, the ion blocking capability within the region can be made uniform, ensuring that the ion injection concentration in the central channel region T corresponding to the first injection region P1 is the same, making the threshold voltage more uniform. By improving the height uniformity of the first injection region P1, the transistor characteristics in the central region of the channel region T can be effectively improved, the uniformity of the threshold voltage and the subthreshold swing characteristics can be improved, and the hysteresis characteristics of the transistor can be effectively improved. In the embodiment of the present application, the gate insulation layer 300 can also protect the surface of the active layer 200 from damage by ion implantation bombardment, thereby improving the ion implantation effect.

[0054] It should be noted that the equal distances described in the embodiments of the present application refer to strict consistency of distances, and nearly equal distances refer to approximate consistency of distances, including the values ​​described and average values ​​within an acceptable deviation range of a specific value, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account process preparation errors or measurement-related errors.

[0055] In the existing thin film transistor structure, when voltage is applied to the gate 400, an electric field is formed between the gate 400 and the active layer 200. Due to the action of the electric field, the carriers in the active layer 200 begin to move and generate current. When the channel region T reaches the saturation current, the thin film transistor is turned on. In related technologies, the edge channel region T may reach the saturation current and turn on first before the central channel region T. The TFT characteristics of the edge channel region T are obvious, which makes the overall threshold voltage of the thin film transistor uneven.

[0056] In one embodiment of the present application, Figure 4 As shown, the shape of the channel region T is a square structure. Along the width W direction of the channel region T, the channel region T includes a high-doping region T1 located in the middle and low-doping regions T2 located on both sides of the high-doping region T1. The ion concentration of the high-doping region T1 is greater than the ion concentration of the low-doping region T2.

[0057] It is understandable that the ion concentrations of the high-doped region T1 and the low-doped region T2 mentioned here are only for the formation of the high-doped region T1 and the low-doped region T2, and are not comparable to the ion concentrations of ion implantation when forming other regions. The embodiments of the present application do not limit the specific values ​​of "high" and "low" corresponding to the high-doped region T1 domain and the low-doped region T2 domain. The low-doped region T2 corresponds to the edge channel region T, and the high-doped region T1 corresponds to the central channel region T. The embodiments of the present application do not limit the specific values ​​of the edge channel region T and the central channel region T. In different embodiments, they can be selected according to the device or application scenario.

[0058] It should be noted that, in the embodiment of the present application, the channel region T of the thin film transistor can be of regular shape or other irregular shape. For example, in other embodiments of the present application, Figure 5 As shown, the shape of the channel region T can also be an irregular shape, for example, the shape of the channel region T is a "J" shape. Along the width W of the channel region T, the channel region T includes a high-doping region T1 located in the middle and low-doping regions T2 located on both sides of the high-doping region T1. The shapes of the high-doping region T1 and the low-doping region T2 are similar to the shape of the channel region T, both of which are "J" shapes. The ion concentration of the high-doping region T1 is greater than the ion concentration of the low-doping region T2.

[0059] In the embodiment of the present application, the ion implantation amount of the low-doped region T2 is smaller than the ion implantation amount of the high-doped region T1, so that the carrier concentration of the low-doped region T2 in the thin film transistor is lower than the carrier concentration of the high-doped region T1. When a voltage is applied to the gate 400, current can be generated in both the low-doped region T2 and the high-doped region T1. The low-doped region T2 will reach the saturation current later than the high-doped region T1, thereby reducing the risk of the low-doped regions T2 on both sides being turned on before the high-doped region T1, ensuring that the thin film transistor mainly reflects the characteristics of the central channel region T, and improving the reliability of the thin film transistor device.

[0060] For example, in the present application, the channel region T of the active layer 200 is doped by ion implantation on the gate insulating layer 300 to realize a high-doping region T1 and a low-doping region T2 with different ion concentrations in the channel region T. For PMOS, the third main group elements, such as boron and indium, are generally implanted into the active layer 200 to achieve positive bias, while for NMOS, the fifth main group elements, such as phosphorus and arsenic, are generally doped into the active layer 200 to achieve negative bias.

[0061] In this embodiment, polycrystalline silicon doped with a small amount of phosphorus (or antimony) as an impurity replaces semiconductor atoms (such as silicon atoms) with impurity atoms. Four of the five outer-shell electrons of the phosphorus atoms form covalent bonds with surrounding semiconductor atoms, leaving the remaining electron virtually unbound and easily free. Consequently, the active layer 200 becomes a semiconductor with a high electron concentration in the highly doped region T1. Under positive bias, the highly doped region T1 in the channel region T first forms a conductive layer, achieving a negative threshold voltage.

[0062] In polysilicon doped with a small amount of impurity boron (or indium), as semiconductor atoms (such as silicon atoms) are replaced by impurity atoms, a "hole" is generated when the three outer electrons of the boron atom form covalent bonds with the surrounding semiconductor atoms. This hole may attract bound electrons to "fill" it, making the boron atom a negatively charged ion. The conduction of PMOS depends on the accumulation of holes. Under negative bias, the highly doped region T1 in the channel region T first forms a conductive layer, achieving a positive threshold voltage.

[0063] It is worth noting that in the embodiments of the present application, a driving transistor applied to a pixel circuit is used as an example for description. By improving the uniformity of its threshold voltage, this will have a good improvement effect on the current low grayscale Mura. By making the threshold voltage of the driving transistor appropriately offset, a good driving effect is achieved. However, in different embodiments, the requirements for the threshold voltage are different. In this application, the positive bias of the threshold voltage for PMOS or the negative bias of the threshold voltage for NMOS are used as an example for description. In different application scenarios, selection can be made according to the offset requirements of the transistor threshold voltage.

[0064] In one embodiment of the present application, the orthographic projection of the first implantation region P1 on the substrate 100 at least covers the orthographic projection of the highly doped region T1 on the substrate 100. The orthographic projection of the second implantation region P2 on the substrate 100 at least covers the orthographic projection of the low doped region T2 on the substrate 100. In order to improve the uniformity of ion implantation in the highly doped region T1 on the active layer 200, the range of the first implantation region P1 is appropriately increased within a reasonable range, especially for the edge of the opening in the gate insulating layer 300 caused by process factors such as etching, which results in uneven etching and thus uneven thickness of the gate insulating layer 300.

[0065] Along the length L of the channel region T, the active layer 200 includes a source region S and a drain region D, each disposed on one side of the channel region T. It should be noted that the semiconductor active layer 200 between the source electrode 610 and the drain electrode 620 can form a conductive channel. The distance between the source electrode 610 and the drain electrode 620 is referred to as the channel length L, and the conductive direction perpendicular to the L direction is the width W of the drain and source electrodes 610. In this embodiment, the direction along the length L of the channel region T is the direction from the source electrode 610 to the drain electrode 620, that is, the direction from the source region S to the drain region D, and the direction along the width W of the channel region T is the direction perpendicular to the length of the channel region T.

[0066] In the embodiment of the present application, a gate electrode 400, an interlayer dielectric layer 500, and a source / drain metal layer 600 are stacked on the gate insulating layer 300. The source / drain metal layer 600 contacts the active layer 200 in the source region S and the drain region D, respectively, to form a source electrode 610 and a drain electrode 620. As can be seen from the above, the structure of the TFT is a top-gate type. However, the structure of the TFT in this embodiment may also be a bottom-gate type, and this embodiment is not limited thereto.

[0067] Optionally, the width of the second injection region P2 along the width W of the channel region T is 1 / 20 to 1 / 3 of the width of the channel region T. Optionally, the difference between the distance from the first upper surface of the first injection region P1 to the upper surface of the active layer 200 and the distance from the second upper surface of the second injection region P2 to the upper surface of the active layer 200 is in a range of 30 nm to 120 nm.

[0068] For example, in this embodiment, the acceleration voltage of ion implantation is in the range of 8KV to 20KV, the overall channel width is in the range of 3um to 6um, the width of the second implantation region P2 is controlled to be in the range of 0.3um to 1um; the thickness of the first implantation region P1 is in the range of 60nm to 200nm, and the thickness of the second implantation region P2 is in the range of 90nm to 200nm; the boron ion doping concentration of the highly doped region T1 is 5E11 to 3E12 ion / cm 2Correspondingly, the low-doping region T2 is 2E11~1E12 ions / cm lower than the high-doping region T1. 2 .

[0069] It can be understood that the above-mentioned thin film transistor is for I-type channel thin film transistors, but the present invention is not limited thereto and is also applicable to thin film transistors with other channel shapes, such as L-type channel thin film transistors and U-type channel thin film transistors. Figure 6 As shown, for a U-channel thin film transistor, a U-shaped channel region T is formed in the portion of the active layer 200 between the source 610 and the drain 620. The length L direction of the channel region T is the source 610 and the drain 620, and the width W direction of the channel region T extends along a U-shaped line. The U-shaped line is perpendicular to the channel length direction and is located in a plane parallel to the base substrate 100.

[0070] For the U-shaped channel region T, if Figure 7 As shown, the shape of the first injection region P1 on the gate insulating layer 300 is similar to the shape of the channel region T. In the direction of the width W of the channel region T, the distances from each position on the upper surface of the first injection region P1 to the upper surface of the active layer 200 are equal or nearly equal. By forming a thinned region on the gate insulating layer 300, a highly doped region T1 can be formed in the middle of the channel region T. The ion concentration of the highly doped region T1 is greater than the ion concentration of the active layer 200. Figure 8 As shown, the present application also provides a method for preparing a thin film transistor, which is used to prepare any of the thin film transistors described above, and the method includes:

[0071] S10 , forming an active layer 200 on the base substrate 100 and patterning it.

[0072] The substrate 100201 can be a glass substrate, a quartz substrate, or other substrates. The active layer 200 can be formed, for example, by forming an amorphous silicon (aSi) thin film on the first buffer layer using plasma-enhanced chemical vapor deposition. The amorphous silicon (a-Si) thin film is then laser annealed to convert the amorphous silicon (a-Si) into polycrystalline silicon (p-Si). For example, the laser annealing process can be an excimer laser annealing process.

[0073] After crystallization is completed, the active layer 200 pattern is exposed, developed, etched, and stripped using a mask plate to form an active layer 200 including a source region S, a drain region D, and a channel region T. For example, a photoresist is coated on the surface of the low-temperature polycrystalline silicon thin film, and the photoresist is exposed using a mask plate to form a photoresist-unretained area and a photoresist-retained area in the photoresist, wherein the photoresist-retained area corresponds to the area where the patterns of the source region S, the drain region D, and the channel region T are located, and the photoresist-unretained area corresponds to the area outside the above patterns; a development process is performed to completely remove the photoresist in the photoresist-unretained area, while the photoresist thickness in the photoresist-retained area remains unchanged; the low-temperature polycrystalline silicon thin film in the photoresist-unretained area is completely etched away through an etching process, and the remaining photoresist is stripped off to form an active layer 200 including a source region S, a drain region D, and a channel region T. The source region S is used to contact the source electrode of the thin film transistor, and the drain region D is used to contact the drain electrode of the thin film transistor.

[0074] S20 , forming a gate insulating layer 300 on the active layer 200 , and patterning the first implantation region P1 and the second implantation region P2 .

[0075] The gate insulating layer 300 may be formed, for example, by chemical vapor deposition, but is not limited thereto. In an exemplary embodiment, the gate insulating layer 300 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0076] It should be noted that in the field of display technology, a patterning process may include only photolithography, or may include both photolithography and etching steps, and may also include other processes such as printing and inkjet printing to form a predetermined pattern. A photolithography process refers to a process that uses photoresist, a mask, and an exposure machine to form a pattern, including film formation, exposure, and development processes. The corresponding patterning process can be selected based on the structure formed in the present invention.

[0077] Through the patterning process of the gate insulation layer 300, the gate insulation layer 300 with different heights corresponding to different areas is formed. Specifically, the gate insulation layer 300 defines an ion injection area, and the ion injection area includes a first injection area P1 located in the middle and a second injection area P2 located on both sides of the first injection area P1. The orthographic projection of the ion injection area on the base substrate 100 overlaps with the orthographic projection of the channel area T on the base substrate 100; the distance from the first upper surface of the first injection area P1 to the upper surface of the active layer 200 is less than the distance from the second upper surface of the second injection area P2 to the upper surface of the active layer 200.

[0078] S30 , through an ion implantation process, implanting ions into the active layer 200 through the gate insulating layer 300 to form a high-doped region T1 corresponding to the first implanted region P1 and a low-doped region T2 corresponding to the second implanted region P2 .

[0079] It should be noted that, in the embodiment of the present application, in step S30, the ion implantation method for the channel region T is full-surface implantation. Optionally, the implanted ions in the ion implantation process are boron ions to form the thin film crystal with a positive threshold voltage. Optionally, the implanted ions in the ion implantation process are phosphorus ions to form the thin film crystal with a negative threshold voltage.

[0080] In the embodiment of the present application, the thin film transistor is illustratively a top-gate TFT, and the fabrication method further comprises: forming a gate electrode 400, an interlayer dielectric layer 500, and a source / drain metal layer 600 on the gate insulating layer 300. The fabrication method of the thin film transistor can be used to form a PMOS transistor and / or an NMOS transistor.

[0081] It is understood that in the embodiments of the present application, the heavily doped source and drain regions have no direct relationship to the doping process of the highly doped region T1 and the lowly doped region T2 of the channel region T, and the doping composition and doping concentration are not directly related. The heavily doped source and drain regions are conventional methods for achieving transistor conductivity in the prior art, and various different methods in the prior art can be used in this application, and this application does not limit this.

[0082] The main difference between an NMOS transistor and a PMOS transistor is that the source region S and drain region D are formed by heavy N-type ion doping and heavy P-type ion doping, respectively. In a PMOS transistor, boron ions are generally doped in the area where the source 610 and drain 620 to be formed are in contact, forming a heavily doped source region and a heavily doped drain region, thereby improving the electrical contact between the active layer 200 to be formed and the source 610 and drain 620. In an NMOS transistor, a high amount of phosphorus ions are generally doped in the area where the source 610 and drain 620 to be formed are in contact, thereby forming a heavily doped source region and a heavily doped drain region, thereby improving the electrical contact between the active layer 200 to be formed and the source 610 and drain 620.

[0083] In the embodiments of the present application, the process of forming the heavily doped source and drain regions can be performed after the doping of the channel region T is completed and before the gate 400 is formed, or after the gate 400 is formed, and the present application does not limit this. After the gate 400 is formed, the gate 400 can be used as a mask for the ion implantation process of the source and drain regions D; before the gate 400 is formed, a photoresist can be used as a mask for the ion implantation process of the source and drain regions D. In specific applications, adjustments can be made based on the type of thin film transistor or the application scenario, and the present application does not limit this.

[0084] For example, the heavily doped source region and the heavily doped drain region are formed after the gate 400 is formed. Specifically, under the shielding of the gate 400, a predetermined element is implanted into the polysilicon active layer 200 through an ion implantation process to form a source region S located on one side of the channel region T and a drain region D located on the other side of the channel region T, wherein the orthographic projection of the channel region T on the base substrate 100 overlaps with the orthographic projection of the gate 400 on the base substrate 100.

[0085] For example, the heavily doped source region and the heavily doped drain region are formed before the gate 400 is formed. Specifically, different photoresist thicknesses have different transmittances to ion implantation. Therefore, depending on the region of the photoresist where ions need to be implanted, a photoresist of a preset thickness can be coated on the active layer 200. The photoresist is partially exposed through an exposure process. After the partial exposure, the remaining unexposed photoresist is thick enough for ions to penetrate, thereby forming the source electrode 610 in the source region S of the active layer 200.

[0086] In an embodiment of the present application, the process of forming the gate 400 includes: depositing a layer of gate 400 metal film on the base substrate 100 by vapor deposition, magnetron sputtering, vacuum evaporation, etc., wherein the material of the gate 400 metal film is selected from one or more of titanium, tantalum, copper, aluminum, molybdenum, chromium, or one or more alloys formed by any combination of the above metals. For example, the gate 400 metal film can be a single-layer or multi-layer structure, and accordingly, the formed gate 400 can be a single-layer or multi-layer structure. A photoresist pattern (not shown) is formed on the gate 400 metal film at a position where the gate 400 pattern is to be formed, and the gate 400 metal film is etched using the photoresist pattern as a mask to form the gate 400 pattern, and the photoresist is stripped off.

[0087] Specifically, SiNx or SiO2 can be deposited above the gate electrode to form an interlayer dielectric layer 500. The interlayer dielectric layer 500 includes vias corresponding to the source region S and the drain region D. Then, a source / drain metal layer 600 with a thickness of approximately 10 ...

[0088] A layer of photoresist is coated on the source-drain metal layer 600, and the photoresist is exposed using a mask plate to form a photoresist-unretained area and a photoresist-retained area in the photoresist, wherein the photoresist-retained area corresponds to the area where the source electrode and the drain electrode patterns are located, and the photoresist-unretained area corresponds to the area outside the above patterns; a development process is performed to completely remove the photoresist in the photoresist-unretained area, and the photoresist thickness in the photoresist-retained area remains unchanged; the source-drain metal film in the photoresist-unretained area is completely etched away through an etching process, and the remaining photoresist is stripped off to form the patterns of the source electrode and the drain electrode, the source electrode is connected to the active layer 200 of the source region S through a via hole penetrating the gate insulating layer 300 and the interlayer dielectric layer 500, and the drain electrode is connected to the active layer 200 of the drain region D through a via hole penetrating the gate insulating layer 300 and the interlayer dielectric layer 500.

[0089] The thin film transistors in the embodiments of the present application are applicable to pixel driving circuits of various structures (eg, 2T1C, 6T1C, 8T1C, 9T1C, 12T1C, or 8T2C, etc.) It is understandable that different pixel circuit structures are selected in different application scenarios.

[0090] Based on the same inventive concept, the present application provides an array substrate, comprising a base substrate 100 and any of the above-described thin film transistors arranged in an array on the base substrate 100 .

[0091] The array substrate may further include a pixel electrode electrically connected to the drain 620 of the transistor. One pixel electrode and one or more transistors constitute a pixel unit. A common electrode may also be included opposite the pixel electrode. That is, the aforementioned pixel unit may also include a common electrode. The arrangement of the various transistors and the array substrate may continue to follow the relevant design, and will not be further described in the embodiments of the present invention.

[0092] Based on the same inventive concept, the present application provides a display device comprising an array substrate as described above. For example, the display device may be a display device such as a liquid crystal display, electronic paper, an OLED (Organic Light-Emitting Diode) display, and any product or component with a display function such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, navigator, etc. comprising these display devices. For different types of display devices, the thin film transistor of the embodiment of the present invention may be formed with a pixel array for an LCD, thereby being combined with an opposing substrate to obtain an LCD, or may be formed with a pixel array for an OLED, thereby being combined with a packaging substrate to obtain an OLED, etc.

[0093] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0094] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more such features. In the description of the present invention, "first" means two or more, unless otherwise specifically defined.

[0095] Unless otherwise defined, the technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present invention. The terms used herein are only for describing specific implementation purposes and are not intended to limit the present invention. Terms such as "setting" appearing in this article can mean that one component is directly attached to another component, or that one component is attached to another component through an intermediate component. Features described in this article in one embodiment can be applied to another embodiment alone or in combination with other features, unless the feature is not applicable in the other embodiment or otherwise specified.

[0096] The present invention has been described through the above embodiments, but it should be understood that the above embodiments are for illustrative and illustrative purposes only and are not intended to limit the present invention to the described embodiments. Those skilled in the art will appreciate that various variations and modifications may be made based on the teachings of the present invention, and such variations and modifications fall within the scope of protection claimed in the present invention.

Claims

1. A thin film transistor, characterized in that: include: An active layer disposed on a substrate, the active layer comprising a channel region; a gate insulating layer disposed on the active layer, the gate insulating layer defining an ion implantation region, the ion implantation region comprising a first implantation region located in the middle and second implantation regions located on both sides of the first implantation region, the orthographic projection of the ion implantation region on the substrate overlapping the orthographic projection of the channel region on the substrate; a distance from a first upper surface of the first implantation region to an upper surface of the active layer being shorter than a distance from a second upper surface of the second implantation region to an upper surface of the active layer; When the shape of the channel region T is a square structure, along the width direction of the channel region, the channel region includes a high-doping region located in the middle and low-doping regions located on both sides of the high-doping region; When the shape of the channel region T is a "J" shape, along the width direction of the channel region, the channel region T includes a high-doping region located in the middle and low-doping regions located on both sides of the high-doping region. The shapes of the high-doping region and the low-doping region are similar to the shape of the channel, both of which are "J" shapes; When the channel region T is formed in a U-shape, the width W of the channel region T extends along the U-shaped line. The channel region T includes a high-doping region T1 in the middle and low-doping regions T2 on both sides of the high-doping region T1.

2. The thin film transistor according to claim 1, wherein The active layer is a low-temperature polysilicon semiconductor layer, and the gate insulating layer is any one or more of silicon oxide, silicon nitride and silicon oxynitride.

3. The thin film transistor according to claim 1, wherein In the width direction of the channel region, distances from various positions on the upper surface of the first implantation region to the upper surface of the active layer are equal or nearly equal.

4. The thin film transistor according to claim 1, wherein The orthographic projection of the first implantation region on the substrate at least covers the orthographic projection of the highly doped region on the substrate.

5. The thin film transistor according to claim 1, wherein Along the length direction of the channel region, the active layer includes a source region and a drain region respectively arranged on one side of the channel region; The thin film transistor further includes: A gate layer, an interlayer dielectric layer, and a source-drain metal layer are stacked on the gate insulating layer. The source-drain metal layer contacts the active layer in the source region and the drain region respectively to form a source electrode and a drain electrode.

6. The thin film transistor according to claim 1, wherein A difference between a distance from a first upper surface of the first injection region to an upper surface of the active layer and a distance from a second upper surface of the second injection region to an upper surface of the active layer is in a range of 30 nm to 120 nm.

7. The thin film transistor according to claim 1, wherein: The width of the second injection region along the width direction of the channel region is 1 / 20 to 1 / 3 of the width of the channel region.

8. A method for preparing a thin film transistor, characterized in that: For preparing the thin film transistor according to any one of claims 1 to 7, the method comprises: forming an active layer on a substrate and patterning the active layer; forming a gate insulating layer on the active layer, and patterning the first implantation region and the second implantation region; Through an ion implantation process, ions are implanted into the active layer through the gate insulating layer to form a high-doping region corresponding to the first implantation region and a low-doping region corresponding to the second implantation region.

9. The method for preparing a thin film transistor according to claim 8, wherein: The implanted ions in the ion implantation process are boron ions, so as to form the thin film crystal with a positive threshold voltage.

10. The method for preparing a thin film transistor according to claim 8, wherein: The implanted ions in the ion implantation process are phosphorus ions, so as to form the thin film crystal with a negative threshold voltage.

11. An array substrate, characterized in that: The invention comprises an array substrate and a plurality of thin film transistors as claimed in any one of claims 1 to 7 arranged in an array on the array substrate.

12. A display device, characterized in that: Comprising the array substrate as claimed in claim 11.

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