A near-field wireless synchronous bidirectional data transmission circuit with multiplexed phase-locked loop

Abstract

A near-field wireless synchronous bidirectional data transmission circuit with a multiplexed phase-locked loop includes: a downlink data link and an uplink data link. The downlink data link includes an external downlink data modulation circuit for performing phase shift keying modulation on the data; includes an internal hysteresis comparator for converting the waveform of the secondary coil into a digital signal; includes an internal multiplexed phase-locked loop and an auxiliary locking circuit for recovering the downlink data and clock; includes an internal start circuit for generating a timing start signal. The uplink data link includes an uplink data modulation circuit for performing pulse load modulation on the data using the multiplexed phase-locked loop and the recovered clock; includes an external uplink data demodulation circuit. The uplink / downlink data links share an off-chip capacitor / inductor for bidirectionally transmitting waveforms inside / outside the body. The present invention connects the uplink and downlink links through a time-division multiplexing phase-locked loop to achieve synchronous near-field bidirectional data transmission, which is beneficial to improving chip integration and data transmission rate.

Description

Technical Field

[0001] The invention relates to the field of analog and mixed signal integrated circuits, and in particular to a near-field wireless synchronous bidirectional data transmission circuit of a multiplexed phase-locked loop. Background Art

[0002] In recent years, the implantable medical device and chip industries have developed rapidly. Most implantable medical devices need to communicate data with the outside world, and in traditional wired data transmission, the wires come into contact with the skin, which may cause wound infection. In order to ensure patient safety, wireless data transfer (WDT) technology has been widely studied and applied. When dealing with diseases such as Parkinson's disease and stroke, it is necessary to input functional electrical stimulation (FES) into the body while sensing the signals in the body, so as to diagnose and respond to the physical condition in real time. This often requires the use of synchronous two-way wireless transmission technology, using the uplink to transmit the collected biological signals from the implantable device in the body to the external terminal, and using the downlink to generate electrical stimulation to the organs in the body.

[0003] The traditional downlink data link uses binary phase shift keying (BPSK) modulation technology. Due to the limitation of the phase-locked loop lock time, the data transmission rate is often difficult to increase. The traditional uplink data link uses load shift keying (LSK) modulation, which modulates and transmits the uplink data by adjusting the load impedance in the body. In the application scenario of energy transmission, it consumes nearly half of the power, resulting in low energy recovery efficiency. Although the improved pulse load keying modulation method improves the energy recovery efficiency, it is difficult to control the modulation moment and the pulse width of the modulation signal due to the lack of a clock signal, resulting in a low data transmission rate and the inability to achieve synchronous transmission with the downlink. Summary of the invention

[0004] The present invention overcomes the shortcomings of the above-mentioned prior art, utilizes time-division multiplexed phase-locked loop technology, and combines with an auxiliary locking circuit to propose a near-field wireless synchronous bidirectional data transmission circuit with a multiplexed phase-locked loop, which solves the problem that near-field bidirectional data transmission cannot be synchronized, is beneficial to improving the integration of the System on Chip (SoC), increasing the uplink and downlink data transmission rates, and reducing the overall power consumption of the link.

[0005] The technical solution of the present invention is as follows:

[0006] A near-field wireless bidirectional synchronous data transmission circuit of a multiplexed phase-locked loop comprises an uplink data link and a downlink data link, wherein the uplink data link comprises an uplink data modulation circuit in a body and an uplink data demodulation circuit outside a body, wherein the downlink data link comprises a hysteresis comparator in a body, a multiplexed phase-locked loop circuit and a start-up circuit, and a downlink data modulation circuit outside a body, wherein the uplink data link and the downlink data link share an off-chip capacitor / inductor, wherein the off-chip capacitor / inductor comprises a coupling coil composed of an off-chip primary coil and an off-chip secondary coil, an off-chip choke coil, and a capacitor C p and capacitor C s And the capacitance C in the body c , used to transmit modulated uplink / downlink data waveform; its characteristics are:

[0007] The uplink data modulation circuit is used to generate a start signal for uplink data transmission, generate a modulation clock Up_CLK for uplink data and an uplink synchronization signal Sys2, and modulate the uplink data so that the uplink data is transmitted when the uplink synchronization signal Sys2 is at a high level;

[0008] The hysteresis comparator is used to receive the waveform on the secondary coil and convert the voltage signal on the coil into a downlink binary digital modulated signal, which is input into the multiplexing phase-locked loop circuit;

[0009] The multiplexed phase-locked loop circuit is used to receive the downlink binary digital modulated signal, and in combination with the digital circuit, recover the carrier signal Carrier with a constant period and a frequency of fc. The carrier signal is “XORed” with the downlink binary digital modulated signal to obtain the recovered downlink data Dn_Rx. The carrier signal is also used as a clock signal to input the uplink data modulation circuit to modulate the uplink data.

[0010] The startup circuit is used to successively generate three timing signals, namely, the data transmission enable signal En_Data for inputting and enabling the hysteresis comparator, the voltage-controlled oscillator enable signal En_Vco for inputting and enabling the voltage-controlled oscillator in the multiplexed phase-locked loop, and the reset module enable signal En_Rs for inputting and enabling the auxiliary locking circuit in the multiplexed phase-locked loop;

[0011] The downlink data modulation circuit is used to modulate the downlink data in vitro, and obtain the downlink modulation clock Dn_CLK and the downlink synchronization signal Sys1 after dividing the carrier signal with a frequency of fc, so that the downlink data is transmitted when the downlink synchronization signal Sys1 is at a low level, and at the same time, the downlink modulation clock Dn_CLK is input into the uplink data demodulation circuit to demodulate the uplink data;

[0012] The uplink data demodulation circuit is used to demodulate the uplink data outside the body to obtain restored uplink data Up_Rx.

[0013] The hysteresis comparator is used to convert the voltage signal on the receiving coil Rx into a digital signal. The input pair tube is composed of two PMOS, which converts the input voltage into a current signal to charge the NMOS connected to the diode. The drain of the NMOS connected to the diode is cross-connected with the drain of the input PMOS. The charge / discharge voltage at the connection controls the NMOS / PMOS pair connected to the inverter respectively, and the output level is the comparison result. The above output level is connected to the input of the multiplexed phase-locked loop circuit after passing through an inverting buffer.

[0014] The multiplexed phase-locked loop circuit includes a frequency detection phase-charge pump circuit, a third-order loop filter, a voltage-controlled oscillator and a multiplexed circuit module. The frequency detection phase-charge pump circuit compares the output digital signal of the hysteresis comparator and the digital signal fed back by the phase-locked loop, and is triggered at the rising edge of the two signals to convert their phase difference into a voltage signal, which is then converted into a current signal through a current pump circuit to control subsequent circuits. At the same time, when the "Reset" generated by the multiplexed circuit module is at a high level, that is, when the downlink data is flipped or the uplink data is modulated, the frequency detection phase-charge pump circuit fails to maintain the restored system carrier clock.

[0015] The third-order loop filter is composed of loop capacitors C1, C2, C3 and loop resistors R1, R2 to achieve the purpose of compensating the loop phase margin, improving the spectrum purity of the phase-locked loop output signal, and ensuring the normal operation of the loop. The output is "vco_in".

[0016] The voltage controlled oscillator is composed of three NMOS / PMOS pairs connected end to end by inverters to form an oscillation loop. When the start signal is set to a high level, the circuit starts to generate an oscillation signal. The frequency of the oscillation signal is determined by the current provided by the current mirror circuit, and the mirror current of the current mirror is determined by the branch where the MOS tube and the resistor controlled by the "vco_in" are located. When the "vco_in" signal changes, the frequency of the output signal of the voltage controlled oscillator will change accordingly, so that the output feedback signal of the phase-locked loop tracks the input signal of the phase-locked loop.

[0017] The multiplexing circuit module includes a logic gate circuit and an auxiliary locking circuit. The output of the voltage-controlled oscillator is used as a clock signal and is connected to the control clock of the D flip-flop and the auxiliary locking circuit. The output of the voltage-controlled oscillator passes through a two-frequency division circuit to obtain a carrier signal "Carrier". This signal is synchronized with the clock with a frequency of fc in the BPSK modulation circuit and serves as a synchronization clock for uplink data transmission. "Carrier" and the phase-locked loop input signal are used as inputs through an XNOR gate, and the output signal passes through a latch to obtain the recovered downlink binary data "Dn_Rx". Furthermore, through the digital gate circuit and the auxiliary locking circuit, an "Rs" signal is output. When the downlink binary data is flipped, "Rs" will generate a high-level pulse of a certain duration. The "Rs" signal and the "Dmod" generated by the uplink data modulation circuit described below are used as inputs through an OR gate, and the output "Reset" signal is connected to the enable signal of the frequency-phase-discrimination charge pump circuit (131). When the "Reset" signal is at a high level (i.e., when "Rs" or "Dmod" is at a high level), the phase-locked loop is disabled to keep the phase of the "Carrier" unchanged. Further, in order to distinguish the function of the phase-locked loop, "Dn_Rx" and the low-level signal pass through a selector, and the selector is controlled by the "Sys2" signal generated by the uplink data modulation circuit (31) described below. When "Sys2" is at a low level, the phase-locked loop performs downlink data demodulation, and the feedback signal of the phase-locked loop is obtained by the OR of "Dn_Rx" and the "Carrier"; when "Sys2" is at a high level, the phase-locked loop performs uplink data modulation, and the feedback signal of the phase-locked loop is obtained by the OR of the low level and the "Carrier".

[0018] The startup circuit is composed of a ring oscillator, a counter, three AND gates and three D flip-flops. The ring oscillator outputs an oscillating square wave signal, which passes through the counter to obtain three counting signals D<0:2> and the inverted signal DN<0:2> of the three signals. Based on the combination of the above six signals, the AND gate and the D flip-flop, three sequential startup signals "En_Data", "En_Vco" and "En_Rs" are output in sequence and respectively input into the hysteresis comparator, the voltage-controlled oscillator and the multiplexing circuit module (134) to ensure normal startup operation.

[0019] The coupling coil is composed of a primary coil (outside the body) and a secondary coil (inside the body). When performing downlink data transmission, the primary coil serves as a transmitting coil and the secondary coil serves as a receiving coil; when performing uplink data transmission, the primary coil serves as a receiving coil and the secondary coil serves as a transmitting coil.

[0020] The uplink data link comprises an uplink data modulation circuit implanted in the body (front end) and an uplink data demodulation circuit implanted outside the body (back end).

[0021] The start signal of the uplink data modulation circuit is controlled by the downlink data "Dn_Rx" recovered above. When the start signal of the downlink data modulation transmission circuit is artificially set to a high level, a system start signal of a data cycle will be generated, causing the downlink data receiving signal "Dn_Rx" to flip a data cycle, and then the start signal in the uplink data demodulation circuit is permanently set to a high level, so that the start signals inside and outside the body are synchronized. When the start signal is set to a high level, the digital module is used to generate the uplink data modulation clock and the system synchronization signal. The modulated uplink binary data signal is synchronized by a D flip-flop, passes through two inverters, and is output through a D flip-flop and simultaneously input into the XOR gate with itself, and the output is the signal "Dmod" that controls the switch of the uplink data transmitter. The uplink data is transmitted when the system synchronization signal is at a high level. After the uplink data is flipped, "Dmod" will generate a high-level pulse of a "Carrier" clock cycle at the next rising edge of the modulation clock, during which the two ends of the secondary coil are short-circuited, thereby achieving the purpose of amplitude modulation.

[0022] The uplink data demodulation circuit includes an envelope detector, a low-pass filter and a dynamic comparator. The input of the envelope detector is obtained by voltage division at the connection point of the main coil (outside the body) and the resonant capacitor, and is connected to the negative input terminal of the operational amplifier; the output of the operational amplifier is connected to the upper board of the charge / discharge capacitor and the gate of the NMOS connected by the diode through the PMOS connected by the current mirror, as the output of the envelope detector, and is connected to the positive input terminal of the operational amplifier to form feedback. The low-pass filter passes the output signal of the above-mentioned envelope detector through the PMOS switch, and the PMOS switch is controlled by the system synchronization signal generated by the downlink data modulation and transmission circuit to ensure that the subsequent circuit only works when the system synchronization signal is at a high level, that is, when the uplink data is transmitted. Then, the signal is amplified and low-pass filtered through the resistor, capacitor and operational amplifier, and its output signal is input into the dynamic comparator at the same time as the output signal itself after passing through the first-order low-pass filter for level comparison. The clock of the dynamic comparator is controlled by the modulation clock generated by the downlink data modulation and transmission circuit, and the output is the recovered uplink binary data.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1. By adopting a multiplexed phase-locked loop circuit, the downlink data is restored and the system clock is restored when the system synchronization signal is at a low level, and the uplink data is modulated and the system clock is restored when the system synchronization signal is at a high level, thereby achieving the purpose of wireless two-way synchronous data transmission and improving the chip integration; design and use an auxiliary locking circuit, so that the control signal of the phase-locked loop is cut off from the loop every time the downlink data flips, thereby eliminating the time for the phase-locked loop to restore lock every time the downlink data flips, and improving the downlink data transmission rate.

[0025] 2. Uplink data transmission is carried out through pulse modulation. When the uplink data is flipped, amplitude modulation is completed within one clock cycle, so that the energy of the AC signal in the remaining clock cycle can be retained, thereby reducing the energy loss of the system; the uplink data is recovered by a dynamic comparator, which is conducive to the accuracy of the recovered data and reduces the bit error rate. At the same time, signal comparison is only performed on the rising edge of the clock, thereby reducing system power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the overall structural framework of the present invention;

[0027] Figure 2 is a schematic diagram of the structure of a downlink data modulation circuit;

[0028] Figure 3 is a circuit diagram of a hysteresis comparator;

[0029] Figure 4 It is a schematic diagram of the circuit structure of a multiplexed phase-locked loop;

[0030] Figure 5 It is a schematic diagram of the structure of the frequency detection and phase detection - charge pump circuit in the multiplexed phase-locked loop circuit;

[0031] Figure 6 It is a schematic diagram of the circuit structure of a voltage-controlled oscillator in a multiplexed phase-locked loop circuit;

[0032] Figure 7 It is a schematic diagram of the starting circuit structure;

[0033] Figure 8 is a schematic diagram of the structure of an uplink data modulation circuit;

[0034] Fig. 9 is a schematic diagram of the structure of an uplink data demodulation circuit;

[0035] Fig.10 It is the key signal timing diagram of the wireless bidirectional synchronous data transmission link. DETAILED DESCRIPTION

[0036] The present invention will be further described below in conjunction with embodiments and with reference to the accompanying drawings, but the protection scope of the present invention shall not be limited thereto.

[0037] Please read first Figure 1 , Figure 1 The present invention is a schematic diagram of the overall architecture of a near-field wireless two-phase synchronous data transmission link of a multiplexed phase-locked loop. As shown in the figure, a near-field wireless two-way synchronous data transmission circuit of a multiplexed phase-locked loop includes an uplink data link and a downlink data link. The uplink data link includes an uplink data modulation circuit in the body and an uplink data demodulation circuit outside the body. The downlink data link includes a hysteresis comparator, a multiplexed phase-locked loop circuit and a start-up circuit in the body, and a downlink data modulation circuit outside the body. The uplink data link and the downlink data link share an off-chip capacitor / inductor. The off-chip capacitor / inductor includes a coupling coil composed of an external primary coil and an internal secondary coil, a choke coil in the body, and a capacitor C p and capacitor C s And the external capacitance C c , used to transmit the modulated uplink / downlink data waveform. The downlink data modulation circuit uses a digital gate circuit to divide the carrier signal with a frequency of fc to obtain the "Dn_CLK" and "Sys1" signals, modulate the downlink data, so that the downlink data is transmitted when "Sys1" is at a low level, and at the same time, it is input into the uplink data demodulation module as a clock signal to demodulate the uplink data. The modulated downlink data is used as a control signal "Vg" to control the switching transistor. The switching transistor is equivalent to a switch, and forms a resonant loop with Cp, Cs and the transmitting coil L1. When "Vg" is at a high level, the switching transistor is turned on, and Cs and L1 form a resonant circuit; when "Vg" is at a low level, the switching transistor is turned off, and Cs, Cp and L1 form a resonant loop, thereby modulating the digital signal "Vg" into an analog voltage signal on the main coil.

[0038] The secondary coil and capacitor Cc form a resonant circuit, and the voltages at both ends are respectively input into the hysteresis comparator, and the compared signals are input into the multiplexed phase-locked loop circuit. The multiplexed phase-locked loop circuit includes a frequency detection and phase detection - charge pump circuit, a third-order loop filter, a voltage-controlled oscillator and a multiplexed circuit module. The start-up circuit generates three timing enable signals in sequence to respectively enable the hysteresis comparator, the voltage-controlled oscillator and the multiplexed circuit module to ensure the normal operation of the system. The multiplexed phase-locked loop circuit recovers the downlink data "Dn_Rx" and the carrier signal "Carrier" of the system;

[0039] The input of the uplink data modulation circuit is the "Carrier" signal, which is used as the modulation clock of the uplink data after frequency division. The uplink data modulation circuit uses a digital gate circuit to generate a modulated pulse signal "Dmod" to control the switches connected to the two ends of the secondary coil. When the uplink data is flipped, the "Dmod" signal generates a high-level pulse with a duration of one "Carrier" clock cycle, turning on the above-mentioned switch, that is, short-circuiting the two ends of the secondary coil, thereby changing the amplitude of the voltage signal sensed by the transmitting end Tx node, thereby achieving the purpose of uplink data modulation.

[0040] The uplink data demodulation circuit includes an envelope detector, two low-pass filters and a dynamic comparator. Node Tx is used as the input of the uplink data demodulation circuit, connected to the input of the above-mentioned envelope detection circuit, the detected envelope signal is connected to the source of the PMOS switch, the gate of the PMOS switch is connected to the clock signal "Sys1" generated by the downlink data modulation circuit, and the drain is connected to the input of the first low-pass filter. When "Sys1" is at a high level, the uplink data is transmitted, the PMOS switch is turned on, and the subsequent circuit starts to work. The output signal of the low-pass filter passes through an AC amplifier, and the obtained output signal is connected to the input of the second low-pass filter. The obtained output and the output signal of the above-mentioned AC amplifier are simultaneously input into the dynamic comparator. The clock signal of the dynamic comparator is the clock signal "Dn_Clk" generated by the downlink data modulation circuit. The compared signal passes through a two-frequency division circuit to obtain the recovered uplink data "Up_Rx".

[0041] Figure 2 It is a schematic diagram of the structure of the downlink data modulation circuit. When the start signal of the digital modulation frequency division module 1 is set to "1", the carrier clock x with a frequency of fc is divided as the transmission clock "Dn_CLK" of the downlink data, and the "Dn_CLK" clock y is divided as the synchronization signal "Sys1" of the entire system. The binary downlink data is transmitted when "Sys1" is at a low level and at the rising edge of "Dn_CLK", and is modulated into "Dn_Tx". In this embodiment, x is selected as 6 and y is selected as 32, that is, the data transmission rate is 2.26Mbps, and 16 binary data are used as a data packet for downlink data transmission. At the same time, in order to prevent interference between the uplink data and the downlink data and facilitate data verification, the first and last bits of each data packet send a "0" signal. Figure 2The start signal shown in the figure passes through six D flip-flops, delaying six carrier clock cycles with a frequency of fc. The output and the start signal pass through the XOR gate XOR at the same time, and the output signal is "St". When the start signal outside the body is set to a high level, "St" generates a pulse with a duration of one binary data duration, and the internal end can receive this pulse. The circuit at the internal end starts working at the same time to achieve the purpose of keeping the internal and external systems synchronized. "St" and the "Dn_Tx" are ORed through the OR gate, and the output and the clock with a frequency of fc are passed through the XOR gate to perform phase shift keying modulation on the binary data. The output passes through the D flip-flop and is synchronized with a clock with a frequency of 2*fc to prevent the generation of glitches. The output forms a modulated signal "Vg" through the buffer BUF to control the gate of the switching transistor NMOS. When the data is low and high, the "Vg" signal will produce a 180-degree phase difference.

[0042] Figure 3 It is a hysteresis comparator circuit. The input pair of tubes M0 and M1 is composed of two PMOS with a size of 6μ:180n, which converts the input voltage into a current signal, and its drain is respectively connected to the NMOS gate of M4 and M5 connected to the diode. The gates of the M2 and M3 pairs of tubes are respectively connected to the gates of M5 and M4, and the drains of the M2 and M3 pairs of tubes are respectively cross-connected with the drains of M0 and M1 to form a positive feedback loop. The ratio of the size of M2 and M5 (that is, the ratio of the size of M3 and M4) is the same. The larger the ratio, the larger the hysteresis voltage. Preferably, the ratio is selected to be 1.8:1. The gates of the PMOS tubes M6 and M7 are charged by the transistors M0 and M1 respectively to form a source-drain current, which charges or discharges the node Vo together with the 1:1 current mirror formed by the PMOS tubes M8 and M9, and then outputs the comparison result through an inverter, which is input into the multiplexed phase-locked loop circuit as the signal "PLL_in".

[0043] Figure 4 This is a schematic diagram of the circuit structure of a multiplexed phase-locked loop. The hysteresis comparison output signal "PLL_in" and the feedback signal "PLL_out" output by the phase-locked loop are input into the frequency discrimination phase-charge pump circuit to compare the phases of the two, and convert the pulse width difference between the two into a current signal, which is input into a third-order loop filter for filtering and phase compensation. The output of the third-order loop filter controls the frequency of the voltage-controlled oscillator, and through the multiplexing circuit module, the feedback signal "PLL_out" is synchronized with the input signal "PLL_in".

[0044] Figure 4The output "Vosc" of the voltage-controlled oscillator of the multiplexing circuit module shown in the figure is divided into two to recover the carrier signal "Carrier". Based on the recovered carrier signal, the downlink data is demodulated by the XOR gate MX2 and the D flip-flop 1, and the recovered downlink binary data Dn_Tx is obtained through the latch. When the system synchronization signal "Sys1" is at a low level, the multiplexing phase-locked loop circuit acts to demodulate the downlink data and the carrier signal, and the downlink recovered data "Dn_Tx" is simultaneously input into the XOR gate MX3 through the selector and the carrier signal to obtain the feedback signal "PLL_out". When the downlink binary data is flipped, "Rsy" is set to a high level, and through the auxiliary locking circuit shown in the figure, the output signal "Rs" generates a high-level pulse of n "Vosc" clock cycles. In this example, preferably, n is taken as 4.5. When "Rs" is at a high level, the non-enable signal "Reset" is at a high level, and the frequency-phase-discrimination-charge pump circuit fails. Since the control signal of the phase-locked loop is cut off from the loop, "Vosc" maintains its locked frequency and does not change with the change of the "PLL_in" signal. After 4.5 "Vosc" clock cycles, "Reset" returns to a low level, and the voltage-controlled oscillator is reconnected to the phase-locked loop. Through the multiplexing circuit module, the locked state of the phase-locked loop is not destroyed when the data is flipped, eliminating the time for the phase-locked loop to lock each time the data is flipped, thereby increasing the downlink data rate. When the system synchronization signal "Sys2" is 1, the function of the multiplexing phase-locked loop circuit is to modulate the uplink data and recover the carrier signal. Since the phase of "PLL_in" does not change, the selector output shown in the figure is low. At the same time, when the uplink data is modulated, the two ends of the secondary coil are short-circuited, resulting in the "PLL_in" signal being a continuous low level. In order to prevent the change of "PLL_in" from affecting the carrier signal "Carrier", the "Dmod" generated by the uplink data modulation circuit is connected to the input of the OR gate OR shown in the figure. When "Dmod" is high, that is, the uplink data is flipped, the reset signal "Reset" of the frequency and phase discrimination-charge pump circuit is also high, and "Vosc" maintains its locked frequency and will not change with the change of the "PLL_in" signal. After Dmod returns to a low level, that is, the uplink data is modulated, "Reset" returns to a low level, and the voltage-controlled oscillator is reconnected to the phase-locked loop.

[0045] Figure 5The invention is a schematic diagram of the structure of a frequency-detection phase-charge pump circuit in a multiplexed phase-locked loop circuit. The frequency-detection phase-charge pump circuit input and feedback are respectively connected to the clock input ends of D flip-flops A and B which are triggered by the rising edge and reset by the falling edge. The synchronized signals "Up" and "Dn" are used as the inputs of the NAND gate. The output signal and the "Reset" signal are input into the NOR gate to control the enable ends of the two D flip-flops (A and B) to achieve the purpose of detecting the difference in the pulse width of the input and feedback signals. The "Reset" is generated by the multiplexed circuit module (134) and is used to disable the phase-locked loop within a period of time after the downlink data or the uplink data is converted to achieve the purpose of maintaining the system clock. "Up" and "Dn" as well as the reverse output signals "Up_N" and "Dn_N" of the D flip-flops A and B are connected to the gates of transistors M1, M2, M3 and M4 respectively to convert the detected voltage difference into a current signal. A five-transistor operational amplifier X1 connected as a unity gain buffer is connected to the drains of M1 and M3 to eliminate the problem of charge shunting and ensure the stable operation of the charge pump. The output signal is used as "cp_out" and input into the third-order loop filter (132).

[0046] Figure 6 It is a schematic diagram of the circuit structure of a voltage-controlled oscillator in a phase-locked loop circuit. The input of the voltage-controlled oscillator is the output "vco_in" of the third-order loop filter, which controls the gate of transistor M0 to form a source-drain current of M0. Transistors M1 and M2-M6 form a current mirror. Transistor M3 is diode-connected, and the drain is connected to the drain of M2. M3 and M7-M9 form a current mirror to provide current for transistors M10-M17. M10-M13 are connected in the form of a NAND gate, and one input is an enable signal "D_Vco"; M14-M17 are connected by two inverters, and the other input Vo3 and output Vo1 of M10-M13 connected to the NAND gate are connected end to end. The three capacitors C1-C3 are respectively connected to the connection points Vo1-Vo3 to form positive feedback, form an oscillation signal Vo3, and form an output digital signal "Vosc" through a buffer BUF. Since the frequency of "Vosc" is related to the delay of the inverter loop, and the above delay is related to the current flowing through the inverter-connected transistor, that is, the source-drain current of M0 of the current mirror image, the size of the input signal "vco_in" can control the oscillation frequency of the output "Vosc".

[0047] Figure 7: This is a schematic diagram of the startup circuit structure; the ring oscillator shown in the figure is composed of three inverters and capacitors connected end to end, and outputs an oscillating square wave signal "Clk_osc". The counter shown in the figure uses "Clk_osc" as the clock signal, and D0-D2 can be regarded as three frequency dividers. At each rising edge of the clock, the Q output of DFF0-DFF2 begins to flip, and at the falling edge of the clock, DFF3-DFF5 samples and saves the corresponding data to generate three counting signals D<0:2> and its reverse signal DN<0:2>. The above six signals are combined with the AND gate and D flip-flop D6-D8 in the figure to generate three startup signals "En_Data", "En_Vco" and "En_Rs". The rising edges of the three signals are separated by 1 "Clk_osc" clock cycle and 2 "Clk_osc" clock cycles respectively, and are respectively input to the hysteresis comparator, voltage-controlled oscillator and multiplexing circuit module to ensure the normal startup of the system.

[0048] Figure 8 Schematic diagram of the structure of the uplink data modulation circuit. The recovered downlink data "Dn_Rx" signal is input as a start signal to the digital modulation frequency division module 2 through the D flip-flop and the OR gate. Figure 2 When the start signal is set to 1, the downlink data modulation circuit generates a pulse of a data cycle, so Figure 8 The recovered downlink data "Dn_Rx" will flip. Due to the existence of the coupling coil, Figure 8 The start signal in Figure 2 The start signal in the delay is 1-2 clock cycles with a frequency of fc, but the delay is relatively small compared to a data cycle, and because the digital modulation frequency division module 1 and the digital modulation frequency division module 2 make the first bit of each uplink / downlink data packet not modulated, the delay will not affect the modulation timing of the uplink and downlink data and can be ignored. Figure 2The functions of the digital modulation frequency division module 1 shown are basically similar: when the start signal is set to "1", the carrier clock (synchronized with the clock signal with a frequency of fc) is divided by x as the transmission clock "Up_CLK" of the uplink data, and the "Up_CLK" clock is divided by y as the synchronization signal "Sys2" of the entire system. The binary uplink data is transmitted when "Sys2" is at a high level and at the rising edge of "Up_CLK", and is modulated into "Up_Tx". In this embodiment, x is selected as 6 and y is selected as 32, that is, the uplink data transmission rate is 2.26Mbps, and 16 binary data are used as a data packet for uplink data transmission. At the same time, in order to prevent interference between uplink data and downlink data and facilitate data verification, the first and last bits of each data packet send a "0" signal. Since the revelation signals arrive almost at the same time, "Sys1" and "Sys2" can be considered as the synchronization signals of the system. The system performs downlink data transmission when the synchronization signal is at a low level, and performs uplink data transmission when the synchronization signal is at a high level, so as to achieve the effect of time division multiplexing. Furthermore, the uplink data "Up_Tx" generates a modulation signal "Dmod" through the D flip-flop and XOR gate shown in the figure. When the binary uplink data is flipped, the "Dmod" signal generates a high-level pulse of the "Carrier" clock cycle when the voltages at both ends of the secondary coil are equal (i.e., the rising edge of the "Carrier" signal) to control Figure 1 The switch S shown in the figure turns it on, short-circuiting the two ends of the secondary coil. Figure 1 The Tx node shown generates a pulse that is first amplified and then reduced in amplitude, thereby achieving the purpose of modulating uplink data.

[0049] Fig. 9 It is a schematic diagram of the structure of the uplink data demodulation circuit, including an envelope detector, a low-pass filter amplifier, a dynamic comparator and a two-frequency division circuit. Figure 1The Tx node shown will generate a pulse that first increases and then decreases, so the uplink data can be recovered by detecting its envelope. After the "Tx" node is divided by a capacitor, it is input to the negative input terminal of the operational amplifier in the envelope detector. The output of the operational amplifier is connected to the transistor N1 through a 1:100 current mirror for charging / discharging the capacitor and the diode equivalent to a resistor, thereby detecting the envelope of the signal "Tx". Because the downlink data recovery envelope is affected when the "Sys1" signal is at a low level, the envelope signal passes through a transistor switch controlled by "Sys1". When the "Sys1" signal is at a high level, that is, when the uplink data is transmitted, the envelope signal is filtered through the resistor R1 and the capacitor C1 to filter out the harmonics of the frequency fc, and then the DC level is set by the capacitor C2 and the resistors R2 and R3. The signal is amplified by the operational amplifier connected with negative feedback to obtain the output signal "LPF1". Then, "LPF1" is passed through a first-order low-pass filter to obtain its DC signal "LPF2". "LPF1" and "LP2" are passed through a dynamic comparator circuit. The two signal levels are compared at the rising edge of "Dn_CLK" generated by the downlink data modulation circuit. The result is divided by two, and the output is the recovered uplink binary data "Up_Rx".

[0050] Fig.10 It is a key signal timing diagram of a wireless bidirectional synchronous data transmission link. During the a phase, the system synchronization signal "Sys1" in the body is high, the link performs uplink data transmission, and the binary uplink data "Up_Tx" in the body is modulated at the rising edge of each "Up_Clk", so that "Dmod" generates a pulse signal of a clock cycle (frequency is fc), and the binary uplink data "Up_Rx" is restored outside the body. During the b phase, the system synchronization signal "Sys2" outside the body is low, the link performs downlink data transmission, and the binary downlink data "Dn_Tx" outside the body is modulated at the rising edge of each "Dn_Clk", and the binary uplink data "Dn_Rx" is restored inside the body. As shown in the figure, in this example, the uplink / downlink data is transmitted as a data packet of 16 binary data. Since the first bit of the uplink / downlink data packet will not be modulated, the system will only modulate the uplink data during the overlapping time of a and b, and there will be no interference caused by simultaneous modulation of the uplink / downlink data. As shown in the figure, in this example, the equivalent of 1.13 Mbps of uplink / downlink data can be correctly and synchronously transmitted bidirectionally through the link.

Claims

1. A near-field wireless bidirectional synchronous data transmission circuit of a multiplexed phase-locked loop, comprising an uplink data link and a downlink data link, wherein the uplink data link comprises an uplink data modulation circuit in the body and an uplink data demodulation circuit outside the body, wherein the downlink data link comprises a hysteresis comparator, a multiplexed phase-locked loop circuit and a start-up circuit in the body, and a downlink data modulation circuit outside the body, wherein the uplink data link and the downlink data link share an off-chip capacitor / inductor, wherein the off-chip capacitor / inductor comprises a coupling coil composed of an external primary coil and an internal secondary coil, an external choke coil, and a capacitor C p and capacitor C s And the capacitance C in the body c , used to transmit the modulated uplink / downlink data waveform; characterized in that, The uplink data modulation circuit is used to generate a start signal for uplink data transmission, generate a modulation clock Up_CLK for uplink data and an uplink synchronization signal Sys2, and modulate the uplink data so that the uplink data is transmitted when the uplink synchronization signal Sys2 is at a high level; The hysteresis comparator is used to receive the waveform on the secondary coil and convert the voltage signal on the coil into a downlink binary digital modulated signal, which is input into the multiplexing phase-locked loop circuit; The multiplexed phase-locked loop circuit is used to receive the downlink binary digital modulated signal, and in combination with the digital circuit, recover the carrier signal Carrier with a constant period and a frequency of fc. The carrier signal is "XORed" with the downlink binary digital modulated signal to obtain the recovered downlink data Dn_Rx. The carrier signal is also used as a clock signal to input the uplink data modulation circuit to modulate the uplink data. The startup circuit is used to successively generate three timing signals, namely, the data transmission enable signal En_Data for inputting and enabling the hysteresis comparator, the voltage-controlled oscillator enable signal En_Vco for inputting and enabling the voltage-controlled oscillator in the multiplexed phase-locked loop, and the reset module enable signal En_Rs for inputting and enabling the auxiliary locking circuit in the multiplexed phase-locked loop; The downlink data modulation circuit is used to modulate the downlink data in vitro, and obtain the downlink modulation clock Dn_CLK and the downlink synchronization signal Sys1 after dividing the carrier signal with a frequency of fc, so that the downlink data is transmitted when the downlink synchronization signal Sys1 is at a low level, and at the same time, the downlink modulation clock Dn_CLK is input into the uplink data demodulation circuit to demodulate the uplink data; The uplink data demodulation circuit is used to demodulate the uplink data outside the body to obtain restored uplink data Up_Rx.

2. The near-field wireless bidirectional synchronous data transmission circuit of multiplexed phase-locked loop according to claim 1, characterized in that: The multiplexed phase-locked loop circuit comprises a frequency-phase-discrimination-charge pump circuit, a third-order loop filter, a voltage-controlled oscillator and a multiplexed circuit module; The frequency detection and phase detection-charge pump circuit is used to compare the input signal PLL_in output by the hysteresis comparator with the feedback signal PLL_out output by the phase-locked loop, and convert the pulse width difference between the two into a current signal cp_out to control the subsequent circuit; at the same time, when the "Reset" generated by the multiplexing circuit module is at a high level, that is, when the downlink data is flipped or the uplink data is modulated, the frequency detection and phase detection-charge pump circuit is disabled to maintain the restored system carrier clock.

3. The near-field wireless bidirectional synchronous data transmission circuit of multiplexed phase-locked loop according to claim 2, characterized in that: The third-order loop filter is used for filtering and phase compensation, and outputs a signal vco_in to control the frequency of the voltage-controlled oscillator, and keeps the feedback signal PLL_out synchronized with the input signal PLL_in.

4. The near-field wireless bidirectional synchronous data transmission circuit of multiplexed phase-locked loop according to claim 2, characterized in that: The voltage-controlled oscillator is composed of three NMOS / PMOS pairs connected end to end by inverters to form an oscillation loop. When the start signal is set to a high level, an oscillation signal is generated. The frequency of the oscillation signal is determined by the current provided by the current mirror circuit. The mirror current of the current mirror is determined by the branch where the MOS tube and the resistor controlled by the output signal vco_in are located. When the vco_in signal changes, the output signal frequency of the voltage-controlled oscillator will change accordingly, so that the output feedback signal of the phase-locked loop tracks the input signal of the phase-locked loop.

5. The near-field wireless bidirectional synchronous data transmission circuit of multiplexed phase-locked loop according to claim 2, characterized in that: The multiplexing circuit module includes a logic gate circuit and an auxiliary locking circuit. The output of the voltage-controlled oscillator is used as a clock signal and is connected to the D flip-flop and the control clock of the auxiliary locking circuit. The output of the voltage-controlled oscillator passes through a two-frequency division circuit to obtain a carrier signal Carrier. The carrier signal Carrier is synchronized with the clock with a frequency of fc in the BPSK modulation circuit and serves as a synchronization clock for uplink data transmission. The carrier signal Carrier and the phase-locked loop input signal are used as inputs through an XOR gate, and the output signal passes through a latch to obtain the recovered downlink binary data Dn_Rx.

6. The near-field wireless bidirectional synchronous data transmission circuit of multiplexed phase-locked loop according to claim 5, characterized in that: Through the digital gate circuit and the auxiliary locking circuit, the "Rs" signal is output. When the downlink binary data is flipped, "Rs" will generate a high-level pulse of a certain length; the "Rs" signal and the "Dmod" generated by the uplink data modulation circuit described below are used as inputs through the OR gate, and the output "Reset" signal is connected to the enable signal of the frequency-phase-discrimination-charge pump circuit. When the "Reset" signal is high, that is, when "Rs" or "Dmod" is high, the phase-locked loop fails to maintain the "Carrier "The phase of " remains unchanged; "Dn_Rx" and the low-level signal are input through the selector, and the selector is controlled by the "Sys2" signal generated by the uplink data modulation circuit described below. When "Sys2" is at a low level, the phase-locked loop performs downlink data demodulation, and the feedback signal of the phase-locked loop is obtained by the same or the same signal of "Dn_Rx" and the "Carrier"; when "Sys2" is at a high level, the phase-locked loop performs uplink data modulation, and the feedback signal of the phase-locked loop is obtained by the same or the same signal of the low level and the "Carrier".

7. The near-field wireless bidirectional synchronous data transmission circuit of multiplexed phase-locked loop according to claim 1, characterized in that: The start signal of the uplink data modulation circuit is controlled by the restored downlink data "Dn_Rx". When the start signal of the downlink data modulation circuit is artificially set to a high level, a system start signal of a data cycle will be generated, causing the downlink data receiving signal "Dn_Rx" to flip a data cycle, thereby making the start signal in the uplink data demodulation circuit permanently set to a high level, so that the start signals inside and outside the body are synchronized; When the start signal is set to a high level, the digital module is used to generate an uplink data modulation clock and a system synchronization signal; the modulated uplink binary data signal is synchronized by a D flip-flop, passes through two inverters, and the output passes through a D flip-flop and is simultaneously input into an XOR gate with itself, and the output is a signal "Dmod" that controls the switch of the uplink data transmitter; the uplink data is transmitted when the system synchronization signal is at a high level; after the uplink data is flipped, "Dmod" will generate a high-level pulse of a "Carrier" clock cycle at the next rising edge of the modulation clock, during which the two ends of the secondary coil are short-circuited, thereby achieving the purpose of amplitude modulation.

8. The near-field wireless bidirectional synchronous data transmission circuit of multiplexed phase-locked loop according to claim 1, characterized in that: The uplink data demodulation circuit includes an envelope detector, two low-pass filter amplifiers and a dynamic comparator; the envelope detector is used to detect the voltage across the main coil, the first low-pass filter amplifier is used to filter the envelope and amplify the output, the second low-pass filter is used to restore the DC signal of the above output, and compare the level with the above output through the dynamic comparator to obtain the restored binary uplink data.

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