Chip testing circuit and circuit testing method

Abstract

A chip test circuit and a circuit test method can be used to test a chip circuit in EDA software, and are used to solve the problems of wiring congestion and complex test configuration in current test schemes. The test circuit transmits input data of a test vector to a data distribution circuit (301) through the input of a test bus, and transmits the data to a scan input channel of a circuit under test (01) through the data distribution circuit (301). After the scan of the circuit under test (01) is completed, the output data of the test vector of the scan output channel of the circuit under test (01) is transmitted to the output of the test bus through the data distribution circuit (301) to complete the test of the circuit under test (01). The dynamic corresponding relationship between the data distribution circuit (301) and the test bus (02) is realized by configuring a first selector (302), so that test resources can be dynamically allocated, and the problem of wiring congestion is optimized to a great extent, so as to reduce the test cost, and the configuration process can be simplified, thereby improving the test efficiency.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a test circuit in a chip and a circuit testing method. Background Art

[0002] With the development of semiconductor technology, the scale of system on a chip (SoC) is getting larger and larger, and the number of circuit modules inside it is increasing. When testing the circuit modules in the SoC, due to the limited resources available for testing, such as the limited chip pins, it is necessary to rationally plan and reuse the limited resources in order to meet large-scale testing requirements. To solve the above problems, the solutions currently used are scan routing fabric (SRF) and scan streaming network (SSN).

[0003] In the SRF scheme, a small number of chip pins are multiplexed using multiplexers (MUX) to test circuits with a larger number of test scan channels. If the number of scan channels of the circuit to be tested continues to increase, there will be a serious problem of winding congestion, and the test cost will be high. In the SSN scheme, the test scan data is transmitted through the bus. During the transmission process, the test data is exchanged between the bus and the test compression logic of the circuit to be tested through a more complex hardware circuit. When the number of circuits to be tested increases, the hardware circuits used for data exchange will also increase, resulting in a larger scale of hardware circuits. In addition, in the SSN scheme, various configurations of the complex hardware circuits are required, and the configuration process is relatively complicated, resulting in low test efficiency. Summary of the invention

[0004] The embodiments of the present application provide a chip testing circuit and a circuit testing method, which can optimize the problems of wiring congestion and complex test configuration in the current testing scheme, so as to reduce the testing cost and improve the testing efficiency.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In the first aspect, a test circuit is provided. The test circuit includes: a plurality of sub-test circuits corresponding to a plurality of circuits under test, and the plurality of sub-test circuits are used to connect the corresponding circuits under test to a test bus. Each circuit under test corresponds to a sub-test circuit, and each sub-test circuit can transmit the data required for the test scan to the scan input channel of the corresponding circuit under test through the test bus, and transmit the test result data of the corresponding circuit under test to the test bus output. Each sub-test circuit can also dynamically allocate the test bus to the corresponding circuit under test. The j-th sub-test circuit in the plurality of sub-test circuits includes Nj data distribution circuits and M first selectors, wherein Nj and M are both positive integers, M is equal to the bit width of the test bus, and M is greater than or equal to Nj. The j-th sub-test circuit can be any sub-test circuit in the plurality of sub-test circuits. The data distribution circuit is used to receive the scan test data of the test bus and transmit it to the scan input channel of the circuit under test, and receive the test result data of the scan output channel of the circuit under test, and transmit it to the test bus output. In the jth sub-test circuit, the connection relationship between the data distribution circuit, the test bus and the circuit under test is as follows: the first input ends of the Nj data distribution circuits are respectively connected to the Nj inputs of the test bus, for receiving the test scan data of the test bus; the first output ends of the Nj data distribution circuits are connected to the scan input channel of the circuit under test corresponding to the jth sub-test circuit, for transmitting the test scan data received by the data distribution circuit to the scan input channel of the circuit under test; the second input ends of the Nj data distribution circuits are connected to the scan output channel of the circuit under test corresponding to the jth sub-test circuit, for transmitting the test result data of the circuit under test to the data distribution circuit, and then transmitting it to the output of the test bus through the data distribution circuit. The first selector can be a two-choice selector, which is used to select the test bus used by the j+1th sub-test circuit to realize the dynamic allocation of the test bus. Specifically, the output ends of the M first selectors in each sub-test circuit are respectively connected to the M outputs of the test bus, and the M first selectors in each sub-test circuit are respectively corresponding to the M bits of the test bus. Among them, the first input ends of Nj first selectors among the M first selectors are respectively connected to the second output ends of Nj data distribution circuits, and the first input ends of the remaining M-Nj first selectors are respectively connected to the inputs of M-Nj test buses that are not provided with data distribution circuits. The second input ends of Nj first selectors among the M first selectors are respectively connected to the second output ends of Nj data distribution circuits, and the second input ends of the remaining M-Nj first selectors are respectively connected to the inputs of M-Nj test buses that are not provided with data distribution circuits. In addition, the test buses connected to the first input end and the second input end of each first selector are different.In the jth sub-test circuit, the first input terminal and the second input terminal of the first selector are connected to different test buses, and the test bus used by the j+1th sub-test circuit can be configured by the first selector.

[0007] Based on the test circuit provided in the first aspect, the test circuit transmits the input data of the test vector, that is, the scan test data, to the data distribution circuit through the input of the test bus, and transmits it to the scan input channel of the circuit under test through the data distribution circuit. After the scan of the circuit under test is completed, the output data of the test vector of the scan output channel of the circuit under test, that is, the test result data, is transmitted to the output of the test bus through the data distribution circuit to complete the test of the circuit under test. The dynamic correspondence between the data distribution circuit and the test bus is realized by configuring the first selector, so that the test resources can be dynamically allocated. For example, assuming that the bit width of the test bus is 8 bits, the number of data distribution circuits used in the first sub-test circuit is 3, and the number of the second data distribution circuits is 5. The three data distribution circuits in the first sub-test circuit are respectively connected to the [0], [1], and [2] bits of the test bus, and the four data distribution circuits in the second sub-test circuit are respectively connected to the [0], [1], [2], [3], and [4] bits of the test bus, and the outputs of the eight first selectors are respectively connected to the eight outputs of the test bus. Then, among the 8 first selectors in the first sub-test circuit, the first input ends of the first 3 first selectors can be connected to the second output ends of the 3 data distribution circuits in the first sub-test circuit; the first input ends of the last 5 first selectors can be connected to the inputs of the [3], [4], [5], [6], and [7] bits of the test bus. The second input ends of the first 5 first selectors can be connected to the inputs of the [3], [4], [5], [6], and [7] bits of the test bus; the second input ends of the last 3 first selectors can be connected to the second output ends of the 3 data distribution circuits in the first sub-test circuit. When the 8 first selectors in the first sub-test circuit are configured such that the first input end of the first selector is connected to the output end, the test bus allocated in the second sub-test circuit is the [0], [1], [2], [3], and [4] bits of the test bus. When the eight first selectors in the first sub-test circuit are configured so that the second input terminal of the first selector is connected to the output terminal, the test bus allocated in the second sub-test circuit is bits [3], [4], [5], [6], and [7] of the test bus. That is, by configuring the first selector in the first sub-test circuit through the above scheme, the test bus used in the second sub-test circuit can be dynamically allocated. During configuration, only the first selector needs to be configured to achieve dynamic allocation, and the configuration process is simple. Therefore, the test circuit provided in the first aspect can dynamically allocate the test bus used by the circuit under test through the data distribution circuit and the first selector, which can greatly optimize the problem of winding congestion, so as to reduce the test cost, and can simplify the configuration process and improve the test efficiency.

[0008] In a possible implementation of the first aspect, in the jth sub-test circuit of the plurality of sub-test circuits, according to a preset test bus sequence, the first inputs of the Nj data distribution circuits are sequentially connected to the inputs of the first Nj test buses; the first inputs of the first Nj first selectors are sequentially connected to the second outputs of the Nj data distribution circuits, and the first inputs of the last M-Nj first selectors are sequentially connected to the last M-Nj inputs of the test bus, that is, in the jth sub-test circuit, when the first input of the first selector is configured to be connected to the output, the output of the first selector corresponds to the same test bus as the input, that is, a direct connection mode. The second inputs of the first M-Nj first selectors are sequentially connected to the last M-Nj inputs of the test bus; the second inputs of the last Nj first selectors are sequentially connected to the second outputs of the Nj data distribution circuits, that is, in the jth sub-test circuit, when the first selector is configured to be connected to the output, the output of the first selector corresponds to a different test bus as the input, that is, a shift connection mode. In the above possible implementations, allocating data distribution circuits to bus resources in a preset order according to established rules can simplify the circuit design of the test circuit while ensuring dynamic allocation of test resources, thereby improving test efficiency.

[0009] Furthermore, the preset test bus sequence is the order or reverse order of the test bus bit sequence. In the above possible implementations, the preset test bus sequence is in a specific order, such as the order or reverse order of the test bus bit sequence, which can further simplify the line structure of the test circuit, thereby simplifying the structure of the test circuit to a certain extent, so as to quickly realize the wiring requirements of the test circuit.

[0010] In another possible implementation of the first aspect, the number Nj of data distribution circuits in the jth sub-test circuit is the number of scan channels of the corresponding circuit under test, wherein the number of scan channels of the corresponding circuit under test is the number CI of scan input channels of the circuit under test. j and scan output channel CO j The maximum value among the numbers, that is, Nj=max(CI j ,CO j ). CI in Nj data distribution circuits j The first output terminals of the data distribution circuits are respectively connected to the CI of the circuit under test corresponding to the j-th sub-test circuit. j The first output end of the data distribution circuit is used to transmit the test scan data received from the test bus to the scan input channel of the corresponding circuit under test. j The second input terminals of the data distribution circuits are respectively connected to the CO of the circuit under test corresponding to the jth sub-test circuit. jThe second input end of the data distribution circuit is connected to a scan output channel, that is, the second input end of the data distribution circuit is used to receive the test result data output by the corresponding scan output channel of the circuit under test, and the test result data is output to the test bus through the second output end of the data distribution circuit. Through this solution, a one-to-one correspondence between the scan input channel and the scan output channel of the circuit under test and the data distribution circuit is achieved, which facilitates the transmission of test data, thereby avoiding outputting output, further improving test efficiency, and reducing test time.

[0011] In another possible implementation of the first aspect, each data distribution circuit may include a fourth selector, a register and a fifth selector. The fourth selector is used to implement the data distribution circuit to select whether to receive data from the test bus or from the scan output channel of the corresponding circuit under test. That is, the first input end and the second input end of the fourth selector are respectively connected to the first input end and the second input end of the data distribution circuit, and the control end of the fourth selector is connected to the first control end of the data distribution circuit. The register is used to temporarily store the data received by the data distribution circuit, so the input end of the register is connected to the output end of the fourth selector, and the output end of the register is connected to the first input end of the fifth selector. The fifth selector is used to implement whether the input data of the test bus passes through the configuration of the register, that is, the second input end of the fifth selector is connected to the first input end of the data distribution circuit, the output end of the fifth selector is connected to the second output end of the data distribution circuit, and the control end of the fifth selector is connected to the second control end of the data distribution circuit. The first output end of the data distribution circuit is connected to the first input end of the data distribution circuit or the output end of the register or the second output end of the data distribution circuit. In the above possible implementation, the data distribution circuit has two inputs, which are respectively for receiving test scan data from the test bus and for receiving test output data from the scan output channel of the corresponding circuit under test; the data distribution circuit realizes the selection of input by configuring the fourth selector, so that the test scan data and the test output data are transmitted in different time periods respectively, and the data transmission conflict is avoided when the circuit structure is more simplified. In addition, the data distribution circuit also controls whether the second output of the data distribution circuit passes through the register inside the data distribution circuit through the configuration of the fifth selector, so that when the circuit under test corresponding to the sub-test circuit where the data distribution circuit is located does not participate in the test, the first input to the second output of the data distribution circuit does not pass through its internal register, so as to reduce the test time, thereby further improving the test efficiency.

[0012] In a possible implementation of the first aspect, each sub-test circuit may further include a controller, wherein the controller may include: a first signal interface, the first signal interface is connected to the control end of each first selector in the sub-test circuit, and is used to control the first input end in the first selector to be connected to the output end or the second input end in the first selector to be connected to the output end. A second signal interface, the second signal interface is connected to the second control end of each data distribution circuit in the sub-test circuit, and is used to control the first input end and the second output end of the data distribution circuit to be directly connected or connected through a register. In the above possible implementation, the dynamic allocation of test resources is realized by configuring the first selector, and the configuration of the fifth selector is realized when the circuit under test does not participate in the test, and the data distribution circuit in the sub-test circuit corresponding to the circuit under test that does not participate in the test is configured to a bypass state, even if the first input to the second output of the data distribution circuit does not pass through its internal register to reduce the test time. Therefore, in this optional scheme, the first selector is configured by outputting a shift selection control signal through the first signal interface of the controller, and the fifth selector in the data distribution circuit is configured by outputting a bypass enable signal through the second signal interface of the controller.

[0013] In a possible implementation of the first aspect, in a j-th sub-test circuit of a plurality of sub-test circuits, a data distribution circuit is connected to a scan input channel of a circuit under test corresponding to the j-th sub-test circuit through a first gating circuit, and is used to control whether data in the data distribution circuit is output to the scan input channel of the circuit under test corresponding to the j-th sub-test circuit. The data distribution circuit is connected to a scan output channel of a circuit under test corresponding to the j-th sub-test circuit through a second gating circuit, and is used to control whether data in a scan output channel of the circuit under test corresponding to the j-th sub-test circuit is output to the data distribution circuit. In the above possible implementation, by setting a corresponding gating circuit between the scan input channel of the circuit under test and the data distribution circuit, and between the scan output channel of the circuit under test and the data distribution circuit, data can be transmitted between the data distribution circuit and the scan input channel of the circuit under test, or between the scan output channel of the circuit under test and the data distribution circuit only when the corresponding gating circuit is turned on, thereby avoiding the transmission of invalid data.

[0014] In a possible implementation of the first aspect, each sub-test circuit may further include a state machine, which may include: a first state control interface connected to the first control terminal of each data distribution circuit in the sub-test circuit, used to generate an output capture enable signal to control whether each data distribution circuit in the sub-test circuit receives the scan output data of the circuit under test. A second state control interface connected to the control terminal of the first gating circuit, used to generate a first gating enable signal to control whether the data of each data distribution circuit in the sub-test circuit is transmitted to the scan input channel of the circuit under test corresponding to the sub-test circuit. A third state control interface connected to the control terminal of the second gating circuit, used to generate a second gating enable signal to control whether the data of the scan output channel of the circuit under test corresponding to the sub-test circuit is transmitted to the data distribution circuit corresponding to the circuit under test. A fourth state control interface connected to the scan enable terminal of the scan structure of the circuit under test, used to generate a scan enable signal to control whether the scan structure of the circuit under test corresponding to the sub-test circuit performs a test scan. In the above possible implementations, an output capture enable signal is generated through the first state control interface of the state machine to configure the fourth selector in the data distribution circuit to control whether the data distribution circuit receives the test scan data of the test bus or the scan output data of the circuit under test at the current time. A first gating enable signal is generated through the second state interface of the state machine to control whether the test scan data of the data distribution circuit is transmitted to the scan input channel of the circuit under test. A third gating enable signal is generated through the third state interface of the state machine to control whether the scan data of the scan output channel of the circuit under test is transmitted to the data distribution circuit corresponding to the circuit under test. A scan enable signal is generated through the fourth state interface to control whether the scan structure of the circuit under test starts the test scan. The above four signals are generated by the state machine to configure the test process of the test circuit and simplify the configuration process.

[0015] In a possible implementation of the first aspect, the test circuit is disposed inside or outside the circuit under test. In the above possible implementation, whether the test circuit is disposed inside or outside the circuit under test, it has no effect on the circuit operation of the test circuit and the circuit under test.

[0016] In a second aspect, a test circuit is provided. The test circuit includes: a plurality of sub-test circuits corresponding to a plurality of circuits under test, and the plurality of sub-test circuits are used to connect the corresponding circuits under test to a test bus. Each circuit under test corresponds to a sub-test circuit, and each sub-test circuit can transmit the data required for the test scan to the scan input channel of the corresponding circuit under test through the test bus, and transmit the test result data of the corresponding circuit under test to the test bus output. Each sub-test circuit can also dynamically allocate the test bus to the corresponding circuit under test. Among them, the jth sub-test circuit in the plurality of sub-test circuits includes M data distribution circuits, M second selectors and CI j The jth sub-test circuit can be any one of the multiple sub-test circuits. The number of data distribution circuits and the number of second selectors M in the jth sub-test circuit are both equal to the bit width of the test bus. The number of third selectors CI in the jth sub-test circuit is j The number of scan input channels of the circuit under test corresponding to the j-th sub-test circuit is equal. The first input ends of the M data distribution circuits are respectively connected to the M inputs of the test bus, that is, the first input end of the data distribution circuit is used to receive the test scan data of the test bus, and the second output ends of the M data distribution circuits are respectively connected to the M outputs of the test bus, that is, the second output end of the data distribution circuit is used to output the test result data to the test bus. In the j-th sub-test circuit, the CO of each of the M second selectors is j Each input terminal is connected to the CO of the circuit under test corresponding to the jth sub-test circuit. j The output ends of the M second selectors are respectively connected to the second input ends of the M data distribution circuits in the sub-test circuit. The second selector is a multiplexer that selects one from many. The number of input ends of the second selector is related to the number of scan output channels of the circuit under test corresponding to the j-th sub-test circuit. If the number of scan output channels of the circuit under test is three, the second selector can select a multiplexer that selects one from three to select the data distribution circuit corresponding to each scan output channel of the circuit under test, and the corresponding test bus. In the j-th sub-test circuit, CI j The M input terminals of each of the three third selectors are respectively connected to the first output terminals of the M data distribution circuits. j The output ends of the third selectors are respectively connected to the CI of the circuit under test corresponding to the jth sub-test circuit. jScan input channel. The third selector is also a multiplexer that selects one from many. The number of input terminals of the third selector is related to the number of data distribution circuits corresponding to the j-th sub-test circuit. The number of data distribution circuits is related to the bit width of the test bus. If the bit width of the test bus is eight bits, the third selector can be an eight-to-one multiplexer for selecting the data distribution circuit corresponding to the scan input channel of the circuit under test and the corresponding test bus.

[0017] Based on the test circuit provided in the second aspect, the test circuit transmits the input data of the test vector, that is, the scan test data, to the data distribution circuit through the input of the test bus, and transmits it to the scan input channel of the circuit under test through the data distribution circuit. After the scan of the circuit under test is completed, the output data of the test vector of the scan output channel of the circuit under test, that is, the test result data, is transmitted to the output of the test bus through the data distribution circuit to complete the test of the circuit under test. The data distribution circuit that is connected to the scan output channel of the circuit under test is configured by the second selector, and the data distribution circuit that is connected to the scan input channel of the circuit under test is configured by the third selector. Since a data distribution circuit is provided on each bit of the test bus corresponding to each sub-test circuit, the configuration of the second selector and the third selector can not only optimize the problem of bus resource planning and wiring congestion, but also realize the allocation of each scan channel of the circuit under test to any bus resource, thereby making the allocation of bus resources more flexible.

[0018] In a possible implementation of the second aspect, each data distribution circuit may include a fourth selector, a register and a fifth selector; the internal structure of the data distribution circuit and the technical effects that can be produced can refer to the internal structure and technical effects of the data distribution circuit of the test circuit provided in the first aspect above, and will not be repeated here.

[0019] In a possible implementation of the second aspect, each sub-test circuit may further include a controller. The controller may include: a second signal interface for configuring the fifth selector of the data distribution circuit in each sub-test circuit, for controlling the first input end and the second output end of the data distribution circuit to be directly connected or connected through a register; multiple third signal interfaces for configuring the multiple second selectors in each sub-test circuit, for controlling the scan output channel of the circuit under test corresponding to the sub-test circuit to be connected to a data distribution circuit in the sub-test circuit; multiple fourth signal interfaces for configuring the multiple third selectors in each sub-test circuit, for controlling the sub-test circuit to select one of the data distribution circuits to be connected to the scan input channel of the circuit under test corresponding to the sub-test circuit. In the above possible implementation, the bypass enable signal output through the second signal interface of the controller is used to configure the fifth selector in the data distribution circuit, so that when the circuit under test does not participate in the test, the data distribution circuit in the sub-test circuit corresponding to the circuit under test that does not participate in the test is configured to be in a bypass state, even if the first input to the second output of the data distribution circuit does not pass through its internal register, thereby reducing the test time cycle. The scan output selection signal is output through the third signal interface of the controller, and the second selector is configured through the scan output selection signal, and the corresponding data distribution circuit is selected to receive the scan output data of the circuit under test. Similarly, the scan input selection signal is output through the fourth signal interface of the controller, and the third selector is configured through the scan input selection signal, and the corresponding data distribution circuit is selected to transmit the test scan data to the scan input channel of the circuit under test. Through this implementation method, the configuration process is simplified, thereby improving the test efficiency.

[0020] In a possible implementation of the second aspect, in the jth sub-test circuit of the plurality of sub-test circuits, the third selector is connected to the scan input channel of the circuit under test corresponding to the jth sub-test circuit through the first gating circuit, and is used to control whether the data in the data distribution circuit is output to the scan input channel of the circuit under test corresponding to the jth sub-test circuit. The scan output channel of the circuit under test corresponding to the jth sub-test circuit is connected to the second selector through the second gating circuit, and is used to control whether the data of the scan output channel of the circuit under test corresponding to the jth sub-test circuit is output to the data distribution circuit. In the above possible implementation, by setting a corresponding gating circuit between the scan input channel of the circuit under test and the data distribution circuit, and between the scan output channel of the circuit under test and the data distribution circuit, data can be transmitted between the data distribution circuit and the scan input channel of the circuit under test, or between the scan output channel of the circuit under test and the data distribution circuit only when the corresponding gating circuit is turned on, thereby avoiding the transmission of invalid data.

[0021] In a possible implementation manner of the second aspect, each sub-test circuit may further include a state machine. The state machine may refer to the state machine in the test circuit provided by the first aspect, and will not be described in detail here.

[0022] In a third aspect, another test circuit is provided, the test circuit comprising: a plurality of sub-test circuits corresponding to the plurality of circuits under test, the sub-test circuits being used to connect the circuits under test to a test bus. Each circuit under test corresponds to a sub-test circuit, each sub-test circuit can transmit the data required for the test scan to the scan input channel of the corresponding circuit under test through the test bus, and transmit the test result data of the corresponding circuit under test to the test bus output. Each sub-test circuit can also dynamically allocate the test bus to the corresponding circuit under test. The jth sub-test circuit among the plurality of sub-test circuits comprises Nj groups of data distribution circuits and CI j The jth sub-test circuit can be any one of the multiple sub-test circuits, and the number of groups of data distribution circuits Nj in the jth sub-test circuit is the number of scanning channels of the corresponding circuit under test, that is, the number of scanning input channels CI of the corresponding circuit under test. j and scan the number of output channels CO j The maximum value in, that is, Nj=Max(CI j ,CO j ). j The OR gates correspond to the CI in the Nj groups of data distribution circuits. j group data distribution circuit, and CI j The OR gates correspond to the CI of the circuit under test. j Nj scan input channels. CO in the data distribution circuit j The group data distribution circuits correspond to the CO of the circuit under test. jScan output channels. For example, the number of scan channels of the circuit under test is four, and the number of scan channels is the maximum value of the number of scan input channels and the number of scan output channels. Then the number of groups of data distribution circuits in the sub-test circuit corresponding to the circuit under test is four, and each group of data distribution circuits may correspond to one scan input channel and one scan output channel. The number of OR gates in the sub-test circuit is the number of scan input channels, that is, three, so each OR gate will also correspond to a group of data distribution circuits and one scan input channel of the circuit under test. In the jth sub-test circuit, each group of data distribution circuits includes M data distribution circuits, and the M data distribution circuits are respectively connected to the M-bit test bus. Each group of data distribution circuits in the Nj groups of data distribution circuits is sequentially connected in series to the corresponding test bus through the first input end and the second output end of each data distribution circuit, that is, multiple data distribution circuits on the same test bus are sequentially connected to the same test bus through the first input end and the second output end in sequence. The first output end of the M data distribution circuits in each group of data distribution circuits is connected to the M input ends of the corresponding OR gate, and the output end of the OR gate is connected to the corresponding scan input channel of the circuit under test. The second input terminals of the M data distribution circuits in each group of data distribution circuits are connected to the scan output channel of the corresponding circuit under test. Each data distribution circuit is also configured to control the reset of the data distribution circuit. When the data distribution circuit is reset, the output of the data distribution circuit is zero, so that in each group of data distribution circuits, the output value of the OR gate is the value output by the first output terminal of the selected data distribution circuit, that is, the input value of the selected test bus.

[0023] Based on the test circuit provided in the third aspect, the test circuit transmits the input data of the test vector, that is, the scan test data, to the data distribution circuit through the input of the test bus, and transmits it to the scan input channel of the circuit under test through the data distribution circuit. After the scan of the circuit under test is completed, the output data of the test vector of the scan output channel of the circuit under test, that is, the test result data, is transmitted to the output of the test bus through the data distribution circuit to complete the test of the circuit under test. By setting an OR gate between the scan input channel of the circuit under test and the data distribution circuit connected to the test bus, the data transmitted into the scan input channel of the circuit under test is selected by the OR gate, which can reduce the area overhead as much as possible, and optimize the winding congestion problem, thereby reducing the test cost. In addition, by resetting the unselected data distribution circuit, the output value of each OR gate can be the value output by the first output terminal of the selected data distribution circuit, thereby achieving correct test bus resource allocation, further simplifying the configuration process, and improving test efficiency.

[0024] In a possible implementation of the third aspect, each data distribution circuit may include a fourth selector, a register and a fifth selector. The internal structure of the data distribution circuit can refer to the internal structure of the data distribution circuit in the test circuit provided in the first aspect, which will not be repeated here. The difference is that the second control end of the data distribution circuit is also connected to the reset end of the register to control the reset of the register. In the above possible implementation, since the data distribution circuit needs to be reset, when the data distribution circuit needs to be bypassed through the fifth selector, the register in the data distribution circuit can be controlled to be reset through the bypass enable signal, and the structure is simpler.

[0025] In a possible implementation of the third aspect, each sub-test circuit may further include a controller. The controller may include: a second signal interface, the second signal interface is connected to the second control terminal of each data distribution circuit in the sub-test circuit, and is used to control the first input terminal and the second output terminal of the data distribution circuit to be directly connected or connected through a register, and to control the register reset. In the above possible implementation, a bypass enable signal is output through the second signal interface of the controller to configure the fifth selector in the data distribution circuit, set the unselected data distribution circuit in the sub-test circuit to bypass, and control the register reset of the data distribution circuit, so as to meet the requirement of the scan input channel of the circuit under test to select one of the data distribution circuits, and the configuration process is simple, which further improves the test efficiency.

[0026] In a possible implementation of the third aspect, in the jth sub-test circuit of the multiple sub-test circuits, the OR gate is connected to the scan input channel of the circuit under test corresponding to the jth sub-test circuit through the first gating circuit, and is used to control whether the data in the data distribution circuit is output to the scan input channel of the circuit under test corresponding to the jth sub-test circuit. The scan output channel of the circuit under test corresponding to the jth sub-test circuit is connected to the data distribution circuit through the second gating circuit, and is used to control whether the data of the scan output channel of the circuit under test corresponding to the jth sub-test circuit is output to the data distribution circuit. In the above possible implementation, by setting a corresponding gating circuit between the scan input channel of the circuit under test and the data distribution circuit, and between the scan output channel of the circuit under test and the data distribution circuit, data can be transmitted between the data distribution circuit and the scan input channel of the circuit under test, or between the scan output channel of the circuit under test and the data distribution circuit only when the corresponding gating circuit is turned on, thereby avoiding the transmission of invalid data.

[0027] In a possible implementation manner of the third aspect, each sub-test circuit may further include a state machine. The state machine may refer to the state machine in the test circuit provided by the first aspect, and will not be described in detail here.

[0028] In a fourth aspect, another test circuit is provided, which includes: a plurality of sub-test circuits corresponding to a plurality of circuits under test, respectively, and the plurality of sub-test circuits are used to respectively connect the corresponding circuits under test to a test bus. Each circuit under test corresponds to a sub-test circuit, and each sub-test circuit can transmit the data required for the test scan to the scan input channel of the corresponding circuit under test through the test bus, and transmit the test result data of the corresponding circuit under test to the test bus output. Each sub-test circuit can also dynamically allocate the test bus to the corresponding circuit under test. Among them, the j-th sub-test circuit among the plurality of sub-test circuits includes Nj data distribution circuits and M first selectors. The j-th sub-test circuit can be any one of the plurality of sub-test circuits, and the number Nj of data distribution circuits in the j-th sub-test circuit is the number of scan channels of the corresponding circuit under test, that is, the number CI of scan input channels of the corresponding circuit under test. j and scan output channel CO j The maximum value among the numbers, that is, Nj=max(CI j ,CO j ). The data distribution circuit is used to receive the scan test data of the test bus and transmit it to the scan input channel of the circuit under test, and receive the test result data of the scan output channel of the circuit under test and transmit it to the test bus output. The first selector can be a two-to-one selector, which is used to select the test bus used by the j+1th sub-test circuit. In the jth sub-test circuit, the first input ends of the Nj data distribution circuits are respectively connected to the Nj inputs of the test bus, that is, the first input ends of the data distribution circuits are used to receive the test scan data of the test bus; the CIs in the Nj data distribution circuits are respectively connected to the Nj inputs of the test bus, that is, the first input ends of the data distribution circuits are used to receive the test scan data of the test bus; j The first output terminals of the data distribution circuits are respectively connected to the CI of the circuit under test corresponding to the jth sub-test circuit. j A scan input channel, that is, the first input end of the data distribution circuit is used to transmit the test scan data received from the test bus to the scan input channel of the corresponding circuit under test; CO in Nj data distribution circuits j The second input terminals of the data distribution circuits are respectively connected to the CO of the circuit under test corresponding to the jth sub-test circuit. jA scan output channel, that is, the second input end of the data distribution circuit is used to receive the test result data output by the scan output channel of the corresponding circuit under test, and the test result data is output to the test bus through the second output end of the data distribution circuit. The number M of first selectors of each sub-test circuit in the multiple sub-test circuits is equal to the bit width of the test bus, and the output ends of the M first selectors in each sub-test circuit are respectively connected to the M outputs of the test bus, and the M first selectors in each sub-test circuit are respectively corresponding to the M bits of the test bus. Among them, the first input ends of the M first selectors are respectively connected to the M inputs of the test bus. The second input ends of the Nj first selectors in the M first selectors are respectively connected to the second output ends of the Nj data distribution circuits, and the second input ends of the remaining M-Nj first selectors are respectively connected to the inputs of the M-Nj test buses without the data distribution circuit. The buses connected to the first input end and the second output end of each first selector are different. In the jth sub-test circuit, the test buses connected to the first input end and the second input end of the first selector are different, and the test bus used by the j+1th sub-test circuit can be selected by the first selector.

[0029] Based on the test circuit provided in the fourth aspect, the test circuit transmits the input data of the test vector to the data distribution circuit through the input of the test bus, and transmits it to the scan input channel of the circuit under test through the data distribution circuit. After the scan of the circuit under test is completed, the output data of the test vector of the scan output channel of the circuit under test is transmitted to the output of the test bus through the data distribution circuit to complete the test of the circuit under test. The dynamic correspondence between the data distribution circuit and the test bus is realized by configuring the first selector, so that the test resources can be dynamically allocated. For example, the M first selectors in the jth sub-test circuit are configured to select the first input end of the first selector to be connected to the output end, and the test bus allocated to the j+1th sub-test circuit is the test bus A. Similarly, if the M first selectors in the jth sub-test circuit are configured to select the second input end of the first selector to be connected to the output end, the test bus allocated to the j+1th sub-test circuit is B. Among them, the data distribution circuit in the j+1th sub-test circuit will correspond to a group of first selectors in the jth sub-test circuit, recorded as the first selector X, so the test bus A is the test bus connected to the first selector X when the first selector X is configured to select the first input end of the first selector to be connected to the output end; the test bus B is the test bus connected to the first selector X when the first selector X is configured to select the second input end of the first selector to be connected to the output end. The test circuit provided by the fourth aspect can greatly optimize the problem of winding congestion, so as to reduce the test cost, and can simplify the configuration process and improve the test efficiency. In addition, in the jth sub-test circuit, the first input end of the first selector is directly connected to the input of the test bus, so that when the circuit under test corresponding to the jth sub-test circuit does not participate in the test, the input data of the j+1th sub-test circuit does not pass through the data distribution circuit in the jth sub-test circuit, thereby reducing the test time.

[0030] In a possible implementation of the fourth aspect, in the jth sub-test circuit among the multiple sub-test circuits, according to a preset bus order, the first input ends of the Nj data distribution circuits are connected to the inputs of the first Nj buses in sequence. The first input ends of the M first selectors are connected to the M inputs of the test bus in sequence. The second input ends of the first M-Nj first selectors are connected to the last M-Nj inputs of the test bus in sequence. The second input ends of the last Nj first selectors are connected to the second output ends of the Nj data distribution circuits in sequence. In the above possible implementation, the data distribution circuits are allocated to the bus resources in a preset order according to established rules, which can make the line design of the test circuit simpler and easier to wire while ensuring the dynamic allocation of test resources.

[0031] In a possible implementation of the fourth aspect, the preset bus order is the order of the number of bus bits or the reverse order. In the above possible implementation, the preset test bus order is in a specific order, such as the order of the test bus or the reverse order, so that the line structure of the test circuit can be further made simple and effective, thereby simplifying the structure of the test circuit to a certain extent, so as to quickly realize the wiring requirements of the test circuit.

[0032] In a possible implementation of the fourth aspect, each data distribution circuit may include a fourth selector and a register. The first input terminal and the second input terminal of the fourth selector are respectively connected to the first input terminal and the second input terminal of the data distribution circuit, and the control terminal of the fourth selector is connected to the first control terminal of the data distribution circuit. The input terminal of the register is connected to the output terminal of the fourth selector, and the output terminal of the register is connected to the second output terminal of the data distribution circuit. The first output terminal of the data distribution circuit is connected to the first input terminal of the data distribution circuit or the output terminal of the register. In the above possible implementation, the data distribution circuit has two inputs, which respectively receive test scan data from the test bus and receive test output data from the scan output channel of the corresponding circuit under test; the data distribution circuit realizes the selection of input by configuring the fourth selector, so that the test scan data and the test output data are transmitted in different time periods respectively, and the data transmission conflict is avoided when the circuit structure is more simplified.

[0033] In a possible implementation of the fourth aspect, each sub-test circuit may further include a controller, and the controller may include a first signal interface, the first signal interface is connected to the control end of the M first selectors in the sub-test circuit, and is used to control the first input end in the first selector to be connected to the output end or the second input end in the first selector to be connected to the output end. In the above possible implementation, the shift selection control signal output by the first signal interface of the controller is used to configure the first selector, and the configuration is simple and easy. When the first selector is configured so that the first input end and the output end of the first selector are connected, then in the sub-test circuit corresponding to the first selector, all test bus resources will not pass through the data distribution circuit, so when the circuit under test corresponding to the sub-test circuit does not participate in the test, the first selector is configured so that the first input end and the output end of the first selector are connected, which can reduce the test time.

[0034] In a possible implementation of the fourth aspect, in the jth sub-test circuit of the multiple sub-test circuits, the data distribution circuit is connected to the scan input channel of the circuit under test corresponding to the jth sub-test circuit through the first gating circuit, and is used to control whether the data in the data distribution circuit is output to the scan input channel of the circuit under test corresponding to the jth sub-test circuit. The data distribution circuit is connected to the scan output channel of the circuit under test corresponding to the jth sub-test circuit through the second gating circuit, and is used to control whether the data of the scan output channel of the circuit under test corresponding to the jth sub-test circuit is output to the data distribution circuit. In the above possible implementation, by setting a corresponding gating circuit between the scan input channel of the circuit under test and the data distribution circuit, and between the scan output channel of the circuit under test and the data distribution circuit, data can be transmitted between the data distribution circuit and the scan input channel of the circuit under test, or between the scan output channel of the circuit under test and the data distribution circuit only when the corresponding gating circuit is turned on, thereby avoiding the transmission of invalid data.

[0035] In a possible implementation manner of the fourth aspect, each sub-test circuit may further include a state machine. The state machine may refer to the state machine in the test circuit provided by the first aspect above, and will not be described in detail here.

[0036] Optionally, each sub-test circuit in the first to fourth aspects may further include a frequency division circuit, which is respectively connected to the bus clock interface and the scan clock interface of the circuit under test, and is used to divide the clock of the test bus into the scan clock of the circuit under test. In the above optional scheme, the high-speed scan clock of the test bus is divided into the low-speed scan clock in the circuit under test, which facilitates the scan test of the circuit under test.

[0037] In a fifth aspect, an integrated circuit is provided. The integrated circuit comprises: a plurality of circuits under test, a test bus, and any possible test circuit as described in the first to fourth aspects above. The plurality of circuits under test are connected to the test bus through a plurality of sub-test circuits corresponding to the circuits under test in the test circuit.

[0038] In a sixth aspect, an electronic device is provided, comprising a printed circuit board and the integrated circuit provided in the fifth aspect; the integrated circuit is arranged on the printed circuit board.

[0039] In the seventh aspect, a method for designing a test circuit is provided. The method for designing a test circuit includes: obtaining the number of scan input channels, the number of scan output channels, and the bus width of the test bus for each circuit under test. According to the bus width of the test bus, and the number of scan input channels and the number of scan output channels of each circuit under test, a data distribution circuit in a sub-test circuit corresponding to each circuit under test is configured on the test bus to generate any possible test circuit in the first to fourth aspects above. The number of data distribution circuits in the sub-test circuit corresponding to each circuit under test is determined by the bus width of the test bus, or the number of scan input channels and scan output channels of each circuit under test.

[0040] In an eighth aspect, a circuit testing method is provided. The circuit testing method can be used in EDA software and is suitable for testing a circuit under test using a test circuit, wherein the test circuit is any possible test circuit in the first aspect to the fourth aspect above. The circuit testing method includes: generating configuration information and a test vector; wherein the configuration information is used to configure the test circuit; and the test vector is test stimulus data of the circuit under test and is determined by the circuit structure of the circuit under test.

[0041] In a possible implementation of the eighth aspect, the circuit testing method may further include: configuring the test circuit according to the configuration information, transmitting the test vector to a test bus, and transmitting the test vector to a scan input channel of the circuit under test through the test circuit, and transmitting the test result data of the circuit under test to an output of the test bus through the circuit under test.

[0042] It should be understood that when configuring the test circuit, the specific configuration method and configuration content are different according to different test circuit structures.

[0043] For example, in the test circuit of the first aspect as described above, a shift selection control signal can be configured through the first signal interface of the controller to control the connection relationship between the input and output selected by the first selector. When the circuit under test does not participate in the test, the first selector in the sub-test circuit corresponding to the circuit under test is placed in direct connection mode, that is, the first selector is configured to connect the first input terminal with the output terminal. A bypass enable signal can be configured through the second signal interface of the controller to place the data distribution circuit in the sub-test circuit corresponding to the circuit under test that does not participate in the test in a bypass state, that is, the first input terminal and the second output terminal in the corresponding data distribution circuit do not pass through the register.

[0044] In the test circuit of the second aspect as described above, a scan output selection signal and a scan input selection signal can be configured by a controller. The scan output selection signal is output by the third signal interface and is used to configure the second selector so that the scan output channel of the circuit under test corresponding to the sub-test circuit is connected to a data distribution circuit in the sub-test circuit. The scan input selection signal is output by the fourth signal interface and is used to configure the third selector so that the sub-test circuit selects one of the data distribution circuits and is connected to the scan input channel of the circuit under test corresponding to the sub-test circuit.

[0045] In the test circuit of the third aspect as described above, a bypass enable signal can be configured through the second signal interface of the controller. The bypass enable signal can be used as a reset signal of the data distribution circuit. When the data distribution circuit is reset, it indicates that the data distribution circuit is not selected. Therefore, the value output by the first output terminal of the selected data distribution circuit is the input value of the selected test bus, thereby realizing a one-to-one correspondence between the test bus, the data distribution circuit and the scanning channel of the circuit under test.

[0046] In the test circuit of the fourth aspect as above, the shift selection control signal can be configured through the first signal interface of the controller to control the connection relationship between the input and output selected by the first selector. When the circuit under test does not participate in the test, the first selector in the sub-test circuit corresponding to the circuit under test is placed in direct connection mode, that is, the first selector is configured to connect the first input terminal and the output terminal.

[0047] In addition, in the test circuits of the first aspect to the fourth aspect as described above, the output capture enable signal is configured through the first state control interface of the state machine, the first gating enable signal is configured through the second state control interface of the state machine, the second gating enable signal is configured through the third state control interface of the state machine, and the scan enable signal is configured through the fourth state control interface of the state machine. For the functions of the output capture enable signal, the first gating enable signal, the second gating enable signal, and the scan enable signal, please refer to the description of the state machine in the first aspect, which will not be repeated here.

[0048] In a possible implementation of the eighth aspect, the test vector is transmitted to the scan input channel of the circuit under test through the test circuit, including: according to the corresponding relationship between the scan input channel of the circuit under test and the input of the test bus, the test vector is transmitted to the scan input channel of the circuit under test through the input of the test bus corresponding to the scan input channel of the circuit under test. Wherein, the corresponding relationship between the scan input channel of the circuit under test and the input of the test bus is determined by the data distribution circuit in the sub-test circuit corresponding to the circuit under test. For example, in the test circuits in the first and fourth aspects above, the scan input channel of the circuit under test and the data distribution circuit in the corresponding sub-test circuit are in a one-to-one correspondence. Therefore, the corresponding relationship between the scan input channel of the circuit under test and the input of the test bus is actually the actual connection relationship between the data distribution circuit in the sub-test circuit corresponding to the circuit under test and the test bus. In the test circuit in the second aspect above, the scan input channel of the circuit under test and the data distribution circuit in the sub-test circuit corresponding to the circuit under test are in a one-to-many relationship. Therefore, the corresponding relationship between the scan input channel of the circuit under test and the input of the test bus can be configured by the scan input selection signal configured by the controller. After the configuration, the test bus connected to the data distribution circuit selected by the scan input channel of the circuit under test corresponds to the scan input channel of the circuit under test. In the test circuit in the third aspect as above, the scan input channel of the circuit under test and the data distribution circuit in the sub-test circuit corresponding to the circuit under test belong to a one-to-many relationship. Therefore, the corresponding relationship between the scan input channel of the circuit under test and the input of the test bus can be controlled by a bypass enable signal, and the bypass enable signal can control the data distribution circuit to reset. When the data distribution circuit is not reset, the data distribution circuit is selected by the corresponding scan input channel of the circuit under test. That is, the corresponding relationship between the scan input channel of the circuit under test and the input of the test bus is determined by the data distribution circuit that has not been reset.

[0049] In a possible implementation of the eighth aspect, the test result data of the circuit under test is transmitted to the test bus output through the circuit under test, including: according to the correspondence between the scan output channel of the circuit under test and the output of the test bus, the test result data output by the scan output channel of the circuit under test is transmitted to the output of the test bus corresponding to the scan output channel of the circuit under test; wherein the correspondence between the scan output channel of the circuit under test and the output of the test bus is determined by the data distribution circuit in the sub-test circuit corresponding to the circuit under test. The method for determining the correspondence between the scan output channel of the circuit under test and the output of the test bus is similar to the method for determining the correspondence between the scan input channel of the circuit under test and the input of the test bus above, and will not be repeated here.

[0050] Furthermore, according to the correspondence between the scan input channel of the circuit under test and the input of the test bus, the test vector is transmitted to the scan input channel of the circuit under test through the input of the test bus corresponding to the scan input channel of the circuit under test, including: the test bus transmits the test vector to the scan input channel of the circuit under test in sequence during multiple bus clock cycles; wherein, the number of scan input channels of the circuit under test corresponding to one of the inputs of the test bus exceeds one.

[0051] It should be noted that when testing a circuit under test, multiple circuits under test may be tested at the same time. However, the bit width of the test bus is limited, so the test bus will be multiplexed, that is, the test bus will transmit data to the scan input channels of multiple circuits under test by timing splitting. In one bus clock cycle, the test bus can only transmit data to one scan input channel, so if one of the inputs of the test bus needs to transmit data to multiple scan input channels, the data will be split and transmitted in sequence in multiple bus clock cycles.

[0052] Further, according to the correspondence between the scan output channel of the circuit under test and the output of the test bus, the test result data output by the scan output channel of the circuit under test is transmitted to the output of the test bus corresponding to the scan output channel of the circuit under test, including: the test bus sequentially transmits the test result data in the scan output channel of the circuit under test to the output of the test bus in multiple clock cycles, wherein the number of scan output channels of the circuit under test corresponding to one of the outputs of the test bus exceeds one. The test result data is transmitted to the test bus, and similarly, the scan test data, i.e., the test vector, is transmitted to the scan input channel of the circuit under test, which will not be described in detail here.

[0053] In a ninth aspect, a computer-readable storage medium is provided, the computer-readable storage medium comprising a program or an instruction, which, when executed on a computer, enables the computer to execute any possible circuit testing method in the eighth aspect.

[0054] In a tenth aspect, a computer program product is provided, the computer program product comprising: a computer program code, when the computer program code is run on a computer, the computer executes any possible circuit testing method in the eighth aspect.

[0055] It can be understood that any of the integrated circuits, electronic devices, test circuit design methods, circuit testing methods, computer-readable storage media, and computer program products provided above can be implemented by or associated with the corresponding test circuits provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects in the test circuits provided above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application;

[0057] Figure 2 for Figure 1 Schematic diagram of the structure of the circuit under test, test bus and test circuit Figure 1 ;

[0058] Figure 3 A schematic diagram of the structure of a data distribution circuit in a test circuit provided in an embodiment of the present application;

[0059] Figure 4 A schematic diagram of the structure of a gate control circuit in a test circuit provided in an embodiment of the present application;

[0060] Figure 5 for Figure 1 Schematic diagram of the structure of the circuit under test, test bus and test circuit Figure 2 ;

[0061] Figure 6 for Figure 1 Schematic diagram of the structure of the circuit under test, test bus and test circuit Figure 3 ;

[0062] Figure 7 for Figure 1 Schematic diagram of the structure of the circuit under test, test bus and test circuit Figure 4 ;

[0063] Figure 8 for Figure 7 A schematic diagram of the structure of the data distribution circuit in FIG.

[0064] Fig. 9 for Figure 1 Schematic diagram of the structure of the circuit under test, test bus and test circuit Figure 5 ;

[0065] Fig.10 for Fig. 9 A schematic diagram of the structure of the data distribution circuit in FIG.

[0066] Fig.11 A flow chart of a circuit testing method provided for an embodiment of the present application;

[0067] Fig.12 for Figure 2 A structural schematic diagram of a corresponding test scheme;

[0068] Fig.13 for Figure 2 A structural schematic diagram of another corresponding test scheme;

[0069] Fig.14for Fig.13 A waveform diagram of the scanning process of the corresponding test solution;

[0070] Fig.15 A flow chart of a test circuit design method provided in an embodiment of the present application.

[0071] Reference numerals:

[0072] 01-circuit under test; 02-test bus; 03-test circuit; 30-sub-test circuit; 301-data distribution circuit; 302-first selector; 303-controller; 304-state machine; 305-frequency division circuit; 306-first gating circuit; 307-second gating circuit; 308-second selector; 309-third selector; 310-OR gate; 3011-fourth selector; 3012-register; 3013-fifth selector. DETAILED DESCRIPTION

[0073] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0074] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0075] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0076] In this application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can refer to a physical direct connection, or it can refer to an electrical connection achieved through an intermediate medium, such as a connection achieved through a resistor, inductor, capacitor, or other electronic device.

[0077] Some embodiments of the present application provide a test circuit 03 (such as Figure 1The test circuit 03 is used to test multiple functional modules of the integrated circuit so that the integrated circuit can complete the predetermined functions. Different integrated circuits can realize different functions, so their functional modules are also different. For example, a mobile phone chip includes a processor module, a touch screen control module, a storage module, a power management module, etc.

[0078] Some embodiments of the present application provide an integrated circuit. Figure 1 For a schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application, please refer to Figure 1 The integrated circuit includes a plurality of circuits under test 01, a test bus 02 and a test circuit 03. Different circuits under test in each integrated circuit can realize the same function or completely different functions. The test circuit 03 includes a plurality of sub-test circuits 30 corresponding to the plurality of circuits under test 01, that is, each circuit under test 01 corresponds to a sub-test circuit 30. The plurality of circuits under test 01 are connected to the test bus 02 through the plurality of sub-test circuits 30, so that the integrated circuit can perform functional tests on the plurality of circuits under test 01 according to the planned test rules.

[0079] The embodiment of the present application also provides an electronic device. The electronic device includes a printed circuit board and an integrated circuit provided in the above embodiment, wherein the integrated circuit provided in the above embodiment is arranged on the printed circuit board. The electronic device includes electronic products such as mobile phones, tablet computers (pads), computers, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, etc. The embodiment of the present application does not impose any special restrictions on the specific form of the above electronic devices.

[0080] A test circuit 03 provided in some embodiments of the present application is described in detail below in conjunction with the accompanying drawings.

[0081] Figure 2 for Figure 1 Schematic diagram of the structure of the circuit under test, test bus and test circuit Figure 1 ; Figure 5 for Figure 1 Schematic diagram of the structure of the circuit under test, test bus and test circuit Figure 2 ; Figure 6 for Figure 1 Schematic diagram of the structure of the circuit under test, test bus and test circuit Figure 3 ; Figure 7 for Figure 1 Schematic diagram of the structure of the circuit under test, test bus and test circuit Figure 4 ; Fig. 9 for Figure 1Schematic diagram of the structure of the circuit under test, test bus and test circuit Figure 5 Please refer to Figure 2 , Figure 5 , Figure 6 , Figure 7 and Fig. 9 , and combined with Figure 1 In an integrated circuit, multiple functional modules that implement different functions or the same functions may be included. All functional modules need to be tested by a test circuit to know whether the function of the functional module can be executed normally. At this time, the functional module can be referred to as a tested circuit 01 during the test. Therefore, a test circuit in an embodiment of the present application may include: multiple corresponding to the multiple tested circuits 01, such as Figure 1 The sub-test circuit 30 shown in FIG. Figure 1 The sub-test circuit 30 shown is used to connect the corresponding circuit under test 01 to the test bus 02, wherein the test bus 02 corresponds to Figure 2 , Figure 5 , Figure 6 , Figure 7 and Fig. 9 In the scanbus, scanbus_in is the input channel of the test bus 02, and scanbus_out is the output channel of the test bus 02.

[0082] It should be noted that if Figure 1 The sub-test circuit 30 shown is used to connect the corresponding circuit under test 01 to the test bus, wherein each Figure 1 The sub-test circuit 30 shown may include a plurality of data distribution circuits 301, each of which is as shown in FIG. Figure 1 The number of data distribution circuits 301 in the sub-test circuit 30 shown is related to the number of scan channels in the circuit under test 01 corresponding to the sub-test circuit. Figure 2 In the example shown, each Figure 1 The number of data distribution circuits 301 in the sub-test circuit 30 shown is equal to the number of scan channels in the corresponding circuit under test 01. The number of scan channels of the circuit under test 01 is the maximum value between the number of scan input channels and the number of scan output channels of the circuit under test 01. Figure 1 The sub-test circuit 30 shown can connect the circuit under test 01 to the test bus via a plurality of data distribution circuits 301 .

[0083] Specifically, the data distribution circuit 301, also known as a dynamic routing unit (DRU), has two input terminals and two output terminals. The first input terminal of the data distribution circuit 301 is connected to the input channel scanbus_in of the test bus 02, the second input terminal is connected to the scan output channel channel_out of the circuit under test 01, the first output terminal is connected to the scan input channel channel_in of the circuit under test 01, and the second output terminal is connected to the output channel scanbus_out of the test bus 02.

[0084] In the test circuit of the embodiment of the present application, the data distribution circuit 301 receives the data of the input channel scanbus_in of the test bus 02, and the data input in the input channel scanbus_in of the test bus 02 is the test vector required by the circuit under test 01. The data distribution circuit 301 transmits the received data in the input channel scanbus_in of the test bus 02 to the scan structure (scanstucture) of the circuit under test 01 through the scan input channel channel_in of the circuit under test 01. Among them, the scan structure of the circuit under test 01 is a structural block in the circuit under test 01 for performing a scan test on the circuit under test 01. The scan input channel and the scan output channel of the circuit under test 01 are both connected to the scan structure in the circuit under test 01. The scan structure receives the input data of the scan input channel channel_in and performs a scan test on the circuit under test. After the test is completed, the test result data is output through the scan output channel channel_out on the scan structure. When the scan structure of the circuit under test 01 completes the scan test, the data distribution circuit 301 outputs the test result data from the scan output channel channel_out of the circuit under test 01, and transmits the test result data to the output channel scanbus_out of the test bus 02, and transmits it to the test software for comparison with the expected test result data, or directly compares it with the expected test result data on the test machine to determine whether the circuit under test 01 has a fault, where the test software is such as EDA software.

[0085] In the entire test circuit, the role of the data distribution circuit 301, i.e., DRU, is to distribute and transmit the test data. In the process of data distribution and transmission, the data distribution circuit 301 is used to receive the input data of the input channel scanbus_in of the test bus and transmit it to the scan input channel channel_in of the circuit under test 01. After the test scan of the circuit under test 01 is completed, the data distribution circuit 301 receives the test result data of the scan output channel channe_out of the circuit under test 01, and transmits it to the output channel scanbus_out of the test bus 02 to complete the test. The corresponding relationship between the data distribution circuit 301 and the test bus 02 can be dynamically allocated, such as a data distribution circuit can be connected to multiple inputs or outputs of the test bus, and the actual connection relationship between the data distribution circuit 301 and the multiple inputs or outputs of the test bus 02 can be dynamically configured in the form of a multiplexer, so as to achieve the purpose of dynamic connection between the data distribution circuit 301 and the test bus 02. Through the dynamic connection relationship between the data distribution circuit 301 and the test bus 02, the test bus 02 is dynamically allocated to meet the demand for testing a larger number of circuits under test 01, thereby optimizing line connections, reducing line congestion, and reducing area overhead.

[0086] Regarding how the data distribution circuit 301 is dynamically connected to the test bus, various exemplary embodiments are provided in the embodiments of the present application.

[0087] For example 1, please refer to Figure 2 ,exist Figure 2 In the circuit structure diagram in, multiple Figure 1 In the sub-test circuit 30 shown in FIG. 1 , the j-th sub-test circuit includes Nj data distribution circuits 301 and M first selectors 302. The first selectors 302 refer to Figure 2The shift selector SHIFT_MUX in the structure can be set according to the following relationship for the connection relationship between the first selector 302 and the test bus 02: the first input ends of the first Nj first selectors 302 are connected to the second output ends of the Nj data distribution circuits 301 in sequence; the first input ends of the last M-Nj first selectors 302 are connected to the last M-Nj input channels scanbus_in of the test bus 02 in sequence, that is, in the j-th sub-test circuit, when the first selector is configured so that the first input end and the output end of the first selector are connected, the test buses corresponding to the output and input of the first selector are the same, that is, the direct connection mode. The second input ends of the first M-Nj first selectors 302 are connected in sequence to the last M-Nj input channels scanbus_in of the test bus; the second input ends of the last Nj first selectors 302 are connected in sequence to the second output ends of the Nj data distribution circuits 301, that is, in the jth sub-test circuit, the first selector is configured so that when the second input end and the output end of the first selector are connected, the output of the first selection corresponds to different test buses than the input, that is, a shift connection mode.

[0088] It should be noted that the preset test bus sequence can be the order or reverse order of the test bus bit sequence. It can also be any other preset or specified bus sequence, which is not limited here. For example, the preset test bus sequence is [0][2][4][6][1][3][5][7], [0] is the [0]th bit of test bus 02, i.e. scanbus_in[0] and scanbus_out[0].

[0089] Please refer to Figure 2 ,exist Figure 2 The connection relationship between the first selector 302 and the test bus and the data distribution circuit 301 is connected in accordance with the order of the test bus bit sequence. Figure 2 , which is described in detail.

[0090] exist Figure 2 In the figure, three circuits under test 01 are shown as an example, namely, circuit under test A (core_A), circuit under test B (core_B) and circuit under test C (core_C); Figure 1 The sub-test circuits 30 shown are respectively a first sub-test circuit corresponding to the circuit A under test, a second sub-test circuit corresponding to the circuit B under test, and a third sub-test circuit corresponding to the circuit B under test.

[0091] It is worth noting that in Figure 2In the example shown, although the first, second, and third sub-test circuits corresponding to the circuits under test A, B, and C, respectively, are arranged inside the circuits under test A, B, and C, in fact, the circuit structures of the circuits under test A, B, and C may not include the corresponding sub-test circuits, that is, the sub-test circuits corresponding to the circuits under test A, B, and C are only arranged inside the circuits under test A, B, and C in terms of circuit position relationship.

[0092] In addition, the sub-test circuits corresponding to the circuits under test A, B and C can be arranged outside the circuits under test A, B and C, for example. Figure 5 The circuit structure shown. Figure 1 Whether the sub-test circuit 30 is arranged inside or outside the circuit under test 01 has no effect on the circuit operation of the test circuit and the circuit under test 01. Figure 1 The test circuit 03 shown in FIG. Figure 1 The sub-test circuit 30 shown is arranged inside the circuit under test 01.

[0093] exist Figure 2 In the scanning structure of the circuit A under test, there are three scanning input channels channel_in, namely channel_in[0], channel_in[1], and channel_in[2]; and three scanning output channels channel_out, namely channel_out[0], channel_out[1], and channel_out[2] (please refer to Figure 2 Channel_in / out in the scan structure A, detailed correspondence Figure 2 not shown).

[0094] The scan structure of the circuit under test B has five scan input channels channel_in, namely channel_in[0], channel_in[1], channel_in[2], channel_in[3], channel_in[4]; and five scan output channels channel_out, namely channel_out[0], channel_out[1], channel_out[2], channel_out[3], channel_out[4] ( Figure 2 not shown).

[0095] The scan structure of the circuit under test C has four scan input channels channel_in, namely channel_in[0], channel_in[1], channel_in[2], channel_in[3]; and four scan output channels channel_out, namely channel_out[0], channel_out[1], channel_out[2], channel_out[3] ( Figure 2 not shown).

[0096] Therefore, the first sub-test circuit corresponding to the tested circuit A has three data distribution circuits 301 , the second sub-test circuit corresponding to the tested circuit B has five data distribution circuits 301 , and the third sub-test circuit corresponding to the tested circuit C has four data distribution circuits 301 .

[0097] For example, Figure 2 The bit width of the test bus is eight bits. The first input terminals of the three data distribution circuits 301 in the first sub-test circuit are respectively connected to the first three bits of the test bus, namely scanbus_in[0], scanbus_in[1], and scanbus_in[2]. Similarly, the first input terminals of the five data distribution circuits 301 in the second sub-test circuit are respectively connected to the first five bits of the test bus, namely scanbus_in[0], scanbus_in[1], scanbus_in[2], scanbus_in[3], and scanbus_in[4]. The first input terminals of the four data distribution circuits 301 in the third sub-test circuit are respectively connected to the first four bits of the test bus, namely scanbus_in[0], scanbus_in[1], scanbus_in[2], and scanbus_in[3].

[0098] As for the first selectors 302 , in this example, the number of the first selectors 302 corresponding to each sub-test circuit is equal to the bit width of the test bus, that is, the number of the first selectors 302 corresponding to each sub-test circuit is eight.

[0099] Therefore, in the first sub-test circuit corresponding to the circuit under test A, the first input ends of the first three first selectors 302 are connected to the second output ends of the three data distribution circuits 301, and the first input ends of the last five first selectors 302 are connected to the input scanbus_in of the last five test buses, that is, scanbus_in[3], scanbus_in[4], scanbus_in[5], scanbus_in[6], and scanbus_in[7] of the test bus. The second input ends of the first five first selectors 302 are connected to the input scanbus_in of the last five test buses, that is, scanbus_in[3], scanbus_in[4], scanbus_in[5], scanbus_in[6], and scanbus_in[7] of the test bus, and the second input ends of the last three first selectors 302 are connected to the second input ends of the three data distribution circuits 301.

[0100] By analogy, in the second sub-test circuit corresponding to the circuit under test B, the first input ends of the first five first selectors 302 are connected to the second output ends of the five data distribution circuits 301, and the first input ends of the last three first selectors 302 are connected to the input scanbus_in of the last three test buses, that is, scanbus_in[5], scanbus_in[6], and scanbus_in[7] of the test bus. The second input ends of the first three first selectors 302 are connected to the input scanbus_in of the last three test buses, that is, scanbus_in[5], scanbus_in[6], and scanbus_in[7] of the test bus, and the second input ends of the last five first selectors 302 are connected to the second input ends of the five data distribution circuits 301.

[0101] In the third sub-test circuit corresponding to the circuit under test C, the first input ends of the first four first selectors 302 are connected to the second output ends of the four data distribution circuits 301, and the first input ends of the last four first selectors 302 are connected to the input scanbus_in of the last four test buses, that is, scanbus_in[4], scanbus_in[5], scanbus_in[6], and scanbus_in[7]. The second input ends of the first four first selectors 302 are connected to the input scanbus_in of the last four test buses, that is, scanbus_in[4], scanbus_in[5], scanbus_in[6], and scanbus_in[7] of the test bus, and the second input ends of the last four first selectors 302 are connected to the second input ends of the four data distribution circuits 301.

[0102] It should be understood that in this example, in order to control the first selector 302 to select whether the first input terminal is connected to the output terminal or the second input terminal is connected to the output terminal, the control terminal of the first selector 302 receives the shift selection control signal bus_shift for control. The shift selection control signal bus_shift is generated by the controller 303, that is, corresponds to the first signal interface of the controller 303, and the controller 303 can be configured by the IEEE 1687 standard (Internal JTAG, IJTAG) protocol pin.

[0103] When the shift selection control signal bus_shift instructs the first selector 302 to select the first input terminal to be connected to the output terminal, the input scanbus_in and output scanbus_out of the test bus in the sub-test circuit are in a direct connection mode, for example, scanbus_in[0] of the test bus corresponds to scanbus_out[0] of the test bus, and so on.

[0104] When the shift selection control signal bus_shift indicates that the first selector 302 selects the second input terminal to be connected to the output terminal, the input scanbus_in and the output scanbus_out of the test bus in the sub-test circuit are in a shifted connection mode, that is, corresponding to Figure 2 In the example, in the first sub-test circuit, the scanbus_in[0] of the test bus corresponds to the scanbus_out[5] of the test bus; the scanbus_in[3] of the test bus corresponds to the scanbus_in[0] of the test bus, and so on.

[0105] It is worth noting that, through such a shift connection mode, in some test scenarios, the circuit under test 01 may not participate in the test. For the circuit under test 01 not participating in the test, its corresponding Figure 1 The bus in the sub-test circuit 30 shown adopts a direct connection mode, which can keep the bus resource allocation of the tested circuit 01 participating in the test continuous, thereby reducing the complexity of the test circuit configuration.

[0106] exist Figure 2In the example diagram shown, assuming that the circuit under test B does not participate in the test, the shift selection control signal bus_shift in the sub-test circuit corresponding to the circuit under test B is controlled to instruct the first selector 302 to select the first input end to be connected to the output end, that is, the direct connection mode. Therefore, the input channels of the test bus used by the circuit under test A are scanbus_in[0], scanbus_in[1], and scanbus_in[2] of the test bus 02, and the output channels are scanbus_out[1], scanbus_out[2], and scanbus_out[3] of the test bus 02. The input channels of the test bus occupied by the circuit under test B are scanbus_in[3], scanbus_in[4], scanbus_in[5], and scanbus_in[6] of the test bus 02, and the output channels are scanbus_out[4], scanbus_out[5], scanbus_out[6], and scanbus_out[7] of the test bus 02.

[0107] Figure 3 The structure diagram of the data distribution circuit 301 in a test circuit provided in this embodiment is shown, which is suitable for Figure 2 For example 1 shown, please refer to Figure 3 , each data distribution circuit 301 includes a fourth selector 3011 , a register 3012 and a fifth selector 3013 .

[0108] The fourth selector 3011 is used to implement the data distribution circuit 301 to select whether to receive data from the test bus 02 or from the scan output channel channel_out of the corresponding circuit under test 01. That is, the first input terminal and the second input terminal of the fourth selector 3011 are respectively connected to the first input terminal and the second input terminal of the data distribution circuit 301. The control terminal of the fourth selector 3011 is connected to the first control terminal of the data distribution circuit 301, and is used to control the selection of input bus data to the data distribution circuit 301, or select the input of the scan output data of the corresponding circuit under test 01 to the data distribution circuit 301.

[0109] The register 3012 is used to temporarily store the data received by the data distribution circuit 301 , so the input end of the register 3012 is connected to the output end of the fourth selector 3011 , and the output end of the register 3012 is connected to the first input end of the fifth selector 3013 .

[0110] The fifth selector 3012 is used to realize whether the input data of the test bus 02 passes through the configuration of the register 3012, that is, the second input end of the fifth selector 3013 is connected to the first input end of the data distribution circuit 301, the output end of the fifth selector 3013 is connected to the second output end of the data distribution circuit 301, and the control end of the fifth selector 3013 is connected to the second control end of the data distribution circuit 301.

[0111] The first output terminal of the data distribution circuit 301 is connected to the first input terminal of the data distribution circuit 301 or the output terminal of the register 3012 or the second output terminal of the data distribution circuit 301 .

[0112] In the case that there is a circuit under test 01 that does not participate in the test, in order to reduce the test time, a fifth selector 3013 is provided in the above-mentioned data distribution circuit 301. The fifth selector 3013 is a selector that selects one of two, and generates a bypass enable signal dru_bp through the configuration of the controller 303, that is, corresponding to the second signal interface of the controller 303, controls the first input end of the fifth selector 3013 to connect its output end, or controls the second input end of the fifth selector 3013 to connect its output end. When the bypass enable signal dru_bp indicates that the fifth selector 3013 selects the first input end to connect its output end, the data distribution circuit 301 is in a bypass state, that is, the first input end and the second output end of the data distribution circuit 301 are directly connected. Therefore, when a circuit under test 01 does not participate in the test, all data distribution circuits 301 in the sub-test circuit corresponding to the circuit under test 01 are set to a bypass state, and no additional time period will be occupied during the data transmission process, thereby reducing the test time.

[0113] Example 2, please refer to Figure 6 ,exist Figure 6 In the circuit structure diagram in, multiple Figure 1 The j-th sub-test circuit in the sub-test circuit 30 shown includes M data distribution circuits 301, M second selectors 308 and CI j A third selector 309, wherein the jth sub-test circuit can be any one of the multiple sub-test circuits, and the second selector 308 can refer to Figure 6 The scan output selector SO_MUX in the third selector 309 can be found in Figure 6 The number of data distribution circuits 301 and the number of second selectors 308 in the j-th sub-test circuit are both equal to the bit width of the test bus, and the number of third selectors 309 in the j-th sub-test circuit is equal to the bit width of the test bus. jThe number of scan input channels channel_in of the tested circuit 01 corresponding to the jth sub-test circuit is equal. The first input ends of the M data distribution circuits 301 are respectively connected to the M input channels scanbus_in of the test bus 02, that is, the first input end of the data distribution circuit 301 is used to receive the test scan data of the test bus 02, and the second output ends of the M data distribution circuits 301 are respectively connected to the M output channels scanbus_out of the test bus.

[0114] In the j-th sub-test circuit, the CO of each of the M second selectors 308 is j The input terminals are connected to the CO of the tested circuit 01 corresponding to the jth sub-test circuit. j The output ends of the M second selectors 308 are respectively connected to the second input ends of the M data distribution circuits 301 in the sub-test circuit. The second selector 308 is a multiplexer that selects one from many. The number of input ends of the second selector 308 is related to the number of scan output channels channel_out of the tested circuit 01 corresponding to the j-th sub-test circuit. If the number of scan output channels channel_out of the tested circuit 01 is three, the second selector 308 can select a multiplexer that selects one from three to select the data distribution circuit 301 corresponding to each scan output channel channel_out of the tested circuit 01, and the corresponding input channel scanbus_in or output channel scanbus_out of the test bus 02.

[0115] In the jth sub-test circuit, CI j The M input terminals of each of the third selectors 309 are connected to the first output terminals of the M data distribution circuits 301, respectively. j The output terminals of the third selectors 309 are respectively connected to the CI of the tested circuit 01 corresponding to the j-th sub-test circuit. j Scan input channel channel_in. The third selector 309 is also a multiplexer that selects one from many. The number of input terminals of the third selector 309 is related to the number of data distribution circuits 301 corresponding to the j-th sub-test circuit. The number of data distribution circuits 301 is related to the bit width of the test bus 02. For example, if the bit width of the test bus 02 is eight bits, the third selector 309 can be an eight-to-one multiplexer for selecting the data distribution circuit 301 corresponding to the scan input channel channel_in of the circuit under test 01, and the corresponding input channel scanbus_in or output channel scanbus_out of the test bus 02.

[0116] In this example, the scan output channel channel_out of the circuit under test 01 is configured by the second selector 308 to select the connected data distribution circuit 301, and the scan input channel channel_in of the circuit under test 01 is configured by the third selector 309 to select the connected data distribution circuit 301. Figure 1 In the sub-test circuit 30 shown, a data distribution circuit 301 is provided on each bit of the test bus. Therefore, through the configuration of the second selector 308 and the third selector 309, it is possible to optimize the problem of bus resource planning and routing congestion, and also to realize the allocation of each scanning channel of the circuit under test 01 to any bus resource, thereby making the allocation of bus resources more flexible.

[0117] Corresponds to Figure 6 In the example in FIG. 1 , the second selector 308 and the third selector 309 are both multiplexers that select one from many. The configuration of the second selector 308 and the third selector 309 is configured by using the signal generated by the controller 303. At this time, the second selector 308 corresponds to the scan output selection signal so_select, and the third selector 309 corresponds to the scan input selection signal si_select. In the controller 303, the scan output selection signal so_select is generated by the third signal interface, and the scan input selection signal si_select is generated by the fourth signal interface. In other words, the scan output selection signal so_select is output through the third signal interface of the controller 303, and the second selector 308 is configured through the scan output selection signal so_select, and the corresponding data distribution circuit 301 is selected to receive the scan output data of the circuit under test 01. Similarly, the scan input selection signal si_select is output through the fourth signal interface of the controller 303, and the third selector 309 is configured through the scan input selection signal si_select, and the corresponding data distribution circuit 301 is selected to transmit the test scan data to the scan input channel channel_in of the circuit under test 01. This configuration makes the configuration of the test circuit simple and easy.

[0118] It should be noted that please refer to Figure 6 ,by Figure 6For example, the second selector 308 is a three-to-one selector, so the scan output selection signal so_select should actually be a two-bit signal, and the output values ​​are 00, 01 and 10, respectively, which correspond to a scan output channel of the circuit A under test. The third selector 309 is an eight-to-one selector, so the scan input selection signal si_select should actually be a three-bit signal, and the output values ​​are 000, 001, 010, 011, 100, 101, 110, 111, respectively, which correspond to a data distribution circuit in the sub-test circuit corresponding to the circuit A under test.

[0119] It should also be noted that in Figure 6 In the example, there are multiple second selectors 308 and multiple third selectors 309, so there is a scan output selection signal so_select corresponding to each second selector 308 (only one scan output selection signal so_select is drawn for example in the figure), and there is a scan input selection signal si_select corresponding to each third selector 309 (only one scan input selection signal si_select is drawn for example in the figure).

[0120] In addition, corresponding to Figure 6 In the example, Figure 6 The structure of the data distribution circuit 301 can refer to Figure 3 The structure of the data distribution circuit 301 shown in FIG. 3 is not repeated here.

[0121] Example 3, please refer to Figure 7 ,exist Figure 7 In the circuit structure diagram in, multiple Figure 1 The j-th sub-test circuit in the sub-test circuit 30 shown includes Nj groups of data distribution circuits 301 and CI j The j-th sub-test circuit may be any one of the multiple sub-test circuits, and the number of groups of data distribution circuits Nj in the j-th sub-test circuit is the number of scanning channels of the corresponding circuit under test, that is, the number of scanning input channels channel_in of the corresponding circuit under test CI j and scan the number of output channels channel_out CO j The maximum value among them, that is, Nj=max(CI j ,CO j ).

[0122] CI j The OR gates 310 correspond to the CI in the Nj groups of data distribution circuits 301. j Group data distribution circuit 301, and CI jThe OR gates 310 correspond to the CI of the circuit under test 01. j The CO in the Nj group of data distribution circuits 301 is j The group data distribution circuit 301 corresponds to the CO of the circuit under test 01 j Scan output channels channel_out. For example, the number of scan channels of the tested circuit 01 is four, and the number of scan channels is the maximum value of the number of scan input channels channel_in and the number of scan output channels channel_out. Then, the number of groups of data distribution circuits 301 in the sub-test circuit corresponding to the tested circuit 01 is four, and each group of data distribution circuits 301 may correspond to one scan input channel channel_in and one scan output channel channel_out. The number of OR gates in the sub-test circuit is the number of scan input channels channel_in, that is, three, so each OR gate 301 will also correspond to a group of data distribution circuits 301 and one scan input channel channel_in of the tested circuit 01.

[0123] In the j-th sub-test circuit, each group of data distribution circuits 301 includes M data distribution circuits 301 , and the M data distribution circuits 301 are respectively connected to an M-bit test bus.

[0124] Each group of data distribution circuits 301 in the Nj groups of data distribution circuits 301 is sequentially connected in series to the corresponding test bus through the first input terminal and the second output terminal of each data distribution circuit 301. That is, multiple data distribution circuits 301 on the same test bus 02 are sequentially connected to the same test bus 02 through the first input terminal and the second output terminal in sequence.

[0125] The first output terminals of the M data distribution circuits 301 in each group of data distribution circuits 301 are connected to the M input terminals of the corresponding OR gates 310 , and the output terminals of the OR gates 310 are connected to the corresponding scan input channels channel_in of the circuit under test 01 .

[0126] The second input terminals of the M data distribution circuits 301 in each group of data distribution circuits 301 are connected to the scan output channel channel_out of the corresponding circuit under test 01 .

[0127] Each data distribution circuit 301 is also configured to control the reset of the data distribution circuit 301. When the data distribution circuit 301 is reset, the output of the data distribution circuit 301 is zero. This can ensure that in each group of data distribution circuits 301, the output value of the OR gate 310 is the value output by the first output terminal of the selected data distribution circuit 301, that is, the value input by the input channel scanbus_in of the selected test bus 02.

[0128] In this example three, by setting an OR gate 310 between the scan input channel channel_in of the circuit under test 01 and the data distribution circuit 301 connected to the test bus, the data transmitted into the scan input channel channel_in of the circuit under test 01 is selected by the OR gate 310, so that the area overhead can be reduced as much as possible and the wiring congestion problem can be solved. In addition, by resetting the unselected data distribution circuit 301, the output value of each OR gate 310 can be the value output by the first output terminal of the selected data distribution circuit 301, thereby realizing more flexible test bus resource allocation.

[0129] Corresponds to Figure 7 In the example, in order to reset the data distribution circuit 301, a reset signal needs to be configured. Since the reset signal and the bypass enable signal dru_bp are associated signals, the reset signal and the bypass enable signal dru_bp can be shared, that is, generated through the second signal interface of the controller 303. In other words, the bypass enable signal dru_bp is output through the second signal interface of the controller 303 to configure the fifth selector 3013 in the data distribution circuit 301, set the unselected data distribution circuit 301 in the sub-test circuit to bypass, and control the reset of the register 3012 of the data distribution circuit 301, so as to meet the requirement that the scan input channel channel_in of the circuit under test 01 selects one of the data distribution circuits 301, and the configuration operation is simple.

[0130] It is worth mentioning that Figure 7 The bypass enable signal dru_bp in the example shown in is a multi-bit signal, and each data distribution circuit in each sub-test module corresponds to one bit signal of the bypass enable signal dru_bp.

[0131] Figure 8 Shows the corresponding Figure 7 A schematic diagram of the structure of the data distribution circuit 301, Figure 7 The data distribution circuit 301 shown in FIG. Figure 3 The data distribution circuit 301 shown in the figure, the second control terminal in the data distribution circuit 301 is also connected to the reset terminal of the register 3012, for controlling the register 3012 to reset. It should be noted that the reset signal and the bypass enable signal may be opposite signals. If the trigger levels of the reset signal and the bypass enable signal are opposite, the bypass enable signal can be transmitted to the control terminal of the register 301 for reset operation after performing negation operation.

[0132] Example 4, please refer to Fig. 9 ,exist Fig. 9In the circuit structure diagram in FIG. 1 , multiple sub-test circuits corresponding to multiple circuits under test 01 are provided. Figure 1 The sub-test circuits 30 shown are used to connect the corresponding circuits under test 01 to the test bus. Figure 1 The j-th sub-test circuit in the sub-test circuit 30 shown in FIG. 1 includes Nj data distribution circuits 301 and M first selectors 302. The first selectors 302 refer to FIG. Figure 2 The j-th sub-test circuit can be multiple Figure 1 The number Nj of data distribution circuits in the jth sub-test circuit is the number of scan channels of the corresponding circuit under test, that is, the number CI of scan input channels of the corresponding circuit under test. j and scan output channel CO j The maximum value among the numbers, that is, Nj=max(CI j ,CO j ).

[0133] In the jth sub-test circuit 3, the first input terminals of the Nj data distribution circuits 301 are respectively connected to the Nj input channels scanbus_in of the test bus, that is, the first input terminal of the data distribution circuit 301 is used to receive the test scan data input by the input channel scanbus_in of the test bus 02. j The first output terminals of the data distribution circuits 301 are respectively connected to the CI of the tested circuit 01 corresponding to the j-th sub-test circuit. j The first output end of the data distribution circuit 301 is connected to the scan input channel channel_in, that is, the first output end of the data distribution circuit 301 is used to transmit the test scan data received from the test bus 02 to the scan input channel channel_in of the corresponding circuit under test 01. j The second input terminals of the data distribution circuits 301 are respectively connected to the CO of the tested circuit 01 corresponding to the j-th sub-test circuit. j The second input end of the data distribution circuit 301 is connected to a scan output channel channel_out, that is, the second input end of the data distribution circuit 301 is used to receive the test result data output by the corresponding scan output channel channel_out of the tested circuit 01, and the test result data is output to the output channel scanbus_out of the test bus 02 through the second output end of the data distribution circuit 301.

[0134] Multiple Figure 1The number M of first selectors 302 in each sub-test circuit in the sub-test circuit shown is equal to the bit width of the test bus 02, and the output ends of the M first selectors 302 in each sub-test circuit are respectively connected to the M output channels scanbus_out of the test bus 02, that is, the M first selectors 302 in each sub-test circuit are respectively corresponded one by one to the M bits of the test bus 02.

[0135] The first input ends of the M first selectors 302 are respectively connected to the M input channels scanbus_in of the test bus 02. The second input ends of the Nj first selectors 302 among the M first selectors 302 are respectively connected to the second output ends of the Nj data distribution circuits 301, and the second input ends of the remaining M-Nj first selectors 302 are respectively connected to the input channels scanbus_in of the M-Nj test buses that are not provided with the data distribution circuit 301. The first input end and the second output end of each first selector 302 are connected to different buses.

[0136] In this example, Figure 1 The circuit structure of the sub-test circuit 30 shown is similar to Figure 2 The example 1 shown is different in that the first input terminals of the M first selectors 302 are all connected to the M inputs of the test bus. In the jth sub-test circuit, the first input terminal of the first selector is directly connected to the input of the test bus, so that when the circuit under test corresponding to the jth sub-test circuit does not participate in the test, the input data of the j+1th sub-test circuit does not pass through the data distribution circuit in the jth sub-test circuit, thereby reducing the test time.

[0137] In this fourth example, the test resources are allocated and transferred in the test circuit through the data distribution circuit 301, and the test resources can be dynamically allocated by configuring the first selector 302, which greatly solves the problem of wiring congestion and simplifies the configuration process.

[0138] Optionally, multiple Figure 1In the j-th sub-test circuit of the sub-test circuit 30 shown, according to the preset test bus sequence, the first input terminals of the Nj data distribution circuits 301 are sequentially connected to the input channels scanbus_in of the first Nj buses. The first input terminals of the M first selectors 302 are sequentially connected to the M inputs of the test bus. The second input terminals of the first M-Nj first selectors 302 are sequentially connected to the last M-Nj inputs of the test bus. The second input terminals of the last Nj first selectors 302 are sequentially connected to the second output terminals of the Nj data distribution circuits 301. In the above possible implementations, the data distribution circuits 301 are allocated to the bus resources according to the established rules in a preset order, so that the test circuit can simplify the circuit design and facilitate wiring while ensuring the dynamic allocation of test resources.

[0139] For an explanation of the preset test bus sequence, please refer to Figure 2 Example 1 is shown and will not be described in detail here.

[0140] It should be noted that the corresponding Fig. 9 In the example four shown, since the first input terminal of the first selector 302 is directly connected to the input scanbus_in of the bus, when the first selector 302 is configured to select the first input terminal and the output terminal to be connected, the test bus connected to the first selector 302 is actually in a direct connection state and does not pass through the data distribution circuit 301.

[0141] Corresponds to Fig. 9 Example 4 in Fig.10 Shows Fig. 9 Please refer to the structural diagram of the data distribution circuit in Fig.10 , each data distribution circuit 301 includes a fourth selector 3011 and a register 3012. The first input terminal and the second input terminal of the fourth selector 3011 are respectively connected to the first input terminal and the second input terminal of the data distribution circuit 301, and the control terminal of the fourth selector 3011 is connected to the first control terminal of the data distribution circuit 301. The input terminal of the register 3012 is connected to the output terminal of the fourth selector 3011, and the output terminal of the register 3012 is connected to the second output terminal of the data distribution circuit 301. The first output terminal of the data distribution circuit 301 is connected to the first input terminal of the data distribution circuit 301 or the output terminal of the register 3012.

[0142] In addition, the configuration of the first selector 302 can still be controlled by using the controller 303 to generate the shift selection control signal bus_shift. For details, please refer to Figure 2 Example 1 is shown and will not be described in detail here.

[0143] It should also be noted that Figure 4The schematic diagram of the structure of a gate control circuit in a test circuit provided by an embodiment of the present application is shown. The gate control circuit may correspond to Figure 2 , Figure 5 , Figure 6 , Figure 7 and Fig. 9 In order to effectively transmit data, when the data distribution circuit 301 transmits data to the scan input channel channel_in of the circuit under test 01, and when the scan output channel channel_out of the circuit under test 01 transmits data to the data distribution circuit 301, a gate circuit is provided, which are a first gate circuit 306 and a second gate circuit 307. Figure 4 As shown, the first gating circuit 306 and the second gating circuit 307 are integrated together. In an actual circuit, the first gating circuit 306 and the second gating circuit 307 can also be separated into two circuit modules.

[0144] Corresponds to Figure 2 and Figure 5 Example 1 and Fig. 9 In example 4, multiple Figure 1 In the j-th sub-test circuit of the sub-test circuit 30 shown, the data distribution circuit 301 is connected to the scan input channel channel_in of the circuit under test 01 corresponding to the j-th sub-test circuit through the first gating circuit 306, which is used to control whether the data in the data distribution circuit 301 is output to the scan input channel channel_in of the circuit under test 01 corresponding to the j-th sub-test circuit. The data distribution circuit 301 is connected to the scan output channel channel_out of the circuit under test 01 corresponding to the j-th sub-test circuit through the second gating circuit 307, which is used to control whether the data in the scan output channel channel_out of the circuit under test 01 corresponding to the j-th sub-test circuit is output to the data distribution circuit 301.

[0145] For example, in the jth sub-test circuit, the CI in the Nj data distribution circuits 301 j The first output terminals of the data distribution circuits 301 are respectively connected to the CI j The input terminal of the first gating circuit 306, CI j The output terminals of the first gating circuits 306 are respectively connected to the CI of the tested circuit 01 corresponding to the j-th sub-test circuit. j In the jth sub-test circuit, the CO of the circuit under test 01 corresponding to the jth sub-test circuit j The scan output channels channel_out are connected to CO j The input terminal of the second gating circuit 307, COj The output ends of the second gating circuits 307 are connected to the COs of the Nj data distribution circuits 301. j The second input terminal of the data distribution circuit 301.

[0146] Corresponds to Figure 6 In Example 2, in multiple Figure 1 In the j-th sub-test circuit of the sub-test circuit 30 shown, the third selector 309 is connected to the scan input channel channel_in of the circuit under test 01 corresponding to the j-th sub-test circuit through the first gating circuit 306, and is used to control whether the data in the data distribution circuit 301 is output to the scan input channel channel_in of the circuit under test 01 corresponding to the j-th sub-test circuit. The scan output channel channel_out of the circuit under test 01 corresponding to the j-th sub-test circuit is connected to the second selector 308 through the second gating circuit 307, and is used to control whether the data of the scan output channel channel_out of the circuit under test 01 corresponding to the j-th sub-test circuit is output to the data distribution circuit 301.

[0147] For example, the CO of the circuit under test 01 corresponding to the jth sub-test circuit j The scan output channels channel_out are connected to CO j The input terminal of the second gating circuit 307, CO j The output end of each of the M second gating circuits 307 is connected to the CO of each of the M second selectors 308. j Input. CI j The output terminals of the third selectors 309 are connected to the CI j The input terminal of the first gating circuit 306, CI j The output terminals of the first gating circuits 306 are respectively connected to the CI of the tested circuit 01 corresponding to the j-th sub-test circuit. j Scan input channel channel_in.

[0148] Corresponds to Figure 7 In example three, multiple Figure 1In the j-th sub-test circuit of the sub-test circuit 30 shown, the OR gate 310 is connected to the scan input channel channel_in of the circuit under test 01 corresponding to the j-th sub-test circuit through the first gating circuit 306, and is used to control whether the data in the data distribution circuit 301 is output to the scan input channel channel_in of the circuit under test 01 corresponding to the j-th sub-test circuit. The scan output channel channel_out of the circuit under test 01 corresponding to the j-th sub-test circuit is connected to the data distribution circuit 301 through the second gating circuit 307, and is used to control whether the data of the scan output channel channel_out of the circuit under test 01 corresponding to the j-th sub-test circuit is output to the data distribution circuit 301.

[0149] For example, CI j The output terminals of the OR gates 310 are connected to CI j The input terminal of the first gating circuit 306, CI j The output terminals of the first gating circuits 306 are respectively connected to the CI of the tested circuit 01 corresponding to the j-th sub-test circuit. j The CO of the tested circuit 01 corresponding to the jth sub-test circuit j The scan output channels channel_out are connected to CO j The input terminal of the second gating circuit 307, CO j The second gating circuits 307 correspond to CO j The data distribution circuits 301 are grouped together, and the second input terminal of each data distribution circuit 301 in each group of data distribution circuits 301 is connected to the output terminal of the corresponding second gating circuit 307 .

[0150] It should be understood that by setting corresponding gating circuits between the scan input channel channel_in of the circuit under test 01 and the data distribution circuit 301, and between the scan output channel channel_out of the circuit under test 01 and the data distribution circuit 301, data can be transmitted between the data distribution circuit 301 and the scan input channel channel_in of the circuit under test 01, or between the scan output channel channel_out of the circuit under test 01 and the data distribution circuit 301 only when the corresponding gating circuits are turned on, thereby avoiding the transmission of invalid data.

[0151] For example, in order to facilitate the testing of the circuit under test 01, some parameters need to be configured in the entire test process, for example, the test parameters are configured by the state machine 304, so in each Figure 1The sub-test circuit 30 shown also includes a state machine 304, where the state machine 304 is a finite state machine (FSM), and the state machine 304 may include: a first state control interface, a second state control interface, a third state control interface, and a fourth state control interface. The state machine 304 is suitable for Figure 2 , Figure 5 , Figure 6 , Figure 7 and Fig. 9 Examples described.

[0152] The first state control interface is used to generate an output capture enable signal so_cap_en and transmit the output capture enable signal so_cap_en to each state control interface. Figure 1 The first control terminal of each data distribution circuit 301 in the sub-test circuit 30 shown controls whether the data distribution circuit 301 receives the test scan data of the test bus or the scan output data of the circuit under test 01 at the current time by configuring the fourth selector 3011.

[0153] The second state control interface is used to generate a first gating enable signal ch_in_gate_en, and use the first gating enable signal ch_in_gate_en to configure the first gating circuit 306, so as to control Figure 1 Whether the test scan data of each data distribution circuit 301 in the sub-test circuit 30 is transmitted to the Figure 1 The sub-test circuit 30 shown corresponds to the scan input channel channel_in of the circuit under test 01 .

[0154] The third state control interface is used to generate a second gating enable signal ch_out_gate_en, and use the second gating enable signal ch_out_gate_en to configure the second gating circuit, thereby controlling the Figure 1 Whether the scan output data of the scan output channel channel_out of the circuit under test 01 corresponding to the sub-test circuit 30 shown is transmitted to the data distribution circuit 301 corresponding to the circuit under test 01. Figure 2 , Figure 5 , Figure 6 , Figure 7 and Fig. 9 The signal on the state machine FSM side is identified as gate_en, which may correspond to ch_in_gate_en in the first gating circuit 306 and ch_out_gate_en in the second gating circuit 307).

[0155] The fourth state control interface is used to generate a scan enable signal scan_enable and use the scan enable signal to configure the scan structure of the circuit under test 01, thereby controlling the Figure 1 The sub-test circuit 30 shown in the figure determines whether the scan structure of the circuit under test 01 corresponding to the sub-test circuit 30 performs the test scan.

[0156] The above four signals are generated by the finite state machine 304 to configure the test process of the test circuit, and the configuration is simple and easy.

[0157] Optionally, corresponding to Figure 2 , Figure 5 , Figure 6 , Figure 7 and Fig. 9 In the example, each Figure 1 The sub-test circuit 30 shown may also include a frequency dividing circuit 305, which may be a frequency divider (DIV). The frequency dividing circuit 305 is connected to the bus clock interface and the scan clock interface of the circuit under test 01, respectively, and is used to divide the clock scanbus_clk of the test bus into the scan clock scan_clock of the circuit under test 01. In the above optional solution, the high-speed scan clock of the test bus is divided into the low-speed scan clock in the circuit under test 01, which is convenient for scanning the circuit under test 01.

[0158] For example, Fig.11 A flow chart of a circuit testing method provided in an embodiment of the present application. The circuit testing method can be used to test the circuit under test in EDA software, and is suitable for use Figure 2 , Figure 5 , Figure 6 , Figure 7 and Fig. 9 Use any of the test circuits shown in to test the circuit under test.

[0159] Please refer to Fig.11 , the circuit testing method includes:

[0160] S1101, generate configuration information and test vectors. It should be understood that the configuration information and test vectors can be generated by EDA software. During the test process, the EDA software can generate configuration information and test stimulus data according to some test parameters given by the tester. The configuration information can be used to configure the test circuit; the test vector is the test stimulus data of the circuit under test and is determined by the circuit structure of the circuit under test.

[0161] S1102, configure a test circuit according to the configuration information.

[0162] Before configuring the test circuit, it is necessary to identify the circuits to be tested simultaneously. Therefore, the circuits to be tested can be grouped during testing. The principle of grouping can generally be based on the principle of shortest total test time.

[0163] When configuring a test circuit, specific configuration methods and configuration contents are different according to different test circuit structures.

[0164] For example, in the above Figure 2 and Figure 5 In the test circuit shown, the shift selection control signal bus_shift can be configured through the first signal interface of the controller 303 to control the connection relationship between the input and output selected by the first selector 302. When the circuit under test does not participate in the test, the first selector in the sub-test circuit corresponding to the circuit under test is placed in the direct connection mode, that is, the first selector 302 is configured to connect the first input terminal with the output terminal. The bypass enable signal dru_bp can be configured through the second signal interface of the controller 303 to place the data distribution circuit in the sub-test circuit corresponding to the circuit under test that does not participate in the test in the bypass state, that is, the first input terminal and the second output terminal in the corresponding data distribution circuit 301 do not pass through the register.

[0165] As above Figure 6 In the test circuit shown in FIG. 1 , the scan output selection signal so_select and the scan input selection signal si_select can be configured by the controller 303. The scan output selection signal so_select is output by the third signal interface and is used to configure the second selector 308 so as to be connected with the control circuit 303. Figure 1 The scan output channel channel_out of the circuit under test 01 corresponding to the sub-test circuit 30 is connected to a data distribution circuit 301 in the sub-test circuit 30. The scan input selection signal is output by the fourth signal interface and is used to configure the third selector 309 so that the sub-test circuit 30 selects one of the data distribution circuits 301 to be connected to the scan input channel channel_in of the circuit under test 01 corresponding to the sub-test circuit 30.

[0166] As above Figure 7 In the test circuit shown, the bypass enable signal dru_bp can be configured through the second signal interface of the controller 303. The bypass enable signal dru_bp can be used as a reset signal of the data distribution circuit. When the data distribution circuit 301 is reset, it indicates that the data distribution circuit 301 is not selected. Therefore, the value output by the first output end of the selected data distribution circuit 301 is the input value of the selected test bus 02, thereby realizing a one-to-one correspondence between the test bus 02, the data distribution circuit 301 and the scanning channel of the circuit under test 01.

[0167] As above Fig. 9 In the test circuit shown in FIG. 1 , the first signal interface of the controller 303 can be used to configure the shift selection control signal bus_shift to control the connection relationship between the input and output selected by the first selector 302. When the circuit under test does not participate in the test, the corresponding input of the circuit under test 01 is Figure 1 The first selector 302 in the sub-test circuit 30 is shown to be placed in the direct connection mode, that is, the first selector 302 is configured such that the first input terminal is connected to the output terminal.

[0168] In addition, in the above Figure 2 , Figure 5 , Figure 6 , Figure 7 and Fig. 9 In any of the test circuits shown in , the output capture enable signal so_cap_en is further configured through the first state control interface of the state machine 304, the first gating enable signal ch_in_gate_en is configured through the second state control interface of the state machine 304, the second gating enable signal ch_out_gate_en is configured through the third state control interface of the state machine 304, and the scan enable signal scan_enable is configured through the fourth state control interface of the state machine 304. For the functions of the output capture enable signal so_cap_en, the first gating enable signal ch_in_gate_en, the second gating enable signal ch_out_gate_en, and the scan enable signal scan_enable, please refer to Figure 2 The description of the state machine in the corresponding example will not be repeated here.

[0169] In addition, the frequency division ratio of the frequency division circuit 305 needs to be configured during the configuration process, wherein the frequency division ratio of the frequency division circuit 305 is determined by the number of scan input channels channel_in, the number of scan output channels channel_out of the circuit under test 01, and the bit width of the test bus 02. The frequency division ratio R of the frequency division circuit 305 is div The calculation formula is:

[0170]

[0171] Among them, CI i is the number of scan input channels of the i-th circuit under test, CO i is the number of scan output channels of the i-th circuit under test, and B is the bus width.

[0172] S1103, transmitting the test vector to the test bus, and transmitting it to the scan input channel of the circuit under test through the test circuit. The test vector is the test stimulus data of the circuit under test, and is determined by the circuit structure of the circuit under test.

[0173] The test vector is transmitted to the scan input channel of the circuit under test through the test circuit, including: according to the correspondence between the scan input channel of the circuit under test and the input of the test bus, the test vector is transmitted to the scan input channel of the circuit under test through the input of the test bus corresponding to the scan input channel of the circuit under test.

[0174] The corresponding relationship between the scan input channel channel_in of the circuit under test and the input channel scanbus_in of the test bus 02 is determined by the corresponding channel of the circuit under test 01. Figure 1 The data distribution circuit 301 in the sub-test circuit 30 is shown to determine.

[0175] For example, in the above Figure 2 and Figure 5 In the test circuit shown in the figure, the scan input channel channel_in of the circuit under test is connected to the corresponding Figure 1 The data distribution circuit 301 in the sub-test circuit 30 shown in FIG. 3 is in a one-to-one correspondence. Therefore, the correspondence between the scan input channel channel_in of the circuit under test and the input channel scanbus_in of the test bus 02 is actually the correspondence between the circuit under test 01 and the input channel scanbus_in of the test bus 02. Figure 1 The actual connection relationship between the data distribution circuit 301 in the sub-test circuit 30 and the test bus 02 is shown.

[0176] As above Figure 6 In the test circuit shown in FIG. 1 , the scan input channel channel_in of the circuit under test 01 corresponds to the circuit under test 01. Figure 1 The data distribution circuit 301 in the sub-test circuit 30 shown in the figure is in a one-to-many relationship. Therefore, the corresponding relationship between the scan input channel channel_in of the circuit under test and the input channel scanbus_in of the test bus can be configured by the scan input selection signal si_select configured by the controller 303. After the configuration, the test bus 02 connected to the data distribution circuit 301 selected by the scan input channel channel_in of the circuit under test 01 corresponds to the scan input channel channel_in of the circuit under test 01.

[0177] As above Figure 7 In the test circuit shown in FIG. 1 , the scan input channel channel_in of the circuit under test 01 corresponds to the circuit under test 01. Figure 1The data distribution circuit 301 in the sub-test circuit 30 shown is in a one-to-many relationship. Therefore, the corresponding relationship between the scan input channel channel_in of the circuit under test 01 and the input channel scanbus_in of the test bus 02 can be controlled by the bypass enable signal dru_bp. The bypass enable signal dru_bp can control the data distribution circuit 301 to reset. When the data distribution circuit 301 is not reset, the data distribution circuit 301 is selected by the corresponding scan input channel channel_in of the circuit under test 01. That is, the corresponding relationship between the scan input channel channel_in of the circuit under test 01 and the input channel scanbus_in of the test bus 02 is determined by the data distribution circuit 301 that is not reset.

[0178] S1104, the test result data of the circuit under test is transmitted to the output of the test bus through the circuit under test. Specifically, according to the correspondence between the scan output channel of the circuit under test and the output of the test bus, the test result data output by the scan output channel of the circuit under test is transmitted to the output of the test bus corresponding to the scan output channel of the circuit under test.

[0179] The corresponding relationship between the scan output channel of the circuit under test and the output channel of the test bus is determined by the data distribution circuit in the sub-test circuit corresponding to the circuit under test. The method for determining the corresponding relationship between the scan output channel channel_out of the circuit under test 01 and the output channel scanbus_out of the test bus 02 is similar to the method for determining the corresponding relationship between the scan input channel of the circuit under test and the input of the test bus in step S1103, and will not be repeated here.

[0180] It should be noted that when the test circuit tests the circuit under test, multiple circuits under test may be tested at the same time. However, the bit width of the test bus is limited, so the test bus will be multiplexed, that is, the test bus will transmit data to the scan input channels of multiple circuits under test by timing splitting. In one bus clock cycle, the test bus can only transmit data to one scan input channel or output data from one scan output channel. Therefore, if one of the inputs of the test bus needs to transmit data to multiple scan input channels channel_in, or one of the outputs needs to output data from multiple scan output channels channel_out, the transmitted data will be split and transmitted in sequence in multiple bus clock cycles. For specific examples, please refer to Fig.13 The test scenario shown.

[0181] In addition, each time the test bus transmits a cycle of scan data, a bus clock cycle is added to transmit the test vector data in the data distribution circuit to the scan input channel channel_in of the circuit under test 01, and the test result data of the scan output channel channel_out of the circuit under test 01 is transmitted to the data distribution circuit. One cycle of scan data refers to the test scan data of all the circuits under test to be tested scanned once.

[0182] For the test method of the above circuit, the following Figure 2 The test circuit shown is used as an example. Figure 2 In the example shown, it is assumed that the circuit under test A (core_A) and the circuit under test C (core_C) are scan tested at the same time, while the circuit under test B (core_B) is not tested temporarily. Since the circuit under test B is not tested, the first selector 302 in the sub-test circuit corresponding to the circuit under test B is configured to be in a direct connection state through the shift selection control signal bus_shift, that is, the shift selection control signal bus_shift is set to 0 in this example, and the bypass enable signal dru_bp for controlling the bypass of the data distribution circuit 301 in the sub-test circuit corresponding to the circuit under test B is set to 0, so that the first input terminal and the second output terminal of the data distribution circuit 301 are directly connected.

[0183] Table 1

[0184]

[0185] Please refer to Fig.12 The test scheme shown, Fig.12 In this embodiment Figure 2 A schematic diagram of the structure of a corresponding test solution. Fig.12 In the test bus resource allocation shown in , when the scan test is performed on the circuits under test A and C at the same time, and the circuit under test B is not tested temporarily, please refer to Table 1 for the corresponding relationship between the test bus 02 and the scan channel of the circuit under test 01.

[0186] According to the corresponding relationship between the test bus 02 and the scan channel of the circuit under test 01 in Table 1, the test vector is transmitted to the scan input channel of the circuit under test through the input channel scanbus_in of the test bus, and the test result data is transmitted from the scan output channel of the circuit under test to the output channel scanbus_out of the test bus. Since each input or output of the test bus corresponds to only one scan channel of the circuit under test, the test vector and the test result data can be transmitted in one cycle.

[0187] exist Figure 2In the example shown, it is assumed that the circuit under test A (core_A), the circuit under test B (core_B), and the circuit under test C (core_C) are tested at the same time. Fig.13 The test scheme shown, Fig.13 In this embodiment Figure 2 A schematic diagram of the structure of another corresponding test scheme.

[0188] In this example, the bus width of the test bus 02 is 8 bits, the circuit under test A has 3 scan channels, the circuit under test B has 5 scan channels, and the circuit under test C has 4 scan channels, where the number of scan channels is the maximum value of the number of scan input channels and the number of scan output channels of the circuit under test. Therefore, for the allocation of the test bus, the circuit under test A needs to allocate 3 bits of input and output of the test bus, and the circuit under test B needs to allocate 5 bits of input and output of the test bus, that is, the circuit under test A and the circuit under test B have occupied all the resources of the test bus. For the circuit under test C, the test bus can only be reused, and the test vector input data and the test result data are input or output in two different clock cycles. In this test scheme, please refer to Table 2 for the correspondence between the scan input channels of the test bus 02 and the circuit under test 01, where channel[x] in Table 2 can represent Figure 2 In channel_in[x] or channel_out[x], x is an integer representing the number of bits. For example, when the test vector input data is transmitted, channel[x] in Table 2 represents channel_in[x]; when the test result data is transmitted, channel[x] in Table 2 represents channel_out[x].

[0189] Table 2

[0190] input Cycle1 Cycle2 output scanbus_in[0] core_C.channel[0] core_A.channel[0] scanbus_out[4] scanbus_in[1] core_C.channel[1] core_A.channel[1] scanbus_out[5] scanbus_in[2] core_C.channel[2] core_A.channel[2] scanbus_out[6] scanbus_in[3] core_C.channel[3] core_B.channel[0] scanbus_out[7] scanbus_in[4] / core_B.channel[1] scanbus_out[0] scanbus_in[5] / core_B.channel[2] scanbus_out[1] scanbus_in[6] / core_B.channel[3] scanbus_out[2] scanbus_in[7] / core_B.channel[4] scanbus_out[3]

[0191] exist Fig.13 In the test scheme shown above, Fig.15 The test method shown is used for testing, and the final test waveform is as follows Fig.14 shown.

[0192] It should be noted that the above Fig.13The test scheme shown is only an example. When the actual circuit under test is tested, the number of scan channels of one of the circuits under test may exceed the bit width of the test bus. In this case, the number of scan input channels channel_in of the circuit under test 01 corresponding to an input channel scanbus_in of the test bus 02 may exceed one, and the number of scan input channels channel_out of the circuit under test 01 corresponding to an output channel scanbus_out of the test bus 02 may also exceed one. In this case, it is also necessary to transmit data in multiple bus clock cycles through timing splitting.

[0193] For example, Fig.15 A flowchart of a method for designing a test circuit is provided for an embodiment of the present application.

[0194] Please refer to Fig.15 , the design method of the test circuit includes:

[0195] S1501, obtaining the number of scan input channels, the number of scan output channels, and the bus width of the test bus of each circuit under test.

[0196] S1502, according to the bus width of the test bus, and the number of scan input channels and scan output channels of each circuit under test, configure the data distribution circuit in the sub-test circuit corresponding to each circuit under test on the test bus to generate the above Figure 2 , Figure 5 , Figure 6 , Figure 7 and Fig. 9 Any of the test circuits shown in .

[0197] The number of data distribution circuits in the sub-test circuit corresponding to each circuit under test is determined by the bus width of the test bus, or the number of scan input channels and scan output channels of each circuit under test.

[0198] exist Figure 2 and Figure 5 In the example, each circuit under test 01 corresponds to Figure 1 The number of data distribution circuits 301 in the sub-test circuit 30 shown is associated with the number of scan input channels channel_in and scan output channels channel_out in the circuit under test 01, that is, equal to the maximum value of the number of scan input channels channel_in and the number of scan output channels channel_out in the corresponding circuit under test.

[0199] The embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-readable instructions, and when a computer reads and executes the computer-readable instructions, the computer executes the above-mentioned Fig.11 The circuit testing method in the method embodiment shown.

[0200] The present application also provides a computer program product. When a computer reads and executes the computer program product, the computer executes the above-mentioned Fig.11 The circuit testing method in the method embodiment shown.

[0201] It should be understood that the processor in the embodiments of the present application may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0202] It should also be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0203] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0204] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A test circuit, It is characterized in that include: A plurality of sub-test circuits corresponding to the plurality of circuits under test, respectively, the plurality of sub-test circuits being used to respectively connect the corresponding circuits under test to the test bus; The j-th sub-test circuit of the plurality of sub-test circuits comprises Nj data distribution circuits and M first selectors, wherein Nj and M are both positive integers, M is equal to the bit width of the test bus, and M is greater than or equal to Nj; The j-th sub-test circuit is any sub-test circuit among the multiple sub-test circuits; In the j-th sub-test circuit, the first input terminals of the Nj data distribution circuits are respectively connected to the Nj inputs of the test bus, the first output terminals of the Nj data distribution circuits are connected to the scan input channels of the circuit under test corresponding to the j-th sub-test circuit, and the second input terminals of the Nj data distribution circuits are connected to the scan output channels of the circuit under test corresponding to the j-th sub-test circuit; In the j-th sub-test circuit, the output ends of the M first selectors are respectively connected to the M outputs of the test bus; The first input ends of Nj of the M first selectors are respectively connected to the second output ends of the Nj data distribution circuits, and the first input ends of the remaining M-Nj first selectors are respectively connected to the inputs of the M-Nj test buses that are not provided with the data distribution circuits; The second input ends of Nj of the M first selectors are respectively connected to the second output ends of the Nj data distribution circuits, and the second input ends of the remaining M-Nj first selectors are respectively connected to the inputs of the M-Nj test buses that are not provided with the data distribution circuits; The first input terminal and the second input terminal of each of the first selectors are connected to different test buses.

2. The test circuit according to claim 1, It is characterized in that In the jth sub-test circuit of the plurality of sub-test circuits, the first input ends of the Nj data distribution circuits are sequentially connected to the inputs of the first Nj test buses according to a preset test bus sequence; The first input ends of the first Nj selectors are connected in sequence to the second output ends of the Nj data distribution circuits; the first input ends of the last M-Nj selectors are connected in sequence to the last M-Nj inputs of the test bus; The second input ends of the first M-Nj first selectors are connected in sequence to the last M-Nj inputs of the test bus; the second input ends of the last Nj first selectors are connected in sequence to the second output ends of the Nj data distribution circuits.

3. The test circuit according to claim 2, It is characterized in that The preset test bus sequence is the order or reverse order of the test bus bit sequence.

4. The test circuit according to any one of claims 1 to 3, It is characterized in that The CI of the Nj data distribution circuits j The first output terminals of the data distribution circuits are respectively connected to the CI of the circuit under test corresponding to the j-th sub-test circuit. j The Nj scan input channels are connected, and the CO of the Nj data distribution circuits j The second input terminals of the data distribution circuits are respectively connected to the CO of the circuit under test corresponding to the j-th sub-test circuit. j Scan output channel connection; where Nj = Max (CI j ,CO j ).

5. The test circuit according to any one of claims 1 to 4, It is characterized in that Each of the data distribution circuits includes a fourth selector, a register, and a fifth selector; The first input terminal and the second input terminal of the fourth selector are connected to the first input terminal and the second input terminal of the data distribution circuit respectively; The input end of the register is connected to the output end of the fourth selector, and the output end of the register is connected to the first input end of the fifth selector; The second input terminal of the fifth selector is connected to the first input terminal of the data distribution circuit, and the output terminal of the fifth selector is connected to the second output terminal of the data distribution circuit; The first output end of the data distribution circuit is connected to the first input end of the data distribution circuit or the output end of the register or the second output end of the data distribution circuit.

6. The test circuit according to claim 5, It is characterized in that Each of the sub-test circuits further includes a controller, wherein the controller includes: A first signal interface, used to control the first input end and the output end of the first selector to be connected, or the second input end and the output end of the first selector to be connected; The second signal interface is used to control the first input terminal and the second output terminal of the data distribution circuit to be directly connected or connected through the register.

7. The test circuit according to any one of claims 1 to 6, It is characterized in that In a j-th sub-test circuit of the plurality of sub-test circuits, the data distribution circuit is connected to a scan input channel of the circuit under test corresponding to the j-th sub-test circuit through a first gating circuit, and is used to control whether data in the data distribution circuit is output to the scan input channel of the circuit under test corresponding to the j-th sub-test circuit; The data distribution circuit is connected to the scan output channel of the circuit under test corresponding to the jth sub-test circuit through a second gating circuit, and is used to control whether the data of the scan output channel of the circuit under test corresponding to the jth sub-test circuit is output to the data distribution circuit.

8. The test circuit according to claim 7, It is characterized in that Each of the sub-test circuits further includes a state machine, wherein the state machine includes: A first state control interface, used to generate an output capture enable signal to control whether each of the data distribution circuits in the sub-test circuit receives scan output data of the circuit under test; A second state control interface, used to generate a first gating enable signal to control whether the data of each of the data distribution circuits in the sub-test circuit is transmitted to a scan input channel of the circuit under test corresponding to the sub-test circuit; A third state control interface, used to generate a second gating enable signal to control whether the data of the scan output channel of the circuit under test corresponding to the sub-test circuit is transmitted to the data distribution circuit in the circuit under test; The fourth state control interface is used to generate a scan enable signal for controlling whether the scan structure of the circuit under test corresponding to the sub-test circuit performs a test scan.

9. The test circuit according to any one of claims 1 to 8, It is characterized in that The test circuit is arranged inside or outside the circuit under test.

10. The test circuit according to any one of claims 1 to 9, It is characterized in that Each of the sub-test circuits further comprises a frequency dividing circuit, which is respectively connected to a bus clock interface and a scan clock interface of the circuit under test and is used for dividing the clock of the test bus into a scan clock of the circuit under test.

11. An integrated circuit, It is characterized in that include: A plurality of circuits under test, a test bus, and a test circuit as claimed in any one of claims 1 to 10; The multiple circuits under test are connected to a test bus through multiple sub-test circuits in the test circuit corresponding to the circuits under test.

12. An electronic device, Features: It comprises a printed circuit board and the integrated circuit as claimed in claim 11; the integrated circuit is arranged on the printed circuit board.

13. A circuit testing method, It is characterized in that Suitable for testing a circuit under test using a test circuit, wherein the test circuit is a test circuit as claimed in any one of claims 1 to 10; The method comprises: Generate configuration information and test vectors; The configuration information is used to configure the test circuit; the test vector is the test stimulus data of the circuit under test and is determined by the circuit structure of the circuit under test.

14. The circuit testing method according to claim 13, It is characterized in that The method further comprises: According to the configuration information, configure the test circuit; Transmitting the test vector to a test bus, and transmitting the test vector to a scan input channel of the circuit under test through the test circuit; The test result data of the circuit under test is transmitted to the output of the test bus through the circuit under test.

15. The circuit testing method according to claim 14, It is characterized in that The step of transmitting the test vector to a test bus and transmitting the test vector to a scan input channel of the circuit under test through the test circuit comprises: According to the correspondence between the scan input channel of the circuit under test and the input of the test bus, the test vector is transmitted to the scan input channel of the circuit under test through the input of the test bus corresponding to the scan input channel of the circuit under test; The corresponding relationship between the scan input channel of the circuit under test and the input of the test bus is determined by the data distribution circuit in the sub-test circuit corresponding to the circuit under test.

16. The circuit testing method according to claim 14, It is characterized in that The step of transmitting the test result data of the circuit under test to the output of the test bus through the circuit under test includes: According to the correspondence between the scan output channel of the circuit under test and the output of the test bus, the test result data output by the scan output channel of the circuit under test is transmitted to the output of the test bus corresponding to the scan output channel of the circuit under test; The corresponding relationship between the scan output channel of the circuit under test and the output of the test bus is determined by a data distribution circuit in a sub-test circuit corresponding to the circuit under test.

17. The circuit testing method according to claim 15, It is characterized in that The step of transmitting the test vector to the scan input channel of the circuit under test through the input of the test bus corresponding to the scan input channel of the circuit under test according to the correspondence between the scan input channel of the circuit under test and the input of the test bus comprises: The test bus transmits the test vector to the scan input channel of the circuit under test in sequence during multiple bus clock cycles; wherein the number of scan input channels of the circuit under test corresponding to one of the inputs of the test bus exceeds one.

18. The circuit testing method according to claim 16, It is characterized in that The step of transmitting the test result data output by the scan output channel of the circuit under test to the output of the test bus corresponding to the scan output channel of the circuit under test according to the correspondence between the scan output channel of the circuit under test and the output of the test bus comprises: The test bus transmits the test result data in the scan output channel of the circuit under test to the output of the test bus in sequence during multiple clock cycles, wherein the number of scan output channels of the circuit under test corresponding to one of the outputs of the test bus exceeds one.

19. A computer-readable storage medium, It is characterized in that The computer-readable storage medium includes a program or an instruction. When the program or the instruction is executed on a computer, the computer is caused to execute the circuit testing method according to any one of claims 13 to 18.

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