A multi-matrix node bus topology based on a RISC-V instruction set and a working method thereof

Abstract

The application relates to a multi-matrix node bus topology based on a RISC-V instruction set and a working method thereof, which comprises a high-speed bus matrix node, a plurality of slow-speed bus matrix nodes and a plurality of low-speed bus matrix nodes; each matrix node controls power consumption forming efficiency difference through different widths, different working frequencies or different working voltages of bus channels, a multi-stage working voltage mode is designed to meet the working mode of the same kind of matrix node under different voltages or different working frequencies, the matrix nodes of the same stage can also be connected with each other, and normal communication and working states are maintained. Meanwhile, the application designs internal nodes of each matrix node, decides access authority according to different channels in the matrix nodes, and provides a DMAP working mode under an extremely low power consumption mode, so that the nodes without CORE can also perform data interaction of peripherals.

Description

Technical Field

[0001] This invention relates to a multi-matrix node bus topology based on the RISC-V instruction set and its working method, belonging to the field of integrated circuit processor hierarchical design technology. Background Technology

[0002] Over the years, with the advancement of chip design technology and the wide range of applications, RISC-V has demonstrated more and more advantages that traditional ARM and x86 architectures lack, such as complete open source and simple architecture. RISC-V is now widely used, but because the official RISC-V documentation only provides the TILELINK bus protocol, its market compatibility is currently not good.

[0003] At the same time, the system bus of SoC is becoming increasingly diversified. Traditional system buses can no longer meet the ever-changing SoC designs. Due to the inconsistency of the core bus interfaces of various CPUs, lower-performance processors are used to drive complex SoCs, resulting in a mismatch between SoC performance and core performance, causing various problems. To solve this problem, the number of cores is often increased to drive the entire SoC. However, this method involves extremely complex consistency checks in the complex on-chip network composed of cores and various core clusters. In addition, the number of parallel bus channels can be increased by modifying the bus interface within the core. However, this method cannot modify the bus interface if the CORE IP provider provides hard IP or fixed IP. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a multi-matrix node bus topology based on the RISC-V instruction set, solving the bus protocol compatibility problem of RISC-V on mid-to-high-end processors;

[0005] This invention also provides a method for operating the above-described hardware architecture;

[0006] This invention utilizes a RISC-V-based instruction set kernel; this invention consists of three types of matrix nodes, namely a high-speed bus matrix node, a medium-speed bus matrix node, and a low-speed bus matrix node. Each matrix node can control power consumption and form efficiency differences by using different bus channel widths, different operating frequencies, or different operating voltages.

[0007] Terminology Explanation:

[0008] 1. DMAP: Direct Memory Access for Peripherals, a type of DMA that operates on low-speed nodes. In addition to performing normal DMA functions (i.e., three paths: memory to peripheral, peripheral to memory, and memory to memory), it can also perform data conversion from peripheral to peripheral.

[0009] 2. Master end: The end that issues commands when two devices interact with each other.

[0010] 3. Slave end: The end that receives instructions when two devices interact with each other.

[0011] 4. DMA: Direct memory access, an off-core unit that can operate on all nodes and is used to move data.

[0012] 5. CORE: The computing unit that can work in MSMN and HSMN, the core unit for processing data in a node.

[0013] 6. MATRIX: A communication matrix formed by the interaction between the master and slave ends. Each point that can access the intersection of the master and slave ends is called an internal node.

[0014] 7. FLASH: Flash memory, which in this invention can be configured as NOR flash or NAND flash, a non-volatile storage unit.

[0015] 8. SRAM: Static Random Access Memory, a type of volatile memory.

[0016] 9. LOW SPEED BUS: Low-speed bus, generally used to connect peripherals.

[0017] 10. BRIDGE: Buses of different speeds must be connected via a bridge for address allocation and chip select.

[0018] The technical solution of this invention is as follows:

[0019] A multi-matrix node bus topology based on the RISC-V instruction set includes a high-speed bus matrix node, multiple slow-speed bus matrix nodes, and multiple low-speed bus matrix nodes.

[0020] Each matrix node controls power consumption to create efficiency differences by using different bus channel widths, operating frequencies, or operating voltages, while maintaining the correct node communication direction.

[0021] According to a preferred embodiment of the present invention, in the low-speed bus matrix node, DMAP and other slow bus matrix nodes or high-speed bus matrix nodes serve as the master end of the low-speed bus matrix node. In addition, control signals from the high-speed bus matrix node need to reach the low-speed bus matrix node through a BRIDGE. The low-speed bus matrix node and a SRAM of less than 128KB serve as the slave end of the low-speed bus matrix node. The small-capacity SRAM is configured with its own independent operating voltage domain, and can still maintain normal operation and store data from peripherals after the voltage domain of the low-speed bus matrix node is turned off.

[0022] According to a preferred embodiment of the present invention, in the slow bus matrix node, the DMA, the configurable core, and the control signals issued by the high-speed bus matrix node serve as the master of the slow bus matrix node; the control signals from the high-speed bus matrix node need to reach the slow bus matrix node through a BRIDGE; and the peripherals serve as the slaves of the slow bus matrix node.

[0023] According to a preferred embodiment of the present invention, in a high-speed bus matrix node, a high-performance core, DMA, and other configurable accelerators serve as the master device of the high-speed bus matrix node; in the case where the slow bus matrix node has an independent core but no FLASH storage for the bootloader, a slave device of the high-speed bus matrix node is configured to store the boot program of the slow bus matrix node. After the SoC starts working, the DMA is controlled by the program of the high-performance core to move the boot program of the slow bus matrix node to the SRAM or other storage unit of the slow bus matrix node.

[0024] According to a preferred embodiment of the present invention, the entire SoC is divided into three voltage domains: a main domain, a backup domain, and an analog voltage domain. Each matrix node operates in a main domain and works independently through different power gating. Alternatively, all matrix nodes operate in different main domains, with frequency differences created by voltage, so that the same type of matrix nodes have different operating frequencies to meet the diversity of low power consumption.

[0025] According to a preferred embodiment of the present invention, a unidirectional instruction filter is added to the bridge between the high-speed bus matrix node and the slow bus matrix node.

[0026] According to a preferred embodiment of the present invention, the high-speed bus matrix node communicates with each slow bus matrix node and each low-speed bus matrix node, and follows the principle of instruction filtering when transferring instructions;

[0027] The high-speed bus matrix node serves as the master terminal for the slow-speed bus matrix node and the low-speed bus matrix node.

[0028] In the slack bus matrix node, slack bus matrix nodes of the same level are connected to ensure that different slack bus matrix nodes have a master frequency difference. The slack bus matrix node with the higher operating frequency is used as the master end of the two slack bus matrix nodes, and the slack bus matrix node with the lower operating frequency is used as the slave end of the two slack bus matrix nodes.

[0029] When a slow bus matrix node is connected to a high-speed bus matrix node, the slow bus matrix node acts as a slave; when a slow bus matrix node is connected to a low-speed bus matrix node, and when interacting with low-speed bus matrix nodes of the same frequency or lower, the slow bus matrix node acts as a master.

[0030] In a low-speed bus matrix node, when a low-speed bus matrix node is connected to a slow-speed bus matrix node of the same or higher frequency, the low-speed bus matrix node acts as the slave end of the slow-speed bus matrix node of the same or higher frequency; when a low-speed bus matrix node is connected to a high-speed bus matrix node, the higher-frequency matrix node acts as the master end and the lower-frequency matrix node acts as the slave end.

[0031] According to a preferred embodiment of the present invention, in the slow bus matrix node, the control signals issued by the high-speed bus matrix node, the three sets of buses of two DMAs and one CORE serve as the master end of the MATRIX, and FLASH, SRAM, LOW SPEED BUS and BRIDGE serve as the slave end of the MATRIX. Each master end is configured with the corresponding slave end access permissions. On the channel without node access, two or more sets of channels operate synchronously.

[0032] The above-described working method for the multi-matrix node bus topology based on the RISC-V instruction set includes the following steps:

[0033] Each matrix node operates independently in a different voltage domain. Each matrix node refers to any one of the high-speed bus matrix node, slow-speed bus matrix node, and low-speed bus matrix node.

[0034] Initially, for each matrix node with FLASH, the Bootloader in the FLASH is read out. For matrix nodes without FLASH, the data in the matrix node with FLASH is transferred to the matrix node without FLASH via DMA or CORE. After all matrix nodes are working, the data exchanged is also transferred to the matrix node with FLASH via DMA or CORE.

[0035] Before the voltage of each matrix node is turned off, the algorithm needs to delay for several cycles to wait for the data processing in the matrix node to be completed before turning off the voltage domain through the voltage switch. For those that can transfer data to other matrix nodes for execution, the voltage domain is turned off through the voltage switch after the data is transferred to other nodes.

[0036] The beneficial effects of this invention are as follows:

[0037] 1. This invention designs three types of matrix nodes to meet the power consumption performance ratio under different conditions. Since each matrix node can work independently, the power consumption requirement is determined only based on the current performance requirements, which is a typical design method that trades area for power consumption.

[0038] 2. This invention designs multiple operating voltage modes to meet the operating modes of the same matrix node at different voltages or operating frequencies, allowing matrix nodes at the same level to connect to each other and maintain normal communication and operation.

[0039] 3. This invention designs internal nodes for each matrix node, and determines access permissions based on different paths within the matrix node. It also provides a DMAP working mode in extremely low power mode, enabling data interaction with peripherals even in nodes without a core.

[0040] 4. This paper proposes two design methods to ensure data consistency without the need for a second-level cache. One method is to use instruction filtering to ensure that the input instructions of each matrix node can be executed and recognized by the kernel of the matrix node. The other method is to set up an independent storage space for each matrix node and provide cross-node memory protection.

[0041] 5. By combining the above points, this invention designs a brand-new bus topology. This topology consists of the three types of nodes mentioned above. Nodes (except HSMN) can operate in up to three different voltage domains, thus forming up to seven data nodes. The relationship between data nodes is divided into absolutely link and possible link. An absolutely link is a node relationship that can definitely be accessed, while a possible link is a node relationship that is not recommended to be the starting point of a possible link as the master. Attached Figure Description

[0042] Figure 1 This invention presents a schematic diagram of the multi-matrix node bus topology based on the RISC-V instruction set, its working method, the connection relationships between nodes, and the classification of node types.

[0043] Figure 2 This is a schematic diagram of a five-node, three-core SoC designed using a bus topology according to the present invention. Detailed Implementation

[0044] The present invention will be further defined below with reference to the accompanying drawings and embodiments, but is not limited thereto.

[0045] Example 1

[0046] A multi-matrix node bus topology based on the RISC-V instruction set includes a high-speed bus matrix node, multiple slow-speed bus matrix nodes, and multiple low-speed bus matrix nodes.

[0047] Each matrix node uses a different bus channel width, operating frequency, or operating voltage. This is achieved through a voltage controller or frequency divider to control power consumption and create efficiency differences, while maintaining the correct node communication direction.

[0048] Example 2

[0049] The difference between the multi-matrix node bus topology based on the RISC-V instruction set described in Example 1 and the one described in Example 1 is as follows:

[0050] In a low-speed bus matrix node, DMAP and other slow-speed or high-speed bus matrix nodes serve as the master of the low-speed bus matrix node. In addition, control signals from the high-speed bus matrix node need to reach the low-speed bus matrix node through a BRIDGE. The low-speed bus matrix node and a SRAM of less than 128KB serve as the slave of the low-speed bus matrix node. The smaller SRAM is configured with its own independent operating voltage domain, and can still maintain normal operation and store data from peripherals after the voltage domain of the low-speed bus matrix node is turned off.

[0051] In a slow bus matrix node, the DMA, configurable core, and control signals from the high-speed bus matrix node serve as the master of the slow bus matrix node; control signals from the high-speed bus matrix node need to reach the slow bus matrix node through a BRIDGE; peripherals such as common FLASH and SRAM serve as slaves of the slow bus matrix node.

[0052] In a high-speed bus matrix node, a high-performance core, DMA, and other configurable accelerators act as the master device. In a slow bus matrix node, which has an independent core but no FLASH storage for the bootloader, a slave device is configured on the high-speed bus matrix node to store the slow bus matrix node's boot program. After the SoC begins operation, the high-performance core's program controls the DMA to move the slow bus matrix node's boot program to the slow bus matrix node's SRAM or other storage units. Typically, a system has only one high-speed bus matrix node, and the high-speed bus matrix node uses more data channels than the slow and low-speed matrix nodes.

[0053] Example 3

[0054] The difference between the multi-matrix node bus topology based on the RISC-V instruction set described in Embodiment 1 or 2 is as follows:

[0055] The voltage control unit and voltage domain division: the entire SoC is divided into three voltage domains: the primary domain, the backup domain, and the analog voltage domain. Each matrix node operates in a primary domain, functioning independently through different power gating. Alternatively, all matrix nodes can operate in different primary domains, with frequency differences created by voltage, allowing similar matrix nodes to have different operating frequencies to meet low-power versatility requirements. Analog circuits such as ADCs and DACs operate in the analog voltage domain, while some peripherals operate in the backup domain, which can be controlled without power gating.

[0056] Data consistency issues across different matrix nodes: Since the entire system may have multiple cores operating concurrently, data conflicts are possible. The system design does not employ multi-level caching to resolve data consistency conflicts, primarily because caching involves extremely complex cross-clock domain signal processing and cache consistency checks under various operating voltage conditions. However, to address potential data conflicts in the system, this invention employs the following method:

[0057] By using unidirectional RISC-V instruction filtering, since a separate core can be configured in the MSMN without configuring a corresponding bootloader FLASH, the boot program in the HSMN needs to be moved to the MSMN via DMA. However, because the instruction sets of the two nodes may not be compatible, it is easy to accidentally move instructions that should be executed by the HSMN but cannot be recognized by the MSMN to the MSMN's memory. To solve this problem, since communication between the MSMN and HSMN must be through a set of bridges, a unidirectional instruction filter is added to the bridge between the high-speed bus matrix node and the slow-speed bus matrix node. If a program operation error sends an unexecutable instruction to the MSMN through the bridge, the original data will remain unchanged, and a brief interrupt instruction will be issued, with the next address of this instruction as the interrupt vector for this interrupt signal.

[0058] The high-speed bus matrix node communicates with each slow bus matrix node and each low-speed bus matrix node, and follows the principle of instruction filtering when transferring instructions;

[0059] The high-speed bus matrix node serves as the master terminal for the slow-speed bus matrix node and the low-speed bus matrix node.

[0060] In the sluggish bus matrix node, sluggish bus matrix nodes of the same level are connected to ensure that different sluggish bus matrix nodes have a certain master frequency difference (distributed through voltage and frequency adjustment units). The sluggish bus matrix node with the higher operating frequency is used as the master end of the two sluggish bus matrix nodes, and the sluggish bus matrix node with the lower operating frequency is used as the slave end of the two sluggish bus matrix nodes.

[0061] When a slow bus matrix node is connected to a high-speed bus matrix node, the slow bus matrix node acts as a slave. When a slow bus matrix node is connected to a low-speed bus matrix node, and when interacting with a low-speed bus matrix node of the same frequency or lower, the slow bus matrix node acts as a master. When connected to a high-frequency LSMN, the LSMN needs to be down-clocked or down-voltaged, otherwise data conflicts may easily occur.

[0062] In a low-speed bus matrix node, when a low-speed bus matrix node is connected to a slow-speed bus matrix node of the same or higher frequency, the low-speed bus matrix node acts as a slave of the slow-speed bus matrix node of the same or higher frequency. When a low-speed bus matrix node is connected to a high-speed bus matrix node, the higher-frequency matrix node acts as the master and the lower-frequency matrix node acts as the slave. Continuing this design method reduces the likelihood of data conflicts and not only maintains control under various low-power conditions but also preserves the rationality of the design.

[0063] Each matrix node contains several sets of internal nodes. Each internal node represents whether the master can access the corresponding node's slave. In the slow bus matrix node, control signals are issued by the high-speed bus matrix node. The three buses—two DMAs (DMA1 and DMA2) and one CORE—serve as the master of the MATRIX. FLASH, SRAM, LOW SPEED BUS, and BRIDGE serve as the slaves of the MATRIX. Each master is configured with the corresponding slave's access permissions. On channels without node access, two or more channels can operate synchronously. For example, while DMA1 is accessing FLASH, DMA2, which has no internal node conflicts, can also access SRAM but cannot access FLASH.

[0064] Each of the three types of matrix nodes has its own independent storage space. High-speed bus matrix nodes and slow bus matrix nodes execute their own separate boot programs. However, the SoC allows cross-node data interaction. The DMA of high-speed bus matrix nodes and slow bus matrix nodes is only a memory-to-memory transfer type. Data can only be transferred when the nodes inside the matrix are not occupied. When a matrix node is occupied, it is necessary to wait for the node occupation time to end, or to forcibly interrupt the nodes inside the matrix through an interrupt program.

[0065] Figure 1This is a schematic diagram of the proposed multi-matrix node bus topology based on the RISC-V instruction set, its working method, the connection relationship between nodes, and the classification of node types. Figure 1 Seven types of matrix nodes are listed, with the top to bottom representing different types of matrix nodes and the left to right representing different operating voltage ranges. Voltage or frequency ranges are divided by solid and dashed lines. The types of matrix nodes are... Figure 1 In the naming convention, the arrows between matrix nodes indicate the connection direction between the master and slave ends. Solid lines represent accessible matrix nodes, while dashed lines represent matrix nodes that require frequency or voltage reduction before access. Figure 1 The circuit shown is the actual circuit architecture after the matrix nodes are amplified.

[0066] Example 4

[0067] The working method of any of the multi-matrix node bus topologies based on the RISC-V instruction set described in Examples 1-3 includes the following steps:

[0068] Each matrix node operates independently in a different voltage domain. Each matrix node refers to any one of the high-speed bus matrix node, slow-speed bus matrix node, and low-speed bus matrix node.

[0069] Initially, for each matrix node with FLASH, the bootloader in the FLASH is read out. For matrix nodes without FLASH, the data in the matrix node with FLASH is transferred to the matrix node without FLASH via DMA or CORE. After all matrix nodes are working, the data exchanged is also transferred to the matrix node with FLASH via DMA or CORE.

[0070] Since each matrix node can be turned off independently, before turning off the voltage of each matrix node, an algorithm needs to delay for several cycles to wait for the data processing in the matrix node to be completed before turning off the voltage domain through a voltage switch. For operations where data can be moved to other matrix nodes for execution, the voltage domain is turned off through a voltage switch after the data is moved to the other node. For example, when moving data from a slow bus matrix node to a high-speed bus matrix node, the internal voltage domain is turned off in batches. First, the instructions and data in the cache are moved to SRAM or FLASH, then the voltage of the CORE in the slow bus matrix node is turned off. After the executable instructions are transferred to the high-speed bus matrix node, the storage voltage is turned off.

[0071] Example 5

[0072] The difference between the working method of the multi-matrix node bus topology based on the RISC-V instruction set described in Example 4 and the following is:

[0073] For ease of explanation, Figure 2 This is a schematic diagram of a five-node, three-core SoC designed using a bus topology; it includes one high-speed bus matrix node operating in the high-frequency domain, two slow-speed bus matrix nodes operating in the mid- and high-frequency domains respectively, and two low-speed bus matrix nodes operating in the mid- and high-frequency domains respectively. Figure 2 All matrix nodes were renamed: the high-speed bus matrix node was renamed Node 1, and the two slow-speed bus matrix nodes operating in the high and mid-frequency domains respectively were renamed Node 2 and Node 3. Figure 2 The three matrices at the top, from left to right, are named Node 1, Node 2, and Node 3. The last two low-speed bus matrix nodes, operating in the high and mid-frequency domains, are named Node 4 and Node 5. Figure 2 The two below, from left to right, are node 4 and node 5;

[0074] Let me briefly introduce the composition of each node. Node 1 consists of a high-performance core and a DMA with more than 11 channels as the master, two FLASH (and the FLASH controller), one SRAM, and a BRIDGE connecting to one of the slow bus matrix nodes and one of the low-speed bus matrix nodes (the other slow bus matrix node has its own flash, and this path is not designed in the overall SoC design, otherwise the connection may cause timing violations due to excessive length). The two slow bus matrix nodes are basically the same, both consisting of a high-node access signal, two 7 or 5-channel DMA, and a CORE as the master of the node. The slave end is designed to connect to the memory unit and the low-speed bus connecting the peripherals. The two low-speed bus matrix nodes are also basically the same, but the slave end of the low-speed bus matrix node does not have a memory unit, but only two sets of low-speed neutral lines connecting the peripherals.

[0075] A complete set of full-node collaborative working modes, showing how each node works;

[0076] Node 1 and Node 3 simultaneously move the instructions stored in their respective matrix FLASH to the instruction coupled memory unit or cache in the core. After the core of Node 1 receives the instruction to move the data of another FLASH to Node 2, it issues a command to the DMA of the same node.

[0077] Since there is no internal node conflict at this time, the DMA moves the data from another FLASH to the storage unit in node 2 (in this cross-frequency transfer method, since the write rate is higher than the read rate, the write operation in the dual-port memory of node 2 does not occupy the access node). At the same time, nodes 1 and 3 still execute their respective instructions normally. Node 3 receives an instruction to access the data of node 5, and node 2 receives an instruction to access the same peripheral of nodes 4 and 5 in sequence. In this case, multiple master access may occur in node 5, causing arbitration.

[0078] Node 2 can access Node 4 normally since there is no arbitration. Node 5 is accessed by both Node 2 and Node 3 at the same time, which triggers arbitration. The arbitration algorithm here is a normal round-robin arbitration, which starts from the high-frequency domain. Therefore, Node 2 has priority to access Node 5.

[0079] While Node 1's DMA is still transferring instructions to Node 2, a RISC-V instruction filter detects an instruction that Node 2 cannot execute. At this point, Node 1's transfer program is interrupted (issued by the DMA, with the interrupt vector set to the next instruction; since this instruction error occurs occasionally, the program can be terminated via an interrupt). Meanwhile, Node 2 is executing instructions and accessing data in Node 3. After the access is completed, the program ends.

[0080] The above mainly describes the connection methods of all nodes, the cross-frequency domain DMA operation mode and node occupancy, the multi-master arbitration of internal nodes, and the program interruption caused by instruction filtering in this 5-node topology.

[0081] Describe the working modes in which each node works independently or in groups of nodes working together under different power consumption conditions;

[0082] Starting with all nodes working simultaneously, since the performance requirements decrease and the high-power mode of the high-speed bus matrix node is no longer needed, the high-speed bus matrix node is shut down by power gating. Before shutting down, the FLASH read channel is shut down first, and then the data in the current register is saved to the always on cell. The two slow bus matrix nodes and the two low-speed bus matrix nodes are still working normally. At this time, the CORE and DMA of the slow bus matrix node can access other nodes normally, as can the PDMA of the high-speed bus matrix node.

[0083] As performance requirements are further reduced, the power gating of the two slow bus matrix nodes is turned off in sequence, so that the entire system enters single-core and non-core working modes in sequence. The shutdown order in single-core mode is the same as the shutdown order of the high-speed bus matrix nodes, and the program can still be saved to each unit.

[0084] When entering kernelless mode, because DMAP cannot recognize instructions, it is necessary to send the peripheral memory transfer instructions to the two low-speed bus matrix nodes before the low-speed bus matrix nodes are shut down. After the two low-speed bus matrix nodes receive the transfer instructions, they can run the transfer of data between different peripherals via DMAP while the CORE is in sleep mode. Figure 2 Nodes 4 and 5 in the system have no storage units. Therefore, after both the slow bus matrix node and the high-speed bus matrix node are turned off, the DMAP of nodes 4 and 5 can only perform peripheral-to-peripheral transmission.

[0085] Finally, in the lowest power mode, only node 5 is still working. It can execute unfinished instructions sent by node 2 to node 4 to access data in node 5, or it can execute unfinished instructions from node 2 or node 3 to access node 5. In this case, DMAP can be driven by the cores of node 2 and node 3 before shutdown, or it can be initiated by peripheral interrupts in coreless mode.

[0086] The above examples describe the individual or combined operating modes of each node in low-power mode. This operating mode is also one of the performance advantages of the multi-matrix node bus topology. Combining the two examples above, it can be seen that this matrix node topology can complete the collaborative work of multiple cores and the controllability of power consumption modes without considering the consistency protocol. At the same time, it can insert RISC-V instruction filters and independent node storage units to maximize the adaptation to various interface options of various RISC-V cores.

Claims

1. A multi-matrix node bus topology based on the RISC-V instruction set, characterized in that, It includes one high-speed bus matrix node, multiple slow-speed bus matrix nodes, and multiple low-speed bus matrix nodes; Each matrix node controls power consumption to create efficiency differences by using different bus channel widths, different operating frequencies, or different operating voltages, while maintaining the correct node communication direction. The high-speed bus matrix node communicates with each slow bus matrix node and each low-speed bus matrix node, and follows instruction filtering when handling instructions. The high-speed bus matrix node serves as the master terminal for the slow-speed bus matrix node and the low-speed bus matrix node. In the slack bus matrix node, slack bus matrix nodes of the same level are connected to ensure that different slack bus matrix nodes have a master frequency difference. The slack bus matrix node with the higher operating frequency is used as the master end of the two slack bus matrix nodes, and the slack bus matrix node with the lower operating frequency is used as the slave end of the two slack bus matrix nodes. When a slow bus matrix node is connected to a high-speed bus matrix node, the slow bus matrix node acts as a slave. When slow bus matrix nodes are connected to low-speed bus matrix nodes, the slow bus matrix node acts as the master when interacting with low-speed bus matrix nodes of the same frequency or lower. In a low-speed bus matrix node, when the low-speed bus matrix node is connected to a slow-speed bus matrix node of the same or higher frequency, the low-speed bus matrix node acts as the slave end of the slow-speed bus matrix node of the same or higher frequency. When a low-speed bus matrix node and a high-speed bus matrix node are connected, the higher-frequency matrix node acts as the master and the lower-frequency matrix node acts as the slave.

2. The multi-matrix node bus topology based on the RISC-V instruction set according to claim 1, characterized in that, In the low-speed bus matrix node, DMAP and other slow bus matrix nodes or high-speed bus matrix nodes serve as the master of the low-speed bus matrix node. In addition, control signals from the high-speed bus matrix node need to reach the low-speed bus matrix node through a BRIDGE. The low-speed bus matrix node and SRAM of less than 128KB serve as the slave of the low-speed bus matrix node. Smaller capacity SRAMs are configured with their own independent operating voltage domain, and can still maintain normal operation and store data from peripherals even after the voltage domain of the low-speed bus matrix node is turned off.

3. The multi-matrix node bus topology based on the RISC-V instruction set according to claim 1, characterized in that, In a slow bus matrix node, the DMA, configurable core, and control signals from the high-speed bus matrix node serve as the master of the slow bus matrix node; control signals from the high-speed bus matrix node need to reach the slow bus matrix node through a BRIDGE; peripherals serve as slaves of the slow bus matrix node.

4. The multi-matrix node bus topology based on the RISC-V instruction set according to claim 1, characterized in that, In a high-speed bus matrix node, the core, DMA, and other configurable accelerators serve as the master device. In a slow bus matrix node with an independent core but no FLASH storage for the bootloader, the slave end of the high-speed bus matrix node is configured to store the boot program of the slow bus matrix node. After the SoC starts working, the DMA is controlled by the program of the high-performance core to move the boot program of the slow bus matrix node to the SRAM or other storage units of the slow bus matrix node.

5. A multi-matrix node bus topology based on the RISC-V instruction set according to claim 1, characterized in that, The entire SoC is divided into three voltage domains: the main domain, the backup domain, and the analog voltage domain.

6. A multi-matrix node bus topology based on the RISC-V instruction set according to claim 5, characterized in that, Each matrix node operates in a primary domain, working independently through different power gating, or all matrix nodes operate in different primary domains, with frequency differences created by voltage, allowing matrix nodes of the same type to have different operating frequencies.

7. A multi-matrix node bus topology based on the RISC-V instruction set according to claim 1, characterized in that, Add a one-way instruction filter to the bridge between the high-speed bus matrix node and the slow bus matrix node.

8. A multi-matrix node bus topology based on the RISC-V instruction set according to claim 1, characterized in that, In the slow bus matrix node, the control signals issued by the high-speed bus matrix node, the three sets of buses of two DMA and one CORE serve as the master end of MATRIX, and FLASH, SRAM, LOW SPEED BUS and BRIDGE serve as the slave end of MATRIX. Each master end is configured with the corresponding slave end access permissions. On the channel without node access, two or more sets of channels operate synchronously.

9. The method for operating the multi-matrix node bus topology based on the RISC-V instruction set as described in any one of claims 1-8, characterized in that, The steps include the following: Each matrix node operates independently in a different voltage domain. Each matrix node refers to any one of the high-speed bus matrix node, slow-speed bus matrix node, and low-speed bus matrix node. Initially, for each matrix node with FLASH, the Bootloader in the FLASH is read out. For matrix nodes without FLASH, the data in the matrix node with FLASH is transferred to the matrix node without FLASH via DMA or CORE. After all matrix nodes are working, the data exchanged is also transferred to the matrix node with FLASH via DMA or CORE. Before the voltage of each matrix node is turned off, the algorithm needs to delay for several cycles to wait for the data processing in the matrix node to be completed before turning off the voltage domain through the voltage switch. For those that can transfer data to other matrix nodes for execution, the voltage domain is turned off through the voltage switch after the data is transferred to other nodes.

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