A nanoscale high-speed neuromorphic device and its fabrication method

Abstract

This invention discloses a nanoscale high-speed neuromorphic device and its fabrication method. The device includes: a substrate; a top trench formed on the front side of the substrate; a lower electrode covering the bottom and sidewalls of the top trench and extending to cover the substrate surface; an oxide functional layer formed on the lower electrode; an adhesion layer formed on the oxide functional layer; a top electrode formed on the adhesion layer, covering the surface of the adhesion layer and completely filling the top trench; a bottom trench formed on the back side of the substrate, penetrating the lower part of the substrate to expose a portion of the lower surface of the lower electrode within the top trench; and a bottom electrode formed in the bottom trench, filling the bottom trench, contacting the lower electrode, and covering the back side of the substrate, wherein the overlap area between the top electrode in the top trench and the bottom electrode in the bottom trench is less than 10 nm.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a nanoscale high-speed neuromorphic device and its fabrication method. Background Technology

[0002] The architecture of mainstream computers today is the von Neumann architecture, where storage and computing units are separate structures. Although the computing power of computing chips continues to improve, the process of reading information from memory limits the overall speed, posing a challenge to the computing power of traditional integrated circuit chips. With the development of integrated circuits, the feature size of chips continues to shrink according to Moore's Law, proposed by Gordon Moore, to meet the needs of high-density chip integration and suitability for high-computing scenarios. Currently, the most advanced chip technology nodes have shrunk to below 10 nanometers, and the development of nanometer-scale semiconductor devices is crucial for the development of integrated circuits.

[0003] The human brain, as a highly efficient intelligent biological system, can complete various complex life activities with a power consumption of only 20W and react at high speed to various emergencies in the natural environment. Inspired by the human brain, the development of electronic devices for neuromorphic computing is of great significance for improving chip processing speed. As a new type of in-memory computing device, neuromorphic devices can directly break through the traditional von Neumann computing bottleneck, completing storage and neuromorphic computing functions on the same device, greatly improving chip computing power. Summary of the Invention

[0004] This invention discloses a method for fabricating a nanoscale high-speed neuromorphic device, comprising the following steps: forming a top trench on the front side of a substrate; depositing a lower electrode on the structure to cover the bottom and sidewalls of the top trench and extend to cover the substrate surface; growing an oxide functional layer on the lower electrode; growing an adhesion layer on the functional layer; growing a top electrode on the adhesion layer to cover the adhesion layer surface and completely fill the top trench; forming a bottom trench on the back side of the substrate, the bottom trench penetrating the lower part of the substrate to expose a portion of the lower surface of the lower electrode in the top trench; growing a bottom electrode in the bottom trench to fill the bottom trench, contacting the lower electrode and covering the back side of the substrate, wherein the overlap area between the top electrode in the top trench and the bottom electrode in the bottom trench is less than 10 nm.

[0005] In the method for fabricating the nanoscale high-speed neuromorphic device of the present invention, preferably, the width of the top trench is 21nm to 70nm and the height is 12nm to 40nm; the width of the bottom trench is 3nm to 10nm and the height is 100nm to 500nm.

[0006] In the method for fabricating high-speed neuromorphic devices at nanoscale in this invention, preferably, the thickness of the oxide functional layer is 3 nm to 10 nm.

[0007] In the method for fabricating the nanoscale high-speed neuromorphic device of the present invention, the oxide functional layer is preferably MoOx, HfO2, TaOx, ZrO2, Al2O3, TiO2, ZnO, NiO, SiO2, or a stack composed of some of the aforementioned materials.

[0008] The present invention also discloses a nanoscale high-speed neuromorphic device, comprising: a substrate; a top trench formed on the front side of the substrate; a lower electrode covering the bottom and sidewalls of the top trench and extending to cover the surface of the substrate; an oxide functional layer formed on the lower electrode; an adhesion layer formed on the functional layer; a top electrode formed on the adhesion layer, covering the surface of the adhesion layer and completely filling the top trench; a bottom trench formed on the back side of the substrate, penetrating the lower part of the substrate to expose a portion of the lower surface of the lower electrode in the top trench; and a bottom electrode formed in the bottom trench, filling the bottom trench, contacting the lower electrode and covering the back side of the substrate, wherein the overlap area between the top electrode in the top trench and the bottom electrode in the bottom trench is less than 10 nm.

[0009] In the nanoscale high-speed neuromorphic device of the present invention, preferably, the width of the top trench is 21nm to 70nm and the height is 12nm to 40nm; the width of the bottom trench is 3nm to 10nm and the height is 100nm to 500nm.

[0010] In the nanoscale high-speed neuromorphic device of the present invention, preferably, the thickness of the oxide functional layer is 3 nm to 10 nm.

[0011] In the nanoscale high-speed neuromorphic device of the present invention, preferably, the oxide functional layer is MoOx, HfO2, TaOx, ZrO2, Al2O3, TiO2, ZnO, NiO, SiO2, or a stack composed of some of the aforementioned materials.

[0012] Beneficial effects:

[0013] (1) Neuromorphic devices have both information storage and neuromorphic computing functions. They can avoid frequent information transfer between different storage and computing units from an architectural perspective, thereby improving the computing power and efficiency of the chip and reducing the power consumption of the chip.

[0014] (2) Nanoscale device size can reduce the distance of charge movement, thereby increasing the speed of charge erasure and writing, promoting neuromorphic devices to achieve high-speed response beyond the human brain level (10ms), which will greatly improve the development of artificial intelligence. Attached Figure Description

[0015] Figure 1 This is a flowchart of a method for fabricating high-speed neuromorphic devices at the nanoscale.

[0016] Figures 2-7 This is a schematic diagram of the structure of each stage in the fabrication method of nanoscale high-speed neuromorphic devices. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining this invention and are not intended to limit this invention. The described embodiments are merely some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0018] In the description of this invention, it should be noted that the terms "upper," "lower," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] Furthermore, many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details. Unless specifically indicated below, various parts of the device may be made of materials known to those skilled in the art, or may employ materials with similar functionality developed in the future.

[0020] Figure 1 This is a flowchart of a method for fabricating high-speed neuromorphic devices at the nanoscale. (For example...) Figure 1 As shown, the fabrication method of nanoscale high-speed neuromorphic devices includes the following steps:

[0021] Step S1: Prepare substrate 100, spin-coat photoresist on the front side, and define the position of the top trench using exposure and development processes. Then, fabricate the trench structure 101 using reactive ion etching in a CF4 atmosphere for the fabrication of nanoscale high-speed neuromorphic devices, such as... Figure 2As shown. The substrate can be a p-type low-doped silicon substrate, a silicon-on-insulator substrate, a silicon oxide substrate, silicon carbide, etc.; the etching gas can also be SF6, etc. The flow rate of the etching gas is 50 sccm to 100 sccm, and the power is 300 W to 600 W. The width of the top trench is 21 nm to 70 nm, and the height is 12 nm to 40 nm.

[0022] Step S2: A lower electrode Pt102 with a thickness of 3nm to 10nm is deposited on the above structure using physical vapor deposition, covering the bottom and sidewalls of the top trench and extending to cover the substrate surface, as shown. Figure 3 As shown. The electrode material is preferably Pt, but it can also be Pd, Cu, TaN, TiN, Au, Al, Ru, Co, Ag, etc. The deposition method can also be electron beam evaporation, thermal evaporation, etc.

[0023] Step S3: An oxide layer of 3 nm to 10 nm, MoOx, is grown on the lower electrode 102 using atomic layer deposition (ALD) technology as the device functional layer 103. The reaction chamber temperature is 200°C to 400°C; the Mo source temperature is 90°C to 130°C; and the water source temperature is 15°C to 25°C. The growth rate of MoOx is controlled at 0.06 nm / cycle to 0.11 nm / cycle. Furthermore, the oxide functional layer is preferably MoOx, but the invention is not limited to this; it can also be HfO2, TaOx, ZrO2, Al2O3, TiO2, ZnO, NiO, SiO2, or a stack composed of some of the aforementioned materials.

[0024] Step S4: An adhesion layer 104 with a thickness of 3 nm to 10 nm is grown on the functional layer 103 using electron beam evaporation, resulting in the structure shown below. Figure 4 As shown. Other growth methods include physical vapor deposition, thermal evaporation, etc.; the adhesion layer can also be Ta, Cr, etc.

[0025] Step S5: A top electrode Al105 with a thickness of 15 nm to 50 nm is grown on the adhesion layer 104 using physical vapor deposition, so that it covers the surface of the adhesion layer 104 and completely fills the top trench, resulting in the structure shown below. Figure 5 As shown. The deposition method can also be electron beam evaporation, thermal evaporation, etc.; the electrode material is preferably Al, but can also be Pt, Pd, Cu, TaN, TiN, Au, Ru, Co, Ag, etc.

[0026] Step S6: Spin-coat photoresist on the back side of substrate 100, and define the location of the bottom trench using exposure and development processes. Then, fabricate the bottom trench 106 using reactive ion etching in a CF4 atmosphere, as shown below. Figure 6As shown. The bottom trench penetrates the lower part of the substrate, exposing part of the lower surface of the lower electrode in the top trench. More preferably, the position of the bottom trench corresponds to the position of the top electrode located in the top trench. To achieve an effective working area of ​​less than 10 nm, i.e., the overlap area of ​​the top and bottom electrodes is less than 10 nm, electron beam lithography is required to achieve precise layout design and overlay alignment, etching a bottom trench of less than 10 nm. The etching gas is preferably CF4, but can also be SF6, etc. The flow rate of the etching gas is 50 sccm to 100 sccm, and the power is 300 W to 600 W. The width of the formed bottom trench is 3 nm to 10 nm, and the height is 100 nm to 500 nm.

[0027] Step S7: A TiN107 bottom electrode with a thickness of 100 nm to 500 nm is grown in the bottom trench using physical vapor deposition, filling the bottom trench and extending to cover the back side of the substrate, thus completing the fabrication of a nanoscale high-speed neuromorphic device. Figure 7 As shown. The formed bottom electrode 107 is in contact with the bottom electrode 102, and its position corresponds to the position of the top electrode, with an overlap area of ​​less than 10 nm. The electrode growth method can also be electron beam evaporation, thermal evaporation, etc.; the electrode material can also be Pt, Pd, Cu, TaN, Au, Al, Ru, Co, Ag, etc.

[0028] like Figure 7 As shown, a nanoscale high-speed neuromorphic device includes: a substrate 100; a top trench formed on the front side of the substrate 100; a lower electrode 102 covering the bottom and sidewalls of the top trench and extending to cover the surface of the substrate 100; an oxide functional layer 103 formed on the lower electrode 102; an adhesion layer 104 formed on the oxide functional layer 103; a top electrode 105 formed on the adhesion layer 104, covering the surface of the adhesion layer 104 and completely filling the top trench; a bottom trench formed on the back side of the substrate 100, penetrating the lower part of the substrate to expose a portion of the lower surface of the lower electrode 102 within the top trench; and a bottom electrode 107 formed in the bottom trench, filling the bottom trench, contacting the lower electrode 102, and covering the back side of the substrate 100, wherein the overlap area between the top electrode 105 located in the top trench and the bottom electrode located in the bottom trench is less than 10 nm.

[0029] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1.A method for fabricating a nanometer-sized high-speed neuromorphic device, comprising the following steps: forming a top trench on a front surface of a substrate; depositing a lower electrode to cover a bottom and sidewalls of the top trench and extend to cover a surface of the substrate; growing an oxide functional layer on the lower electrode; growing an adhesion layer on the oxide functional layer; growing a top electrode on the adhesion layer to cover a surface of the adhesion layer and completely fill the top trench; forming a bottom trench on a back surface of the substrate, the bottom trench penetrating a lower portion of the substrate to expose a part of a lower surface of the lower electrode in the top trench; and growing a bottom electrode in the bottom trench to fill the bottom trench, contact the lower electrode, and cover the back surface of the substrate, wherein an overlapping area of the top electrode in the top trench and the bottom electrode in the bottom trench is less than 10 nm, a width of the top trench is 21-70 nm, a width of the bottom trench is 3-10 nm, and the oxide functional layer is a stack of one or more of MoOx, HfO2, TaOx, ZrO2, Al2O3, TiO2, ZnO, NiO, and SiO2. 2.The method according to claim 1, wherein a height of the top trench is 12-40 nm, and a height of the bottom trench is 100-500 nm. 3.The method according to claim 1, wherein a thickness of the oxide functional layer is 3-10 nm. 4.A nanometer-sized high-speed neuromorphic device, comprising: a substrate; a top trench formed on a front surface of the substrate; a lower electrode covering a bottom and sidewalls of the top trench and extending to cover a surface of the substrate; an oxide functional layer formed on the lower electrode; an adhesion layer formed on the oxide functional layer; a top electrode formed on the adhesion layer to cover a surface of the adhesion layer and completely fill the top trench; a bottom trench formed on a back surface of the substrate, the bottom trench penetrating a lower portion of the substrate to expose a part of a lower surface of the lower electrode in the top trench; and a bottom electrode formed in the bottom trench to fill the bottom trench, contact the lower electrode, and cover the back surface of the substrate, wherein an overlapping area of the top electrode in the top trench and the bottom electrode in the bottom trench is less than 10 nm, a width of the top trench is 21-70 nm, a width of the bottom trench is 3-10 nm, and the oxide functional layer is a stack of one or more of MoOx, HfO2, TaOx, ZrO2, Al2O3, TiO2, ZnO, NiO, and SiO2. 5.The device according to claim 4, wherein a height of the top trench is 12-40 nm, and a height of the bottom trench is 100-500 nm. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 6.The nano-scale high-speed neuromorphic device of claim 4, wherein a thickness of the oxide functional layer is 3 nm to 10 nm. ​

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