Display driving system and related display device

Abstract

The present invention provides a display driving system and a related display device. The display driving system includes a timing control circuit and a plurality of display driving circuit groups. The timing control circuit is used to generate and transmit a plurality of data signals and a plurality of clock signals. The display driving circuit groups each include a plurality of display driving circuits, wherein these display driving circuits are coupled to the timing control circuit, and are used to jointly receive corresponding data signals in the data signals, and to jointly receive corresponding clock signals in the clock signals. The display driving circuits are used to respectively receive corresponding identification signals in a plurality of identification signals, or to respectively store corresponding identification data in a plurality of identification data. The display driving circuits are also used to sequentially latch corresponding data signals according to the identification signals, or to sequentially latch corresponding data signals according to the identification data.

Description

Technical Field

[0001] The present invention relates to passive matrix light emitting diode technology, and more particularly to a display driving system and a related display device using multi-point transmission of data signals and clock signals. Background Art

[0002] The passive matrix light emitting diode (PMLED) panel architecture includes a timing control circuit and multiple display driver circuits. The timing control circuit transmits data signals and clock signals to each display driver circuit, which can control the display panel to display the corresponding image. Traditionally, data signals are transmitted in series between multiple display driver circuits, while clock signals are transmitted in parallel. Since data signals are transmitted in series, each level of display driver circuit will follow the first in first out (FIFO) rule to transmit the data signal to the next level of display driver circuit.

[0003] However, if the timing of the data signal and the clock signal of the previous display driving circuit are not aligned with each other due to transmission delay, the next display driving circuit will access wrong data, further causing the display panel to display wrong images.

[0004] In addition, when a conventional PMLED panel is in operation, the data lines and scan lines that do not receive signals from the display driving circuit will be in a floating state. The floating data lines and scan lines are easily coupled by other signals and have erroneous voltages, which may not only cause pixels to light up by mistake, but also hinder the charging process of the pixels, making the pixels unable to correctly display low grayscales.

[0005] Therefore, how to provide a display driving system that can ensure the timing alignment of data signals and clock signals and ensure that data lines and scan lines do not enter a floating state is a subject in the art. Summary of the invention

[0006] In order to solve the above problems, the present invention provides a display driving system. The display driving system includes a timing control circuit and a plurality of display driving circuit groups. The timing control circuit is used to generate and transmit a plurality of data signals and a plurality of clock signals. The display driving circuit groups each include a plurality of display driving circuits, wherein these display driving circuits are coupled to the timing control circuit, and are used to jointly receive corresponding data signals in the data signals, and to jointly receive corresponding clock signals in the clock signals. These display driving circuits are used to respectively receive corresponding identification signals in a plurality of identification signals, or to respectively store corresponding identification data in a plurality of identification data. The display driving circuit is also used to sequentially latch the corresponding data signal according to the identification signal, or to sequentially latch the corresponding data signal according to the identification data.

[0007] The present invention further provides a display device, comprising a display driving system and a display panel, wherein the display driving system comprises a timing control circuit and a plurality of display driving circuit groups. The timing control circuit is used to generate and transmit a plurality of data signals and a plurality of clock signals. The display driving circuit groups each comprise a plurality of display driving circuits, wherein these display driving circuits are coupled to the timing control circuit, and are used to jointly receive corresponding data signals in the data signals, and to jointly receive corresponding clock signals in the clock signals. These display driving circuits are used to respectively receive corresponding identification signals in a plurality of identification signals, or to respectively store corresponding identification data in a plurality of identification data. The display driving circuits are also used to sequentially latch corresponding data signals according to the identification signals, or to sequentially latch corresponding data signals according to the identification data.

[0008] The advantages of the above display driving system and display device are that they can solve the problem of pixel mis-lighting caused by signal coupling in the LED display device, and can also solve the problem that pixels in the LED display device are difficult to light up. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more obvious and understandable, the description of the accompanying drawings is as follows:

[0010] Figure 1 is a functional block diagram of a display device according to some embodiments of the present invention;

[0011] Figure 2A-2B is a functional block diagram of a display driving circuit according to some embodiments of the present invention;

[0012] Figure 3 A schematic diagram of a voltage divider circuit for generating an identification signal according to some embodiments of the present invention;

[0013] Figures 4A to 4B A timing diagram of a display driving circuit according to some embodiments of the present invention;

[0014] Figure 5 is a functional block diagram of a display driving circuit according to some other embodiments of the present invention;

[0015] Figure 6 FIG. 4 is a functional block diagram of a voltage regulation control circuit according to some embodiments of the present invention.

[0016]

Explanation of symbols

[0017] 1: Display device

[0018] 10: Display driver system

[0019] 12: Scanning switch circuit

[0020] 14: Display Panel

[0021] 16: Voltage divider circuit

[0022] 100_1~100_z: display driving circuit group

[0023] 100_11~100_1p: Display driver circuit

[0024] 102: Timing control circuit

[0025] 122: Switch control register

[0026] 110: receiving interface

[0027] 120: Latch circuit

[0028] 130: Sequential Circuit

[0029] 140: Output circuit

[0030] 150: Voltage stabilization control circuit

[0031] 151: Output divider

[0032] 154: Scanning divider

[0033] 160: Scanning circuit

[0034] 700: Display driver process

[0035] 710, 720, 730, 740: Operation

[0036] CH, CH[1]~CH[X]: Channel

[0037] CLK[1]~CLK[z]: clock signal

[0038] CT: output control signal

[0039] Data[1]~Data[z]: data signal

[0040] DL[1]~DL[N]: data line

[0041] GND: Ground power supply

[0042] IC[1]~IC[p]: latch signal

[0043] ID: Identification data

[0044] IS: Identification signal

[0045] M[1]~M[M]: switch

[0046] N1~NN: Node

[0047] P

[11] ~P[MN]: pixel unit

[0048] R1~R N-1 : Voltage divider resistor

[0049] SCT: Scan control signal

[0050] SL, SL[1]~SL[M]: scan line

[0051] SS[1]~SS[M]: Scanning signal

[0052] STR, STR[1]~STR[p]: start signal

[0053] t STR , t1, t2, t p :time

[0054] VDD: Voltage supply

[0055] VDT1~VDT4: Reference data voltage

[0056] V ID1 ~V IDN : Voltage Level

[0057] VST1~VST4: Reference scanning voltage DETAILED DESCRIPTION

[0058] In this document, when an element is referred to as "connected" or "coupled", it may refer to "electrical connection" or "electrical coupling". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although the terms "first", "second", etc. are used in this document to describe different elements, the terms are only used to distinguish between elements or operations described by the same technical terms. Unless the context clearly indicates otherwise, the terms do not specifically refer to or imply an order or sequence, nor are they used to limit the present invention.

[0059] Figure 1 A simplified functional block diagram of a display device 1 according to some embodiments. The display device 1 includes a display driving system 10, a scan switch circuit 12, and a display panel 14. The display driving system 10 includes a timing control circuit 102 and at least two display driving circuit groups 100_1-100_z. The timing control circuit 102 generates a corresponding number of data signals Data[1]-Data[z] and a corresponding number of clock signals CLK[1]-CLK[z] according to the number of display driving circuit groups 100_1-100_z, and outputs the data signals Data[1]-Data[z] and the clock signals CLK[1]-CLK[z] to the corresponding display driving circuit groups 100_1-100_z.

[0060] Each display driving circuit group 100_1-100_z includes a plurality of display driving circuits. The following embodiments of the present invention will be described by taking the display driving circuit group 100_1 as an example. The components, connection relationships and operations of the remaining display driving circuit groups 100_2-100_z are similar to those of the display driving circuit group 100_1. For the sake of brevity, the relevant contents will not be repeated. The display driving circuit group 100_1 includes p display driving circuits 100_11-100_1p, where p is an integer greater than 0. In some embodiments, the timing control circuit 102 transmits the data signal Data[1] and the clock signal CLK[1] to each display driving circuit 100_11-100_1p in the display driving circuit group 100_1 in a multi-drop manner. In other words, the timing control circuit 102 transmits the data signal Data[1] to each display driving circuit 100_11 to 100_1p in the display driving circuit group 100_1 at the same time point, and transmits CLK[1] to each display driving circuit 100_11 to 100_1p in the display driving circuit group 100_1 at the same time point. After the display driving circuits 100_11 to 100_1p convert the data signal Data[1] into a driving current, each of them passes through a channel (e.g. Figure 2A , 2B The channels CH[1]-CH[X] are shown to transmit driving current to the display panel 14, and each channel corresponds to one of the data lines DL[1]-DL[N].

[0061] The display panel 14 includes M*N pixel units P

[11] ~P[MN], M scan lines SL[1]~SL[M] and N data lines DL[1]~DL[N], where M and N are integers greater than 1. In some embodiments, the display panel 14 is a PMLED panel with a common anode. Structurally, each pixel unit is implemented by a light emitting diode, and the anodes of the N diodes in each row are electrically connected to one of the scan lines SL[1]~SL[M], and the cathodes of the M diodes in each column are electrically connected to a data line. The display panel 14 is coupled to the scan switch circuit 12 through the scan lines SL[1]~SL[M], and is coupled to the display driving system 10 through the N data lines DL[1]~DL[N].

[0062] The scan switch circuit 12 is coupled to the timing control circuit 102 and is used to receive scan signals SS[1]-SS[M]. In some embodiments, the scan switch circuit 12 includes a switch control register 122 and M switches M[1]-M[M]. The switch control register 122 is used to generate scan signals SS[1]-SS[M] and transmit the scan signals SS[1]-SS[M] to corresponding switches M[1]-M[M] to control the conduction of the switches M[1]-M[M], thereby providing a driving voltage (e.g. Figure 1 The switches M[1] to M[M] are each implemented as a P-type transistor, and the P-type transistor includes a first terminal for receiving the voltage power source VDD, a second terminal coupled to one of the scan lines SL[1] to SL[M], and a gate terminal for receiving one of the scan signals SS[1] to SS[M].

[0063] Figure 2A-2B FIG. 1 is a functional block diagram of a display driving circuit 100_11 according to some embodiments. In some embodiments, the display driving circuit 100_11 includes a receiving interface 110 , a latch circuit 120 , a timing circuit 130 , and an output circuit 140 .

[0064] The receiving interface 110 is used to receive the corresponding data signal Data[1] and the corresponding clock signal CLK[1], and transmit the data signal Data[1] to the latch circuit 120, and transmit the clock signal CLK[1] and the data signal Data[1] to the timing circuit 130. The latch circuit 120 is coupled to the receiving interface 110, and is used to sequentially latch multiple display data in the data signal Data[1], and transmit these display data to the output circuit 140. The output circuit 140 is coupled to the latch circuit 120 and the timing circuit 130, and is used to provide multiple driving currents to multiple channels CH[1]~CH[X] respectively, and is used to control the load ratios of the multiple driving currents according to the aforementioned multiple display data, where X is an integer greater than 1. The timing circuit 130 is coupled to the receiving interface 110 and the latch circuit 120. In some embodiments, the timing circuit 130 is also used to receive an identification signal IS (such as Figure 2A ), the timing circuit 130 is used to control the timing of the latch circuit 120 latching multiple display data and the timing of the output circuit 140 providing multiple driving currents according to the identification signal IS and the clock signal CLK[1]. In some embodiments, the identification signal IS can be an SPI signal, an I2C signal, or a UART signal.

[0065] In some embodiments, the timing circuit 130 is used to store identification data ID (eg Figure 2B ) without receiving the identification signal IS from the outside. The timing circuit 130 is used to control the timing of latching multiple display data by the latch circuit 120 according to the identification data ID and the clock signal CLK[1], and to control the timing of the output circuit 140 providing multiple driving currents. The timing of storing the identification data ID by the timing circuit 130 can be the output stage of the display driving circuit 100_11, or after the lamp board corresponding to the display driving circuit 100_11 is completed.

[0066] In some embodiments, the data signal Data[ 1 ] and the clock signal CLK[ 1 ] may be single-ended signals or differential signals.

[0067] In some embodiments, the latch circuit 120 may be a static random access memory (SRAM) or a data line latch (Data Line Latch).

[0068] In some embodiments, the display driving circuits 100_11 ˜ 100_1p receive identification signals IS (or identification data ID) of different values ​​or sizes. Different identification signals IS (or identification data ID) can be understood as being used to set the display driving circuits 100_11 ˜ 100_1p to have different numbers.

[0069] Figure 3 FIG. 1 is a schematic diagram of a voltage divider circuit 16 for generating an identification signal IS according to some embodiments. In some embodiments, the display driving system 10 further includes a voltage divider circuit 16. The voltage divider circuit 16 includes a voltage power source VDD, a ground power source GND, and a plurality of voltage divider resistors R1-R N-1 And multiple nodes N1~NN. Voltage dividing resistors R1~R N-1 are connected in series, and the voltage divider resistor R1 is coupled to the voltage power supply VDD, the voltage divider resistor R N-1 Coupled to the ground power source GND.

[0070] Nodes N1~NN and voltage divider resistors R1~R N-1 For example, the voltage divider resistor R1 is located between nodes N1 and N2, the voltage divider resistor R2 is located between nodes N2 and N3, and so on. N-1 Used to divide the voltage between the voltage power supply VDD and the ground power supply GND so that each node N1-NN has a voltage level V ID1 ~V IDN . Voltage level V ID1 ~V IDN They are respectively used as identification signals IS received by the display driving circuits 100_11 to 100_1p.

[0071] exist Figure 2A , 2B In the embodiment, the components, connection relationships, operations and advantages of the other display driving circuits 100_12 to 100_1p are similar to those of the display driving circuit 100_11, and for the sake of brevity, the relevant contents will not be repeated.

[0072] Figures 4A to 4B for Figure 1 The latch signals IC[1]-IC[p] respectively represent the signals used by the timing circuit 130 to trigger the latch circuit 120 to latch in the display driving circuits 100_11-100_1p.

[0073] In some embodiments, Figure 4A As shown, the data signal Data[1] includes a start data STR and a plurality of display data (marked with a bottom line) following the start data STR. When the timing circuit 130 of each of the display driving circuits 100_11 to 100_1p is at time t STRWhen receiving the start data STR, the timing circuits 130 of the display driving circuits 100_11 to 100_1p respectively count the time length specified by the identification signal IS (or identification data ID) according to the received identification signal IS (or identification data ID), so as to trigger the latch circuit 120 to start the latch operation with the latch signal IC[1] to IC[p] at the corresponding time. For example, the timing circuit 130 of the display driving circuit 100_11 transmits the latch signal IC[1] to the latch circuit 120 of the display driving circuit 100_11 at time t1; the timing circuit 130 of the display driving circuit 100_12 transmits the latch signal IC[2] to the latch circuit 120 of the display driving circuit 100_12 at time t2; the timing circuit 130 of the display driving circuit 100_1p transmits the latch signal IC[1] to the latch circuit 120 of the display driving circuit 100_11 at time t p The latch signal IC[p] is transmitted to the latch circuit 120 of the display driving circuit 100_1p.

[0074] In some embodiments, Figure 4B As shown, the data signal Data[1] includes a plurality of starting data STR[1]-STR[p] and a plurality of display data (indicated by the bottom line) following the starting data STR[1]-STR[p]. When the timing circuit 130 of each of the display driving circuits 100_11-100_1p receives the starting signal specified by the identification signal IS (or the identification data ID), it transmits the latch signal IC[1]-IC[p] to the latch circuit 120. For example, the timing circuit 130 of the display driving circuit 100_11 transmits the latch signal IC[1] to the latch circuit 120 of the display driving circuit 100_11 upon receiving the start signal STR[1]. The timing circuit 130 of the display driving circuit 100_12 transmits the latch signal IC[2] to the latch circuit 120 of the display driving circuit 100_12 upon receiving the start signal STR[2]. The timing circuit 130 of the display driving circuit 100_1p transmits the latch signal IC[p] to the latch circuit 120 of the display driving circuit 100_1p upon receiving the start signal STR[p].

[0075] Figure 5 FIG. 1 is a functional block diagram of a display driving circuit 100_11 according to some other embodiments. Figure 2A , 2B Compared with the display driving circuit 100_11, Figure 5 The display driving circuit 100_11 further includes a voltage regulation control circuit 150 and a scanning circuit 160 . Figure 5 The operation, connection relationship and advantages of the remaining circuit blocks of the display driving circuit 100_11 are similar to those of Figure 2A , 2BFor the sake of brevity, the corresponding circuit blocks of the display driving circuit 100_11 are not repeated here.

[0076] The voltage regulation control circuit 150 is coupled to the timing circuit 130, Figure 1 Some of the data lines DL[1] to DL[X] among the data lines DL[1] to DL[N] and Figure 1 The scanning circuit 160 may be a part of the scanning lines SL[1] to SL[Y] among the scanning lines SL[1] to SL[M]. Figure 1 A portion of the scan switch circuit 12, that is, in some embodiments, Figure 1 Different parts of the scan switch circuit 12 can be respectively integrated into the display driving circuits of the display driving circuit groups 100_1 to 100_z to form Figure 5 The scanning circuit 160 is coupled to the voltage regulation control circuit 150, the timing circuit 130 and the scanning lines SL[1]~SL[Y] to provide a driving voltage to the scanning lines SL[1]~SL[Y]. The voltage regulation control circuit 150 will regulate one or more of the data lines DL[1]~DL[X] that do not receive the driving current and one or more of the scanning lines SL[1]~SL[Y] that do not receive the driving voltage according to the output control signal CT provided by the timing control circuit 130. That is, the voltage regulation control circuit 150 is used to maintain the voltage on the data lines that do not receive the driving current and the scanning lines that do not receive the driving voltage unchanged to prevent these data lines and the scanning lines from floating.

[0077] Please refer to Figure 6 , Figure 6 1 is a functional block diagram of a voltage regulation control circuit 150 according to some embodiments. The voltage regulation control circuit 150 includes a plurality of output multiplexers 151, each of which is coupled to a corresponding plurality (e.g., two) of the data lines DL[1]-DL[X], for receiving reference data voltages VDT1-VDT4, and for outputting one of the reference data voltages VDT1-VDT4 to the data lines coupled to the output multiplexer 151 according to an output control signal CT to maintain the voltages on the data lines. The output control signals CT received by different output multiplexers 151 may be different, and the reference data voltages VDT1-VDT4 received by different output multiplexers 151 may be different.

[0078] In some embodiments, the voltage regulation control circuit 150 includes only one output multiplexer 151. The output multiplexer 151 is coupled to the data lines DL[1]-DL[X] and is used to output one of the reference data voltages VDT1-VDT4 to the data lines DL[1]-DL[X] according to the output control signal CT to regulate one or more of the data lines DL[1]-DL[X] that do not receive the driving current.

[0079] Continue to refer to Figure 6 The voltage regulation control circuit 150 further includes a plurality of scan multiplexers 154, each of which is coupled to a corresponding plurality (e.g., two) of the scan lines SL[1]-SL[Y], and is used to receive reference scan voltages VST1-VST4, and to output one of the reference scan voltages VST1-VST4 to the scan line coupled to the scan multiplexer 154 according to a scan control signal SCT to maintain the voltage on the scan line. The scan control signal SCT received by different scan multiplexers 154 may be different, and the reference scan voltages VST1-VST4 received by different scan multiplexers 154 may be different.

[0080] The number and configuration of the output multiplexers, scanning multiplexers, output control signals, scanning control signals, reference data voltages and reference scanning voltages described above are merely examples, and other numbers and configurations of output multiplexers, scanning multiplexers, output control signals, scanning control signals, reference data voltages and reference scanning voltages are all within the scope of the present invention.

[0081] By using the voltage stabilizing control circuit 150 of the present invention, various display problems in LED display devices can be solved. For example, if the pixel in the LED display device does not use the voltage stabilizing control circuit 150, when the data line or scan line of the pixel does not receive the driving current, the voltage level of the data line or scan line will float. If the data line or scan line of the adjacent pixel receives the driving current at this time, the voltage level of the data line or scan line will be coupled by the adjacent data line or scan line, and then the pixel will be mistakenly lit. By using the voltage stabilizing control circuit 150 of the present invention, floating can be avoided and the problem of mistakenly lighting the pixel in the LED display device can be solved. In addition, when the LED display device is lit, if the picture to be displayed is a low gray scale, the pixel conduction time is short, and the pixel may not light up easily due to the resistor-capacitor (RC) effect. By using the voltage stabilizing control circuit 150 of the present invention, the data line and the scan line can be pre-charged using the reference data voltage and the reference scan voltage, thereby solving the problem of the pixel not lighting up easily in the LED display device.

[0082] exist Figure 5 , 6In the embodiment, the components, connection relationships, operations and advantages of the other display driving circuits 100_12 to 100_1p are similar to those of the display driving circuit 100_11, and for the sake of brevity, the relevant contents will not be repeated.

[0083] In summary, the display driving system and the related display device disclosed in the present invention use a multi-point transmission method to transmit data signals and clock signals. In addition to avoiding data errors caused by using a series transmission method to transmit data signals, it can also be applied to any high-speed transmission LED system. In addition, by setting a voltage stabilization control circuit to control the voltage level of the scan line / data line that does not receive the driving voltage / driving current, in addition to reducing the phenomenon that the scan line / data line is coupled with other signals and mistakenly lights up, it can also ensure that the pixel can light up when receiving a low grayscale driving current.

Claims

1. A display driving system, comprising: A timing control circuit for generating and transmitting a plurality of data signals and a plurality of clock signals; and A plurality of display driving circuit groups, each comprising a plurality of display driving circuits, wherein the display driving circuits are coupled to the timing control circuit to jointly receive corresponding data signals among the data signals and to jointly receive corresponding clock signals among the clock signals, The display driving circuits are used to respectively receive corresponding identification signals among a plurality of identification signals, or to respectively store corresponding identification data among a plurality of identification data. The display driving circuits are used to sequentially latch the corresponding data signals according to the identification signals, or to sequentially latch the corresponding data signals according to the identification data; in, The display driving system further comprises: The voltage divider circuit includes a plurality of resistors connected in series in sequence, and is used to divide the voltage between the voltage power source and the ground power source to generate a plurality of different identification voltage levels, and output the identification voltage levels as the identification signals respectively.

2. The display driving system as claimed in claim 1, wherein each of the display driving circuits comprises: A receiving interface, used for receiving and transmitting the corresponding data signal and the corresponding clock signal; A latch circuit, coupled to the receiving interface, for latching a plurality of display data in the corresponding data signal; as well as A timing circuit, coupled to the receiving interface and the latch circuit, for receiving the corresponding identification signal and controlling the latch circuit to latch the display data according to the corresponding identification signal and the corresponding clock signal; as well as The output circuit is coupled to the latch circuit, and is used for providing driving currents to a plurality of data lines respectively, and for controlling the load ratios of the driving currents respectively according to the display data.

3. The display driving system as claimed in claim 1, wherein each of the display driving circuits comprises: A receiving interface, used for receiving and transmitting the corresponding data signal and the corresponding clock signal; A latch circuit, coupled to the receiving interface, for latching a plurality of display data in the corresponding data signal; A timing circuit, coupled to the receiving interface and the latch circuit, for receiving the corresponding identification signal or for storing the corresponding identification data, and controlling the latch circuit to latch the display data according to the corresponding identification data and the corresponding clock signal; as well as The output circuit is coupled to the latch circuit and the timing circuit, and is used for respectively providing driving currents to a plurality of data lines, and for respectively controlling the load ratios of the driving currents according to the display data.

4. The display driving system as described in claim 1, wherein the corresponding data signal includes a start data and a plurality of display data, and when the display driving circuits receive the start data, each of the display driving circuits starts to latch the corresponding display data among the display data after a time length specified by the corresponding identification signal or the corresponding identification data.

5. The display driving system as described in claim 1, wherein the corresponding data signal includes multiple starting data and multiple display data, and when each of the display driving circuits receives the corresponding starting data among the starting data specified by the corresponding identification signal or the corresponding identification data, it starts to latch the corresponding display data among the display data.

6. The display driving system according to claim 2 or 3, further comprising: A scanning circuit is coupled to the timing circuit and a plurality of scanning lines, and is used to provide a plurality of driving voltages to the scanning lines respectively; and A voltage regulation control circuit is coupled to the timing circuit, the data lines and the scan lines, wherein when one of the data lines does not receive the driving currents, the voltage regulation control circuit is used to regulate the voltage of the one of the data lines, wherein when one of the scan lines does not receive the driving currents, the voltage regulation control circuit is used to regulate the voltage of the one of the scan lines.

7. The display driving system as claimed in claim 6, wherein the voltage stabilization control circuit further comprises: a plurality of output multiplexers, wherein each output multiplexer is coupled to a corresponding plurality of the data lines and is used to receive an output control signal and a plurality of reference data voltages, wherein each output multiplexer is used to output one of the reference data voltages to the corresponding plurality of the data lines according to the output control signal; and A plurality of scan multiplexers, each of which is coupled to a corresponding plurality of the scan lines and is used to receive a scan control signal and a plurality of reference scan voltages, wherein each scan multiplexer is used to output one of the reference scan voltages to the corresponding plurality of the scan lines according to the scan control signal.

8. The display driving system as claimed in claim 6, wherein the voltage stabilization control circuit further comprises: an output multiplexer coupled to the data lines, the output multiplexer being used to receive an output control signal and a plurality of reference data voltages, and output one of the reference data voltages to the data lines according to the output control signal; and The scan multiplexer is coupled to the scan lines, and is used for receiving a scan control signal and a plurality of reference scan voltages, and outputting one of the reference scan voltages to the scan lines according to the scan control signal.

9. A display device, comprising a display driving system and a display panel, wherein the display driving system comprises: A timing control circuit for generating and transmitting a plurality of data signals and a plurality of clock signals; and A plurality of display driving circuit groups, each comprising a plurality of display driving circuits, wherein the display driving circuits are coupled to the timing control circuit to jointly receive corresponding data signals among the data signals and to jointly receive corresponding clock signals among the clock signals, The display driving circuits are used to respectively receive corresponding identification signals among a plurality of identification signals, or to respectively store corresponding identification data among a plurality of identification data. The display driving circuits are used to sequentially latch the corresponding data signals according to the identification signals, or to sequentially latch the corresponding data signals according to the identification data; in, The display driving system further comprises: The voltage divider circuit includes a plurality of resistors connected in series in sequence, and is used to divide the voltage between the voltage power source and the ground power source to generate a plurality of different identification voltage levels, and output the identification voltage levels as the identification signals respectively.

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