Semiconductor device and method of manufacturing

Abstract

The present disclosure relates generally to semiconductor devices and methods of manufacture. Semiconductor devices and methods of manufacture are provided. In some embodiments, a method includes depositing an etch stop layer over a first hardmask material, the first hardmask material over a gate stack; depositing an interlayer dielectric over the etch stop layer; forming a first opening through the interlayer dielectric, the etch stop layer, and the first hardmask material, the first opening exposing a conductive portion of the gate stack; and treating sidewalls of the first opening with a first dopant to form a first treatment region within the interlayer dielectric, a second treatment region within the etch stop layer, a third treatment region within the first hardmask material, and a fourth treatment region within the conductive portion, wherein, after the treating, the fourth treatment region has a higher concentration of the first dopant than the first treatment region.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor devices and manufacturing methods. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is continuously increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: depositing an etch stop layer on a first hard mask material, the first hard mask material being on a gate stack; depositing an interlayer dielectric on the etch stop layer; forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack; and treating the sidewalls of the first opening with a first dopant to form a first processing region within the interlayer dielectric, a second processing region within the etch stop layer, a third processing region within the first hard mask material, and a fourth processing region within the conductive portion, wherein, after the treatment, the fourth processing region has a higher concentration of the first dopant than the first processing region.

[0005] According to another embodiment of this disclosure, a method of manufacturing a semiconductor device is provided, the method comprising: forming a first opening through a dielectric layer, a contact etch stop layer, and a first hard mask material to expose a conductive portion of a gate stack; treating the sidewalls of the first opening with a first plasma from a nitrogen-containing precursor; filling the first opening with a first conductive material; forming a second opening through the dielectric layer and the contact etch stop layer to expose a first source / drain contact; treating the sidewalls of the second opening with a second plasma; and filling the second opening with a second conductive material.

[0006] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a gate stack located above a semiconductor fin; a first hard mask material overlying the gate stack, the first hard mask material including a first processing region; an etch stop layer overlying the first hard mask material, the etch stop layer including a second processing region; a dielectric layer overlying the etch stop layer, the dielectric layer including a third processing region; and a conductive material extending through the first processing region, the second processing region, and the third processing region and substantially contacting the first processing region, the second processing region, and the third processing region, wherein the conductive material also substantially contacts a fourth processing region located within the gate stack. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figures 1A-1B A finFET according to some embodiments is shown.

[0009] Figure 2 The deposition of interlayer dielectrics according to some embodiments is shown.

[0010] Figure 3 The formation of an opening through the interlayer dielectric is shown according to some embodiments.

[0011] Figure 4 The processing according to some embodiments is illustrated.

[0012] Figure 5 The deposition of a conductive material according to some embodiments is shown.

[0013] Figure 6 A planarization process according to some embodiments is illustrated.

[0014] Figure 7 A dielectric recap according to some embodiments is shown.

[0015] Figure 8 The formation of a second opening according to some embodiments is shown.

[0016] Figure 9 The formation of a recess according to some embodiments is shown.

[0017] Figure 10 A second process according to some embodiments is shown.

[0018] Figure 11 The deposition of a conductive material according to some embodiments is shown.

[0019] Figure 12A A planarization process according to some embodiments is illustrated.

[0020] Figure 12B The formation of interconnections according to some embodiments is shown.

[0021] Figures 13A-13B A process without a second processing is shown according to some embodiments.

[0022] Figures 14A-14C A process without recesses according to some embodiments is shown.

[0023] Figures 15A-15B A process without a second processing and without recesses is shown according to some embodiments.

[0024] Figures 16A-16E A process with a second hard mask material is shown according to some embodiments.

[0025] Figures 17A-17D A process with a second hard mask material and a recess is shown according to some embodiments.

[0026] Figures 18A-18C A process with a single processing step is shown according to some embodiments. Detailed Implementation

[0027] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0028] Furthermore, this document may use spatially relevant terms (e.g., "below," "below," "lower than," "above," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0029] Embodiments will now be described with reference to specific examples including finFET devices having a pseudo-bottom-up plugging process for scaling as device size decreases. However, the embodiments are not limited to the examples provided herein, and these ideas can be implemented in a wide range of embodiments, such as nanowire devices, nanosheet devices, or silicon-on-insulator structures.

[0030] Now for reference Figure 1A The image shows a perspective view of a semiconductor device 100, such as a FinFET device. In one embodiment, the semiconductor device 100 includes a substrate 101 and a first trench 103. The substrate 101 may be a silicon substrate, but other substrates may also be used, such as semiconductor-on-insulator (SOI), strained SOI, and silicon-germanium-on-insulator. The substrate 101 may be a p-type semiconductor, but in other embodiments, it may be an n-type semiconductor.

[0031] In other embodiments, substrate 101 may be selected as a material that improves the performance of the device formed from substrate 101 (e.g., improves carrier mobility). For example, in some embodiments, the material of substrate 101 may be selected as a layer of epitaxially grown semiconductor material, such as epitaxially grown silicon-germanium, which helps improve some performance measurements of the device formed from epitaxially grown silicon-germanium. However, while using these materials may improve some performance characteristics of the device, using the same materials may affect other performance characteristics of the device. For example, using epitaxially grown silicon-germanium may worsen interface defects in the device (relative to silicon).

[0032] The first trench 103 can be formed as an initial step in the final formation of the first isolation region 105. A mask layer can be used. Figure 1A(Not shown separately) and a suitable etching process are used to form the first trench 103. For example, the mask layer may be a hard mask comprising silicon nitride formed by a process such as chemical vapor deposition (CVD), but other materials (e.g., oxides, oxide oxynitrides, silicon carbide, combinations thereof, etc.) and other processes (e.g., plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or even silicon oxide formation followed by nitriding) may also be used. Once formed, the mask layer may be patterned by a suitable photolithography process to expose those portions of the substrate 101 that can be removed to form the first trench 103.

[0033] However, as those skilled in the art will recognize, the processes and materials described above for forming the mask layer are not the only methods that can be used to protect some portions of the substrate 101 and expose other portions of the substrate 101 to form the first trench 103. Any suitable process (e.g., a patterned and developed photoresist) can be used to expose the portions of the substrate 101 to be removed to form the first trench 103. All of these methods are fully intended to be included within the scope of this embodiment.

[0034] Once the mask layer has been formed and patterned, a first trench 103 is formed in the substrate 101. The exposed substrate 101 can be removed by a suitable process such as reactive ion etching (RIE) to form the first trench 103 in the substrate 101, but any suitable process may also be used. In one embodiment, the first trench 103 may be formed having a distance of less than approximately [missing information - likely a distance from the surface of the substrate 101]. The first depth, for example, about

[0035] However, as those skilled in the art will recognize, the process for forming the first trench 103 described above is only one possible process and does not imply the only embodiment. Rather, any suitable process capable of forming the first trench 103 can be employed, and any suitable process including any number of masking and removal steps can be used.

[0036] In addition to forming the first trench 103, the masking and etching processes also form fins 107 from those portions of the substrate 101 that remain intact. For convenience, the fins 107 are shown in the figures as separated from the substrate 101 by solid lines, but this separation may or may not be a physical indication. As described below, these fins 107 can be used to form the channel regions of multi-gate FinFET transistors. Although Figure 1A Only three fins 107 formed from the substrate 101 are shown, but any number of fins 107 can be used.

[0037] The fins 107 can be formed such that they have a width between about 5 nm and about 80 nm at the surface of the substrate 101, for example, about 30 nm. Additionally, the fins 107 can be spaced apart from each other by a distance between about 10 nm and about 100 nm, for example, about 50 nm. By spacing the fins 107 in this way, each fin 107 can form an individual channel region, while still being close enough to share a common gate (discussed further below).

[0038] Furthermore, the fin 107 can be patterned using any suitable method. For example, one or more photolithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the fin 107. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 107.

[0039] Once the first trench 103 and fin 107 have been formed, the first trench 103 can be filled with a dielectric material, and the dielectric material can be recessed within the first trench 103 to form a first isolation region 105. The dielectric material can be an oxide material, a high-density plasma (HDP) oxide, etc. After optional cleaning and lining of the first trench 103, the dielectric material can be formed using a chemical vapor deposition (CVD) method (e.g., HARP process), a high-density plasma CVD method, or other suitable formation methods known in the art.

[0040] The first trench 103 can be filled by overfilling the first trench 103 and the substrate 101 with a dielectric material, and then removing excess material outside the first trench 103 and the fin 107 by a suitable process such as chemical mechanical polishing (CMP), etching, or a combination thereof. In one embodiment, the removal process also removes any dielectric material located on the fin 107, such that the removal of the dielectric material exposes the surface of the fin 107 to further processing steps.

[0041] Once the first trench 103 has been filled with dielectric material, the dielectric material can be recessed away from the surface of the fin 107. Recessing can be performed to expose at least a portion of the sidewalls of the fin 107 adjacent to the top surface of the fin 107. The dielectric material can be recessed using wet etching by immersing the top surface of the fin 107 in an etchant such as HF, but other etchants (e.g., H2) and other methods (e.g., reactive ion etching, dry etching using etchants such as NH3 / NF3, chemical oxide removal, or dry chemical cleaning) can also be used. The dielectric material can be recessed to approximately [distance from the surface of the fin 107]. Peace Treaty The distance between them, for example, approximately In addition, the recess can remove any remaining dielectric material on the fin 107 to ensure that the fin 107 is exposed for further processing.

[0042] However, as those skilled in the art will recognize, the above steps may only be part of the overall process flow for filling and recessing the dielectric material. For example, the first trench 103 may also be formed and the first trench 103 filled with dielectric material using a lining step, a cleaning step, an annealing step, a gap filling step, a combination of these steps, etc. All possible processing steps are intended to be fully included within the scope of this embodiment.

[0043] After the first isolation region 105 has been formed, a dummy gate dielectric can be formed on each fin 107. Figures 1A-1B (not shown in the image) Dummy gate electrode above the dummy gate dielectric ( Figures 1A-1B (Not shown in the image), and spacer 113. In one embodiment, the dummy gate dielectric can be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known in the art and used to form the gate dielectric. Depending on the technique used to form the gate dielectric, the thickness of the dummy gate dielectric on the top of the fin 107 may differ from the thickness of the gate dielectric on the sidewalls of the fin 107.

[0044] The dummy gate dielectric can include materials such as silicon dioxide or silicon oxynitride, with a thickness ranging from approximately to approximately For example, about The dummy gate dielectric can be formed of a high dielectric constant (high k) material (e.g., having a relative dielectric constant greater than about 5), such as lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), or zirconium oxide (ZrO₂) or combinations thereof, with an equivalent oxide thickness of about [missing information]. To date Between, for example, about Or even smaller. Furthermore, any combination of silicon dioxide, silicon oxynitride, and / or high-k materials can also be used for the dummy gate dielectric.

[0045] The dummy gate electrode may comprise a conductive or non-conductive material and may be selected from the group consisting of: polysilicon, W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, and combinations thereof. The dummy gate electrode may be deposited by chemical vapor deposition (CVD), sputtering deposition, or other techniques known in the art and used for depositing conductive materials. The thickness of the dummy gate electrode may be approximately [missing information]. to approximately Within this range. The top surface of the dummy gate electrode may have a non-planar top surface and may be planarized before patterning or gate etching of the dummy gate electrode. In this case, ions may or may not be introduced into the dummy gate electrode. For example, ions may be introduced by ion implantation techniques.

[0046] Once formed, the dummy gate dielectric and dummy gate electrode can be patterned to form a series of dummy stacks on top of fin 107. The dummy stacks define multiple channel regions on each side of fin 107 located beneath the dummy gate dielectric. A gate mask can be deposited and patterned on the dummy gate electrode using deposition and photolithography techniques known in the art, for example. Figures 1A-1B (Not shown separately) to form a dummy stack. The gate mask can combine commonly used masking and sacrificial materials, such as (but not limited to) silicon oxide, silicon oxynitride, SiCON, SiC, SiOC and / or silicon nitride, and can be deposited to approximately To date The thickness between them. A dry etching process can be used to etch the dummy gate electrode and the dummy gate dielectric to form a pattern in the dummy stack.

[0047] Once the dummy stack has been patterned, spacers 113 can be formed. Spacers 113 can be formed on the opposite side of the dummy stack. Spacers 113 can be formed by blanket deposition of one or more spacer layers on the previously formed structure. The one or more spacer layers can include SiN, oxide nitride, SiC, SiON, SiOCN, SiOC, oxides, etc., and can be formed by methods used to form such layers, such as chemical vapor deposition (CVD), plasma-enhanced CVD, sputtering, and other methods known in the art. In embodiments with more than one spacer layer, the one or more spacer layers can be formed using similar materials in a similar manner, but different from each other, for example, by including materials with different component percentages and different curing temperatures and porosities. Furthermore, the one or more spacer layers can include different materials with different etch properties, or the same material as the dielectric material within the first isolation region 105. The one or more spacer layers can then be patterned, for example, by removing one or more spacer layers from the horizontal surface of the structure by one or more etching processes. Thus, one or more spacer layers are formed along the sidewalls of the dummy stack and are collectively referred to as spacers 113.

[0048] In one embodiment, the spacer 113 may be formed having approximately To date The thickness between them. Additionally, once spacers 113 are formed, adjacent stacked spacers 113 in a dummy stack can be separated from each other by a distance between approximately 5 nm and approximately 200 nm, for example, approximately 20 nm. However, any suitable thickness and distance can be used.

[0049] Figure 1A Further illustration shows the removal of fins 107 from those areas not protected by the dummy stack and spacers 113, as well as the regrowth of source / drain regions 109. Removal of fins 107 from those areas not protected by the dummy stack and spacers 113 can be performed by reactive ion etching (RIE) using the dummy stack and spacers 113 as a hard mask, or by any other suitable removal process. Removal can continue until fins 107 are flush with (as shown) or below the surface of the first isolation region 105.

[0050] Once these portions of fin 107 have been removed, a hard mask (not shown separately) is placed and patterned to cover the dummy gate electrode to prevent growth, and the source / drain regions 109 can be regrown to contact each fin 107. In one embodiment, the source / drain regions 109 can be regrown, and in some embodiments, the source / drain regions 109 can be regrown to form a stress source that can apply stress to the channel region of the fin 107 located beneath the dummy stack. In embodiments where the fin 107 comprises silicon and the FinFET is a p-type device, the source / drain regions 109 can be regrown via a selective epitaxial process using materials such as silicon or materials having a different lattice constant than the channel region (e.g., silicon-germanium). The epitaxial growth process can use precursors such as silane, dichlorosilane, germane, etc., and can last from about 5 minutes to about 120 minutes, for example, about 30 minutes.

[0051] In one embodiment, the source / drain region 109 can be formed with approximately To date The thickness between, and has a higher density than the first isolation region by approximately 105. To date The height between, for example, approximately In this embodiment, the source / drain region 109 can be formed with a height between about 5 nm and about 250 nm above the upper surface of the first isolation region 105, for example, about 100 nm. However, any suitable height can be used.

[0052] Once the source / drain region 109 is formed, dopant can be implanted into the source / drain region 109 to supplement the dopant in fin 107. For example, p-type dopant (e.g., boron, gallium, indium, etc.) can be implanted to form a PMOS device. Alternatively, n-type dopant (e.g., phosphorus, arsenic, antimony, etc.) can be implanted to form an NMOS device. Dummy stacks and spacers 113 can be used as masks for implanting these dopant. It should be noted that those skilled in the art will recognize that many other processes, steps, etc., can be used for dopant implantation. For example, those skilled in the art will recognize that various combinations of spacers and liners can be used to perform multiple implantations to form source / drain regions with a specific shape or characteristics suitable for a particular purpose. Any of these processes can be used for dopant implantation, and the above description does not imply that this embodiment is limited to the steps described above.

[0053] Additionally, the hard mask covering the dummy gate electrode during the formation of the source / drain region 109 is removed at this time. In one embodiment, the hard mask can be removed using, for example, a wet or dry etching process selective for the material of the hard mask. However, any suitable removal process can be used.

[0054] Figure 1A It is also shown that a first interlayer dielectric (ILD) layer 111 is formed on the dummy stack and the source / drain region 109. Figure 1A (Seen in dashed lines to more clearly illustrate the structure below). The first ILD layer 111 may comprise a material such as borosilicate glass (BPSG), but any suitable dielectric may also be used. The first ILD layer 111 may be formed using a process such as PECVD, but alternatively, other processes, such as LPCVD, may also be used. The first ILD layer 111 may be formed as approximately To date The thickness between them. Once formed, the first ILD layer 111 and the spacer 113 can be planarized using, for example, a planarization process (e.g., chemical mechanical polishing), but any suitable process can also be used.

[0055] Once the first ILD layer 111 has been formed, the dummy gate electrode and dummy gate dielectric are removed. In one embodiment, the dummy gate electrode and dummy gate dielectric can be removed using, for example, one or more wet or dry etching processes that utilize an etchant selective to the materials of the dummy gate electrode and dummy gate dielectric. However, any suitable removal process or one or more can be used.

[0056] Once the dummy gate electrode and dummy gate dielectric have been removed, multiple layers of the gate stack are deposited in their place, including a first dielectric material, a first conductive layer, a first metal material, a work function layer, and a first barrier layer. In one embodiment, the first dielectric material is a high-k material deposited by processes such as atomic layer deposition, chemical vapor deposition, etc., for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, and combinations thereof. The first dielectric material can be deposited to approximately [value missing]. To date The thickness can be between [a certain range], but any suitable material and thickness can also be used.

[0057] Optionally, the interface layer may be formed prior to the formation of the first dielectric material. In one embodiment, the interface layer may be a material such as silicon dioxide formed by a process such as in-situ vapor generation (ISSG). However, any suitable material or formation process may be used.

[0058] The first conductive layer can be a metal silicide material, such as titanium silicon nitride (TSN). In one embodiment, the first conductive layer can be formed using a deposition process such as chemical vapor deposition, but any suitable deposition method such as deposition followed by silicide can also be used to achieve approximately To date The thickness should be within a certain range. However, any suitable thickness can be used.

[0059] The first metallic material can be formed adjacent to the first dielectric material as a barrier layer and can be formed from a metal-containing material, such as TaN, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal nitrides, metal aluminates, zirconium silicate, zirconium aluminate, and combinations thereof. The first metallic material can be deposited to approximately [value missing] using deposition processes such as atomic layer deposition, chemical vapor deposition, sputtering, etc. To date The thickness can be between [thickness range], but any suitable deposition process or thickness can also be used.

[0060] A work function layer is formed on a first metallic material, and the material of the work function layer can be selected based on the type of the desired device. Exemplary p-type work function metals that may be included include Al, TiAlC, TiN, TaN, Ru, Mo, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals that may be included include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function value is associated with the material composition of the work function layer; therefore, the material of the work function layer is selected to adjust its work function value, thereby achieving the desired threshold voltage Vt in the device to be formed in the corresponding region. One or more work function layers can be deposited to approximately [value missing] by CVD, PVD, and / or other suitable processes. To date The thickness between.

[0061] The first barrier layer may be formed adjacent to the work function layer, and in certain embodiments, the first barrier layer may be similar to the first metallic material. For example, the first barrier layer may be formed of a metal-containing material, such as TiN, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal nitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, etc. Furthermore, the first barrier layer can be deposited to approximately [value missing] using deposition processes such as atomic layer deposition, chemical vapor deposition, sputtering, etc. To date The thickness can be between [thickness range], but any suitable deposition process or thickness can also be used.

[0062] The metal layer can be a material suitable for use as a seed layer to facilitate subsequent filling processes, or a material that can be used to help prevent or reduce the transport of fluorine atoms into the work function layer. In a particular embodiment, the metal layer can be crystalline tungsten (W), which is formed using, for example, an atomic layer deposition process in the absence of fluorine atoms, but any suitable deposition process can also be used. The metal layer can be formed to approximately [value missing]. To date The thickness between, for example, approximately To date between.

[0063] Once the metal layer has been formed, a filler material is deposited to fill the remaining portion of the opening. In one embodiment, the filler material may be a material such as Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, or combinations thereof, with a thickness of approximately [thickness missing]. To date Between, for example, about However, any suitable material can be used.

[0064] After the filler material has been deposited to fill and overfill the openings, the materials of the first dielectric material, first conductive layer, first metal material, work function layer, first barrier layer, metal layer, and filler material can be planarized to form the gate stack 115. In one embodiment, these materials can be planarized with the first ILD layer 111 using, for example, a chemical mechanical polishing process, but any suitable process, such as grinding or etching, can also be used. Furthermore, after planarization, the gate stack 115 can have a bottom width between about 10 nm and about 13 nm, but any suitable size can also be used.

[0065] Figures 1A-1BA recess in the gate stack 115 is also shown. After the material of the gate stack 115 has been formed and planarized, an etch-back process can be used to recess the material of the gate stack 115, which employs an etchant selective to the material of the gate stack 115. The etch-back process can be a wet or dry etching process employing an etchant selective to the material of the gate stack 115. In some embodiments, the material of the gate stack 115 can be recessed by a first distance between about 5 nm and about 150 nm, for example, about 120 nm. However, any suitable distance and any suitable etching process using any suitable etchant can be used. Furthermore, during the etch-back process, a portion of the spacer 113 can also be removed below the level of the first ILD layer 111.

[0066] Once the gate stack 115 has been recessed, a first metal layer 117 and a first hard mask layer 119 can be deposited. Once the material of the gate stack 115 has been recessed, the first metal layer 117 (e.g., a capping layer) is deposited to serve as an etch stop layer for subsequent processing (described further below). In one embodiment, the first metal layer 117 is a metallic material, such as tungsten (W), cobalt (Co), molybdenum (Mo), titanium nitride (TiN), ruthenium (Ru), aluminum (Al), zirconium (Zr), gold (Au), platinum (Pt), copper (Cu), alloys of these metallic materials, etc., and is formed using, for example, an atomic layer deposition process that allows selective growth on the material of the gate stack 115 without forming on other exposed surfaces. The first metal layer 117 can be formed to a thickness between about 1 nm and about 10 nm. However, any suitable material, formation process, and thickness can be used.

[0067] In one embodiment, the first hard mask layer 119 is a material with high etch selectivity to other materials used to form the gate stack 115, the first metal layer 117, the first ILD layer 111, and the spacer 113. In a particular embodiment, the first hard mask layer 119 may be a material such as lanthanum oxide, aluminum oxide, ytterbium oxide, tantalum carbonitride (TaCN), zirconium silicon (ZrSi), silicon carbonitride oxynitride (SiOCN), silicon carbonitride (SiOC), silicon carbonitride (SiCN), zirconium nitride (ZrN), aluminum zirconium oxide (ZrAlO), titanium oxide (TiO), tantalum oxide (TaO), zirconium oxide (ZrO), hafnium oxide (HfO), silicon nitride (SiN), hafnium silicon (HfSi), aluminum oxynitride (AlON), silicon carbide (SiC), and combinations thereof. The first hard mask layer 119 may be deposited using deposition processes such as plasma-enhanced atomic layer deposition (PEALD), thermal atomic layer deposition (thermal ALD), and plasma-enhanced chemical vapor deposition (PECVD). However, any suitable deposition process and process conditions can be used.

[0068] Once the first hard mask layer 119 has been deposited, it can be planarized to remove excess material. In one embodiment, a chemical mechanical polishing process, for example, can be used to planarize the first hard mask layer 119, whereby an etchant and an abrasive are used together with a rotating stage to react and remove excess material from the first hard mask layer 119. However, any suitable planarization process can be used to planarize the first hard mask layer 119 and the first ILD layer 111.

[0069] Once the first hard mask layer 119 has been planarized, it may have a first top thickness T1 between about 1 nm and about 30 nm, and a second bottom thickness T2 between about 1 nm and about 50 nm. Finally, the first hard mask layer 119 may have a first width W1 between about 2 nm and about 50 nm. However, any suitable thickness may be used.

[0070] Turn now Figure 1B (shown) Figure 1A A cross-sectional view of the structure, showing an additional gate stack 115 along a single fin 107 and a source / drain region 109. Figure 1B A source / drain contact 121 is shown formed through the first ILD layer 111 to contact some source / drain regions 109 (similar contacts formed along different cross sections to other source / drain regions). In one embodiment, the source / drain contact 121 can be formed initially by forming openings through the first ILD layer 111 using, for example, masking and etching processes. Once the source / drain regions 109 are exposed, optional silicide contacts (not shown separately) can be formed on the source / drain regions 109. Optional silicide contacts may include titanium (e.g., titanium silicide (TiSi)) to reduce the Schottky barrier height of the contacts. However, other metals, such as nickel, cobalt, erbium, platinum, palladium, etc., can also be used. Silicification can be performed by blanket deposition of a suitable metal layer, followed by an annealing step that reacts the metal with the exposed silicon beneath the source / drain regions 109. Unreacted metal is then removed, for example, by a selective etching process. The thickness of the optional silicide contacts can range from about 5 nm to about 50 nm.

[0071] Figure 1BThe remaining portion of the source / drain contact 121, which forms a physical connection with an optional silicide contact (if present) or source / drain region 109, is also shown. In one embodiment, the source / drain contact 121 may be a conductive material, such as W, Al, Cu, AlCu, W, Co, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Ni, Ti, TiAlN, Ru, Mo, or WN, but may also be any suitable material, such as aluminum, copper, alloys thereof, combinations thereof, etc., and may be deposited using deposition processes such as sputtering, chemical vapor deposition, electroplating, electroless plating, etc., to fill and / or overfill the openings within the first ILD layer 111.

[0072] Once the material of the source / drain contact 121 has been deposited, the material of the source / drain contact 121 can be planarized with the first ILD layer 111. In one embodiment, the material of the source / drain contact 121 can be planarized using, for example, a chemical mechanical polishing process, whereby an etchant and an abrasive are used with a rotating stage to react and remove excess material from the source / drain contact 121. However, any suitable planarization process can be used to planarize the source / drain contact 121.

[0073] Figure 2 The formation of a CESL 201 and a second ILD layer 203 on a planarized surface is illustrated. In one embodiment, the contact etch stop layer (CESL) 201 can be formed as a single layer or as multiple etch stop layers using materials such as lanthanum oxide, aluminum oxide, ytterbium oxide, tantalum carbonitride (TaCN), zirconium silicon (ZrSi), silicon carbonitride oxynitride (SiOCN), silicon carbonitride (SiOC), silicon carbonitride (SiCN), zirconium nitride (ZrN), aluminum zirconium oxide (ZrAlO), titanium oxide (TiO), tantalum oxide (TaO), zirconium oxide (ZrO), hafnium oxide (HfO), silicon nitride (SiN), hafnium silicon (HfSi), aluminum oxynitride (AlON), silicon oxide (SiO), silicon carbide (SiC), combinations thereof, etc., and can be blanket-deposited and / or conformally deposited. CESL 201 can be deposited using one or more low-temperature deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. According to some embodiments, CESL 201 can be deposited to approximately [value missing]. To date The total thickness between, for example, approximately However, any suitable etch stop material, any suitable number of etch stop layers, and any suitable combination thereof can be deposited to form CESL 201.

[0074] Once CESL 201 is formed, a second ILD layer 203 is deposited on top of CESL 201. The second ILD layer 203 can be formed from a dielectric material, such as lanthanum oxide, aluminum oxide, ytterbium oxide, tantalum carbonitride (TaCN), zirconium silicon (ZrSi), silicon carbonitride oxynitride (SiOCN), silicon carbonitride (SiOC), silicon carbonitride (SiCN), zirconium nitride (ZrN), aluminum zirconium oxide (ZrAlO), titanium oxide (TiO), tantalum oxide (TaO), zirconium oxide (ZrO), hafnium oxide (HfO), silicon nitride (SiN), hafnium silicon (HfSi), aluminum oxynitride (AlON), silicon oxide (SiO), silicon carbide (SiC), combinations thereof, etc., and formed by any acceptable process (e.g., CVD, PEALD, thermal ALD, PECVD, etc.). However, other suitable insulating materials (e.g., PSG, BSG, BPSG, USG, etc.) deposited by any suitable method (e.g., CVD, PECVD, flowable CVD, etc.) can also be used. After formation, the second ILD layer 203 can be cured, for example, by a UV curing process, and then planarized using a planarization process such as chemical mechanical polishing; however, any suitable process can also be used. Thus, the second ILD layer 203 can be formed with a thickness between about 5 nm and about 20 nm, for example, about 13 nm. However, any suitable thickness can be used.

[0075] Figure 3 It is shown that once the second ILD layer 203 has been formed and planarized, one or more etching processes are used to form the gate via contact 601 through the second ILD layer 203. Figure 3 Not shown in the text, but below about Figure 6 Contact via opening 301 (further shown and described) Figure 3 A single contact via opening 301 is shown for illustrative purposes, but multiple contact via openings 301 may be formed in a single die. According to some embodiments, the contact via opening 301 is formed through the second ILD layer 203, CESL 201, and the first hard mask layer 119. The contact via opening 301 can be formed using any combination of acceptable photolithography techniques and suitable etching techniques, such as dry etching processes (e.g., plasma etching, reactive ion etching (RIE), physical etching (e.g., ion beam etching (IBE))), wet etching, combinations thereof, etc.

[0076] In a particular embodiment, the contact via opening 301 may be formed to have a high aspect ratio. For example, the contact via opening 301 may have an aspect ratio between about 5 and about 8. However, any suitable aspect ratio and any suitable size may be used.

[0077] Figure 4 The use of the first process (in) is shown Figure 4 The process, denoted by curve 401, involves, for example, an NH3 treatment to treat the exposed sidewalls of the second ILD layer 203, CESL 201, the first hard mask layer 119, and the exposed portions of the first metal layer 117, in order to suppress metal growth on the dielectric sidewalls. In one embodiment, the first treatment 401 may be used to implant or react one or more dopants that help suppress the subsequent deposition of conductive material 501 (…). Figure 4 Not shown in the text, but below about Figure 5 (Shown and discussed further) Growth within the contact via opening 301. In some embodiments, the dopant may be nitrogen, hydrogen, a combination thereof, etc. However, any suitable one or more dopant may be used.

[0078] In one embodiment, a plasma process utilizing a dopant precursor can be used to implant the dopant or to react it with the exposed material. For example, in an embodiment where the dopant is nitrogen, the dopant precursor can be a nitrogen-containing precursor, such as ammonia (NH3), N2, or combinations thereof. However, any suitable precursor can be used.

[0079] To initiate the first process 401, the flow rate of the doped precursor can be set in the range of approximately 10 sccm to approximately 1000 sccm. A transformer-coupled plasma generator, an inductively coupled plasma system, a remote plasma generator, etc., can be used to ignite the doped precursor into plasma using a power between approximately 50 W and approximately 500 W, wherein the frequency of the plasma generator can be approximately 13.56 MHz or higher. Furthermore, the first process 401 can be performed at a pressure in the range of approximately 0.5 Torr to approximately 10 Torr. The temperature of the first process 401 can be set in the range of approximately 250 °C to approximately 450 °C. However, any suitable process parameters can be used.

[0080] During the first treatment 401, a dopant (e.g., nitrogen) may diffuse into and react with the material of the second ILD layer 203. This diffusion and reaction may result in the formation of a first treatment layer 403 along the sidewalls and top of the second ILD layer 203. For example, in an embodiment where the second ILD layer 203 is lanthanum oxide, the first treatment layer 403 may be lanthanum oxynitride. However, any suitable material may be used.

[0081] Once formed, the first processing layer 403 can have approximately To date The thickness between [the specified values]. Furthermore, the first processed layer 403 may have a dopant (e.g., nitrogen) concentration decreasing from the exposed surface, and the dopant concentration at the exposed surface is between about 0.3% atom and about 3% atom. However, any suitable concentration can be used.

[0082] Furthermore, during the first treatment 401, a dopant (e.g., nitrogen) will diffuse into and react with the material of CESL 201. This diffusion and reaction will result in the formation of a second treatment layer 405 along the sidewalls of CESL 201. For example, in an embodiment where CESL 201 is alumina, the second treatment layer 405 will be aluminum oxynitride. However, any suitable material can be used.

[0083] Once formed, the second processing layer 405 will have approximately To date The thickness between [the specified values]. Furthermore, the second processing layer 405 will have a dopant (e.g., nitrogen) concentration decreasing from the exposed surface, and the dopant concentration at the exposed surface will be between approximately 0.3% atom and approximately 3% atom. However, any suitable concentration can be used.

[0084] The first treatment 401 will additionally cause a dopant (e.g., nitrogen) to diffuse into and react with the material of the first hard mask layer 119. This diffusion and reaction will result in the formation of a third treatment layer 407 along the sidewalls of the first hard mask layer. For example, in an embodiment where the first hard mask layer is yttrium oxide, the second treatment layer 405 would be yttrium oxynitride. However, any suitable material can be used.

[0085] Once formed, the third processing layer 407 will have approximately To date The thickness between [the specified values]. Furthermore, the third processing layer 407 will have a dopant (e.g., nitrogen) concentration decreasing from the exposed surface, and the dopant concentration at the exposed surface will be between approximately 0.3% atom and approximately 3% atom. However, any suitable concentration can be used.

[0086] Finally, the first treatment 401 may cause a dopant (e.g., nitrogen) to diffuse into and react with the material of the first metal layer 117. This diffusion and reaction may result in the formation of a fourth treatment layer 409 along the exposed surface of the first metal layer 117. For example, in an embodiment where the first metal layer is tungsten, the fourth treatment layer 409 may be tungsten nitride. However, any suitable material may be used.

[0087] Once formed, the fourth processing layer 409 can have a thickness greater than that of the processed dielectric layer. In a particular embodiment, the fourth processing layer 409 can have a thickness 0 nm to 70 nm greater than that of the processed dielectric layer, for example, having a thickness of approximately To date The thickness between [the specified values]. Additionally, the fourth processing layer 409 may have a dopant (e.g., nitrogen) concentration decreasing from the exposed surface, and the dopant concentration at the exposed surface is between about 1% atom and about 30% atom, for example, between about 3% atom and about 30% atom. However, any suitable concentration can be used.

[0088] Figure 5 This illustrates that once processing has been performed, the contact via opening 301 can be filled or overfilled with one or more conductive materials 501, such that the one or more conductive materials 501 are in direct physical contact with the first processing layer 403, the second processing layer 405, the third processing layer 407, and the fourth processing layer 409 without an intermediate liner. According to embodiments, the conductive material can be a high-performance, low-resistance material, such as tungsten, ruthenium, molybdenum, copper, titanium, titanium nitride, cobalt, aluminum, combinations thereof, etc. The one or more conductive materials 501 can be deposited using a chemical vapor deposition process, wherein the precursor may or may not have bottom-up filling capability. For example, in embodiments using non-bottom-up precursors, materials such as Ru(CO) can be used. 12 Precursors such as (when depositing ruthenium), W(CO)6 (when depositing tungsten), and MoO2Cl2 (when depositing molybdenum) can be used. However, any other suitable method can also be used, such as selective, bottom-up deposition processes, such as electroplating, electroless plating, or combinations thereof.

[0089] In embodiments where chemical vapor deposition (CVD) is used to deposit one or more conductive materials 501, the presence of the first processing layer 403, the second processing layer 405, and the third processing layer 407 limits the CVD process's ability to deposit material along the sidewalls of the dielectric material (e.g., the first hard mask layer 119, CESL 201, and the second ILD layer 203) and to form larger grains during deposition. Specifically, the presence of dopants limits the ability of the conductive material to nucleate along the sidewalls, without significantly limiting the ability of the conductive material to nucleate and grow along the bottom. Therefore, in embodiments using non-bottom-up precursors, a more bottom-up deposition process can be achieved without relying on a more limited list of potential precursors. In other words, a pseudo-bottom-up deposition process can be achieved without using bottom-up precursors. For larger, more bottom-up processes, pinch-off is less likely to occur, meaning fewer and / or smaller voids (or even no voids at all) are formed, allowing for the use of higher-performance (e.g., lower-resistance) materials for one or more conductive materials 501.

[0090] Figure 6It is shown that once one or more conductive materials 501 have been deposited, a planarization process such as CMP can be performed to remove excess material from the surface of the second ILD layer 203. The remaining conductive material forms a gate via contact 601 in the opening, and the gate via contact 601 can have a third thickness T3 between about 5 nm and about 40 nm. However, any suitable thickness can be used.

[0091] Figure 7 A dielectric cap 701 is shown formed over a gate via contact 601. In one embodiment, forming the dielectric cap 701 includes a filling step to fill any unwanted recesses (not seen in that particular cross-section but may exist at different points on the substrate 101), followed by a planarization step to planarize the top surface of the dielectric cap 701. According to some embodiments, the dielectric cap 701 comprises silicon oxide, but any suitable material may be used, and it may be deposited using chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, etc. However, any suitable deposition and / or planarization method may be used.

[0092] Figure 8 A source / drain contact opening 801 is shown. In one embodiment, the source / drain contact opening 801 can be formed using one or more etching processes. According to some embodiments, the source / drain contact opening 801 is formed through the second ILD layer 203 and CESL 201. The source / drain contact opening 801 can be formed using any combination of acceptable photolithography techniques and suitable etching techniques, such as dry etching processes (e.g., plasma etching, reactive ion etching (RIE), physical etching (e.g., ion beam etching (IBE)), wet etching, combinations thereof, etc.). However, any suitable etching process can be used to form the source / drain contact opening 801.

[0093] Figure 9 A recessed process that can be used to extend the source / drain contact opening 801 into the material of the source / drain contact 121 is illustrated. In one embodiment, the extension of the source / drain contact opening 801 can be performed using one or more etchants selective for the material of the source / drain contact 121, employing either an isotropic etching process (e.g., wet etching) or an anisotropic etching process (e.g., reactive ion etching).

[0094] In embodiments where an isotropic etching process is used to recess the material of the source / drain contact 121, the recess extends the source / drain contact opening 801 into the material of the source / drain contact 121 and also extends below CESL 201. For example, the recess extends the source / drain contact opening 801 into the material of the source / drain contact 121 by a first distance D1 of approximately 2 nm to approximately 20 nm, and also extends the source / drain contact opening 801 below CESL 201 by a second distance D2 of approximately 1 nm to approximately 10 nm. In some embodiments, the second distance D2 may be sufficient to expose the sidewalls of the first hard mask layer 119, but in other embodiments, the first hard mask layer 119 is not exposed.

[0095] Figure 10 This illustrates that once the source / drain contact opening 801 has been formed, a second process can be performed on the exposed surfaces of the second ILD layer 203, CESL 201, source / drain contact 121, and the first hard mask layer 119 (if exposed). Figure 10 (Indicated by the arrow marked 1001). In one embodiment, the second process 1001 can be performed using a process and parameters similar to those described above with respect to the first process 401. For example, the second process 1001 could be a plasma treatment using ammonia as a precursor to treat exposed surfaces with nitrogen. However, any suitable process and parameters can be used.

[0096] During the second processing 1001, a dopant (e.g., nitrogen) may diffuse into and react with the material of the second ILD layer 203. This diffusion and reaction may result in the formation of a fifth processing layer 1003 along the sidewalls of the second ILD layer 203 within the source / drain contact opening 801. For example, in an embodiment where the second ILD layer 203 is lanthanum oxide, the fifth processing layer 1003 may be lanthanum oxynitride. However, any suitable material may be used.

[0097] Once formed, the fifth processing layer 1003 can have approximately To date The thickness between [the specified values]. Furthermore, the fifth processing layer 1003 may have a dopant (e.g., nitrogen) concentration decreasing from the exposed surface, and the dopant concentration at the exposed surface is between about 0.3% atom and about 3% atom. However, any suitable concentration can be used.

[0098] Furthermore, during the second process 1001, a dopant (e.g., nitrogen) may diffuse into and react with the material of CESL 201 in the source / drain contact opening 801. This diffusion and reaction may result in the formation of a sixth processing layer 1005 along the sidewalls of CESL 201. For example, in an embodiment where CESL 201 is alumina, the sixth processing layer 1005 may be aluminum oxynitride. However, any suitable material may be used.

[0099] Once formed, the sixth processing layer 1005 can have approximately To date The thickness between [the specified values]. Furthermore, the sixth processing layer 1005 may have a dopant (e.g., nitrogen) concentration decreasing from the exposed surface, and the dopant concentration at the exposed surface is between about 0.3% atom and about 3% atom. However, any suitable concentration can be used.

[0100] The second processing 1001 may also (if the first hard mask layer 119 is exposed during the recess) additionally cause dopant (e.g., nitrogen) to diffuse into and react with the material of the first hard mask layer 119. This diffusion and reaction may result in the formation of a seventh processing layer along the sidewalls of the first hard mask layer 119. Figure 10 (Not shown separately). For example, in an embodiment where the first hard mask layer 119 is yttrium oxide, the seventh processing layer could be yttrium oxynitride. However, any suitable material can be used.

[0101] Once formed, the seventh processing layer can have approximately To date The thickness between [the specified values]. Furthermore, the third processing layer 407 may have a dopant (e.g., nitrogen) concentration decreasing from the exposed surface, and the dopant concentration at the exposed surface is between about 0.3% atom and about 3% atom. However, any suitable concentration can be used.

[0102] Finally, the second treatment 1001 may cause a dopant (e.g., nitrogen) to diffuse into and react with the material of the source / drain contact 121. This diffusion and reaction may result in the formation of an eighth treatment layer 1009 along the exposed surface of the source / drain contact 121. For example, in an embodiment where the source / drain contact 121 is tungsten, the eighth treatment layer 1009 may be tungsten nitride. However, any suitable material may be used.

[0103] Once formed, the eighth processing layer 1009 can have a thickness greater than that of the processed dielectric layer. For example, the eighth processing layer 1009 can have a thickness of 0 nm to 70 nm greater than that of the processed dielectric layers (e.g., the fifth processing layer 1003 and the sixth processing layer 1005), for example, approximately To date The thickness between [the specified values]. Additionally, the eighth processing layer 1009 may have a dopant (e.g., nitrogen) concentration decreasing from the exposed surface, and the dopant concentration at the exposed surface is between about 1% atom and about 30% atom. However, any suitable concentration can be used.

[0104] Figure 11 This illustrates that once the second process 1001 has been performed, one or more via drain contact materials 1101 are deposited to fill and / or overfill the source / drain contact opening 801. In one embodiment, the one or more via drain contact materials 1101 can be used with one or more conductive materials 501 (as described above). Figure 5 (Description) Similar methods and materials can be used for deposition. However, any suitable materials and methods can be used.

[0105] Figure 12A It is shown that once one or more via drain contact materials 1101 have been deposited, the via drain contact material 1101 can be planarized to remove any excess material and form the via drain contact 1201. In one embodiment, planarization can be performed using chemical mechanical polishing, grinding, one or more etching processes, combinations thereof, etc. The via drain contact 1201 (without recesses) can be formed to a fourth thickness T4 between about 5 nm and about 40 nm. However, any suitable process can be used.

[0106] Furthermore, once the via drain contact 1201 has been formed using a planarization process, the second ILD layer 203 can have a fifth thickness T5 between approximately 3 nm and approximately 40 nm. At this point, the underlying CESL 201 can have a sixth thickness T6 between approximately 3 nm and approximately 20 nm. However, any suitable thickness can be used.

[0107] By forming the via drain contact 1201 as described, the via drain contact 1201 can have a bowl shape 1204 embedded within the source / drain contact 121. In a particular embodiment, the bowl shape can extend into the source / drain contact 121 from about 2 nm to about 20 nm. However, any suitable size can be used.

[0108] Figure 12B The diagram illustrates the formation of a second CESL 1203, a third ILD layer 1205, and an interconnect 1207. In one embodiment, the second CESL 1203 and the third ILD layer 1205 may be sequentially deposited over both the via drain contact 1201 and the gate via contact 601. In one embodiment, the second CESL 1203 may be used in conjunction with CESL 201 (as described above). Figure 2(Description) Similar materials and deposition processes, while the third ILD layer 1205 can be used with the second ILD layer 203 (as described above). Figure 2 (Description) Similar materials and deposition processes. However, any suitable materials and deposition processes can be used.

[0109] Once the second CESL 1203 and the third ILD layer 1205 have been formed, interconnection openings are formed through the second CESL 1203 and the third ILD layer 1205. Figure 12B (Not shown separately) to expose both the via drain contact 1201 and the gate via contact 601. In one embodiment, the interconnect opening can be formed using one or more photolithographic masking and etching processes. However, any suitable process can be used for the interconnect opening.

[0110] Once the interconnect openings have been formed, one or more conductive materials can be deposited into them. In one embodiment, the one or more conductive materials may include a barrier layer and a filler material. Figure 12B (Not shown separately). In one embodiment, the barrier layer may be formed of a material such as one or more layers of a metal-containing material, for example, TiN, TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal nitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, etc. The barrier layer may be deposited using deposition processes such as atomic layer deposition, chemical vapor deposition, etc., but any suitable deposition process may also be used.

[0111] Once the barrier layer has been formed, a filler material can be deposited to fill and / or overfill the remaining portion of the interconnect openings and electrically connect the via drain contact 1201 and the gate via contact 601. In one embodiment, the filler material may include copper (Cu), aluminum (Al), tungsten (W), or other suitable conductive materials, and can be deposited using ALD, CVD, PVD, electroplating, combinations thereof, etc. However, any suitable material and any suitable process can be used.

[0112] After the filler material and barrier layer have been deposited, the excess portion of the filler material and barrier layer outside the interconnect opening is removed to form the interconnect 1207. In one embodiment, for example, a chemical mechanical polishing process is used to remove the excess portion. However, any suitable removal process can be used to planarize the filler material and barrier layer, such as grinding or even a series of etching steps.

[0113] By utilizing the process described herein, one or more via drain contact materials 1101 can be deposited using a pseudo-bottom-up process without the need for very specific precursors, which would otherwise limit the types of materials that can be used. For example, materials such as Ru(CO) can be used by treating the sidewalls with a dopant (e.g., nitrogen). 12 Precursors such as W(CO)6 and MoO2Cl2 are used to deposit ruthenium, tungsten, or molybdenum. This process allows the use of these materials without the use of bottom-up precursors, which helps to avoid premature pinch-off, voids, or other gaps within the via drain contact 1201.

[0114] Figures 13A-13B Another embodiment is shown, in which the second process 1001 is not used during the formation of the via drain contact 1201. First look... Figure 13A The via drain contact material 1101 is deposited after the source / drain contact opening 801 is formed. The via drain contact material 1101 can be as described above. Figure 11 Deposition is carried out as described.

[0115] However, in this embodiment, the via drain contact material 1101 is deposited without the intervention of the second processing 1001. Therefore, the fifth processing layer 1003, the sixth processing layer 1005, the seventh processing layer, and the eighth processing layer 1009 are not formed and are not present between the via drain contact material 1101 and the second ILD layer 203, between the via drain contact material 1101 and the CESL 201, and between the via drain contact material 1101 and the source / drain contact 121. Therefore, the via drain contact material 1101 is formed to directly contact the unprocessed portions of each of the second ILD layer 203, the CESL 201, and the source / drain contact 121.

[0116] Turn now Figure 13B Once deposited, the via drain contact material 1101 is planarized to form the via drain contact 1201. In one embodiment, the via drain contact material 1101 can be as described above. Figure 12A The material 1101 of the via drain contact can be planarized. For example, a chemical mechanical polishing process can be used to planarize the material. However, any suitable method can be used.

[0117] However, in this embodiment, by not using the second process 1001, the via drain contact 1201 is formed without the intervention of the second process 1001. Therefore, the fifth processing layer 1003, the sixth processing layer 1005, the seventh processing layer, and the eighth processing layer 1009 are not formed and are not present between the via drain contact 1201 and the second ILD layer 203, between the via drain contact 1201 and the CESL 201, and between the via drain contact 1201 and the source / drain contact 121. Therefore, the via drain contact 1201 is formed to directly contact the unprocessed portions of each of the second ILD layer 203, the CESL 201, and the source / drain contact 121.

[0118] Figures 14A-14C Another embodiment utilizing both the first process 401 and the second process 1001 is shown. However, in this embodiment, the recessing of the source / drain contact 121 (as described above) is not performed. Figure 9 (as stated). Conversely, as... Figure 14A As shown, instead of recessing the source / drain contact 121, the source / drain contact 121 is used as an etch stop during the formation of the source / drain contact opening 801. Therefore, the top surface of the source / drain contact 121 is flat within the source / drain contact opening 801.

[0119] Figure 14A It is also shown that once the source / drain contact opening 801 has been formed (the source / drain contact 121 is not recessed), a second process 1001 is performed, thereby forming a fifth process layer 1003 along the sidewall of the second ILD layer 203, a sixth process layer 1005 along the sidewall of the CESL 201, and an eighth process layer 1009 along the exposed portion of the source / drain contact 121. However, since the source / drain contact 121 is not recessed, the width of the eighth process layer 1009 is not greater than the width of the source / drain contact opening 801, and the eighth process layer 1009 does not extend below the CESL 201 or the second ILD layer 203.

[0120] Turn now Figure 14B Once the fifth processing layer 1003, the sixth processing layer 1005, and the eighth processing layer 1009 have been formed using the second processing 1001, the via drain contact material 1101 is deposited. In one embodiment, the via drain contact material 1101 can be as described above regarding... Figure 11 Deposition should be performed as described. However, any suitable materials and processes can be used.

[0121] However, in this embodiment, the via drain contact material 1101 is deposited without recessing the source / drain contact 121. Therefore, the via drain contact material 1101 is deposited such that it remains outside the source / drain contact 121 and above the first ILD layer 111.

[0122] Turn now Figure 14C Once deposited, the via drain contact material 1101 is planarized to form the via drain contact 1201. In one embodiment, the via drain contact material 1101 can be as described above. Figure 12A Planarization can be performed as described. For example, a chemical mechanical polishing process can be used to planarize the via drain contact material 1101. However, any suitable method can be used.

[0123] However, in this embodiment, the via drain contact 1201 is formed without the source / drain contact 121 being recessed. Therefore, the via drain contact 1201 remains outside the source / drain contact 121, has a flat bottom surface, and remains above the first ILD layer 111.

[0124] Figures 15A-15B Another embodiment is shown in which the second process 1001 is not used during the formation of the via drain contact 1201. However, in this embodiment, the source / drain contact 121 is not recessed (as mentioned above regarding...). Figures 14A-14C (as mentioned above). First, let's look at... Figure 15A After forming the source / drain contact opening 801, via drain contact material 1101 is deposited, but the source / drain contact 121 is not recessed. The via drain contact material 1101 can be as described above regarding... Figure 11 Deposition is carried out as described.

[0125] However, in this embodiment, the via drain contact material 1101 is deposited without the intervention of the second processing 1001. Therefore, the fifth processing layer 1003, the sixth processing layer 1005, and the eighth processing layer 1009 are not formed and are not present between the via drain contact material 1101 and the second ILD layer 203, between the via drain contact material 1101 and the CESL 201, and between the via drain contact material 1101 and the source / drain contact 121. Therefore, the via drain contact material 1101 is formed to directly contact the unprocessed portions of each of the second ILD layer 203, the CESL 201, and the source / drain contact 121.

[0126] Turn now Figure 15BOnce deposited, the via drain contact material 1101 is planarized to form the via drain contact 1201. In one embodiment, the via drain contact material 1101 can be as described above. Figure 12A Planarization can be performed as described. For example, a chemical mechanical polishing process can be used to planarize the via drain contact material 1101. However, any suitable method can be used.

[0127] However, in this embodiment, by not using the second process 1001, the via drain contact 1201 is formed without the intervention of the second process 1001. Therefore, the fifth processing layer 1003, the sixth processing layer 1005, and the eighth processing layer 1009 are not formed and are not present between the via drain contact 1201 and the second ILD layer 203, between the via drain contact 1201 and the CESL 201, and between the via drain contact 1201 and the source / drain contact 121. Therefore, the via drain contact 1201 is formed to directly contact the unprocessed portions of each of the second ILD layer 203, the CESL 201, and the source / drain contact 121.

[0128] Figures 16A-16E Another embodiment is shown, in which the second hard mask layer 1601 is used in conjunction with the first hard mask layer 119. In one embodiment, the second hard mask layer 1601 may be formed as follows: initially employing as described above regarding... Figure 1B The structure is described above, and the material of the source / drain contact 121 is recessed using an etch-back process, for example, employing an etchant selectively applied to the material of the source / drain contact 121. The etch-back process can be a wet or dry etching process employing an etchant selectively applied to the material of the source / drain contact 121. However, any suitable etching process employing any suitable etchant can be used.

[0129] Once the source / drain contact 121 has been recessed, the material for the second hard mask layer 1601 can be deposited. In one embodiment, the second hard mask layer 1601 can be a dielectric material different from that of the first hard mask layer 119, and can be, for example, lanthanum oxide, aluminum oxide, ytterbium oxide, tantalum carbonitride (TaCN), zirconium silicon (ZrSi), silicon oxycarbonitride (SiOCN), silicon oxycarbonitride (SiOC), silicon carbonitride (SiCN), zirconium nitride (ZrN), aluminum zirconium oxide (ZrAlO), titanium oxide (TiO), tantalum oxide (TaO), zirconium oxide (ZrO), hafnium oxide (HfO), silicon nitride (SiN), hafnium silicon (HfSi), aluminum oxynitride (AlON), silicon carbide (SiC), zinc oxide, silicon oxide, combinations thereof, etc. The material for the second hard mask layer 1601 can be deposited using deposition processes such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, etc. However, any suitable material and deposition process can be used.

[0130] Once the material of the second hard mask layer 1601 has been deposited, the material of the second hard mask layer 1601 can be planarized to remove excess material over the first ILD layer 111. In one embodiment, the second hard mask layer 1601 can be planarized using a chemical mechanical polishing process, a grinding process, or even a series of etching steps. Once planarized, the second hard mask layer 1601 can have a seventh thickness T7 between about 2 nm and about 20 nm. However, any suitable thickness can be used.

[0131] Looking at it now Figure 16B Once the second hard mask layer 1601 has been formed, the process is as described above. Figures 2-7 The process continues. For example, once the second hard mask layer 1601 has been formed, CESL 201 and the second ILD layer 203 (as described above) are deposited. Figure 2 As described above), forming a contact element through-hole opening 301 (as shown in the description). Figure 3 As described above), execute the first process 401 (as... Figure 4 As described above), one or more conductive materials 501 are deposited (e.g., ...). Figure 5 The above) and then flattened (as described) Figure 6 As described above), and the deposited dielectric top cover 701 (as Figure 7 The above).

[0132] Figure 16BA third opening 1603 is also shown formed through the second ILD layer 203, CESL 201, and the second hard mask layer 1601 to expose the source / drain contact 121. In one embodiment, the third opening 1603 can be formed using one or more etching processes. For example, the third opening 1603 can be formed using any combination of acceptable photolithography and suitable etching techniques, such as dry etching processes (e.g., plasma etching, reactive ion etching (RIE), physical etching (e.g., ion beam etching (IBE)), wet etching, combinations thereof, etc.). However, any suitable etching process can be used to form the contact via opening.

[0133] Figure 16C This shows that once the third opening 1603 has been formed, the third process is performed (in...). Figure 16C (Represented by the wavy line labeled 1605). In one embodiment, the third process 1605 can be performed using a method similar to that of the first process 401 and the second process 1001, for example, by using a plasma process with a precursor such as ammonia. However, any suitable processing technology can be used.

[0134] In an embodiment where the third process 1605 is an ammonia plasma process, the third process 1605 may form a fifth process layer 1003 along the second ILD layer 203, a sixth process layer 1005 along the CESL 201, and an eighth process layer 1009 along the source / drain contact 121. However, in this embodiment, the third process 1605 may also form a ninth process layer 1607 along the exposed portion of the second hard mask layer 1601.

[0135] For example, the third process 1605 may cause a dopant (e.g., nitrogen) to diffuse into and react with the material of the second hard mask layer 1601. This diffusion and reaction may result in the formation of a ninth processing layer 1607 along the sidewalls of the second hard mask layer 1601. For example, in an embodiment where the second hard mask layer 1601 is tantalum carbonitride, the ninth processing layer 1607 may be tantalum carbonitride oxide. However, any suitable material may be used.

[0136] Once formed, the ninth processing layer 1607 can have approximately To date The thickness between [the specified values]. Furthermore, the ninth processing layer 1607 may have a dopant (e.g., nitrogen) concentration decreasing from the exposed surface, and the dopant concentration at the exposed surface is between about 0.3% atom and about 3% atom. However, any suitable concentration can be used.

[0137] Next, let's look at... Figure 16DThis illustrates a continuation of the process, wherein via drain contact material 1101 is deposited to fill and / or overfill the third opening 1603. In one embodiment, the via drain contact material 1101 is as described above regarding... Figure 11 Deposition should be performed as described. However, any suitable materials and processes can be used.

[0138] Figure 16E The planarization of the via drain contact material 1101 is shown. In one embodiment, it can be done as described above regarding... Figure 12A Planarization is performed as described to form the via drain contact 1201. However, any suitable method can be used.

[0139] Figures 17A-17D Another embodiment is shown, in which the source / drain contact 121 is recessed and a second hard mask layer 1601 is used. In this embodiment and as shown... Figure 17A As shown above regarding Figure 16B The third opening 1603 is formed as described above. However, instead of stopping the formation of the third opening 1603 when the source / drain contact 121 is exposed, the formation of the third opening 1603 continues to form a recess within the source / drain contact 121. In one embodiment, the source / drain contact 121 can be formed as described above. Figure 9 It is dented as described. However, any suitable method can be used.

[0140] Next, let's look at... Figure 17B Once the source / drain contact 121 has been recessed, a third process 1605 can be performed. In one embodiment, the third process 1605 can be as described above regarding... Figure 16C The process is performed as described, for example, using plasma treatment with ammonia. In such an embodiment, the third process 1605 is used to form the fifth process layer 1003, the sixth process layer 1005, the ninth process layer 1607, and the eighth process layer 1009. However, in this embodiment, the eighth process layer 1009 is formed along a recess within the source / drain contact 121.

[0141] Figure 17C It is shown that once the third process 1605 has been performed, the third opening 1603 (including the recess within the source / drain contact 121) is filled with the via drain contact material 1101. In one embodiment, the via drain contact material 1101 may be deposited to fill and / or overfill the third opening 1603, as described above regarding... Figure 11 However, any suitable material and deposition method can be used.

[0142] Figure 17DIt is shown that once the via drain contact material 1101 has been deposited, the via drain contact material 1101 is planarized to form the via drain contact 1201. In one embodiment, the via drain contact material 1101 can be as described above regarding... Figure 12A Planarization can be performed as described (e.g., using a chemical mechanical polishing process). However, any suitable method can be used.

[0143] Figures 18A-18C Another embodiment is shown in which a single processing step (e.g., first process 401) is used to process both the contact via opening 301 and the source / drain contact opening 801. In this embodiment, the contact via opening 301 is as described above regarding... Figure 3 It is formed as described. However, the contact via opening 301 is not processed and filled before the source / drain contact opening 801 is formed. In this embodiment, the source / drain contact opening 801 is formed simultaneously with the contact via opening 301, or, although formed separately, it is still before the contact via opening 301 is processed and filled. Therefore, both the contact via opening 301 and the source / drain contact opening 801 exist before the first process 401.

[0144] Figure 18B This illustrates that once both the contact via opening 301 and the source / drain contact opening 801 have been formed, a first process 401 can be performed simultaneously on both openings. In one embodiment, the first process 401 can be as described above regarding... Figure 4 It shall be performed as described. For example, a plasma process using ammonia as a precursor can be used to treat exposed surfaces and form a first treatment layer 403, a second treatment layer 405, a third treatment layer 407, a fourth treatment layer 409, and also a fifth treatment layer 1003, a ninth treatment layer 1607, and an eighth treatment layer 1009. However, any suitable method may be used.

[0145] Figure 18C The diagram illustrates a via opening 301 for the filler contact and a source / drain contact opening 801. In one embodiment, the via opening 301 and the source / drain contact opening 801 can utilize the methods described above. Figure 5 or Figure 11 The materials or processes described herein are filled with one or more conductive materials (e.g., one or more conductive materials 501 or via drain contact material 1101). However, any suitable materials and methods may be used.

[0146] Figure 18CAdditionally, a planarization process for planarizing one or more conductive materials to form gate via contact 601 and via drain contact 1201 is shown. In one embodiment, the one or more conductive materials can be as described above. Figure 12A Planarization can be performed as described (e.g., using a chemical mechanical polishing process). However, any suitable method can be used.

[0147] By utilizing the process described herein, a pseudo-bottom-up process can be used to form the gate via contact 601 and / or the via drain contact 1201 without using very specific precursors, which would otherwise limit the materials that can be used. For example, by treating the sidewalls with a dopant (e.g., nitrogen), materials such as Ru(CO) can be used. 12 Precursors such as W(CO)6 and MoO2Cl2 are used to deposit the required material. This process allows the use of these precursors instead of bottom-up precursors, which helps to avoid premature pinch-off, voids, or other gaps in the gate via contact 601 and / or via drain contact 1201.

[0148] In one embodiment, a method of manufacturing a semiconductor device includes: depositing an etch stop layer over a first hard mask material, the first hard mask material being over a gate stack; depositing an interlayer dielectric over the etch stop layer; forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack; and treating the sidewalls of the first opening with a first dopant to form a first processing region within the interlayer dielectric, a second processing region within the etch stop layer, a third processing region within the first hard mask material, and a fourth processing region within the conductive portion, wherein, after treatment, the fourth processing region has a higher concentration of the first dopant than the first processing region. In one embodiment, the first dopant comprises nitrogen. In one embodiment, the processing sidewalls at least partially comprise a plasma process. In one embodiment, the plasma process utilizes ammonia as a precursor. In one embodiment, the first concentration of the first dopant in the fourth processing region is between about 3% atom and about 30% atom. In one embodiment, the method further includes: depositing a conductive material within the first opening, the conductive material being in solid contact with the first processing region without an intermediate liner. In one embodiment, the method further includes: forming a second opening through an interlayer dielectric and an etch stop layer to expose a source / drain contact; and depositing a conductive material into the second opening without treating the second opening.

[0149] In another embodiment, a method of manufacturing a semiconductor device includes: forming a first opening through a dielectric layer, a contact etch stop layer, and a first hard mask material to expose conductive portions of a gate stack; treating the sidewalls of the first opening with a first plasma from a nitrogen-containing precursor; filling the first opening with a first conductive material; forming a second opening through the dielectric layer and the contact etch stop layer to expose first source / drain contacts; treating the sidewalls of the second opening with a second plasma; and filling the second opening with a second conductive material. In one embodiment, forming the second opening involves forming a recess within the first source / drain contacts. In one embodiment, forming the second opening does not involve forming a recess within the first source / drain contacts. In one embodiment, treating the sidewalls of the first opening and treating the sidewalls of the second opening are performed simultaneously. In one embodiment, forming the second opening involves forming the second opening through a second hard mask material overlying the first source / drain contacts. In one embodiment, forming the second opening involves forming a recess within the first source / drain contacts. In one embodiment, the nitrogen-containing precursor is ammonia.

[0150] In yet another embodiment, a semiconductor device includes: a gate stack over a semiconductor fin; a first hard mask material overlying the gate stack, the first hard mask material including a first processing region; an etch stop layer overlying the first hard mask material, the etch stop layer including a second processing region; a dielectric layer overlying the etch stop layer, the dielectric layer including a third processing region; and a conductive material extending through and in physical contact with the first, second, and third processing regions, wherein the conductive material also in physical contact with a fourth processing region located within the gate stack. In one embodiment, each of the first, second, third, and fourth processing regions includes nitrogen. In one embodiment, the first processing region has a nitrogen concentration between about 0.3% atom and about 3% atom. In one embodiment, the fourth processing region has a nitrogen concentration between about 3% atom and about 30% atom. In one embodiment, the semiconductor device further includes: a second conductive material extending through and physically contacting the unprocessed portions of the dielectric layer and the etch stop layer to make physical contact with source / drain contacts. In one embodiment, the second conductive material extends into the source / drain contacts.

[0151] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0152] Example 1 is a method of manufacturing a semiconductor device, the method comprising: depositing an etch stop layer on a first hard mask material, the first hard mask material being on a gate stack; depositing an interlayer dielectric on the etch stop layer; forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack; and treating the sidewalls of the first opening with a first dopant to form a first processing region within the interlayer dielectric, a second processing region within the etch stop layer, a third processing region within the first hard mask material, and a fourth processing region within the conductive portion, wherein, after the treatment, the fourth processing region has a higher concentration of the first dopant than the first processing region.

[0153] Example 2 is the method described in Example 1, wherein the first dopant comprises nitrogen.

[0154] Example 3 is the method described in Example 2, wherein processing the sidewall at least partially includes a plasma process.

[0155] Example 4 is the method described in Example 3, wherein the plasma process utilizes ammonia as a precursor.

[0156] Example 5 is the method described in Example 4, wherein the first concentration of the first dopant in the fourth processing region is between about 3% atom and about 30% atom.

[0157] Example 6 is the method of Example 1, further comprising: depositing a conductive material within the first opening, the conductive material being in solid contact with the first processing region without an intermediate liner.

[0158] Example 7 is the method of Example 1, further comprising: forming a second opening through the interlayer dielectric and the etch stop layer to expose the source / drain contacts; and depositing a conductive material into the second opening without treating the second opening.

[0159] Example 8 is a method of manufacturing a semiconductor device, the method comprising: forming a first opening through a dielectric layer, a contact etch stop layer, and a first hard mask material to expose a conductive portion of a gate stack; treating the sidewalls of the first opening with a first plasma from a nitrogen-containing precursor; filling the first opening with a first conductive material; forming a second opening through the dielectric layer and the contact etch stop layer to expose a first source / drain contact; treating the sidewalls of the second opening with a second plasma; and filling the second opening with a second conductive material.

[0160] Example 9 is the method described in Example 8, wherein forming the second opening forms a recess within the first source / drain contact.

[0161] Example 10 is the method described in Example 8, wherein forming the second opening does not form a recess within the first source / drain contact.

[0162] Example 11 is the method described in Example 8, wherein processing the sidewall of the first opening and processing the sidewall of the second opening are performed simultaneously.

[0163] Example 12 is the method described in Example 8, wherein the second opening is formed by passing through a second hard mask material overlying the first source / drain contact.

[0164] Example 13 is the method described in Example 12, wherein forming the second opening forms a recess within the first source / drain contact.

[0165] Example 14 is the method described in Example 8, wherein the nitrogen-containing precursor is ammonia.

[0166] Example 15 is a semiconductor device comprising: a gate stack over a semiconductor fin; a first hard mask material overlying the gate stack, the first hard mask material including a first processing region; an etch stop layer overlying the first hard mask material, the etch stop layer including a second processing region; a dielectric layer overlying the etch stop layer, the dielectric layer including a third processing region; and a conductive material extending through the first processing region, the second processing region, and the third processing region and substantially contacting the first processing region, the second processing region, and the third processing region, wherein the conductive material also substantially contacts a fourth processing region located within the gate stack.

[0167] Example 16 is the semiconductor device described in Example 15, wherein each of the first processing region, the second processing region, the third processing region, and the fourth processing region comprises nitrogen.

[0168] Example 17 is the semiconductor device described in Example 16, wherein the first processing region has a nitrogen concentration between about 0.3% atom and about 3% atom.

[0169] Example 18 is the semiconductor device described in Example 17, wherein the fourth processing region has a nitrogen concentration between about 3% atom and about 30% atom.

[0170] Example 19 is the semiconductor device described in Example 15, further comprising: a second conductive material extending through an unprocessed portion of the dielectric layer and an unprocessed portion of the etch stop layer and physically contacting the unprocessed portion of the dielectric layer and the unprocessed portion of the etch stop layer to make physical contact with a source / drain contact.

[0171] Example 20 is the semiconductor device described in Example 19, wherein the second conductive material extends into the source / drain contacts.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: An etch stop layer is deposited on a first hard mask material, which is on top of the gate stack; An interlayer dielectric is deposited on the etch stop layer; A first opening is formed through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing the conductive portion of the gate stack; as well as The sidewall of the first opening is treated with a first dopant to form a first treated region within the interlayer dielectric, a second treated region within the etch stop layer, a third treated region within the first hard mask material, and a fourth treated region within the conductive portion, wherein, after the treatment, the fourth treated region has a higher concentration of the first dopant than the first treated region.

2. The method according to claim 1, wherein, The first dopant includes nitrogen.

3. The method according to claim 2, wherein, The treatment of the sidewalls includes at least a plasma process.

4. The method according to claim 3, wherein, The plasma process utilizes ammonia as a precursor.

5. The method according to claim 4, wherein, The first concentration of the first dopant in the fourth processing region is between about 3% atom and about 30% atom.

6. The method according to claim 1, further comprising: A conductive material is deposited within the first opening, the conductive material being in solid contact with the first processing area without an intermediate liner.

7. The method according to claim 1, further comprising: A second opening is formed through the interlayer dielectric and the etch stop layer to expose the source / drain contacts; as well as Conductive material is deposited into the second opening without treating the second opening.

8. A method for manufacturing a semiconductor device, the method comprising: A first opening is formed through the dielectric layer, the contact etch stop layer, and the first hard mask material to expose the conductive portion of the gate stack; The sidewall of the first opening is treated with a first plasma from a nitrogen-containing precursor to form a first treated region within the dielectric layer, a second treated region within the contact etch stop layer, a third treated region within the first hard mask material, and a fourth treated region within the conductive portion, wherein, after the treatment, the fourth treated region has a higher nitrogen concentration than the first treated region. The first opening is filled with a first conductive material; A second opening is formed through the dielectric layer and the contact etch stop layer to expose the first source / drain contact; The sidewall of the second opening is treated with a second plasma; and The second opening is filled with a second conductive material.

9. The method according to claim 8, wherein, The second opening is formed by forming a recess within the first source / drain contact.

10. The method according to claim 8, wherein, The second opening is formed without forming a recess within the first source / drain contact.

11. The method according to claim 8, wherein, The processing of the sidewall of the first opening and the processing of the sidewall of the second opening are performed simultaneously.

12. The method according to claim 8, wherein, The second opening is formed by passing through a second hard mask material covering the first source / drain contact.

13. The method according to claim 12, wherein, The second opening is formed by forming a recess within the first source / drain contact.

14. The method according to claim 8, wherein, The nitrogen-containing precursor is ammonia.

15. A semiconductor device, comprising: Gate stacks are located on top of semiconductor fins; A first hard mask material is applied over the gate stack, and the first hard mask material includes a first processing region; An etch stop layer is applied over the first hard mask material, and the etch stop layer includes a second processing area; A dielectric layer is overlaid on the etch stop layer, the dielectric layer including a third processing region; as well as A conductive material extends through and substantially contacts the first processing region, the second processing region, and the third processing region, wherein the conductive material also substantially contacts a fourth processing region located within the gate stack. The fourth processing region has a higher concentration of the first dopant than the first processing region.

16. The semiconductor device according to claim 15, wherein, Each of the first processing region, the second processing region, the third processing region, and the fourth processing region includes nitrogen.

17. The semiconductor device according to claim 16, wherein, The first processing region has a nitrogen concentration between approximately 0.3% atom and approximately 3% atom.

18. The semiconductor device according to claim 17, wherein, The fourth processing region has a nitrogen concentration between approximately 3% and approximately 30% atoms.

19. The semiconductor device of claim 15, further comprising: A second conductive material extends through the untreated portion of the dielectric layer and the untreated portion of the etch stop layer and makes physical contact with the untreated portion of the dielectric layer and the untreated portion of the etch stop layer to make physical contact with the source / drain contacts.

20. The semiconductor device according to claim 19, wherein, The second conductive material extends into the source / drain contact.

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