Method for manufacturing semiconductor substrate, semiconductor substrate and method for forming growth layer

Abstract

The present invention is a method for manufacturing a semiconductor substrate, comprising a crystal growth step (S30) of forming a growth layer (20) on a base substrate (10) having a through-hole (11). Further, the present invention is also a method for forming a growth layer (20), comprising a through-hole forming step (S10) of forming a through-hole (11) on a base substrate (10) before forming the growth layer (20) on a surface of the base substrate (10).

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor substrate, a semiconductor substrate, and a method for forming a growth layer. Background Technology

[0002] Semiconductor substrates are typically fabricated by growing crystals on a substrate. However, a problem has been reported where it is difficult to obtain large-diameter semiconductor substrates depending on the composition of the semiconductor material used for crystal growth.

[0003] For example, the example of growing AlN crystals on substrates such as aluminum nitride (AlN) or silicon carbide (SiC) substrates using the sublimation method is given. However, when crystal growth is performed solely by sublimation, there are regions where AlN crystals do not grow, making it difficult to obtain large-diameter semiconductor substrates with good crystallinity.

[0004] To address this problem, Patent Document 1 describes a technique that is, “a method for growing AlN crystals, wherein AlN crystals are grown on a seed substrate disposed in a crystal growth chamber within a crystal growth container disposed in a reaction container by a vapor phase growth method, characterized in that a carbon-containing gas is supplied in the crystal growth chamber during crystal growth.”

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2007-55881 Summary of the Invention

[0008] The problem the invention aims to solve

[0009] The problem to be solved by the present invention is to provide a novel technology capable of manufacturing large-diameter semiconductor substrates.

[0010] Furthermore, the problem to be solved by the present invention is to provide a novel technique for manufacturing large-diameter semiconductor substrates with good crystallinity.

[0011] Problem-solving methods

[0012] The present invention, which solves the above problems, is a method for manufacturing a semiconductor substrate, including a crystal growth step of forming a growth layer on a substrate having through holes.

[0013] In this way, by forming a growth layer on a substrate with through holes, a semiconductor substrate with a diameter equal to that of the substrate can be manufactured. Therefore, by using a large-diameter substrate, a large-aperture semiconductor substrate can be obtained.

[0014] Additionally, the term "large aperture" in this specification means obtaining a large-area growth layer compared to forming a growth layer on a substrate without through holes.

[0015] In a preferred embodiment of the invention, the crystal growth step involves heating to create a temperature gradient along the vertical direction of the substrate.

[0016] In a preferred embodiment of the present invention, the crystal growth step involves arranging the substrate and the raw material of the growth layer relative to each other and heating them to form a temperature gradient between the substrate and the raw material.

[0017] In a preferred embodiment of the present invention, the crystal growth step includes a lateral growth step in which the growth layer is grown in the horizontal direction of the substrate and a longitudinal growth step in which the growth layer is grown in the vertical direction of the substrate.

[0018] In a preferred embodiment of the present invention, it further includes:

[0019] The through-hole forming step of forming a through-hole on the substrate; and

[0020] The strain layer removal step removes the strain layer introduced by the through-hole forming step.

[0021] In a preferred embodiment of the present invention, the through-hole forming step is performed by irradiating the substrate with a laser to form the through-hole.

[0022] In a preferred embodiment of the invention, the strain layer removal step removes the strain layer of the substrate by performing heat treatment.

[0023] In a preferred embodiment of the present invention, the substrate is silicon carbide; the strain layer removal step involves etching the substrate in a silicon atmosphere.

[0024] Furthermore, the present invention also relates to a method for forming a growth layer. Specifically, the present invention, which solves the above-mentioned problems, is a method for forming a growth layer, comprising: a through-hole forming step of forming through-holes on the substrate before forming the growth layer on the surface of the substrate.

[0025] In a preferred embodiment of the invention, the method further includes a strain layer removal step to remove the strain layer introduced by the through-hole forming step.

[0026] In a preferred embodiment of the invention, the strain layer removal step involves etching the substrate by performing a heat treatment.

[0027] The effects of the invention

[0028] Based on the disclosed technology, a novel technique for manufacturing large-diameter semiconductor substrates can be provided.

[0029] Furthermore, based on the disclosed technology, a novel technique can be provided for manufacturing large-diameter semiconductor substrates with good crystallinity.

[0030] Other issues, features, and advantages will become apparent from reading the embodiments of the invention described below, in conjunction with the accompanying drawings and claims. Attached Figure Description

[0031] Figure 1 This is an explanatory diagram illustrating the steps of a method for manufacturing a semiconductor substrate according to an embodiment.

[0032] Figure 2 This is an explanatory diagram illustrating the through-hole formation step and the strain layer removal step according to the embodiment.

[0033] Figure 3 This is an explanatory diagram of the through-hole formation steps according to the embodiment.

[0034] Figure 4 This is an explanatory diagram illustrating the crystal growth steps according to the embodiment.

[0035] Figure 5 This is an explanatory diagram illustrating the crystal growth steps according to the embodiment.

[0036] Figure 6 This is an explanatory diagram of the through-hole formation steps according to Example 1.

[0037] Figure 7 This is an explanatory diagram of the strain layer removal steps according to Example 1.

[0038] Figure 8 This is an explanatory diagram of the crystal growth steps according to Example 1.

[0039] Figure 9 This is an explanatory diagram of the crystal growth steps according to Example 1.

[0040] Figure 10 This is an explanatory diagram based on the crystal growth steps of Comparative Example 1. Detailed Implementation

[0041] The preferred embodiments of the method for manufacturing a semiconductor substrate according to the present invention will be described in detail below with reference to the accompanying drawings. The scope of the present invention is not limited to the embodiments shown in the drawings, and can be appropriately modified within the scope of the claims. Furthermore, the drawings are conceptual diagrams, and the relative dimensions of the components, etc., do not limit the present invention. In addition, in this specification, for the purpose of explaining the present invention, "up" and "down" may refer to each other based on the figures, but this does not limit the "up" and "down" in relation to the use of the semiconductor substrate of the present invention. Furthermore, in the following description of the embodiments and the accompanying drawings, the same reference numerals are used for the same structures, and repeated descriptions are omitted.

[0042] Manufacturing Methods of Semiconductor Substrates

[0043] Figures 1 to 4 An explanatory diagram illustrating a method for manufacturing a semiconductor substrate according to an embodiment of the present invention is shown.

[0044] The method for manufacturing a semiconductor substrate according to the embodiments may include: a through-hole forming step S10 for forming a through-hole 11 on a substrate 10; a strain layer removal step S20 for removing the strain layer 12 introduced by the through-hole forming step S10; and a crystal growth step S30 for forming a growth layer 20 on the substrate 10 having the through-hole 11.

[0045] Furthermore, this embodiment can be understood as a method for forming a growth layer 20 over a large area, including a through-hole forming step S10 of forming through-holes 11 on the substrate 10 before forming the growth layer 20 on the surface of the substrate 10.

[0046] The following is a detailed description of each step of the implementation method.

[0047] <Steps for forming a through hole>

[0048] The through-hole forming step S10 is the step of forming a through-hole 11 on the substrate 10. This through-hole forming step S10 can be any method that can form a through-hole 11 on the substrate 10.

[0049] The through-hole 11 can be formed by methods such as laser processing, focused ion beam system (FIB), reactive ion etching (RIE), or plasma etching. Furthermore, in the embodiment shown... Figure 2 The illustration shows a method for forming a through hole 11 by irradiating a substrate 10 with a laser L.

[0050] The substrate 10 can be any material commonly used in the manufacture of semiconductor substrates. Examples of materials for the substrate 10 include known group IV materials such as silicon (Si), germanium (Ge), and diamond (C). Alternatively, the substrate 10 can be made of known group IV-IV compound materials such as silicon carbide (SiC). Furthermore, the substrate 10 can be made of known group II-VI compound materials such as zinc oxide (ZnO), zinc sulfide (ZnS), zinc selenide (ZnSe), cadmium sulfide (CdS), and cadmium telluride (CdTe). Additionally, the substrate 10 can be made of known group III-V compound materials such as boron nitride (BN), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium phosphide (GaP), indium phosphide (InP), and indium antimonide (InSb). Finally, the substrate 10 can be made of oxide materials such as aluminum oxide (Al2O3) and gallium oxide (Ga2O3). Furthermore, the material of the substrate 10 is, for example, a metallic material such as copper (Cu) or nickel (Ni). Alternatively, the substrate 10 may also be a structure with known additive atoms appropriately added according to its material.

[0051] In addition, the substrate 10 can be a wafer or substrate processed from bulk crystal, or a substrate having a buffer layer made of the aforementioned semiconductor material.

[0052] The via 11 can be any shape made of a semiconductor material suitable for growth, and can be formed as a single or multiple vias 11. In addition, a via group (pattern) formed by arranging multiple vias 11 can also be used.

[0053] The following is a detailed description of an example of a pattern for growing a hexagonal semiconductor material.

[0054] Figure 3 This is an explanatory diagram illustrating pattern 100 according to an embodiment. The line segments represented by pattern 100 are the substrate 10. Pattern 100 preferably presents a three-dimensionally symmetrical regular hexagonal displacement shape. (Refer to the following...) Figure 3The term "regular hexagonal displacement shape" as used in this specification will be described in detail. A regular hexagonal displacement shape is a dodecagon. Furthermore, the regular hexagonal displacement shape is composed of 12 line segments of equal length and in a straight line configuration. The pattern 100 presenting the regular hexagonal displacement shape includes a reference figure 101, which is an equilateral triangle with an area and includes three vertices 104. Each of these three vertices 104 is included in the vertex of the pattern 100. Here, the three vertices 104 can be understood as being located on the line segments constituting the pattern 100. The pattern 100 includes: a line segment 102 extending from and including the vertex 104 (equivalent to a first line segment), and a line segment 103 adjacent to the line segment 102 that does not extend from and does not include the vertex 104 (equivalent to a second line segment). Here, the angle θ between two adjacent line segments 102 in the pattern 100 is constant and equal to the angle θ between two adjacent line segments 103 in the pattern 100. In addition, the term "displaced regular hexagon" in this specification can be understood as a dodecagon formed by displacing (deforming) a regular hexagon based on an angle θ representing the degree of concavity or convexity while maintaining the area of ​​the regular hexagon.

[0055] The angle θ is preferably greater than 60°, more preferably 66° or more, more preferably 80° or more, more preferably 83° or more, more preferably 120° or more, more preferably 150° or more, and more preferably 155° or more. Furthermore, the angle θ is preferably less than 180°, more preferably less than 155°, more preferably less than 150°, more preferably less than 120°, more preferably less than 83°, more preferably less than 80°, and more preferably less than 66°.

[0056] The pattern 100 according to the embodiment can also be a six-fold symmetric regular dodecagonal displacement shape, instead of a three-fold symmetric regular hexagonal displacement shape. The regular dodecagonal displacement shape is a 24-sided polygon. Furthermore, the regular dodecagonal displacement shape is composed of 24 line segments of equal length and straight lines. The pattern 100 presenting the regular dodecagonal displacement shape includes a reference figure 101 as a regular hexagon with an area and including 6 vertices 104. Each of the 6 vertices 104 is included in the vertex of the pattern 100. In addition, as with the regular hexagonal displacement shape, the angle θ between two adjacent line segments 102 in the pattern 100 is constant and equal to the angle θ between two adjacent line segments 103 in the pattern 100. That is to say, the "regular dodecagonal displacement shape" in the description of this specification can be understood as a 24-sided polygon formed by displacing (deforming) a regular dodecagon based on an angle θ representing the degree of concavity or convexity while maintaining the area of ​​the regular dodecagon. Alternatively, pattern 100 can also be a 4n-gon, or 2n-gon displacement shape, formed by shifting (deforming) a regular 2n-gon based on an angle θ representing the degree of concavity or convexity while maintaining the area of ​​the regular 2n-gon. In this case, the 2n-gon displacement shape can be understood as containing a regular n-gon (equivalent to the reference figure 101). Here, the reference figure 101 can be understood as including n vertices.

[0057] The pattern 100 according to the embodiment may also be a structure including a regular 2n-gon displacement shape (including a regular hexagonal displacement shape and a regular 12-gon displacement shape). Furthermore, the pattern 100 may also be a structure that, in addition to the line segments constituting the regular 2n-gon displacement shape, includes at least one line segment (equivalent to a third line segment) connecting the intersection point of two adjacent line segments 103 in the regular 2n-gon displacement shape to the centroid of the reference shape 101. Furthermore, the pattern 100 may also be a structure that, in addition to the line segments constituting the regular 2n-gon displacement shape, includes at least one line segment connecting the intersection point of two adjacent line segments 103 in the regular 2n-gon displacement shape to the vertex 104 constituting the reference shape 101. Furthermore, the pattern 100 may also be a structure that, in addition to the line segments constituting the regular 2n-gon displacement shape, includes at least one line segment constituting the reference shape 101 included in the regular 2n-gon displacement shape.

[0058] Furthermore, the through-hole forming step S10 is preferably a step of removing more than 50% of the effective area of ​​the substrate 10. More preferably, it is a step of removing more than 60% of the effective area, even more preferably, it is a step of removing more than 70% of the effective area, and even more preferably, it is a step of removing more than 80% of the effective area.

[0059] Furthermore, the effective area in this specification refers to the surface of the substrate 10 to which the raw material is attached during the crystal growth step S30. In other words, it refers to the remaining area on the growth surface of the substrate 10 excluding the area removed by the through-hole 11.

[0060] In addition, it is desirable that the effective area of ​​the substrate 10 or the shape / pattern of the through hole 11 can be determined by taking into account the difference in lattice constant or thermal expansion coefficient between the substrate 10 and the growth layer 20, the crystal structure of the growth layer 20, and the growth method.

[0061] <Strain Layer Removal Steps>

[0062] The strain layer removal step S20 is a step of removing the strain layer 12 formed on the substrate 10 through the through-hole forming step S10. As this strain layer removal step S20, an example can be given by means of etching the substrate 10 by heat treatment.

[0063] Furthermore, any means that can remove the strain layer 12 can certainly be used.

[0064] The method for removing the strain layer 12 may include, for example, hydrogen etching using hydrogen as the etching gas, Si vapor etching (SiVE) performed under Si atmosphere, and the etching method described in Example 1 below.

[0065] <Crystal Growth Steps>

[0066] The crystal growth step S30 is the step of forming a growth layer 20 on a substrate 10 with through holes 11.

[0067] The semiconductor material of the growth layer 20 can be the same semiconductor material as the substrate 10 (homogeneous epitaxial growth) or a different semiconductor material than the substrate 10 (heterogeneous epitaxial growth).

[0068] As for the material of the growth layer 20, any material that is commonly used as a semiconductor material for epitaxial growth can be used. The material of the growth layer 20 can be the material of the substrate 10, a known material that can be used as the material of the substrate 10, or a known material that can be epitaxially grown on the substrate 10.

[0069] The material of the growth layer 20 can be, for example, Si, Ge, GaN, AlN, InN, ZnS, ZnSe, CdTe, GaP, GaAs, InP, InAs, InSb, SiC, etc.

[0070] The combination of the material of the substrate 10 and the material of the growth layer 20 can be appropriately selected by taking into account the difference in the lattice constant or thermal expansion coefficient of the two materials.

[0071] As for the growth method of growth layer 20, the crystal growth step S30 can employ known vapor phase growth methods (equivalent to vapor phase epitaxy), such as Physical Vapor Transport (PVT), sublimation recrystallization, modified Rayleigh method, Chemical Vapor Transport (CVT), Molecular-Organic Vapor Phase Epitaxy (MOVPE), and Hydride Vapor Phase Epitaxy (HVPE). Alternatively, the crystal growth step S30 can be performed using Physical Vapor Deposition (PVD) instead of PVT. Furthermore, the crystal growth step S30 can be performed using Chemical Vapor Deposition (CVD) instead of CVT. Furthermore, as a growth method for the growth layer 20, the crystal growth step S20 can employ known liquid phase growth methods (equivalent to liquid phase epitaxy) such as the TSSG method (Top-Seeded Solution Growth) and Metastable Solvent Epitaxy (MSE). Additionally, as a growth method for the growth layer 20, the crystal growth step S30 can employ the CZ method (Czochralski method). The crystal growth step S30 can be appropriately selected and the growth method employed based on the materials of the substrate 10 and the growth layer 20.

[0072] Figure 4 and Figure 5 This is an explanatory diagram illustrating the crystal growth step S30 according to the embodiment.

[0073] According to the embodiment, the crystal growth step S30 is a step in which the substrate 10 and the semiconductor material 40, which becomes the raw material for the growth layer 20, are arranged opposite each other (facing each other) in a crucible 30 having a quasi-enclosed space and heated. Furthermore, in this specification, "quasi-enclosed space" refers to a space that, although capable of being evacuated, can contain at least a portion of the vapor generated inside the container.

[0074] Furthermore, the crystal growth step S30 is a step of heating to form a temperature gradient along the vertical direction of the substrate 10. By heating the crucible 30 (substrate 10 and semiconductor material 40) in this temperature gradient, the raw material is transported from the semiconductor material 40 to the substrate 10 through the raw material transport space 31.

[0075] The driving force for transporting raw materials can be the temperature gradient or the chemical potential difference between the substrate 10 and the semiconductor material 40, as described above.

[0076] Specifically, within the quasi-enclosed space, vapor composed of elements sublimated from the semiconductor material 40 is transported by diffusion in the raw material transport space 31, and reaches supersaturation and condenses on the substrate 10, where the temperature is set below that of the semiconductor material 40. As a result, a growth layer 20 is formed on the substrate 10.

[0077] Furthermore, the crystal growth step S30 includes a lateral growth step S31 in which the growth layer 20 is grown in the horizontal direction of the substrate 10, and a longitudinal growth step S32 in which the growth layer 20 is grown in the vertical direction of the substrate 10.

[0078] In addition, in the lateral growth step S31, it is sufficient that the growth component in the horizontal direction is greater than the growth component in the vertical direction, and it may also include the growth component in the vertical direction (growth component: horizontal direction > vertical direction).

[0079] Furthermore, in the longitudinal growth step S32, it is sufficient that the growth component in the vertical direction is greater than the growth component in the horizontal direction, and it may also include the growth component in the horizontal direction (growth component: vertical direction > horizontal direction).

[0080] That is, such as Figure 4 As shown, the lateral growth step S31 is a step in which a horizontal temperature gradient is formed on the surface of the substrate 10 as heat escapes from the through hole 11 of the substrate 10, causing the growth layer 20 to grow toward the through hole 11.

[0081] Subsequently, when the growth layer 20 is formed on the through hole 11 through the lateral growth step S31, the temperature gradient in the horizontal direction on the surface of the substrate 10 decreases / disappears, and the process automatically proceeds to the longitudinal growth step S32.

[0082] In addition, in the crystal growth step S30, inert gas or doping gas can be introduced into the raw material transport space 31 and the doping concentration or growth environment of the growth layer 20 can be controlled.

[0083] According to the present invention, a large-diameter semiconductor substrate can be manufactured by growing a growth layer 20 on a substrate 10 having through holes 11. That is, as heat escapes from the region where the through holes 11 are formed, the growth driving force acts in the horizontal direction of the substrate 10. As a result, bonding of the growth layer 20 is promoted in the region where the through holes 11 are formed, and a growth layer 20 having a diameter equal to that of the substrate 10 can be formed. Therefore, by using a large-diameter substrate 10, a large-diameter semiconductor substrate can be obtained.

[0084] Furthermore, according to the present invention, by forming a growth layer 20 on the region where the through-hole 11 is formed, the crystallinity of the growth layer 20 can be improved. That is, the growth layer 20 formed on the region where the through-hole 11 is formed is not located directly above the substrate 10. Therefore, through-system dislocations (e.g., through-screw dislocations, through-edge dislocations, microtubes, etc.) present on the substrate 10 are not perpetuated, and through-system dislocations in the growth layer 20 can be reduced.

[0085] As one embodiment of the method for manufacturing a semiconductor substrate according to the present invention, an embodiment of growing AlN on a SiC substrate is illustrated in the following examples.

[0086] Furthermore, as one embodiment of the method for manufacturing a semiconductor substrate according to the present invention, embodiments that do not include growing AlN on a SiC substrate are listed.

[0087] Example

[0088] The present invention will be described in more detail by way of Example 1 and Comparative Example 1.

[0089] In addition, in Example 1 and Comparative Example 1, an AlN growth layer 20 was grown on a SiC substrate 10 to manufacture a semiconductor substrate.

[0090] Example 1

[0091] <Steps for forming a through hole>

[0092] Under the following conditions, a laser is irradiated onto the substrate 10 to form a through hole 11.

[0093] (Substrate 10)

[0094] Semiconductor material: 4H-SiC

[0095] Substrate dimensions: 11mm wide × 11mm long × 524μm thick

[0096] Growth surface: Si surface

[0097] Offset angle: coaxial

[0098] (Laser processing conditions)

[0099] Type: Green laser

[0100] Wavelength: 532nm

[0101] Spot diameter: 40μm

[0102] Average output: 4W (at 30kHz)

[0103] (Details of the pattern)

[0104] Figure 6 This is an explanatory diagram illustrating the pattern of the through hole 11 formed in step S10 of the through hole formation according to Embodiment 1. Figure 6 (a) is an explanatory diagram showing the arrangement of the plurality of through holes 11. Figure 6 In (a), the black area represents a portion of the through hole 11, and the white area is reserved as the substrate 10.

[0105] Figure 6 (b) is shown Figure 6 An explanatory diagram showing the enlarged view of the through hole 11 in (a). Figure 6 In (b), the white area represents part of the through hole 11, and the black area is reserved as the substrate 10.

[0106] In addition, Figure 6 In the pattern, more than 80% of the effective area of ​​the substrate 10 is removed, thereby reducing the strength of the substrate 10.

[0107] (Strain layer removal step S20)

[0108] Figure 7 This is an explanatory diagram illustrating step S20 of strain layer removal according to Example 1.

[0109] The substrate 10, which has formed the through-hole 11 through the through-hole forming step S10, is housed in a SiC container 50, and the SiC container 50 is further housed in a TaC container 60, and heated under the following conditions.

[0110] (Heating conditions)

[0111] Heating temperature: 1800℃

[0112] Heating time: 2 hours

[0113] Etching depth: 8μm

[0114] (SiC container 50)

[0115] Material: Polycrystalline SiC

[0116] Container dimensions: 60mm in diameter × 4mm in height

[0117] Distance between the substrate 10 and the bottom surface of the SiC container 50: 2mm

[0118] (Details of SiC container 50)

[0119] like Figure 5 As shown, the SiC container 50 is a fitted container including an upper container 51 and a lower container 52 that can be fitted together. A small gap 53 is formed at the fitting part of the upper container 51 and the lower container 52, which is configured to allow air to be vented (vacuumed) inside the SiC container 50 through the gap 53.

[0120] The SiC container 50 has an etching space 54 formed by positioning a portion of the SiC container 50 positioned on the low-temperature side of the temperature gradient relative to the substrate 10 while the substrate 10 is positioned on the high-temperature side of the temperature gradient. This etching space 54 is used to transport Si atoms and C atoms from the substrate 10 to the SiC container 50 and etch them using the temperature difference between the substrate 10 and the bottom surface of the SiC container 50 as a driving force.

[0121] Furthermore, the SiC container 50 has a substrate holder 55 for holding the substrate 10 in mid-air and forming the etching space 54. Alternatively, the substrate holder 55 may be omitted depending on the direction of the temperature gradient of the furnace. For example, if the furnace forms a temperature gradient so that the temperature drops from the lower container 52 to the upper container 51, the substrate 10 may be disposed on the bottom surface of the lower container 52 without the substrate holder 55.

[0122] (TaC container 60)

[0123] Materials: TaC

[0124] Container dimensions: 160mm in diameter × 60mm in height

[0125] Si vapor supply source 64 (Si compound): TaSi2

[0126] (Details of TaC container 60)

[0127] Similar to the SiC container 50, the TaC container 60 is a fitted container comprising an upper container 61 and a lower container 62 that can fit together, and is configured to house the SiC container 50. A small gap 63 is formed at the fitting portion of the upper container 61 and the lower container 62, which allows for venting (vacuuming) of the TaC container 60 through the gap 63.

[0128] The TaC container 60 has a Si vapor supply source 64 capable of supplying a vapor pressure of gaseous species containing Si within the TaC container 60. The Si vapor supply source 64 is only required to be a structure for generating a vapor pressure of gaseous species containing Si within the TaC container 60 during heat treatment.

[0129] <Crystal growth step S30>

[0130] Figure 8 This is an explanatory diagram illustrating the crystal growth step S30 according to Example 1.

[0131] The substrate 10, after the strain layer 12 has been removed in the strain layer removal step S20, is placed in the crucible 30 in a manner opposite to the semiconductor material 40, and is heated under the following conditions.

[0132] (Heating conditions)

[0133] Heating temperature: 2040℃

[0134] Heating time: 70 hours

[0135] Growth thickness: 500 μm

[0136] N2 gas pressure: 10 kPa

[0137] (Crucible 30)

[0138] Materials: Tantalum carbide (TaC) and / or tungsten (W)

[0139] Container dimensions: 10mm × 10mm × 1.5mm

[0140] Distance between substrate 10 and semiconductor material 40: 1 mm

[0141] (Details of crucible 30)

[0142] The crucible 30 has a material delivery space 31 between the substrate 10 and the semiconductor material 40. The material is delivered from the semiconductor material 40 to the substrate 10 through the material delivery space 31.

[0143] Figure 8 (a) is an example of the crucible 30 used in the crystal growth step S30. Like the SiC container 50 and the TaC container 60, the crucible 30 is a fitted container comprising an upper container 32 and a lower container 33 that can fit together. A small gap 34 is formed at the fitting portion of the upper container 32 and the lower container 33, which is configured to allow venting (vacuuming) of the crucible 30 through the gap 34.

[0144] Additionally, the crucible 30 has a substrate holder 35 for forming the raw material delivery space 31. The substrate holder 35 is disposed between the base substrate 10 and the semiconductor material 40, with the semiconductor material 40 positioned on the high-temperature side and the base substrate 10 positioned on the low-temperature side, thus forming the raw material delivery space 31.

[0145] Figure 8 (a) and Figure 8 (c) is another example of the crucible 30 used in the crystal growth step S30. Figure 8 (b) and Figure 8 The temperature gradient of (c) is set to be similar to... Figure 8 The temperature gradient is opposite to that of (a), and the substrate 10 is disposed on the upper side. That is, with Figure 8 Similar to (a), the semiconductor material 40 is disposed on the high-temperature side and the substrate 10 is disposed on the low-temperature side to form the raw material transport space 31.

[0146] Figure 8 (b) shows an example of forming a material delivery space 31 between the substrate 10 and the semiconductor material 40 by fixing the substrate 10 to the side of the upper container 32.

[0147] Figure 8 (c) shows an example of forming a material delivery space 31 between the semiconductor material 40 and a through window at the upper container 32 and a base substrate 10 disposed thereon. Furthermore, as shown in the diagram... Figure 8 As shown in (c), the raw material conveying space 31 can also be formed by setting an intermediate component 36 between the upper container 32 and the lower container 33.

[0148] (Semiconductor Materials 40)

[0149] Material: AlN sintered body

[0150] Dimensions: 20mm wide x 20mm long x 5mm thick

[0151] (Details of semiconductor material 40)

[0152] The AlN sintered body of semiconductor material 40 is sintered in the following sequence.

[0153] AlN powder was placed inside a TaC block and compacted with moderate force. The compacted AlN powder and TaC block were then placed in a thermally decomposed carbon crucible and heated under the following conditions.

[0154] Heating temperature: 1850℃

[0155] N2 gas pressure: 10 kPa

[0156] Heating time: 3 hours

[0157] Figure 9 This is a schematic diagram illustrating the crystal growth step S30 of Embodiment 1. By growing the growth layer 20 on the substrate 10 where the through-hole 11 is formed, a temperature gradient can be formed in the horizontal direction of the substrate 10 and used as a driving force for the lateral growth of the growth layer 20. That is, even for semiconductor materials such as AlN, which are difficult to grow in the horizontal direction, the growth layer 20 can be formed in the region where the through-hole 11 is formed, and a large-diameter semiconductor substrate can be manufactured.

[0158] Furthermore, in the semiconductor substrate manufactured according to Example 1, no through-system dislocations were found in the growth layer 20 formed on the region where the through-hole 11 is formed.

[0159] Comparative Example 1

[0160] The substrate 10 of Comparative Example 1 has a groove 13 formed to replace the through hole 11 of Example 1. For this substrate 10, the crystal growth step S30 is performed under the same conditions as in Example 1. That is, Comparative Example 1 performs the crystal growth step S30 but does not perform the through hole formation step S10.

[0161] Figure 10 This is a schematic diagram showing the crystal growth step S30 of Comparative Example 1. The semiconductor substrate manufactured according to Comparative Example 1 has an area on the trench 13 where the growth layer 20 has not been grown.

[0162] That is, when the trench 13 is formed instead of the through hole 11, the temperature in the region of the trench 13 does not decrease, and no temperature gradient is formed in the horizontal direction of the substrate 10. As a result, no lateral growth driving force is generated, and no growth layer 20 is formed in the region of the trench 13.

[0163] As can be understood from the results of Example 1 and Comparative Example 1, a large-diameter semiconductor substrate can be manufactured by forming a growth layer 20 on a substrate 10 having a through-hole 11.

[0164] Explanation of reference numerals in the attached figures

[0165] 10. Substrate

[0166] 11 Through Holes

[0167] 12 Strain Layer

[0168] 13 slots

[0169] 20 growth layers

[0170] 30 crucibles

[0171] 31 Raw material conveying space

[0172] 40 Semiconductor Materials

[0173] 50 SiC container

[0174] 60 TaC containers

[0175] S10 Through Hole Formation Steps

[0176] S20 strain layer removal steps

[0177] S30 crystal growth steps

[0178] S31 Lateral growth steps

[0179] S32 Vertical growth steps

Claims

1. A method for manufacturing a semiconductor substrate, comprising: The crystal growth step of forming a growth layer on a substrate with through holes. The crystal growth step involves arranging the substrate and the raw material of the growth layer relative to each other and heating them to create a temperature gradient between the substrate and the raw material, with the raw material on the high-temperature side and the substrate on the low-temperature side.

2. The method for manufacturing a semiconductor substrate according to claim 1, wherein, The crystal growth step involves heating to create a temperature gradient along the vertical direction of the substrate.

3. The method for manufacturing a semiconductor substrate according to claim 1 or 2, wherein, The crystal growth step includes a lateral growth step in which the growth layer is grown in the horizontal direction of the substrate, and a longitudinal growth step in which the growth layer is grown in the vertical direction of the substrate.

4. The method for manufacturing a semiconductor substrate according to claim 1 or 2, further comprising: A through-hole forming step, wherein a through-hole is formed on the substrate; and The strain layer removal step removes the strain layer introduced by the through-hole forming step.

5. The method for manufacturing a semiconductor substrate according to claim 4, wherein, The through-hole forming step forms the through-hole by irradiating the substrate with a laser.

6. The method for manufacturing a semiconductor substrate according to claim 4, wherein, The strain layer removal step removes the strain layer from the substrate by performing heat treatment.

7. The method for manufacturing a semiconductor substrate according to claim 4, wherein, The substrate is silicon carbide; The strain layer removal step involves etching the substrate in a silicon atmosphere.

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