Nvm synapse element with stepwise reset capability

Abstract

An analog magnetoresistive random access memory (MRAM) cell is provided. The analog MRAM cell includes a magnetic free layer having a first domain, a second domain, and a domain wall, the first domain having a first magnetization direction, the second domain having a second magnetization direction opposite the first magnetization direction, the domain wall located between the first domain and the second domain. The analog MRAM cell further includes a magnetic pinned layer. The analog MRAM cell also includes an insulating tunnel barrier between the magnetic free layer and the magnetic pinned layer. The analog MRAM cell additionally includes an electrode located proximate to the magnetic free layer, the electrode configured to generate heat by supplying a current to reduce an electrical conductivity of the magnetic free layer.

Description

Background Technology

[0001] This invention relates generally to memory devices, and more particularly to non-volatile memory synaptic elements with step-reset capability.

[0002] The use of non-volatile memory (NVM) in analog multiply-add accelerators has attracted considerable interest as a means of achieving very low power consumption. Different types of NVMs, such as phase-change memory (PCM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), are under serious investigation for use in analog synaptic elements within analog multiply-add accelerators. While each NVM type has its advantages and disadvantages, a significant advantage of MRAM is that it allows for symmetrical setup (increased conductivity) / reset (decreased conductivity) operations.

[0003] However, when using MRAM as a simulated synaptic element, the following problems exist: when applying a set operation, the set operation sometimes exceeds its upper limit, and it is not easy to reduce the conductivity. The conventional RESET method using a static magnetic field has the following disadvantages: (1) a strong magnetic field is necessary; and (2) the RESET method is forced to be applied to all synaptic elements.

[0004] Furthermore, when MRAM is used as an analog synaptic element, (1) it cannot be integrated into a large-scale integrated circuit (LSI), and (2) the RESET operation cannot be applied with the selected synaptic element (but must be applied to all synaptic elements). Summary of the Invention

[0005] According to an embodiment of the present invention, an analog magnetoresistive random access memory (MRAM) cell is provided. The analog MRAM cell includes a magnetic free layer having a first domain, a second domain, and domain walls. The first domain has a first magnetization direction, the second domain has a second magnetization direction opposite to the first magnetization direction, and the domain walls are located between the first and second domains. The analog MRAM cell further includes a magnetic pinning layer. The analog MRAM cell also includes an insulating tunnel barrier between the magnetic free layer and the magnetic pinning layer. The analog MRAM cell further includes electrodes positioned adjacent to the magnetic free layer, the electrodes being configured to generate heat by supplying current to reduce the conductivity of the magnetic free layer.

[0006] In one or more embodiments of the present invention, the analog MRAM cell is included in a synaptic element.

[0007] In one or more embodiments of the present invention, the electrode reduces only the conductivity of the magnetic free layer of the synaptic element among a plurality of synaptic elements.

[0008] In one or more embodiments of the invention, the analog MRAM further includes a selection circuit configured to select only the synaptic element for reducing conductivity from the plurality of synaptic elements.

[0009] In one or more embodiments of the invention, the electrodes are configured to generate heat by providing current to reduce the conductivity of the magnetic free layer, thereby randomizing the magnetization direction of at least a portion of the magnetic free layer.

[0010] In one or more embodiments of the present invention, heat generated from the electrodes generates a local magnetic field only in the analog MRAM cells among the plurality of MRAM cells forming the memory array.

[0011] According to another aspect of the invention, a method for resetting an analog MRAM is provided. The method includes detecting the state of a magnetic free layer of the analog MRAM. The magnetic free layer has a first domain, a second domain, and domain walls, the first domain having a first magnetization direction, the second domain having a second magnetization direction opposite to the first magnetization direction, and the domain walls located between the first and second domains. The state is detected based on the alignment of the first and second magnetization directions and the removal of the domain walls. The method further includes providing a current to electrodes to generate heat to randomize the magnetization of cells, and in response to the alignment of the first and second magnetization directions and the removal of the domain walls, applying a magnetic torque to at least a heated portion of the magnetic free layer to reverse the magnetization direction of the heated portion and form domain walls.

[0012] In one or more embodiments, the method further includes applying one or more control signals to a selection circuit configured to select only the analog NVM for conductivity reduction from a plurality of NVMs.

[0013] According to further embodiments of the present invention, an analog magnetoresistive random access memory (MRAM) is provided. The MRAM comprises a plurality of MRAM cells. Each of the plurality of cells includes a magnetic free layer having a first domain, a second domain, and a domain wall, the first domain having a first magnetization direction, the second domain having a second magnetization direction opposite to the first magnetization direction, and the domain wall being located between the first domain and the second domain. Each of the plurality of cells further includes a magnetic pinning layer. Each of the plurality of cells also includes an insulating tunnel barrier between the magnetic free layer and the magnetic pinning layer. Each of the plurality of cells further includes an electrode located adjacent to the magnetic free layer, the electrode being configured to generate heat by supplying current to reduce the conductivity of the magnetic free layer.

[0014] In one or more embodiments of the invention, each of the plurality of MRAM cells is coupled to a corresponding thermal selection circuit for heating one or more electrodes of the plurality of MRAM cells.

[0015] In one or more embodiments of the present invention, each of the plurality of analog MRAM cells is included in a corresponding synaptic element among a plurality of synaptic elements.

[0016] In one or more embodiments of the invention, the electrode reduces the conductivity of the magnetic free layer of only selected synaptic elements among the plurality of synaptic elements.

[0017] In one or more embodiments of the invention, the analog MRAM cell further includes a selection circuit configured to select one or more, but less than all, of the plurality of synaptic elements in response to a decrease in conductivity.

[0018] According to another aspect of the present invention, a method for resetting an analog magnetoresistive random access memory (MRAM) having a plurality of MRAM cells is provided. The method includes detecting the state of a magnetic free layer of each of the plurality of MRAM cells. The magnetic free layer has a first domain, a second domain, and a domain wall, the first domain having a first magnetization direction, the second domain having a second magnetization direction opposite to the first magnetization direction, and the domain wall being located between the first domain and the second domain. The state is detected based on the alignment of the first and second magnetization directions and the removal of the domain wall. The method further includes selecting one or more of the plurality of MRAM cells for a reset operation in response to detecting that the first and second magnetization directions are aligned and the domain wall is removed. The method further includes: supplying current to the electrodes of the selected one or more of the plurality of MRAM cells to generate heat to randomize the magnetization of the cells; and applying a magnetic torque to at least a heated portion of the magnetic free layer to reverse the magnetization direction of the heated portion and form the domain wall.

[0019] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which will be read in conjunction with the accompanying drawings. Attached Figure Description

[0020] The following description will provide details of preferred embodiments with reference to the following figures, in which:

[0021] Figure 1 This is a schematic diagram illustrating four exemplary conductive states of an analog MRAM cell to which the present invention can be applied;

[0022] Figure 2 This is a block diagram illustrating an exemplary analog MRAM cell according to an embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of an exemplary analog MRAM cell according to an embodiment of the present invention;

[0024] Figure 4 This is a flowchart illustrating an exemplary method for performing a step-by-step reset on a selected non-volatile memory (NVM) element according to an embodiment of the present invention;

[0025] Figure 5 This is a block diagram illustrating an exemplary analog MRAM cell according to an embodiment of the present invention;

[0026] Figure 6 This is a block diagram illustrating an exemplary structure of an analog MRAM cell according to an embodiment of the present invention;

[0027] Figure 7 This is a block diagram illustrating the computation of an exemplary neural network unit according to an embodiment of the present invention;

[0028] Figure 8 This is a block diagram illustrating an exemplary simulated multiply-accumulate operation using NVM according to an embodiment of the present invention;

[0029] Figure 9 This is a block diagram illustrating an exemplary two-layer sensor according to an embodiment of the present invention;

[0030] Figure 10 This is a block diagram illustrating an exemplary simulated multiply-accumulate operation using multiple NVMs according to an embodiment of the present invention;

[0031] Figure 11 An exemplary computing device to which the invention can be applied is shown according to an embodiment of the invention;

[0032] Figure 12 This is a block diagram illustrating an exemplary artificial neural network (ANN) architecture according to an embodiment of the present invention; and

[0033] Figure 13 This is a block diagram illustrating an exemplary neuron according to an embodiment of the present invention. Detailed Implementation

[0034] Embodiments of the present invention relate to a non-volatile memory synaptic element with step-reset capability.

[0035] Embodiments of the present invention are capable of applying a stepwise reset operation to one or more selected synaptic elements and all synaptic elements, as required by the prior art reset methods described above.

[0036] Embodiments of the present invention involve placing an electrode on or adjacent to a magnetic free layer to generate heat in a selected synaptic element (having the magnetic free layer) and to randomize the magnetization in the edge of the magnetic free layer where the electrode is placed or adjacent.

[0037] The embodiments of the present invention can be used for deep learning.

[0038] Embodiments of the present invention can be integrated into large-scale integrated circuits (LSI). Heating and magnetic torque can be achieved by applying electrical signals using selected wires.

[0039] The embodiments of the present invention can be applied to reset operations based on Ampere's law and the principle of spin-transfer torque.

[0040] The embodiments of the present invention can be applied to vertically magnetized MRAM and horizontally magnetized MRAM.

[0041] To clearly describe the present invention, a brief description of the MRAM cell will now be given.

[0042] Data in MRAM is stored by magnetic storage elements. Each element consists of two ferromagnetic plates, each of which remains magnetized and is separated by a thin insulating layer. One of the plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match the magnetization of an external field to store the memory. This configuration is called a magnetic tunnel junction and is the simplest structure for MRAM bits. Memory devices are constructed from a grid of these "cells".

[0043] The simplest reading method is achieved by measuring the resistance of the battery. A particular cell is typically selected by powering an associated transistor that switches current from the power line through the cell to ground. Due to tunneling magnetoresistance, the resistance of a cell changes with the relative orientation of the magnetization in the two plates. By measuring the resulting current, the resistance inside any particular cell can be determined, and thus the magnetization polarity of the writable board can be determined. Generally, if the two plates have the same magnetization alignment (low resistance state), this is considered to represent a value of "1," while if the alignment is antiparallel, the resistance will be higher (high resistance state) and this represents a value of "0," although it should be understood that the invention is specifically aimed at analog outputs from an NVM with a gradually changing reset resistance, for example, with regard to multi-multiply-add operations using an analog NVM.

[0044] Furthermore, to clearly describe the invention, a brief description of specific conditions under which the MRAM cell to which the invention can be applied will now be given. These conditions relate to a charge distribution that would be quite difficult to reduce the conductivity of the MRAM cell without the invention.

[0045] See Figure 1The diagram shows four exemplary conductive states 110, 120, 130 and 140 of the analog MRAM cell 190 to which the present invention can be applied. Figure 1 Examples involve the case of vertically magnetized MRAM.

[0046] The analog MRAM cell 190 includes a synthetic antiferromagnetic portion 191, a tunnel barrier layer 192, a magnetic free layer 193, and a magnetic domain wall 194.

[0047] As shown by arrow 181 on the right, the conductivity increases with each state, starting from the first conductivity state 110 and progressing upwards through the fourth conductivity state 140.

[0048] The synthetic antiferromagnetic portion 191 comprises a first layer 191A above a second layer 191B. In each of the conductivity states 110 to 140, the first layer 191A and the second layer 191B have opposite magnetic orientations.

[0049] Antiferromagnetism is a type of magnetism in solids (such as manganese oxide (MnO)), where adjacent ions (in this case, manganese ions, MnO) act as tiny magnets. 2+ At relatively low temperatures, they spontaneously align themselves into opposite or antiparallel arrangements throughout the material, making it exhibit almost no overall external magnetism. In antiferromagnetic materials, which include some metals and alloys in addition to some ionic solids, the magnetism from magnetic atoms or ions oriented in one direction is canceled out by the same group of magnetic atoms or ions aligned in the opposite direction.

[0050] The tunnel barrier layer 192 is an insulating barrier between the synthetic antiferromagnetic portion 191 and the magnetic free layer 193. Electrons tunnel through the tunnel barrier layer via quantum tunneling, thereby applying a magnetic field to the magnetic free layer 193.

[0051] While the first layer 191A and the second layer 191B of the synthetic antiferromagnetic portion 191 have fixed magnetic polarities, the magnetic free layer 193 has variable magnetic polarities. When a magnetic field of appropriate strength is applied, the magnetic free layer 193 switches polarities, resulting in two distinct states: a parallel, low-resistance state; and an antiparallel, high-resistance state. Therefore, the first layer 191A and the second layer 19B of the synthetic antiferromagnetic portion 191 are considered magnetically "hard," while the magnetic free layer 193 is considered magnetically "soft." The resistance is higher when the magnetic layers are antiparallel than when they are aligned.

[0052] The magnetic domain wall 194 located in the magnetic free layer separates magnetic atoms or ions oriented in a first direction from magnetic atoms or ions oriented in a second direction opposite to the first direction.

[0053] In the first conductivity state 110, the second conductivity state 120, and the third conductivity state 130, there is a mixture of magnetic atoms or ions oriented along the first and second directions in the magnetic free layer 193.

[0054] However, in the fourth conductivity state 140, only magnetic atoms or ions in the second layer 191B of the adjacent magnetic free layer 193 exist in a single direction of the first and second directions, matching the orientation of the magnetic atoms or ions. Therefore, once the simulated MRAM cell 190 is in the fourth conductivity state 140, it is not easy to reduce the conductivity.

[0055] Therefore, an NVM synaptic element is needed, which has a gradual reset capability, especially the ability to reduce conductivity in the fourth conductivity state 140. The present invention satisfies the above-mentioned need.

[0056] See Figure 2 An exemplary analog MRAM cell 200 according to an embodiment of the present invention is shown. Figure 2 Examples involve the case of vertically magnetized MRAM.

[0057] The analog MRAM cell 200 includes a magnetic pinning layer 291, an insulating tunnel barrier layer 292, a magnetic free layer 293, magnetic domain walls (not shown, corresponding to a fourth conductivity state 140 which lacks such domain walls due to the presence of charge in only one orientation in the magnetic free layer 293), and electrodes 295.

[0058] The magnetic pinning layer 291 comprises a first layer 291A and a second layer 291B disposed below the first layer 291A. The magnetic pinning layer 291 is formed of an antiferromagnetic material. Exemplary antiferromagnetic materials that can be used in the magnetic pinning layer 291 include, but are not limited to, any of molybdenum (CoPt), ruthenium (Ru), tantalum (Ta), and ferroboron (FeB). Other materials can, of course, be used. In some embodiments herein, an intermediate layer of Ru (or other antiferromagnetic material) may be disposed between the first layer 291A and the second layer 291B. The top pinning layer 291A is antiferromagnetically coupled to the bottom pinning layer 291B via interlayer exchange coupling with a non-magnetic layer (e.g., Ru). The purpose of the intermediate layer is to utilize the antiferromagnetic interlayer exchange coupling effect, which prevents read / write interference caused by insufficient stability of the pinned layer. In practice, the intermediate layer cannot be removed, as removal would result in insufficient stability of the pinned layer. Ru or iridium (Ir) is typically used as the intermediate layer.

[0059] The insulating tunnel barrier layer 292 is formed of any material such as magnesium oxide (MgO), but is not limited to this. Of course, other materials can be used.

[0060] The magnetic free layer 293 is formed from, but is not limited to, any iron boron (FeB), tantalum (Ta), etc. Of course, other materials can be used.

[0061] Domain walls, when present, form in adjacent portions with different domain orientations.

[0062] Electrode 295 is formed of a conductor. In an embodiment, electrode 295 may be formed of a metal. Of course, the metal may include, but is not limited to, titanium nitride (TiN), nickel-chromium alloy, iron-chromium-aluminum alloy (Kanthal), and copper-chromium alloy, and other materials may also be used.

[0063] The MRAM cell 200 has a stepwise reset capability provided by placing the electrode 295 on or near the magnetic free layer 293. Specifically, the edge 293E of the magnetic free layer 293 is heated by the electrode 295 to randomly magnetize the edge 293E. This reduces the conductivity.

[0064] See Figure 3 An exemplary analog MRAM cell 300 according to an embodiment of the present invention is shown.

[0065] The analog MRAM cell 300 includes a memory device 301, a first metal-oxide-semiconductor field-effect transistor (MOSFET) 311, a second MOSFET 312, a third MOSFET 313, a fourth MOSFET 314, a set of vertically oriented control lines 321, and a set of horizontally oriented control lines 322.

[0066] Memory device 301 includes the following inputs:

[0067] rl: Read line input

[0068] wl: Write line input

[0069] cm: ordinary

[0070] heat: heat input

[0071] The set of vertically oriented control lines 321 includes the following:

[0072] rcs: Read column selection

[0073] rwc1: Read / Write column line

[0074] WCs: Write Column Selection

[0075] HTCL: Hot Column Pipeline

[0076] The set of horizontally oriented control lines 322 includes the following:

[0077] rrl: Read line count

[0078] wrl: Write line

[0079] rws: Read / Write line selection

[0080] HTS: Hot Selectivity

[0081] Reference Figure 4 An exemplary method 400 for performing a step-by-step reset of a selected non-volatile memory (NVM) element according to an embodiment of the present invention is illustrated. In this embodiment, the selected NVM element is an NVM synaptic element.

[0082] At box 410, the state of the magnetic free layer of the MRAM is detected. The magnetic free layer has a first domain, a second domain, and domain walls. The first domain has a first magnetization direction, the second domain has a second magnetization direction opposite to the first magnetization direction, and the domain walls are located between the first and second domains. The state is detected based on the alignment of the first and second magnetization directions and the removal of the domain walls. In an embodiment, detection is achieved based on the detected conductivity of the magnetic free layer indicating a single magnetic direction without domain walls.

[0083] In box 420, determine whether the detection state indicates that the first and second magnetization directions are aligned and the domain walls have been removed. If yes, proceed to box 430. Otherwise, return to box 410.

[0084] In box 430, one or more selection signals are used to select the synaptic element. (The remaining text appears to be incomplete and requires further context.) Figure 3 In one embodiment, the synaptic element is selected by choosing hts / htcl.

[0085] In box 440, a stepwise reset is applied using one or more reset signals to supply current to the electrodes to generate heat, thereby randomizing the magnetization of the cells (at locations near the electrodes in the magnetic free layer) and applying a magnetic torque to at least the heated portion of the magnetic free layer to reverse the magnetization direction of the heated portion and form domain walls. The heat can be controlled by applying short-duration current pulses. For example, a 100 μA current of 50-100 ns can be applied. Of course, depending on the implementation, other amplitudes, durations, and wave types can be applied. (The text then abruptly shifts to a seemingly unrelated topic about induction and frequency.) Figure 3 In this embodiment, a gradual reset is applied by selecting wrl / wcs and rwrs / rwcl. The RESET is described as gradual because it can be applied to the heated portion of the magnetic free layer 293.

[0086] See Figure 5 An exemplary analog MRAM cell 500 according to an embodiment of the present invention is shown. Compared with the previous... Figure 2 and Figure 3 And subsequently Figure 6 Compared to the examples, Figure 5 Examples involve the case of horizontally magnetized MRAM.

[0087] The analog MRAM cell 500 includes a magnetic pinning layer 591 (formed by layers 591A and 591B), an insulating tunnel barrier layer 592, a magnetic free layer 593, a magnetic domain wall (not shown, corresponding to a fourth conductivity state 140 in which there is charge in only one orientation in the magnetic free layer 593 and such a domain wall is lacking), and an electrode 595.

[0088] refer to Figure 6 An exemplary structure 601 of an analog MRAM cell 600 according to an embodiment of the present invention is shown. Figure 6 Examples involve the case of vertically magnetized MRAM.

[0089] Structure 601 includes a pinned layer 691 of synthetic antiferromagnetic material (formed by layers 691A and 691B), an insulating tunnel barrier 692, a magnetic free layer 693, a magnetic domain wall 694, and an electrode 695. Structure 601 also includes a write line (W1L) 611, a read line (RL) 612, and a cm 613. Electrode 695 is heated by a heating wire 621, one end of which is connected to a power source and the other end is grounded.

[0090] WL 611 can be formed from materials such as, but not limited to, copper, aluminum, etc.

[0091] rl 612 can be formed from materials such as, but not limited to, copper, aluminum, etc.

[0092] cm 613 can be formed from materials such as, but not limited to, copper, aluminum, etc.

[0093] The heating wire 621 can be formed from any suitable conductor, including but not limited to copper, aluminum, etc.

[0094] As depicted, heating of electrode 695 via heating wire 621 causes randomization of magnetic atoms or ions in adjacent electrode 695, thereby causing a decrease in the conductivity of analog MRAM cell 600.

[0095] Thus, the simulated NVM 600 can be extracted from the fourth conductivity state 140, resulting in a mixture of magnetic atoms or ions with oriented directions in the magnetic free layer 693. This mixture comprises a first domain 631 having a first orientation, a second domain 632 having a second orientation opposite to the first orientation, and domain walls 633 for separating the first domain 631 from the second domain 632. As can be seen, such heating can cause the simulated NVM 600 to be placed in the second conductivity state 120, where here... Figure 6 The charge distribution shown is similar to Figure 1 The charge distribution is shown in the figure.

[0096] Embodiments of the present invention can be used for neural network unit computation. (See also...) Figure 7 An exemplary neural network unit computation 700 according to an embodiment of the present invention is illustrated. This computation involves simulating output. The neural network unit computation 700 can be performed using one or more NVMs configured according to embodiments of the present invention.

[0097] The inputs to the neural network unit for computation 700 include: x1; x2; x3; and x4, where x i It is the value of the i-th feature of the input vector. The output of the neural network unit, calculated as 700, is z. The activation function is... ,

[0098] in

[0099]

[0100] ,

[0101] w i This represents the i-th weight.

[0102] Embodiments of the present invention can be used for simulating multiplication-addition operations using NVM. (See reference) Figure 8 An exemplary analog multiply-accumulate operation 800 using NVM 801 is shown according to an embodiment of the present invention.

[0103] The NVM 801 is coupled to a voltage source V and a current source I.

[0104] The inputs to the NVM include: x1; x2; x3; and x4, where x i It is the value of the i-th feature of the input vector.

[0105] The current through the i-th element (transistor) is equal to

[0106] in

[0107] g i This represents the conductivity value of the i-th element.

[0108] The following equations apply:

[0109]

[0110]

[0111]

[0112]

[0113]

[0114]

[0115] Embodiments of the present invention can be used in a two-layer sensor. (See reference...) Figure 9 An exemplary two-layer sensor 900 according to an embodiment of the present invention is shown. The sensor 900 provides an analog output.

[0116] The inputs to the two-layer perceptron 900 include: x1; x2; x3; and x4, where x i It is the value of the i-th feature of the input vector. The output of the neural network unit, which calculates 700, is... .right The activation function is ,

[0117] right The activation function is ,,

[0118] right The activation function is ,,

[0119] in

[0120]

[0121]

[0122]

[0123] and w ij This represents the i-th weight of the j-th eigenvector.

[0124] Embodiments of the present invention can be used for simulated multiplication-addition operations with multiple NVMs. See reference... Figure 10 An exemplary analog multiplication-addition operation 1001-1003 using multiple NVMs 1011 to 1013 is shown according to an embodiment of the present invention.

[0125] The first analog multiplication-addition operation 1001 involves conductivity g. 11 g 12 g 13 and g 14 .

[0126] The second analog multiplication-addition operation 1002 involves conductivity g. 21 g 22 g 23 and g 24 .

[0127] The third analog multiplication-addition operation 1003 involves conductivity g. 31 g 32 g 33 and g 34 .

[0128] The current through the i-th element (transistor) is equal to ,

[0129] in

[0130] g ij This represents the conductivity value of the i-th column in the j-th column.

[0131] The following equations apply:

[0132]

[0133]

[0134]

[0135]

[0136] In the implementation, I1, I2 and I3 are used independently (i.e., I is not counted).

[0137] refer to Figure 11 An exemplary computing device 1100 according to an embodiment of the present invention is shown. The computing device 1100 is configured for deep learning and includes NVM synaptic elements 130A in memory 130, wherein the NVM synaptic elements have a gradual reset capability. In particular, the NVM synaptic elements can be selectively reset (e.g., a subset of the set of NVM synaptic cells) and can reduce conductivity even when the selected synaptic element is in a conductivity state 140.

[0138] The computing device 1100 can be embodied as any type of computing or computer device capable of performing the functions described herein, including but not limited to computers, servers, rack-based servers, blade servers, workstations, desktop computers, laptop computers, notebook computers, tablet computers, mobile computing devices, wearable computing devices, network devices, web devices, distributed computing systems, processor-based systems, and / or consumer electronics devices. Alternatively or additionally, the computing device 200 can be embodied as one or more computing racks, memory racks, or other racks, chassis, or other components of a physically separate computing device. Figure 11As shown, computing device 1100 illustratively includes processor 1110, input / output subsystem 1120, memory 1130, data storage device 1140, and communication subsystem 1150, and / or other components and means typically found in servers or similar computing devices. Of course, in other embodiments, computing device 1100 may include other or additional components, such as those typically found in server computers (e.g., different input / output devices). Additionally, in some embodiments, one or more of the illustrative components may be incorporated into another component or otherwise formed part of another component. For example, in some embodiments, memory 1130 or a portion thereof may be incorporated into processor 1110.

[0139] Processor 1110 may be embodied as any type of processor capable of performing the functions described herein. Processor 1110 may be embodied as a single processor, multiple processors, (or multiple) central processing units (CPUs), (or multiple) graphics processing units (GPUs), (or multiple) single-core or multi-core processors, (or multiple) digital signal processors, (or multiple) microcontrollers, or (or multiple) other processors or (or multiple) processing / control circuitry.

[0140] Memory 1130 may be embodied as any type of volatile or non-volatile memory or data storage device capable of performing the functions described herein. In operation, memory 1130 may store various data and software used during the operation of computing device 1100, such as operating systems, applications, programs, libraries, and drivers. Memory 1130 is communicatively coupled to processor 1110 via I / O subsystem 1120, which may be embodied as circuitry and / or components for facilitating input / output operations with processor 1110, memory 1130, and other components of computing device 1100. For example, I / O subsystem 1120 may be embodied as or otherwise include a memory controller hub, input / output control hub, platform controller hub, integrated control circuitry, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, optical fibers, printed circuit board traces, etc.) and / or other components and subsystems to facilitate input / output operations. In some embodiments, the I / O subsystem 1120 may be part of a system-on-a-chip (SOC) and integrated onto a single integrated circuit chip along with the processor 1110, memory 1130, and other components of the computing device 1100.

[0141] Data storage device 1140 can be embodied as one or more devices of any type configured for short-term or long-term data storage, such as, for example, memory devices and circuitry, memory cards, hard disk drives, solid-state drives, or other data storage devices. Data storage device 1140 can store program code for a deep learning algorithm 1140A using one or more NVM synaptic elements with step-reset capability. Part or all of the program code 1140A may be stored in memory 1130. Communication subsystem 1150 of computing device 1100 can be embodied as any network interface controller or other communication circuitry, device, or combination thereof capable of enabling communication between computing device 1100 and other remote devices via a network. Communication subsystem 1150 can be configured to implement such communication using any one or more communication technologies (e.g., wired or wireless communication) and associated protocols (e.g., Ethernet, InfiniBand®, Bluetooth®, Wi-Fi®, WiMAX, etc.).

[0142] As shown in the figure, the computing device 1100 may also include one or more peripheral devices 1160. Peripheral devices 1160 may include any number of additional input / output devices, interface devices, and / or other peripheral devices. For example, in some embodiments, peripheral devices 1160 may include a display, touchscreen, graphics circuitry, keyboard, mouse, speaker system, microphone, network interface, and / or other input / output devices, interface devices, and / or peripheral devices.

[0143] Of course, the computing device 1100 may also include other elements (not shown), as readily apparent to those skilled in the art, and some elements may be omitted. For example, different other input and / or output devices may be included in the computing device 1100, depending on the specific implementation of the computing device 1100, as readily understood by those skilled in the art. For example, different types of wireless and / or wired input and / or output devices may be used. Furthermore, additional processors, controllers, memories, etc., in different configurations may be utilized. Given the teachings of the invention provided herein, those skilled in the art will readily conceive of these and other variations of the processing system 1100.

[0144] As used herein, the terms "hardware processor subsystem" or "hardware processor" can refer to a processor, memory (including RAM, cache, etc.), software (including memory management software), or a combination thereof that cooperate to perform one or more specific tasks. In useful embodiments, a hardware processor subsystem may include one or more data processing elements (e.g., logic circuitry, processing circuitry, instruction execution means, etc.). These one or more data processing elements may be included in a central processing unit, a graphics processing unit, and / or a separate processor- or computing element-based controller (e.g., logic gates, etc.). A hardware processor subsystem may include one or more on-board memories (e.g., cache, dedicated memory array, read-only memory, etc.). In some embodiments, a hardware processor subsystem may include one or more memories (e.g., ROM, RAM, basic input / output system (BIOS), etc.) that may be on-board or off-board, or may be dedicated to use by the hardware processor subsystem.

[0145] In some embodiments, the hardware processor subsystem may include and execute one or more software elements. The one or more software elements may include an operating system and / or one or more applications and / or specific code for implementing a specified result.

[0146] In other embodiments, the hardware processor subsystem may include dedicated, special-purpose circuitry that performs one or more electronic processing functions to achieve a specified result. Such circuitry may include one or more application-specific integrated circuits (ASICs), FPGAs, and / or PLAs.

[0147] These and other variations of the hardware processor subsystem are also considered according to embodiments of the invention.

[0148] Reference Figure 12 An exemplary artificial neural network (ANN) architecture 1200 according to an embodiment of the present invention is shown. It should be understood that this architecture is purely exemplary and other architectures or types of neural networks may be used alternatively. Specifically, while hardware embodiments of ANNs are described herein, it should be understood that neural network architectures can be implemented or simulated in software. The hardware embodiments described herein are intended to illustrate the general principles of neural network computation in a high-level general sense and should not be construed as limiting in any way.

[0149] Furthermore, the neuron layers and the weights connecting them described below are described in a general manner and can be replaced by any type of neural network layer with any appropriate degree or type of interconnectivity. For example, layers may include convolutional layers, pooling layers, fully connected layers, softmax layers, or any other suitable type of neural network layer. Additionally, layers can be added or removed as needed, and weights can be omitted for more complex forms of interconnection.

[0150] During the feedforward operation, a group of input neurons 1202 each provide an input voltage in parallel with the weights 1204 of the corresponding row. In the hardware embodiment described herein, each weight 1204 has a configurable resistance value such that the current output flows from the weight 1204 to the corresponding hidden neuron 1206 to represent the weighted input. In the software embodiment, the weights 1204 can be simply represented as coefficient values ​​multiplied by the output of the relevant neuron.

[0151] Following the hardware implementation, the current output by a given weight 1204 is determined, where V is the input voltage from the input neuron 1202, and r is the set resistance of the weight 1204. The currents from each weight are summed column-wise and flow to the hidden neuron 1206. A reference weight set 1207 has a fixed resistance and combines its outputs into a reference current provided to each hidden neuron in the hidden neuron 1206. Because conductivity values ​​can only be positive, some reference conductivity is needed to encode positive and negative values ​​in the matrix. The currents generated by the weights 1204 are continuously positive, and therefore the reference weights 1207 are used to provide a reference current above which the current is considered positive and below which the current is considered negative. In the software implementation, the reference weights 1207 are not required; in the software implementation, the values ​​of the outputs and weights can be obtained precisely and directly. As an alternative to using reference weights 1207, another embodiment may use a separate array of weights 1204 to capture negative values.

[0152] Hidden neurons 1206 use current from weight array 1204 and reference weights 1207 to perform a certain calculation. Hidden neurons 1206 then output their own voltages to another weight array 1204. This array operates in the same manner, where a column of weights 1204 receives voltages from its corresponding hidden neurons 1206 to produce a weighted current output that is added row-by-row and provided to output neurons 1208.

[0153] It should be understood that any number of these stages can be achieved by inserting additional layers of the array and hidden neurons 1206. It should also be noted that some neurons can be constant neurons 1209 that provide a constant output to the array. Constant neurons 1209 may be present between input neurons 1202 and / or hidden neurons 1206, and are used only during feedforward operations.

[0154] During backpropagation, output neurons 1208 provide a reverse voltage across weight array 1204. The output layer compares the generated network response with the training data and calculates the error. The error is applied to the array as a voltage pulse, where the pulse height and / or duration is modulated proportionally to the error value. In this example, a row of weights 1204 receives the voltage from the corresponding output neuron 1208 in parallel and converts it into a current, which is then phased column-wise to provide input to the hidden neuron 1206. The hidden neuron 1206 combines the weighted feedback signal with its derivative calculated from its feedforward and stores the error value before outputting the feedback signal voltage to its corresponding weight column 1204. This backpropagation travels through the entire network 1200 until all hidden neurons 1206 and input neurons 1202 have stored the error value.

[0155] During weight updates, input neurons 1202 and hidden neurons 1206 apply a first weight update voltage forward through network 1200, and output neurons 1208 and hidden neurons 1206 apply a second weight update voltage backward through network 1200. The combination of these voltages produces a state change within each weight 1204, causing weight 1204 to exhibit a new resistance value. In this way, weights 1204 can be trained to adapt the neural network 1200 to errors in its processing. It should be noted that the three operating modes (feedforward, feedback propagation, and weight update) do not overlap.

[0156] As described above, the weights 1204 can be implemented in software or hardware, for example, using relatively complex weighting circuits or resistive cross-point devices. Such resistive devices can have switching characteristics that provide nonlinearity for data processing. The weights 1204 can belong to a class of devices known as resistive processing units (RPUs) because their nonlinear characteristics are used to perform computations in the neural network 1200. RPU devices can be implemented using resistive random access memory (RRAM), phase-change memory (PCM), programmable metallized cell (PMC) memory, or any other device with nonlinear resistive switching characteristics. Such RPU devices can also be considered memristor systems.

[0157] refer to Figure 13 An exemplary neuron 1300 according to an embodiment of the present invention is shown. This neuron may represent any one of input neuron 1202, hidden neuron 1206, or output neuron 1208. It should be noted that... Figure 13The components that handle all three operational phases are shown: feedforward, backpropagation, and weight update. However, since the different phases do not overlap, there must be some form of control mechanism within neuron 1300 to control which components are active. Therefore, it should be understood that switches and other structures, not shown, may exist within neuron 1300 to handle mode switching.

[0158] In feedforward mode, difference block 1302 determines the value of the input by comparing the input from the array with a reference input. This sets the magnitude and sign (e.g., + or -) of the input from the array to neuron 1300. Block 1304 performs a computation based on this input, and the output of this input is stored in memory 1305. Specifically, block 1304 computes a nonlinear function and can be implemented as an analog or digital circuit or executed in software. The value determined by function block 1304 is converted into a voltage at feedforward generator 1306, which applies a voltage to the next array. The signal propagates through multiple layers of the array and neurons until it reaches the final output layer of the neuron. In block 1308, the input is also applied to the derivative of the nonlinear function, and its output is stored in memory 1309.

[0159] During the backpropagation phase, an error signal is generated. This error signal can be generated at the output neuron 1208, or it can be computed by a separate unit that receives input from the output neuron 1208 and compares the output with the correct output based on training data. Alternatively, if neuron 1300 is a hidden neuron 1206, it receives backpropagation information from the weight array 1204 and compares the received information with a reference signal at the difference block 1310 to provide a signed error signal with continuous values. This error signal is multiplied by multiplier 1312 with the derivative of the nonlinear function of the previous feedforward step stored in memory 1309, the result of which is stored in memory 1313. The value determined by multiplier 1312 is converted into a backpropagation voltage pulse proportional to the error computed at backpropagation generator 1314, which applies a voltage to the previous array. The error signal propagates in this way through multiple layers of the array and neurons until it reaches the input layer 1202 of the neuron.

[0160] During the weight update mode, after each forward and backward pass, each weight 1204 is updated proportionally to the product of the signals passed through the weights during the forward and backward passes. The update signal generator 1316 provides voltage pulses in both directions (although note that only one direction will be available for both input and output neurons). The shape and amplitude of the pulses from the update generator 1316 are configured to change the state of the weights 1204, causing the resistance of the weights 1204 to be updated.

[0161] It should be understood that the present invention will be described based on the given illustrative architecture; however, other architectures, structures, substrate materials, and process features and steps may vary within the scope of the present invention.

[0162] It should also be understood that when a component, such as a layer, region, or substrate, is referred to as being "on" or "above" another component, the component may be directly on the other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly on" or "directly on" another component, there are no intermediate components. It should also be understood that when a component is referred to as being "connected" or "coupled" to another component, it may be directly connected or coupled to the other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0163] This embodiment may include a design for an integrated circuit chip, which can be created using a graphical computer programming language and stored in a computer storage medium, such as a disk, magnetic tape, physical hard disk drive, or virtual hard disk drive, such as in a storage access network. If the designer does not manufacture the chip or the photomask used to manufacture the chip, the designer may transfer the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for manufacturing the photomask, which typically comprises multiple copies of the chip design in question to be formed on a wafer. The photomask is used to define areas of the wafer (and / or layers thereon) to be etched or otherwise processed.

[0164] The methods described herein can be used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other more advanced carrier) or a multi-chip package (such as a ceramic carrier with one or two surface interconnects or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0165] It should also be understood that the material compounds will be described based on the listed elements (e.g., SiGe). These compounds include elements in different proportions within the compound; for example, SiGe includes Si.x Ge 1-x Where x is less than or equal to 1, etc. Furthermore, other elements may be included in the compound and still function according to the principles of the invention. Compounds with additional elements will be referred to herein as alloys.

[0166] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. It should be further understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0167] For ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” are used herein to describe the relationship of one element or feature to another. It will be understood that spatial relative terms are intended to cover different orientations of a device in use or operation beyond those depicted in the figure. For example, if the device in the figure is flipped, an element described as “below” or “beneath” of another element or feature will be oriented as “above” of that element or feature. Thus, the term “below” can encompass both above and below orientations. A device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein will be interpreted accordingly. Furthermore, it should be understood that when a layer is referred to as “between” two layers, the layer may be the only layer between the two layers, or one or more intermediate layers may exist.

[0168] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the scope of the inventive concept, the first element discussed below may be referred to as the second element.

[0169] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0170] References to the invention in this specification as "one embodiment" or "embodiment" and other variations thereof mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification, as well as any other variations, do not necessarily refer to the same embodiment.

[0171] It should be understood that, for example, in the cases of “A / B,” “A and / or B,” and “at least one of A and B,” the use of any of the following “ / ,” “and / or,” and “at least one of” is intended to include selecting only the first listed item (A), or only the second listed item (B), or selecting both options (A and B). As another example, in the cases of “A, B, and / or C” and “at least one of A, B, and C,” this wording is intended to cover only the selection of the first listed option (A), or only the selection of the second listed option (B), or only the selection of the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed items (A and C), or only the second and third listed items (B and C), or all three options (A, B, and C). It will be apparent to those skilled in the art that this can be extended for many of the listed items.

[0172] Preferred embodiments of the systems and methods have been described (these are intended to be illustrative and not restrictive), and it should be noted that modifications and variations can be made by those skilled in the art based on the foregoing teachings. Therefore, it should be understood that changes may be made to the specific embodiments disclosed within the scope of the invention as outlined in the appended claims. Various aspects of the invention, having the details and features required by patent law, have thus been described, and the claimed and desired protection by a patent certificate is set forth in the claims.

[0173] In a preferred embodiment of the invention described herein, a method for resetting an analog magnetoresistive random access memory (MRAM) having a plurality of MRAM cells is provided, comprising: detecting the state of a magnetic free layer of each of the plurality of MRAM cells, the magnetic free layer having a first domain having a first magnetization direction, a second domain having a second magnetization direction opposite to the first magnetization direction, and a domain wall located between the first and second domains, wherein the detection state is based on alignment of the first and second magnetization directions and removal of the domain wall; selecting one or more of the plurality of MRAM cells for a reset operation in response to alignment of the first and second magnetization directions and removal of the domain wall; and supplying current to electrodes of the selected one or more MRAM cells to generate heat to randomize the magnetization of the cells, and applying a magnetic torque to at least a heated portion of the magnetic free layer to reverse the magnetization direction of the heated portion and form the domain wall.

Claims

1. An analog magnetoresistive random access memory (MRAM) cell, comprising: A magnetic free layer having a first domain, a second domain, and domain walls, wherein the first domain has a first magnetization direction, the second domain has a second magnetization direction opposite to the first magnetization direction, and the domain walls are located between the first domain and the second domain; Magnetic pinning layer; An insulating tunnel barrier between the magnetic free layer and the magnetic pinning layer; as well as An electrode, located near the magnetic free layer, is configured to generate heat by supplying current to reduce the conductivity of the magnetic free layer, thereby providing step-by-step reset capability for the analog MRAM cell.

2. The analog MRAM cell according to claim 1, wherein, The magnetic pinning layer includes at least one antiferromagnetic material.

3. The analog MRAM cell according to claim 1, wherein, The first domain and the second domain include magnetic elements.

4. The analog MRAM cell according to claim 1, wherein, The analog MRAM cell is contained within the synaptic element.

5. The analog MRAM cell according to claim 4, wherein, The electrode reduces the conductivity of the magnetic free layer of the synaptic element only among the plurality of synaptic elements.

6. The analog MRAM cell of claim 5, further comprising a selection circuit configured to select only the synaptic elements from the plurality of synaptic elements for reducing conductivity.

7. The analog MRAM cell according to claim 1, wherein, The analog MRAM is horizontally magnetized.

8. The analog MRAM cell according to claim 1, wherein, The analog MRAM is vertically magnetized.

9. The analog MRAM cell according to claim 1, wherein, The electrode is in contact with a portion of the magnetic free layer.

10. The analog MRAM cell of claim 1, further comprising at least one thermal control transistor configured to control the application of current to the electrodes.

11. The analog MRAM cell according to claim 10, wherein, The at least one thermal control transistor is configured to supply current to the electrodes in response to corresponding control signals applied to the gate and drain of the at least one thermal control transistor.

12. The analog MRAM cell according to claim 1, wherein, The electrode is placed at the first end, which is one of the first and second ends, so that the magnetization direction of at least the first end is randomized.

13. The analog MRAM cell according to claim 1, wherein, The electrode is configured to generate heat by providing the current to reduce the conductivity of the magnetic free layer, thereby randomizing the magnetization direction of at least a portion of the magnetic free layer.

14. The analog MRAM cell according to claim 1, wherein, The analog MRAM cell is integrated into a large-scale integrated circuit.

15. The analog MRAM cell according to claim 1, wherein, The heat generated from the electrodes produces a local magnetic field only in the analog MRAM cells among the multiple MRAM cells forming the memory array.

16. A method for resetting analog MRAM, comprising: The state of the magnetic free layer of the simulated MRAM is detected. The magnetic free layer has a first domain, a second domain, and domain walls. The first domain has a first magnetization direction, the second domain has a second magnetization direction opposite to the first magnetization direction, and the domain walls are located between the first and second domains. The detection state is based on the alignment of the first and second magnetization directions and the removal of the domain walls. In response to the alignment of the first and second magnetization directions and the removal of domain walls, current is supplied to the electrodes to generate heat to randomize the magnetization of the cells, thereby reducing the conductivity of the magnetic free layer, providing the analog MRAM with step-reset capability, and applying magnetic torque to at least the heated portion of the magnetic free layer to reverse the magnetization direction of the heated portion and form domain walls.

17. The method of claim 16, further comprising applying one or more control signals to a selection circuit configured to select only the analog MRAM used for conductivity reduction from a plurality of MRAMs.

18. The method according to claim 17, wherein, A local magnetic field is applied to the analog MRAMs in the plurality of MRAMs only by applying the current to the electrodes.

19. The method of claim 16, wherein, The provided steps include using the electrode to generate heat by supplying the current to reduce the conductivity of the magnetic free layer, thereby randomizing the magnetization direction of at least a portion of the magnetic free layer.

20. An analog magnetoresistive random access memory (MRAM), comprising: A plurality of MRAM cells, each of which is an MRAM cell as described in any one of claims 1 to 15.

21. The analog MRAM of claim 20, wherein each of the plurality of MRAM cells is coupled to a corresponding thermal selection circuit for heating one or more of the electrodes in the plurality of MRAM cells.

22. The analog MRAM according to claim 20, wherein, Each of the plurality of MRAM cells is included in a corresponding synaptic element among the plurality of synaptic elements.

23. The analog MRAM according to claim 22, wherein, The electrodes in the MRAM cell reduce the conductivity of the magnetic free layer of a selected synaptic element among the plurality of synaptic elements.

24. The analog MRAM of claim 23, further comprising a selection circuit configured to select one or fewer, but fewer than, of the plurality of synaptic elements in response to a decrease in conductivity.

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