A method and system for multiprocessor time division multiplexed GPIO

Abstract

The application provides a method and system for multiprocessor time division multiplexing GPIO, the method runs in a chip and comprises the following steps: initializing the value of each bit of a register to indicate the priority of a processor, the processor is connected with the corresponding bit of the register; gating a first processor to control a GPIO module; when the Nth processor needs to obtain the control right of the GPIO module, modifying the value of the corresponding bit of the register connected with the Nth processor in response to the interaction between the Nth processor and the first processor to obtain the control right; sending an enable signal of a bus control operation to enable the Nth processor to send a bus control operation to the back end; the Nth processor is any processor different from the first processor. Based on the method, a system for multiprocessor time division multiplexing GPIO is also provided. The application adopts the mode of multiprocessor time division multiplexing, uses the existing pins, and when the number of processors increases, different processors can be time division multiplexed through the priority arbitration scheme mechanism.

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