Integrated circuit device, method of manufacturing the same, and chip package

Abstract

Embodiments of the present application provide an integrated circuit (IC) device including a chip having a semiconductor substrate, and a thermoelectric module embedded in the semiconductor substrate, wherein the thermoelectric module includes a first semiconductor structure electrically connected to a second semiconductor structure, wherein a bottom of the thermoelectric module extends through a thickness of the semiconductor substrate, and wherein the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types. According to another embodiment of the present application, a chip package is also provided. According to yet another embodiment of the present application, a method for manufacturing an integrated circuit device is also provided.

Description

Technical Field

[0001] Embodiments of this application relate to chip packages, integrated circuit devices, and methods for manufacturing integrated circuit devices. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC design and materials have resulted in several generations of ICs, each with smaller and more complex circuits than the previous ones. In the course of IC development, functional density (i.e., the number of interconnect devices per chip area) has typically increased, while geometry (i.e., the smallest component (or wire) that can be produced using manufacturing processes) has decreased.

[0003] As semiconductor devices continue to shrink proportionally, manufacturing challenges may arise. For example, the processes for existing cooling devices in IC packages are not simple enough and may rely on external cooling systems to lower their operating temperatures. Therefore, while existing semiconductor manufacturing methods are generally sufficient to meet their intended purpose, they are not entirely satisfactory in every aspect. Summary of the Invention

[0004] According to an embodiment of this application, an integrated circuit device is provided, comprising: a chip including a semiconductor substrate; and a thermoelectric module embedded in the semiconductor substrate, wherein the thermoelectric module includes a first semiconductor structure electrically connected to a second semiconductor structure, wherein the bottom of the thermoelectric module extends through the thickness of the semiconductor substrate, and wherein the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types.

[0005] According to another embodiment of this application, a chip package is provided, comprising: a bottom chip including a first substrate; a top chip electrically bonded to the bottom chip, wherein the top chip includes a second substrate; and a thermoelectric device embedded in the second substrate, wherein the thermoelectric device includes an n-type structure connected to a p-type structure, and wherein each n-type structure and p-type structure extends to contact the bottom chip.

[0006] According to another embodiment of this application, a method for manufacturing an integrated circuit device is provided, comprising: forming a first semiconductor structure extending into a substrate; forming a second semiconductor structure extending into the substrate and adjacent to the first semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types; and forming a dielectric pad along the sidewalls of each of the first semiconductor structure and the second semiconductor structure.

[0007] Embodiments of this application relate to thermoelectric cooling of semiconductor devices. Attached Figure Description

[0008] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0009] Figure 1 This is a schematic diagram of an exemplary integrated chip package (or a portion thereof) according to various aspects of the present invention;

[0010] Figure 2A , Figure 3A , Figure 3B , Figure 3C , Figure 5A , Figure 5B , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E , Figure 8F , Figure 9A , Figure 9B , Figure 10E , Figure 10F , Figure 10G ,and Figure 10H This is a cross-sectional view of an exemplary integrated chip package (or a portion thereof) according to various aspects of the present invention;

[0011] Figure 2B and Figure 2C This is a schematic diagram illustrating the operation of an exemplary integrated chip package (or a portion thereof) according to various aspects of the present invention;

[0012] Figure 2D This is a flowchart of a method for using an exemplary integrated chip package (or a portion thereof) according to various aspects of the present invention;

[0013] Figure 4A , Figure 4B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 10A , Figure 10B , Figure 10C ,and Figure 10D This is a plan view of an exemplary integrated chip package (or a portion thereof) according to various aspects of the present invention;

[0014] Figure 11 This is a flowchart of a method for manufacturing an exemplary integrated chip package according to various aspects of the present invention;

[0015] Figure 12This is a flowchart of a method for manufacturing an exemplary integrated chip package (or a portion thereof) according to various aspects of the present invention;

[0016] Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 13E , Figure 13F ,and Figure 13G It is according to various aspects of the present invention, such as Figure 11 and / or Figure 12 A cross-sectional view of an exemplary integrated chip package (or a portion thereof) of an intermediate stage of the described method;

[0017] Figure 14 This is a flowchart of a method for manufacturing an exemplary integrated chip package (or a portion thereof) according to various aspects of the present invention;

[0018] Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 15E , Figure 15F , Figure 15G , Figure 15H , Figure 15I , Figure 15J ,and Figure 15K It is according to various aspects of the present invention, such as Figure 11 and / or Figure 14 A cross-sectional view of an exemplary integrated chip package (or a portion thereof) of an intermediate stage of the described method;

[0019] Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E , Figure 16F , Figure 16G , Figure 16H , Figure 16I , Figure 16J , Figure 16K , Figure 16L , Figure 16M , Figure 16N , Figure 16O , Figure 16P , Figure 16Q , Figure 16R ,and Figure 16S It is according to various aspects of the present invention, such as Figure 11 and / or Figure 14 A cross-sectional view of an exemplary integrated chip package (or a portion thereof) at an intermediate stage of the described method. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to readily describe the relationship between one element or component and another (or other) element or component as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. For example, if the device in the figure is flipped, an element described as “below” or “under” other elements or components will be oriented “above” other elements or components. Thus, the exemplary term “below” can encompass both above and below orientations. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0022] Furthermore, when using terms such as "approximately," "about," etc., to describe numbers or ranges of numbers, the term is intended to cover numbers that fall within a reasonable range of the numbers being described, such as within + / - 10% of the number being described, or other values ​​as understood by a person skilled in the art. For example, the term "approximately 5nm" covers a size range from 4.5nm to 5.5nm.

[0023] This invention generally relates to structures and methods for cooling semiconductor devices on an IC chip package. More specifically, the invention relates to internally cooling an IC chip package by utilizing a thermoelectric base module (or device) formed within the IC chip package. In some embodiments, the IC chip package may be formed as a System-on-Chip (SoIC) configuration, a Chip-on-Wafer-on-Substrate (CoWoS) configuration, an Integrated Fan-Out (InFO) configuration, a three-dimensional structure (3D structure) configuration, other configurations, or combinations thereof.

[0024] refer to Figure 1An exemplary IC chip package 100 is provided to include various semiconductor devices, such as a memory controller 110, multiple core devices 120, memory devices (e.g., L3 cache) 130, and other components 140, which may include non-core devices, queue devices, and / or I / O devices. The temperature of these and other devices in the package 100 may unintentionally increase during operation due to heat generation, and the resistance of various metal components (e.g., wires) may also increase. The heat generated by the various components of the IC chip package 100 may differ due to variations in pattern density. In this example, the core device 120 may generate more heat than other devices. This temperature rise can adversely affect the lifetime of dielectric components such as gate oxide materials. While existing chip cooling technologies are generally sufficient, they are not entirely satisfactory in all aspects. As next-generation devices are developed, multiple chips may need to be integrated (e.g., by bonding) to form a system with a reduced footprint. In some cases, it may be desirable to integrate cooling technologies internally within the chip system rather than using an external cooling system, or, in addition to using an external cooling system, to integrate cooling technologies internally within the chip system. Additionally, due to the varying amounts of heat generated, it may be desirable to integrate thermal detectors and associated control circuitry with cooling techniques to detect heating events in the chip system and implement cooling in the target area where such heating events occur.

[0025] Figure 2A A schematic cross-sectional view of an IC device 150 constructed in the XZ plane according to various embodiments of the present invention is shown. In some embodiments, the IC device 150 may be part of an IC chip package 100. In exemplary embodiments, the IC device 150 may include one or more core devices similar to the core device 120 of the IC chip package 100.

[0026] In this embodiment, the IC device 150 includes at least a thermal detector 200_1, a control circuit 200_2, and a heating / cooling device 200_3. In some embodiments, as depicted herein, the IC device 150 may include one or more of the thermal detector 200_1, the control circuit 200_2, and the heating / cooling device 200_3. In some embodiments, such as Figure 2A As depicted, the IC device 150 is formed (or provided) on a single chip above the substrate 202. In some embodiments, such as reference... Figure 3B The IC device 150 includes a top chip 200a, which is integrated with the bottom chip 200b.

[0027] refer to Figure 2AThe substrate 202 may include: elemental (single-element) semiconductors, such as silicon (Si), germanium (Ge), and / or other suitable materials; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 202 may be a single-layer material with a uniform composition. Alternatively, the substrate 202 may include multiple material layers with similar or different compositions suitable for IC device fabrication.

[0028] Substrate 202 may include various devices 204 separated by isolation structure 203, such as field-effect transistors (FETs), memory cells, imaging sensors, passive devices, other devices, or combinations thereof. In some embodiments, device 204 includes planar FETs, multi-gate 3D FETs (e.g., FinFETs, nanosheets, or all-around gate FETs), other suitable FETs, or combinations thereof. Reference Figure 1 Each device 204 may include a gate structure 205 that is coupled to an active region formed in or protruding from the substrate 202. In some embodiments, the substrate 202 may also include a through-silicon via (TSV) 206 that extends partially or entirely through the thickness of the substrate 202 to partially interconnect the top chip 200a and the bottom chip 200b.

[0029] The isolation structure 203 may include dielectric materials such as silicon oxide, tetraethyl orthosilicate (TEOS), doped silicon oxide (borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), etc.), low-k dielectric materials (having a dielectric constant less than that of silicon oxide, approximately 3.9), other suitable materials, or combinations thereof. The isolation structure 203 may include shallow trench isolation (STI) components.

[0030] In this embodiment, reference is also made to Figure 2AThe IC device 150 also includes a multilayer interconnect (MLI) structure 220 disposed above the device 204 and electrically connected to the device 204 via device-level contacts 218 formed in an interlayer dielectric (ILD) layer 208. The ILD layer 208 may include silicon oxide, a low-k dielectric material, TEOS, doped silicon oxide (e.g., BPSG, FSG, PSG, BSG, etc.), other suitable dielectric materials, or combinations thereof. The device-level contacts 218 may include at least a bulk conductive layer disposed above a barrier layer, wherein the bulk conductive layer may include W, Cu, Ru, Co, Al, other suitable materials, or combinations thereof, and the barrier layer may include TiN, TaN, or combinations thereof.

[0031] The MLI structure 220 may include various interconnect components, such as conductors 224 and vias 226 disposed in dielectric layers such as the ILD layer 221 and the etch stop layer (ESL) 222. In some embodiments, the via 226 is a vertical interconnect component configured to interconnect device-level contacts 218 with conductors 224, or configured to interconnect conductors 224 as horizontal interconnect components at various layers. The conductors 224 are distributed in multiple metal layers, such as a first metal layer (e.g., layer M1), a second metal layer (e.g., layer M2), etc.

[0032] In some embodiments, the IC device 150 further includes conductive pads 232 disposed in the dielectric layer 234 and above the MLI structure 220. The conductive pads 232 may be configured to electrically connect the MLI structure 220 to additional conductive components during the packaging process. The conductive pads 232 may comprise any suitable material, such as Al.

[0033] In some embodiments, the IC device 150 further includes a sealing ring structure 228 surrounding a portion of the IC device 150 to prevent stress and contaminants from adversely affecting the circuitry of the IC device 150 during the die-cutting process. The sealing ring structure 228 may include a conductive material, such as Cu, disposed above the seed layer and may be configured to extend through the MLI structure 220 to contact the substrate 202. The IC device 150 may include a passivation layer 231 disposed above the MLI structure 220 (e.g., above the topmost metal layer), which may be configured to provide isolation and protection for the components of the underlying IC device 150. In some embodiments, the passivation layer 231 includes silicon nitride (SiN), undoped silicon dioxide glass (USG), or a combination thereof.

[0034] Additionally, IC device 150 may include multiple chips packaged together in a desired configuration (e.g., top chip 200a above bottom chip 200b). In this regard, dielectric bonding film 238 may be formed over MLI structure 220. Dielectric bonding film 238 may include any suitable material, such as silicon oxide (SiO2). In some embodiments, dielectric bonding film 238 provides an interface for the hybrid bonding process discussed in detail below. In some embodiments, bumps 244 are also formed over the package material to electrically connect top chip 200a to another chip(s) or an external power source (e.g., external power source 250). Bumps 244 may include, for example, controlled-collapse chip connectors, or C4, and / or microbumps (μbumps), and may be electrically connected to portions of MLI structure 220 and / or TSV 206 via contact members 242 comprising, for example, Cu. In some embodiments, bump 244 is configured to electrically connect portions of IC device 150 to a package substrate, a through-hole, a redistribution layer (RDL), other suitable components, or combinations thereof, according to a desired package configuration. Furthermore, dielectric layer (or gap-filling layer) 236 may be formed along the sidewalls of substrate 202 to accommodate any differences in lateral dimensions between two stacked chips of IC device 150 during the packaging process. Dielectric layer 236 may comprise any suitable material, such as TEOS, silicon oxide, low-k dielectric materials, other suitable materials, or combinations thereof.

[0035] In some embodiments, still refer to Figure 2A The IC device 150 also includes a thermoelectric module (or thermoelectric device; hereinafter referred to as "module") 212 extending from the top surface of the substrate 202 to the bottom surface of the substrate 202. In this embodiment, module 212 is an integrated component of each thermal detector 200_1 and heating / cooling device 200_3. In this embodiment, module 212 is embedded in the substrate 202.

[0036] Relative to the heating / cooling device 200_3, module 212 can be electrically connected to an external power supply 250 via contact parts 242 and bumps 244. Alternatively, for which IC device 150 includes a stacked chip configuration (see, for example, see...) Figure 3BIn one embodiment, module 212 (e.g., top module 212a) of the top chip (e.g., top chip 200a) can be electrically connected to module 212 (e.g., bottom module 212b) of the bottom chip (e.g., bottom chip 200b) via a dielectric bonding film 238, conductive pads 232, MLI structure 220, and device-level contacts 218 disposed between the substrate of the top chip 200a (e.g., substrate 202a) and the substrate of the bottom chip 200b (e.g., substrate 202b). In this embodiment, heating / cooling device 200_3 is configured to transfer heat between the two junctions of module 212 when connected to an external power supply 250.

[0037] Relative to thermal detector 200_1, module 212 can be electrically connected to voltage sensor (e.g., voltmeter) 251, which is configured to detect the temperature difference between two junctions of module 212. Voltage sensor 251 can be connected to module 212 of thermal detector 200_1 in any suitable configuration.

[0038] Module 212 is configured as a thermoelectric device. In this embodiment, module 212 includes a pair of semiconductor structures, an n-type structure 214n and a p-type structure 214p, wherein the majority charge carriers in the n-type structure 214n are negatively charged (e.g., electrons), while the majority charge carriers in the p-type structure 214p are positively charged (e.g., holes). In this embodiment, module 212 is electrically and / or physically connected to device-level contacts 218 via a metal silicide layer 216. In some embodiments, the metal silicide layer (or silicide contact) 216 is formed over the top surface of each n-type structure 214n and p-type structure 214p by first depositing a metal layer comprising, for example, cobalt, nickel, and / or other suitable metals over the n-type structure 214n and p-type structure 214p, then applying a heat treatment to form the metal silicide, and removing any unreacted metal layer to expose the metal silicide layer 216. In some embodiments, a metal silicide layer 216 may also be formed between a device-level contact 218 and one or more devices 204.

[0039] In this embodiment, the n-type structure 214n includes a semiconductor material doped with an n-type dopant, and the p-type structure 214p includes a semiconductor material doped with a p-type dopant. The n-type structure 214n may include semiconductor materials such as Si, Ge, SiGe, other suitable materials, or combinations thereof, and the n-type dopant may include arsenic (As), phosphorus (P), other suitable dopant, or combinations thereof. The p-type structure 214p may include semiconductor materials such as Si, Ge, SiGe, other suitable materials, or combinations thereof, and the p-type dopant may include boron (B), gallium (Ga), indium (In), other suitable dopant, or combinations thereof. In some embodiments, the n-type structure 214n and the p-type structure 214p include the same semiconductor material but different dopants. For example, both the n-type structure 214n and the p-type structure 214p may include Si. In some embodiments, the n-type structure 214n and the p-type structure 214p include semiconductor materials with the same composition as the substrate 202 (or 202b). In some embodiments, the n-type structure 214n and the p-type structure 214p include different semiconductor materials. For example, the n-type structure 214n may include Si doped with an n-type dopant, while the p-type structure 214p may include SiGe doped with a p-type dopant. In this embodiment, the concentration of each type of dopant in the n-type structure 214n and the p-type structure 214p is at least about 10. 17 cm -3 In some embodiments, the concentration of each type of dopant is at least about 10. 19 cm -3 In some embodiments, if the concentration of charge carriers is less than about 10 17 cm -3 If the heat dissipated during the thermoelectric process is insufficient to achieve the desired cooling effect of the IC device 150.

[0040] refer to Figure 2A and Figure 2B Relative to the heating / cooling device 200_3, module 212 provides internal cooling of the IC device 150 through the Peltier effect, which describes the transfer of heat from the first region 252 to the second region 254 at the thermally conductive surfaces of two different materials (such as n-type structure 214n and p-type structure 214p) connected at each end by thermally conductive surfaces. In this regard, the n-type structure 214n and p-type structure 214p are thermally parallel and electrically series connected to each other, such that when direct current (DC) generated by the external power supply 250 flows through the n-type structure 214n and p-type structure 214p, a temperature difference is generated between the thermally conductive surfaces. Specifically, according to... Figure 2AIn the depicted arrangement, heat is transferred from a first region 252 near the top surface of the IC device 150 to a second region 254 near the bottom surface of the substrate 202, thereby cooling (some) of the circuitry 252 disposed in the first region. In other words, the first region 252 becomes a relatively cooler region, while the second region 254 becomes a relatively hotter region. In this respect, charge carriers in the module 212 move from the first region 252 to the second region 254, as... Figure 2A As shown. While the present invention is generally directed to a method of cooling components of IC device 150, the heating / cooling device 200_3 can also be implemented to heat components of IC device 150 to a suitable temperature for operation in freezing or other cold environments (e.g., polar environments). In this regard, the components of IC device 150 that need to be heated by the heating / cooling device 200_3 will be located in the second region 254.

[0041] refer to Figure 2A and Figure 2C Relative to thermal detector 200_1, module 212 is configured to sense the temperature difference (ΔT) between the two thermally conductive surfaces of thermal detector 200_1 based on the Seebeck effect. Specifically, ΔT between the first region 252 and the second region 254 generates a potential difference (ΔV) in an open circuit. ΔV can be measured by connecting module 212 to voltage sensor 251. In this respect, module 212 functions as a temperature-sensing thermocouple.

[0042] Figure 2D An exemplary embodiment of a method 160 for using IC device 150 is depicted. In operation 162, thermal detector 200_1 senses a temperature increase ΔT in one or more regions (e.g., first region 252) of IC device 150 due to heat generated during operation. In operation 164, if the temperature change exceeds a threshold of IC device 150 (or a portion thereof), which may be determined based on specific design requirements, method 160 activates control circuitry 200_2. Subsequently, in operation 166, control circuitry 200_2 applies a voltage, for example, provided by external power supply 250, to heating / cooling device 200_3 to remove heat from the first region 252 where the functional device is located via a thermoelectric mechanism (e.g., Peltier effect).

[0043] Figures 3A-10H Various embodiments of IC device 150 (or a portion thereof) are depicted. Unless otherwise specified, module 212 (e.g., top module 212a and bottom module 212b) may be a component of thermal detector 200_1 or a component of heating / cooling device 200_3.

[0044] Figure 3A An exemplary embodiment of the IC device 150 is depicted. Figure 3ABasically similar Figure 2A The difference lies in the illustration, which shows an alternative configuration in which voltage sensor 251 is connected to module 212. In this regard, voltage sensor 251 can be connected to module 212 via contact member 242 and TSV 206. In some embodiments, module 212 can be electrically connected to voltage sensor 251 via TSV 206 to form thermal detector 200_1. In some embodiments, module 212 can be electrically connected to an external power source via TSV 206. Figure 3A (Not depicted in the text) to form a heating / cooling device 200_3.

[0045] In some embodiments, reference Figure 3B The IC device 150 includes a top chip (or top die) 200a on a substrate 202, which is bonded to a bottom chip (or bottom die) 200b on a substrate 202b, thereby obtaining a stacked chip IC device 150. Figure 3B The depicted embodiments may be substantially similar to one or both of the top chip 200a and the bottom chip 200b. Therefore, Figure 2A and Figure 3B Components are typically depicted using reference numerals with the letters "a" or "b" to indicate whether the reference is to the top chip 200a or the bottom chip 200b.

[0046] In this embodiment, the top chip 200a and the bottom chip 200b are stacked vertically and bonded directly to each other at the interface in the 3D integrated package design. In some embodiments, as depicted herein, the top chip 200a is bonded to the bottom chip 200b in a back-to-back configuration. In some embodiments, the top chip 200a and the bottom chip 200b are bonded in a face-to-face configuration. The IC device 150 may be part of a SoIC configuration, a CoWoS configuration, an InFO configuration, other suitable 3D package configurations, or a combination thereof. In some embodiments, the top chip 200a and the bottom chip 200b are bonded using a hybrid bonding process. The hybrid bonding process can be achieved by fusing the dielectric bonding film 238 on the bottom surface of the top chip 200a to the dielectric bonding film 238 on the top surface of the bottom chip 200b, and by fusing the exposed metal surface of the bottom surface of the top chip 200a to the exposed dielectric element of the top surface of the bottom chip 200b. An exemplary hybrid bonding process may include: multiple chemical mechanical polishing (CMP) steps to provide a highly flat bonding surface; a cleaning step to clean the bonding surface (including dielectric and metal surfaces); a surface activation step to activate the bonding surface; a wafer-to-wafer alignment step; and an annealing / bonding step.

[0047] Still referencing Figure 3BThe top chip 200a and the bottom chip 200b may include similar components. For example, both the top chip 200a and the bottom chip 200b may include a substrate 202a / 202b, modules 212a / 212b, a plurality of devices 204 disposed above and / or therein on the substrate 202b, an MLI structure 220 disposed above the devices 204 and electrically connected to the devices 204 via device-level contacts 218, and a passivation layer 231 disposed above the MLI structure 220. The bottom chip 200b may also include a plurality of conductive pads 232 embedded in one or more dielectric bonding films 238 to electrically connect portions of the bottom chip 220b (e.g., TSV 206 and MLI 220) to portions of the top chip 200a via the hybrid bonding process described above. Additional and / or alternative bonding materials may also be used according to various embodiments of the invention. For example, inserts and / or bumps such as bump 244 can be used to bond the top chip 200a to the bottom chip 200b, another chip, and / or a package substrate.

[0048] In some embodiments, top module 212a extends from the top surface of substrate 202a to the bottom surface of substrate 202a and contacts the top of bottom chip 200b, while bottom module 212b extends from the top surface of substrate 202b to the bottom surface of substrate 202b. In the depicted embodiment, top module 212a and bottom module 212b are electrically connected via dielectric bonding film 238, conductive pads 232, MLI structure 220, and device-level contacts 218. Additionally, top module 212a and bottom module 212b can be connected to an external power supply 250 via contact members 242 and bumps 244. In this embodiment, top module 212a and bottom module 212b are embedded in substrate 202 and substrate 202b, respectively.

[0049] In some embodiments, reference Figure 3C The IC device 150 includes a top module 212a embedded in a substrate 202a, but does not include a bottom module 212b embedded in a substrate 202b, such as Figure 3A As shown. In this respect, the top module 212a is electrically connected to the external power supply 250 via the MLI220 of the top chip 200a, rather than via the bottom chip 200b. Therefore, the movement of charge carriers is related to... Figure 2A and Figures 3A-3B Conversely, a first heat-removing region 252 is disposed within the bottom chip 200b. In some embodiments, Figure 3C The depicted first region 252 includes at least a portion of the device 204 of the bottom chip 200b and the MLI 220.

[0050] Figure 4A The IC device 150 is shown as follows Figure 2Aand Figures 3A-3C A top plan view of the portion within the dashed ellipse enclosed in the XY plane. Figure 4B The top module 212a (or bottom module 212b) is shown in more detail. The top 215 of the top module 212a (or bottom module 212b) extends through the top surface of the substrate 202 (or substrate 202b) and is disposed between the isolation structure 203 and the gate structure 205 (or other components of the device 204). In this embodiment, the n-type structure 214n and the p-type structure 214p are surrounded by a dielectric pad 210 configured to electrically decouple (or isolate) each structure from the substrate 202 (or substrate 202b). The dielectric pad 210 may comprise any suitable material, such as silicon oxide (SiO2). In this embodiment, a metal silicide layer 216 is disposed above each n-type structure 214n and p-type structure 214p. In some embodiments, the metal silicide layer 216 surrounds each n-type structure 214n and p-type structure 214p. In some examples, the metal silicide layer 216 may be configured to have a substantially circular shape. The metal silicide layer may include suitable materials such as cobalt silicide (CoSi), nickel silicide (NiSi), other suitable materials, or combinations thereof.

[0051] The top 215 of the n-type structure 214n and the p-type structure 214p can be formed in different configurations to accommodate various design requirements. In some embodiments, reference is made to... Figure 4B The tops 215 of both the n-type structure 214n and the p-type structure 214p are configured to have a substantially circular shape. In the depicted embodiment, the top 215 of the n-type structure 214n is defined by a diameter S1, while the top 215 of the p-type structure 214p is defined by a diameter S2, wherein diameter S1 may be substantially the same as or different from diameter S2. In this embodiment, the metal silicide layer 216 is configured to have a diameter S3 smaller than diameters S1 and S2. In some embodiments, such as Figure 2A and Figures 3A-3C The sidewalls of the bottom 217 of each of the depicted n-type structures 214n and p-type structures 214p are substantially vertical, such that the width of the bottom 217 of each of the n-type structures 214n and p-type structures 214p is defined by diameters S1 and S2, respectively.

[0052] In some embodiments, reference Figures 5A-5B and Figures 6A-6B It shows alternatives Figure 2A , Figures 3A-3C and Figures 4A-4B In embodiments of the depicted content, the tops 215 of both the n-type structure 214n and the p-type structure 214p are configured to have substantially elongated shapes, i.e., one dimension is substantially larger than the other. In some embodiments, reference... Figures 6A-6B The tops 215 of both the n-type structure 214n and the p-type structure 214p are configured to have a rectangular shape oriented longitudinally along the X-axis. In the depicted embodiment, the top 215 of the n-type structure 214n is defined by a length S4, while the top 215 of the p-type structure 214p is defined by a length S5, wherein lengths S4 and S5 may be substantially the same or different. As depicted herein, length S4 is greater than length S5. In this embodiment, the diameter S3 of the metal silicide layer 216 is smaller than lengths S4 and S5. For example... Figures 5A-5B In the depicted embodiment, the sidewalls of the bottom 217 of each n-type structure 214n and p-type structure 214p are substantially vertical, and the width of the bottom 217 of each n-type structure 214n and p-type structure 214p is defined by lengths S4 and S5, respectively. In some embodiments, the elongated shape increases the conductive area of ​​module 212, thereby reducing its resistance and improving its cooling effect.

[0053] Centralized Reference Figures 7A-7D ,Apart from Figure 2A , Figures 3A-3C ,and Figures 4A-6B In addition to the depicted circular and elongated shapes, the top 215 of each n-type structure 214n and p-type structure 214p can be formed in other configurations in a planar top view (i.e., in the XY plane) to increase the effective thermoelectric detection area. In some embodiments, each n-type structure 214n and p-type structure 214p extends laterally through the top surface of the substrate 202a (or substrate 202b). In some embodiments, reference... Figure 7A and Figure 7B The n-type structure 214n and / or the p-type structure 214p include segments 215a that are substantially aligned longitudinally along the X-axis. In some embodiments, reference... Figures 7A-7D The n-type structure 214n and / or the p-type structure 214p include segments 215b that are substantially aligned longitudinally along the Y-axis. In some embodiments, reference... Figure 7A The n-type structure 214n and / or the p-type structure 214p include a segment 215c oriented at an angle relative to the X-axis or Y-axis. In some embodiments, reference... Figure 7C The n-type structure 214n and / or the p-type structure 214p includes a segment 215d having a substantially annular structure. In some embodiments, reference... Figure 7DThe n-type structure 214n and / or the p-type structure 214p includes a segment 215e having a substantially arcuate structure. In some embodiments, the widths of the individual segments of the n-type structure 214n and / or the p-type structure 214p are different. In other embodiments, the n-type structure 214n and the p-type structure 214p do not need to have identical or symmetrical structures to achieve the thermoelectric effect. Furthermore, the isolation structure 203 may be disposed outside the top 215 (see, for example, see...). Figure 7A and Figure 7C ) and / or between the sections at the top 215 (see, for example, see Figure 7A , Figure 7B ,and Figure 7D ).

[0054] refer to Figures 8A-8F Each of these shows a portion of an IC device 150 having a module 212 embedded in a substrate 202; wherein Figure 8A , Figure 8B and Figure 8E An embodiment in which the IC device 150 includes a single substrate is depicted, for example, similar to Figure 2A and Figure 3A The described embodiments, while Figure 8C , Figure 8D and Figure 8F An embodiment in which the IC device 150 includes a stacked structure is depicted, similar to Figure 3B The illustrated embodiment differs in that only the bottom chip 200b includes module 212 (i.e., bottom module 212b), while the top chip 200a does not include module 212 (i.e., top module 212a). As described herein, heat generated during operation by the circuitry in the first region 252 is dissipated through module 212 and collected at or near the second region 254, thereby directly cooling the circuitry in the first region 252 disposed above the top surface of module 212. In other words, charge carriers move in a direction away from the first region 252 toward the second region 254.

[0055] in addition, Figures 8A-8F Each is illustrated with an exemplary embodiment, wherein the bottom 217 of each n-type structure 214n and p-type structure 214p is configured to have a shape different from a rectangular (or substantially rectangular) shape, for example... Figure 2A and Figures 3A-3C What is depicted.

[0056] Figures 8A-8D Each embodiment is depicted, wherein the sidewalls are straight but inclined, such that each n-type structure 214n and p-type structure 214p is configured to have a trapezoidal (or substantially trapezoidal) shape. Reference Figure 8AThe top and bottom surfaces of each n-type structure 214n and p-type structure 214p are defined by widths D1 and D2 along the X-axis, respectively, where width D1 is greater than width D2. In some non-limiting examples, the ratio of D2 / D1 can be from about 0.7 to about 0.9, for example, about 0.8. Figure 8B Similar to Figure 8A The difference is that the width D1 is smaller than the width D2. In some non-limiting examples, the ratio of D1 / D2 can be from about 0.7 to about 0.9, for example, about 0.8. Figure 8C and Figure 8D Each is shown as an IC device 150 with a stacked configuration, corresponding to... Figure 8A and Figure 8B The single-substrate counterpart described in the figure.

[0057] Figure 8E and Figure 8F Each example is described with its sidewalls curved. (See references.) Figure 8E Each n-type structure 214n and p-type structure 214p has its top and bottom surfaces defined by widths D1 and D2, respectively, and its central portion is defined by a width D3 greater than both D1 and D2, such that each n-type structure 214n and p-type structure 214p is configured to have a barrel-like shape. This invention does not limit the relative dimensions of widths D1 and D2. For example, width D1 can be greater than, equal to, or less than width D2. Figure 8F Similar to Figure 8E The difference is that the IC devices have a stacked configuration, in which module 212 (i.e., bottom module 212b) is embedded in bottom chip 200b, and top chip 200a does not have module 212.

[0058] For where width D1 is greater than width D2 (see...) Figure 8A and Figure 8C In one embodiment, the area of ​​the first region 252 cooled by module 212 (or bottom module 212b) is increased, thereby improving the overall cooling effect. For which width D1 is smaller than width D2 (see...) Figure 8B and Figure 8D In one embodiment, the area occupied by the top surface of module 212 is reduced, thereby increasing the space available to accommodate other circuitry.

[0059] refer to Figure 9A and Figure 9B The top 215 (surrounded by a dashed ellipse) of the n-type structure 214n and the p-type structure 214p can extend through the XY plane. Figures 10A-10D Each shows a top plan view of the top 215 in the XY plane according to various embodiments; Figure 10E IC device 150 is shown along Figure 10A A cross-sectional view of line BB'; Figure 10F IC device 150 is shown along Figure 10A A cross-sectional view of line CC'; Figure 10G and Figure 10H Each shows IC device 150 along Figure 10A A cross-sectional view of line DD'. Although only one chip is depicted, the features discussed here can be applied to stacked configurations.

[0060] refer to Figure 9A and Figure 10A Each n-type structure 214n and p-type structure 214p of the top module 212a includes segments extending along the X-axis and Y-axis, respectively, in a line pattern across the top surface of the substrate 202. It should be noted that the top 215 configurations of the n-type structures 214n and p-type structures 214p are not necessarily identical. In the depicted embodiment, portions of the n-type structures 214n and p-type structures 214p are disposed between the isolation structure 203 and the gate structure 205. In some embodiments, portions of the top module 212a are physically separated from the gate structure 205 (or other portions of the device 204) by a distance D4 to avoid electric field interference when a voltage is applied to the top module 212a. In some examples, the distance D4 may be at least about 0.5 μm. Additionally, portions of the top module 212a may be separated from the isolation structure 203 by a distance D5, although the distance D5 is not limited in this invention. In some examples, the distance D5 may be greater than 0 μm. In some examples, the distance D5 can be approximately 0 μm, meaning that module 212 is in direct contact with isolation structure 203. Figure 10B yes Figure 10A Alternative embodiments include p-type structure 214p extending into different portions of contact isolation structure 203, and the tops 215 of n-type structure 214n and p-type structure 214p being substantially symmetrical about the Y-axis. Figure 10C yes Figure 10A Another alternative embodiment is in which the p-type structure 214p does not contact the isolation structure 203.

[0061] refer to Figure 9B and Figure 10D The top 215 of the n-type structure 214n extends along the XY plane in a linear pattern, while the top 215 of the p-type structure 214p is configured as a circular region. In other words, the top 215 of the p-type structure 214p does not... Figure 9A and Figures 10A-10C The tops 215 of both the depicted n-type structure 214n and p-type structure 214p partially surround the isolation structure 203 and / or the gate structure 205.

[0062] refer to Figure 10EThe bottom 217a of module 212 extends vertically along the Z-axis through the thickness of substrate 202, while the isolation structure 203 only partially penetrates substrate 202 through a depth D6 less than the thickness of substrate 202. In other words, the top module 212a extends vertically below isolation structure 203 and device 204.

[0063] refer to Figure 10F Module 212 also includes a bottom 217b that partially penetrates the substrate 202 through a depth D7 less than the thickness of the substrate 202. In some examples, the depth D7 can be any suitable value depending on specific design requirements, and can be less than, equal to, or greater than the depth D6.

[0064] refer to Figure 10G and Figure 10H Module 212 also includes a bottom 217c that partially penetrates the substrate 202 through a depth D8 less than the thickness of the substrate 202. In some examples, the depth D8 can be any suitable value according to specific design requirements and can be less than, equal to, or greater than depths D6 and D7. The depicted embodiments illustrate exemplary embodiments in which depth D8 is greater than depth D6 in 10G, and exemplary embodiments in which depth D8 is less than depth D6.

[0065] Figure 11 As shown Figure 2A and Figures 3A-10H A flowchart of one or more of the embodiments of the method 300 for manufacturing an IC device 150 or a portion thereof as depicted. Figure 12 and Figure 14 Flowcharts of methods 400 and 500, respectively, of embodiments for manufacturing a portion of the IC device 150, are shown. Method 300 combines... Figures 13A-16S The description is a cross-sectional view of IC device 150. Specifically, method 400 is combined with... Figures 13A-13G Describe the method, combining 500. Figures 15A-15K and Figures 16A-16I The following description is provided. In some examples, methods 400 and 500 may be implemented in place of one or more operations of method 300. Methods 300, 400, and 500 are merely examples and are not intended to limit the invention beyond what is expressly stated in the claims. Other operations may be provided before, during, and after methods 300, 400, and 500, and some of the described operations may be replaced, removed, or moved for other embodiments of the methods.

[0066] It should be noted that since the processes for forming the top chip 200a and the bottom chip 200b provided by the embodiments of method 300 can be substantially the same, for simplicity, the following operations of method 300 are discussed with respect to the formation of the top chip 200a embedded therein in the top module 212a.

[0067] refer to Figure 11 Method 300 forms a top module 212a in operation 302 within the top chip. In this embodiment, the top module 212a includes an n-type structure 214n and a p-type structure 214p electrically connected to an external power supply 250, which is in contrast to the above. Figure 2A and Figures 3A-10H One or more of them are discussed in detail. In this embodiment, a metal silicide layer 216 is formed over the top surface of each n-type structure 214n and p-type structure 214p, wherein the metal silicide layer 216 is configured to electrically connect the top module 212a to the subsequently formed MLI structure 220.

[0068] In this embodiment, the top module 212a is formed during operation 302 by means of, for example Figures 12-13G The method described is 400 or as follows Figures 14-15 and Figures 16A-16I Any one of the 500 methods described may be implemented.

[0069] refer to Figure 12 and Figure 13A In method 400, an implantation process 420 is performed on a portion of substrate 202 in operation 402. In this embodiment, the implantation process 420 is an ion implantation process configured to dope a region of substrate 202 with one or more n-type dopants, thereby forming an n-type structure 214n in substrate 202. As described herein, the n-type structure 214n may be formed as part of a top module 212a (i.e., embedded in substrate 202). In some embodiments, performing the implantation process 420 includes first forming a patterned mask element 260a over substrate 202, wherein the patterned mask element 260a exposes a portion of substrate 202 in an opening 262a. The patterned mask element 260a may be formed by a photolithography process. The photolithography process may include forming a photoresist layer on substrate 202, exposing the photoresist layer to pattern it, performing a post-exposure baking process, and developing the exposed photoresist layer to form the patterned mask element 260a. Subsequently, method 400 implements implantation process 420 to introduce or dope exposed portions of substrate 202 using an n-type dopant to form an n-type structure 214n. In some embodiments, the n-type dopant includes As, P, other n-type dopants, or combinations thereof. In some embodiments, the n-type dopant is at a concentration of at least about 10 17 cm -3The concentration of the n-type dopant is introduced. In some embodiments, the concentration of the n-type dopant is at least about 10. 19 cm -3 Subsequently, the patterned mask element 260a is removed from the substrate 202 by any suitable method, such as plasma ashing and / or resist stripping.

[0070] refer to Figure 12 and Figure 13B In method 400, an implantation process 422 is performed on another portion of the substrate 202 adjacent to the n-type structure 214n during operation 404. In this embodiment, the implantation process 422 is an ion implantation process configured to dope a region of the substrate 202 with one or more p-type dopants to form a p-type structure 214p, thereby obtaining... Figure 13C The top module 212a is depicted. In some embodiments, implantation process 422 is performed in a manner substantially similar to implantation process 420. For example, method 400 first forms a patterned mask element 260b over substrate 202 to expose a portion of substrate 202 in an opening 262b adjacent to n-type structure 214n, and then performs implantation process 422 to introduce p-type dopant into the exposed portion of substrate 202. The patterned mask element 260b may be substantially similar to patterned mask element 260a in terms of composition and formation method. In some embodiments, the p-type dopant includes B, In, Ga, other p-type dopants, or combinations thereof. In some embodiments, the p-type dopant is at least about 10 17 cm -3 The concentration of the p-type dopant is introduced. In some embodiments, the concentration of the p-type dopant is at least about 10. 19 cm -3 As provided herein, the n-type structure 214n and the p-type structure 214p comprise the same semiconductor material as the substrate 202 (e.g., both are Si).

[0071] Afterwards, refer to Figure 13C The patterned mask element 260b is removed from the substrate 202 by any suitable method, such as plasma ashing and / or resist stripping. In some embodiments, the n-type structure 214n and the p-type structure 214p are formed as described above relative to... Figures 4A-4B , Figures 6A-6B , Figures 7A-7D ,and Figures 10A-10D One or more of the various configurations discussed in detail in the top view (i.e., in the XY plane).

[0072] refer to Figure 12 and Figures 13D-13E In method 400, a trench 266 is formed in operation 406, which extends into the substrate 202 and along the sidewalls of the n-type structure 214n and the p-type structure 214p. (See reference...) Figure 13D In method 300, a patterned mask element 260c is first formed over an n-type structure 214n and a p-type structure 214p to expose a portion of the substrate 202 in an opening 262c. In terms of composition and formation method, the patterned mask element 260c can be substantially similar to the patterned mask element 260a. For example, the patterned mask element 260c can be formed by performing a photolithography process. (Reference) Figure 13E Method 300 then uses a patterned mask element 260c as an etching mask to perform an etching process 424 to form trenches 266 in the substrate 202, wherein the trenches 266 expose the sidewalls of the n-type structure 214n and the p-type structure 214p. The etching process 424 can be any suitable etching process, such as dry etching, wet etching, reactive ion etching (RIE), or a combination thereof. Subsequently, the patterned mask element 260c is removed from the substrate 202 by any suitable method, such as plasma ashing and / or resist stripping.

[0073] refer to Figure 12 and Figure 13F In method 400, during operation 408, a dielectric layer 268 is formed in trench 266 in deposition process 426, during which a portion of dielectric layer 268 is formed over substrate 202. Dielectric layer 268 is configured such that n-type structure 214n and p-type structure 214p are electrically isolated or separated from each other and from other components (e.g., device 204) formed in substrate 202. In this embodiment, dielectric layer 268 is an oxide material, such as silicon oxide (SiO and / or SiO2). Deposition process 426 can be any suitable process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), other processes, or combinations thereof. In this embodiment, deposition process 426 is an ALD process.

[0074] refer to Figure 12 and Figure 13G In method 400, a polishing process, such as chemical mechanical polishing / planarization (CMP), is performed in operation 410 to remove a portion of the dielectric layer 268 formed above the substrate 202, leaving dielectric pads 210 along the sidewalls of the n-type structure 214n and the p-type structure 214p. Subsequently, still referring to... Figure 13G In operation 412, method 400 may implement additional manufacturing processes, such as thinning substrate 202 (e.g., from the back side of substrate 202) to expose the bottom of top module 212a. In this embodiment, thinning substrate 202 includes removing (e.g., by one or more CMP processes) portions of substrate 202 without removing or substantially removing portions of n-type structure 214n, p-type structure 214p, and dielectric pad 210.

[0075] It should be noted that the present invention does not limit the order in which the n-type structure 214n and the p-type structure 214p are formed; that is, method 400 may form the n-type structure 214n before forming the p-type structure 214p, as described herein, or alternatively, the p-type structure 214p may be formed before forming the n-type structure 214n. After the formation of the top module 212a is completed, method 300 may continue to be implemented as follows: Figure 11 The operation described is 304.

[0076] In an alternative embodiment, operation 302 of method 300 can be implemented by method 500, which combines... Figure 14 and Figures 15A-15K Let's discuss this. (Reference) Figure 14 and Figures 15A-15B In method 500, in operation 502, an opening 274 is formed that extends vertically into the substrate 202. (See reference...) Figure 15A In method 500, a patterned mask element 260d is first formed to expose a portion of the substrate 202 in an opening 262d. In terms of composition and formation method, the patterned mask element 260d can be substantially similar to the patterned mask element 260a. For example, the patterned mask element 260d can be formed by a photolithography process. (Reference) Figure 15B Method 500 then uses the patterned mask element 260d as an etching mask to perform an etching process 520 to form an opening 274 in the substrate 202. The etching process 520 can be any suitable etching process, such as dry etching, wet etching, RIE, or a combination thereof. Subsequently, the patterned mask element 260d is removed from the substrate 202 by any suitable method, such as plasma ashing and / or resist stripping.

[0077] refer to Figure 14 and Figure 15C In method 500, during operation 504, a dielectric layer 268 is conformally deposited in opening 274 in deposition process 522, during which a portion of the dielectric layer 268 is formed over the top surface of substrate 202. In this embodiment, the portion of the dielectric layer 268 formed in opening 274 becomes dielectric pad 210. The dielectric layer 268 may comprise silicon oxide, and deposition process 522 may be similar to the ALD process discussed in detail above with respect to operation 408.

[0078] Subsequently, in operation 506, in deposition process 524, method 500 forms a semiconductor layer 276 over dielectric layer 268 to fill opening 274, thereby obtaining... Figure 15D The portion depicted is of the semiconductor layer 276 formed above the top surface of the substrate 202. Next, refer to... Figure 15EMethod 500 implements one or more CMP processes to remove portions of the dielectric layer 268 and semiconductor layer 276 formed above the top surface of the substrate 202, thereby obtaining an n-type structure 214n.

[0079] In this embodiment, semiconductor layer 276 comprises a semiconductor material in a polycrystalline phase. For example, semiconductor layer 276 may comprise polycrystalline Si (or polycrystalline Ge), polycrystalline SiGe, polycrystalline SiGe, other suitable semiconductor materials, or combinations thereof, doped with one or more n-type dopants. In some embodiments, semiconductor layer 276 has the composition of substrate 202 (e.g., all comprising Si). The n-type dopant may comprise As, P, other n-type dopants, or combinations thereof. In some embodiments, the n-type dopant in semiconductor layer 276 has a concentration of at least about 10. 17 cm -3 The concentration of the n-type dopant. In some embodiments, the concentration of the n-type dopant is at least about 10. 19 cm -3 .

[0080] In some embodiments, deposition process 524 is performed using CVD processes such as low-pressure CVD (LP-CVD), high-density plasma CVD (HDP-CVD), metal-organic CVD (MO-CVD), remote plasma CVD (RP-CVD), PVD processes, other suitable processes, or combinations thereof. n-type dopant may be introduced in situ to the desired concentration provided herein during deposition process 524 or during a subsequent ion implantation process. In some examples, as depicted herein, deposition process 524 may obtain seams (or voids) 278 extending along the Z-axis into semiconductor layer 276.

[0081] Now for reference Figure 14 and Figure 15F In operation 508, in a process similar to that discussed above relative to operation 502, an opening 280 is formed in a substrate 202 of adjacent n-type structure 214n.

[0082] Then, in operation 510, method 500 forms a dielectric layer 268 over the substrate 202 in deposition process 526, thereby partially filling the opening 280, as... Figure 15G The deposition process 526 can be substantially similar to the deposition process 522 discussed above with respect to operation 504. In the embodiment in which seam 278 is formed in n-type structure 214n, dielectric layer 268 fills seam 278 in operation 510.

[0083] Subsequently, in operation 512, method 500 forms a semiconductor layer 282 over the dielectric layer 268 in deposition process 528 to fill the opening 280, thereby obtaining the desired result. Figure 15HThe depicted portion is a semiconductor layer 282 formed above the top surface of substrate 202. In this embodiment, similar to semiconductor layer 276, semiconductor layer 282 comprises a semiconductor material in a polycrystalline phase. For example, semiconductor layer 282 may comprise polycrystalline Si, polycrystalline Ge, polycrystalline SiGe, other suitable semiconductor materials, or combinations thereof, doped with one or more p-type dopants. In some embodiments, semiconductor layer 282 has the composition of substrate 202 (e.g., both comprising Si). In some embodiments, semiconductor layers 276 and 282 have different compositions (e.g., one may comprise Si, while the other may comprise SiGe). The p-type dopant may comprise B, Ga, In, other p-type dopants, or combinations thereof. In some embodiments, the p-type dopant in semiconductor layer 282 has a p-type dopant concentration of at least about 10. 17 cm -3 The concentration of the p-type dopant. In some embodiments, the concentration of the p-type dopant is at least about 10. 19 cm -3 .

[0084] Deposition process 528 can be substantially similar to deposition process 524 as discussed above with respect to operation 506. In some embodiments, reference is made to... Figure 15H Deposition process 528 obtains a seam 284 extending vertically into the semiconductor layer 282. Then, refer to... Figure 15I Method 500 implements one or more CMP processes to remove portions of the dielectric layer 268 and semiconductor layer 282 formed above the top surface of the substrate 202, thereby obtaining a p-type structure 214p.

[0085] refer to Figure 14 and Figure 15J In method 500, in operation 514, the seam 284 is filled using a dielectric layer 286. The dielectric layer 286 may comprise any suitable material, such as silicon oxide, and may be formed by any suitable process, such as ALD. Method 500 may first perform a deposition process to form the dielectric layer 286 over the n-type structure 214n and the p-type structure 214p, and then perform one or more CMP processes to planarize the top surface of the dielectric layer 286 with the top surface of the substrate 202, thereby obtaining the top module 212a. For embodiments in which the seam 284 is not formed during operation 512, operation 514 may be omitted.

[0086] Subsequently, reference Figure 14 and Figure 15KMethod 500 may perform additional operations in operation 516, such as thinning the back side of substrate 202 to expose the bottom of n-type structure 214n and p-type structure 214p. In this embodiment, thinning the back side of substrate 202 in operation 516 includes removing (e.g., by one or more CMP processes) the bottom of substrate 202 and dielectric pads 210 oriented parallel to the bottom surface of substrate 202, without removing or substantially removing n-type structure 214n and p-type structure 214p. In some embodiments, thinning the back side of substrate 202 may be performed after forming other components such as MLI structure 220, TSV 206, sealing ring structure 228, etc.

[0087] In some embodiments, the n-type structure 214n and the p-type structure 214p are formed as described above relative to... Figures 4A-4B , Figures 6A-6B , Figures 7A-7D ,and Figures 10A-10D The various configurations discussed in detail in the top view (i.e., in the XY plane). In this regard, Figures 16A-16I Alternative embodiments of forming the top module 212a using method 500 are depicted. (See reference...) Figure 14 and Figure 16A Method 500 in operation 502 is similar to... Figure 15B In the process of forming opening 274, a patterned mask element 260e is used as an etching mask to form opening 290 in substrate 202a. In the depicted embodiment, opening 290 at least partially defines the top 215 of an n-type structure 214n extending laterally through the XY plane (see, for example, [link to previous embodiment]). Figure 16D ). refer to Figure 16B In method 500, an opening 292 is formed in operation 502 such that the opening 290 extends vertically into the substrate 202a. In this embodiment, the opening 292 at least partially defines the bottom 217 of the n-type structure 214n embedded in the substrate 202a (see, for example, [reference needed]). Figure 16D The opening 292 can be formed by a process similar to that used to form the opening 290. For example, a mask element (not depicted) including a photoresist layer can be deposited over the substrate 202a to fill the opening 290 and then patterned to form an opening (not depicted) that exposes a portion of the substrate 202a, which can then be etched using the patterned mask element as an etch mask to form the opening 292.

[0088] refer to Figure 14 and Figure 16C In method 500, operations 504 and 506 deposit a dielectric layer 268 over substrate 202a and a semiconductor layer 276 over dielectric layer 268, thereby filling openings 290 and 292. The processes for depositing dielectric layer 268 and semiconductor layer 276 are described above relative to... Figure 15C and Figure 15D A detailed discussion was held. Subsequently, references were made. Figure 16D Method 500 implements one or more CMP processes to remove portions of the dielectric layer 268 and the semiconductor layer 276 from the substrate 202a, thereby obtaining an n-type structure 214n above the dielectric pad 210.

[0089] refer to Figure 14 and Figures 16E-16F In method 500, in operation 508, openings 294 and 296 are formed in substrate 202a and adjacent to n-type structure 214n. The processes for forming openings 294 and 206 are substantially similar to the processes for forming openings 290 and 292, respectively, as described above relative to... Figures 16A-16B The details discussed.

[0090] refer to Figure 14 and Figures 16G-16H Method 500 in operations 510 and 512 as described above relative to... Figure 16C In the series of processes discussed in detail, which are similar to those used in operations 504 and 506, a dielectric layer 268 is deposited over substrate 202a, and a semiconductor layer 282 is deposited over dielectric layer 268, thereby filling openings 294 and 296. Subsequently, refer to... Figure 16I Method 500 implements one or more CMP processes to remove portions of the dielectric layer 268 and the semiconductor layer 282 from the substrate 202a, thereby obtaining a p-type structure 214p above the dielectric pad 210.

[0091] Then, method 500 can implement additional processing steps in operation 516. It should be noted that the present invention does not limit the order in which the n-type structure 214n and the p-type structure 214p are formed; that is, method 500 may form the n-type structure 214n before forming the p-type structure 214p as described herein, or alternatively, the p-type structure 214p may be formed before forming the n-type structure 214n.

[0092] After completing the formation of the top module 212a, method 300 can proceed to operation 304. (See reference) Figure 11 and Figure 16JIn method 300, device 204 is formed in and / or on substrate 202 in operation 304. Device 204 may be a FET (e.g., planar FET, FinFET, nanosheet FET, and / or other suitable device), memory cell, imaging sensor, passive device, other device, or combination thereof, separated by isolation structure 203. Device 204 may include gate structure 205 that is coupled to source / drain components of one or more active regions (e.g., fins, nanosheets, doped wells, and / or other suitable regions) formed in and / or on substrate 202a. Additional components such as ILD layer 108, device-level contact 218, and a portion of sealing ring structure 228 may be formed in and / or on substrate 202a before, after, or during the process of forming device 204.

[0093] refer to Figure 16K In method 300, in operation 306, an MLI structure 220 is formed over substrate 202a, wherein the MLI structure 220 is electrically connected to device 204 and top module 212a, for example, via device-level contacts 218. The MLI structure 220 may be formed to include various interconnect components, such as wires 224 and vias 226, disposed in dielectric layers such as ILD layer 221 and ESL 222.

[0094] refer to Figure 16L-Figure 16N In method 300, operation 306 forms additional components, such as TSV 206, in IC device 150. In the depicted embodiment, method 300 first forms a trench 297 through at least a portion of the MLI structure 220 and substrate 202a, such as... Figure 16L As described, the trench 297 can be formed using a patterned mask element (not depicted) similar to the patterned mask element 260a discussed in detail above with respect to the formation of the opening 290 in operation 502. (See reference...) Figure 16M Then, in method 300, a seed layer 298 is deposited over trench 297, and a conductive layer 299 is deposited over the seed layer 298. The seed layer 298 and the conductive layer 299 can be deposited by any suitable method such as ALD, CVD, PVD, plating, other suitable methods, or combinations thereof.

[0095] Subsequently, reference Figure 16N Method 300 performs one or more CMP processes to planarize the top surface of TSV206 and the top surface of MLI structure 220. Then, still referring to... Figure 16N In method 300, a passivation layer 231 is formed over TSV 206 in operation 306. (See reference...) Figure 16OIn operation 306, method 300 may form additional conductive components, such as conductive pads 232 and sealing ring structures 228 embedded in various insulating components, and form bonding films, such as dielectric bonding films 238 for hybrid bonding over MLI structure 220.

[0096] Method 300 can then perform further operations after operation 308 to process IC device 150. For example, refer to... Figure 16P In method 300, operation 308 may form a passivation layer 231 above the MLI structure 220, and one or more bonding films above the passivation layer 231, such as fusion bonding films 240 (including, for example, silicon oxynitride, silicon oxide, other suitable materials, or combinations thereof), to allow the top chip 200a to be bonded to other chips or substrates in a desired configuration (e.g., SoIC, CoWoS, InFO, or combinations thereof). Reference Figure 16Q Method 300 can form a dielectric layer 236 above the IC device 150 to fill any gaps along the sidewalls of the top chip 200a, and perform a CMP process to planarize the dielectric layer 236. Subsequently, refer to... Figure 16R Method 300 performs a thinning process to remove a portion of the substrate 202a, thereby exposing the top module 212a and TSV 206. The thinning process can be substantially similar to the process discussed above relative to operation 516. Then, refer to... Figure 16S Method 300 may form another dielectric bonding film 238 over the back side of the top chip 200a, and form contact portions 242 over the exposed top module 212a and TSV 206. Although not depicted, bumps 244 may be formed over the contact portions 242 to electrically connect the top chip 200a to additional components such as a package substrate, through-hole, RDL, other suitable components, or combinations thereof, depending on the desired package configuration.

[0097] While not intended to be limiting, one or more embodiments of the present invention provide numerous benefits for semiconductor devices and their fabrication. The present invention relates to thermoelectric devices embedded within an IC chip package for providing cooling to portions of the IC chip package when a voltage is applied. The present invention also relates to thermoelectric devices embedded within an IC chip package for detecting temperature changes in portions of the IC chip package during operation. In this embodiment, the thermoelectric device includes an n-type semiconductor structure disposed adjacent to a p-type semiconductor structure and electrically connected to an external power source. The thermoelectric device may be embedded in one or more chips of the IC chip package and electrically connected to allow cooling of various portions of the IC chip package and / or detection of temperature changes of the device. In some embodiments, the top of the thermoelectric device spans the surface of the substrate to increase the detection area. In some embodiments, the thermoelectric device is electrically isolated from the substrate by a dielectric pad. Embodiments of the present invention can be readily incorporated into various 3D chip package configurations such as SoIC, CoWoS, InFO, 3D structures, other suitable configurations, or combinations thereof.

[0098] In one aspect, the present invention provides an IC device comprising a chip having a semiconductor substrate. The IC device further includes a thermoelectric module embedded in the semiconductor substrate, wherein the thermoelectric module includes a first semiconductor structure electrically connected to a second semiconductor structure, wherein the bottom of the thermoelectric module extends through the thickness of the semiconductor substrate, and wherein the first and second semiconductor structures include dopants of different conductivity types.

[0099] In another aspect, the present invention provides a chip package comprising a bottom chip having a first substrate and a top chip electrically bonded to the bottom chip, wherein the top chip includes a second substrate. The chip package further includes thermoelectric devices embedded in the second substrate, wherein the thermoelectric devices include n-type structures connected to p-type structures, and wherein each n-type structure and p-type structure extends to contact the bottom chip.

[0100] In another aspect, the present invention provides a method comprising forming a first semiconductor structure extending into a substrate. The method further comprises forming a second semiconductor structure extending into the substrate and adjacent to the first semiconductor structure, wherein the first and second semiconductor structures comprise dopants of different conductivity types. The method further comprises forming a dielectric pad along the sidewalls of each of the first and second semiconductor structures.

[0101] According to embodiments of this application, an integrated circuit device is provided, comprising: a chip including a semiconductor substrate; and a thermoelectric module embedded in the semiconductor substrate, wherein the thermoelectric module includes a first semiconductor structure electrically connected to a second semiconductor structure, wherein the bottom of the thermoelectric module extends through the thickness of the semiconductor substrate, and wherein the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types. In some embodiments, the chip is a first chip, the semiconductor substrate is a first semiconductor substrate, and the thermoelectric module is a first thermoelectric module; the integrated circuit device further includes a second chip, wherein the second chip includes a second semiconductor substrate and a second thermoelectric module embedded in the second semiconductor substrate, and wherein the first thermoelectric module and the second thermoelectric module are electrically connected. In some embodiments, each of the first semiconductor structure and the second semiconductor structure is separated from the semiconductor substrate by a dielectric layer. In some embodiments, the bottom of the thermoelectric module includes a sloping sidewall. In some embodiments, the bottom of the thermoelectric module includes a curved sidewall. In some embodiments, the thermoelectric module includes a top that extends laterally through a surface parallel to the top surface of the semiconductor substrate. In some embodiments, the integrated circuit device further includes a voltage sensor electrically connected to the thermoelectric module. In some embodiments, the integrated circuit device further includes a power source electrically connected to the thermoelectric module.

[0102] According to another embodiment of this application, a chip package is provided, comprising: a bottom chip including a first substrate; a top chip electrically bonded to the bottom chip, wherein the top chip includes a second substrate; and a thermoelectric device embedded in the second substrate, wherein the thermoelectric device includes an n-type structure connected to a p-type structure, and wherein each n-type structure and p-type structure extends to contact the bottom chip. In some embodiments, the thermoelectric device further includes a dielectric pad separating the sidewalls of the n-type and p-type structures from the second substrate. In some embodiments, one of the top chip and the bottom chip further includes: a transistor disposed above the second substrate; an isolation structure disposed above the second substrate and adjacent to the transistor; a multilayer interconnect structure electrically connected to the transistor; and a silicide layer disposed between the multilayer interconnect structure and each n-type and p-type structure. In some embodiments, the thermoelectric device is electrically connected to a power supply or a voltmeter. In some embodiments, at least one of the n-type and p-type structures is configured with a sidewall inclined in cross-sectional view. In some embodiments, the thermoelectric device is a first thermoelectric device, and the chip package further includes a second thermoelectric device extending through a first substrate and electrically connected to the first thermoelectric device, wherein a power source is electrically connected to the first thermoelectric device via the second thermoelectric device. In some embodiments, the dopant concentration for each n-type structure and p-type structure is at least about 10. 17 cm -3 .

[0103] According to another embodiment of this application, a method is provided, comprising: forming a first semiconductor structure extending into a substrate; forming a second semiconductor structure extending into the substrate and adjacent to the first semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types; and forming a dielectric pad along the sidewalls of each of the first semiconductor structure and the second semiconductor structure. In some embodiments, the method further comprises forming a transistor over the substrate, wherein the first semiconductor structure and the second semiconductor structure extend below the bottom of the transistor. In some embodiments, forming the first semiconductor structure and the second semiconductor structure comprises selectively doping a first region of the substrate with a first dopant to obtain the first semiconductor structure, and selectively doping a second region of the substrate with a second dopant having a different conductivity type than the first dopant to obtain the second semiconductor structure, and wherein forming the dielectric pad comprises forming a trench along the sidewalls of each of the first semiconductor structure and the second semiconductor structure, depositing a dielectric material in the trench, and planarizing the dielectric material to form the dielectric pad. In some embodiments, forming the first semiconductor structure and the second semiconductor structure includes: forming a first opening in a substrate; forming a dielectric material in the first opening; depositing a first semiconductor layer doped with a first dopant over the dielectric material to fill the first opening; planarizing the dielectric material and the first semiconductor layer to form a first semiconductor structure located above a dielectric pad; forming a second opening in the substrate; forming a dielectric material in the second opening; depositing a second semiconductor layer doped with a second dopant over the dielectric material to fill the second opening; wherein the first dopant and the second dopant have different conductivity types; and planarizing the dielectric material and the second semiconductor layer to form a second semiconductor structure located above a dielectric pad. In some embodiments, the method further includes polishing the back side of the substrate to expose the bottom of the first semiconductor structure and the second semiconductor structure.

[0104] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit device, comprising: Chips, including semiconductor substrates; Multiple transistors are disposed on the first surface of the semiconductor substrate; An isolation structure extends into the semiconductor substrate and separates the plurality of transistors; A multilayer interconnect structure is disposed above the first surface of the semiconductor substrate and connects the plurality of transistors; as well as A thermoelectric module is embedded in the semiconductor substrate, wherein the thermoelectric module includes a first semiconductor structure electrically connected to a second semiconductor structure, wherein the thermoelectric module extends from a first surface of the semiconductor substrate to an opposite back surface through the thickness of the semiconductor substrate, and wherein the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types.

2. The integrated circuit device according to claim 1, wherein the chip is a first chip, the semiconductor substrate is a first semiconductor substrate, and the thermoelectric module is a first thermoelectric module, the integrated circuit device further comprising a second chip, wherein the second chip comprises a second semiconductor substrate and a second thermoelectric module embedded in the second semiconductor substrate, and wherein, The first thermoelectric module and the second thermoelectric module are electrically connected.

3. The integrated circuit device according to claim 1, wherein, Each of the first semiconductor structure and the second semiconductor structure is separated from the semiconductor substrate by a dielectric layer.

4. The integrated circuit device according to claim 1, wherein, The bottom of the thermoelectric module includes sloping sidewalls.

5. The integrated circuit device according to claim 1, wherein, The bottom of the thermoelectric module includes curved sidewalls.

6. The integrated circuit device according to claim 1, wherein, The thermoelectric module includes a top that extends laterally through a surface parallel to the first surface of the semiconductor substrate.

7. The integrated circuit device according to claim 1 further includes a voltage sensor electrically connected to the thermoelectric module.

8. The integrated circuit device according to claim 1, further comprising a power supply electrically connected to the thermoelectric module.

9. A chip package, comprising: Bottom chip, including the first substrate; A top chip, electrically bonded to the bottom chip, wherein the top chip includes a second substrate, a plurality of transistors disposed on a first surface of the second substrate, an isolation structure extending into the second substrate and separating the plurality of transistors, and a multilayer interconnect structure disposed above the first surface of the second substrate and connecting the plurality of transistors; and A thermoelectric device, embedded in a second substrate and extending through the second substrate from a first surface to an opposite second surface, wherein the thermoelectric device includes an n-type structure connected to a p-type structure, and wherein each of the n-type structure and the p-type structure extends to contact the bottom chip.

10. The chip package according to claim 9, wherein, The thermoelectric device further includes a dielectric pad that separates the sidewalls of the n-type structure and the p-type structure from the second substrate.

11. The chip package according to claim 9, wherein, The top chip also includes: A silicide layer is disposed between the multilayer interconnect structure and each of the n-type and p-type structures.

12. The chip package according to claim 9, wherein, The thermoelectric device is electrically connected to a power source or a voltmeter.

13. The chip package according to claim 9, wherein, At least one of the n-type structure and the p-type structure is configured with a sidewall that is inclined in the cross-sectional view.

14. The chip package according to claim 9, wherein, The thermoelectric device is a first thermoelectric device, and the chip package further includes a second thermoelectric device extending through the first substrate and electrically connected to the first thermoelectric device, wherein a power source is electrically connected to the first thermoelectric device through the second thermoelectric device.

15. The chip package according to claim 9, wherein, The dopant concentration of each of the n-type and p-type structures is at least 10. 17 cm -3 .

16. A method for manufacturing an integrated circuit device, comprising: A first semiconductor structure extending into the substrate is formed; A second semiconductor structure is formed extending into the substrate and adjacent to the first semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types; A plurality of transistors separated by isolation structures in the substrate are formed on a first surface of the substrate, and a multilayer interconnect structure connecting the plurality of transistors is formed above the substrate; and Dielectric pads are formed along the sidewalls of each of the first semiconductor structure and the second semiconductor structure.

17. The method according to claim 16, wherein, The first semiconductor structure and the second semiconductor structure extend below the bottom of the transistor.

18. The method according to claim 16, wherein, Forming the first semiconductor structure and the second semiconductor structure includes selectively doping a first region of the substrate with a first dopant to obtain the first semiconductor structure, and selectively doping a second region of the substrate with a second dopant having a different conductivity type than the first dopant to obtain the second semiconductor structure, wherein forming the dielectric pad includes forming a trench along the sidewall of each of the first semiconductor structure and the second semiconductor structure, depositing a dielectric material in the trench, and planarizing the dielectric material to form the dielectric pad.

19. The method of claim 16, wherein, Forming the first semiconductor structure and the second semiconductor structure includes: A first opening is formed in the substrate. A dielectric material is formed in the first opening. A first semiconductor layer, doped with a first dopant, is deposited over the dielectric material to fill the first opening. The dielectric material and the first semiconductor layer are planarized to form the first semiconductor structure located above the dielectric pad. A second opening is formed in the substrate. The dielectric material is formed in the second opening. A second semiconductor layer, doped with a second dopant, is deposited over the dielectric material to fill the second opening. The first and second dopants have different conductivity types. The dielectric material and the second semiconductor layer are planarized to form the second semiconductor structure located above the dielectric pad.

20. The method of claim 16, further comprising polishing the back side of the substrate opposite to the first surface to expose the bottom of the first semiconductor structure and the second semiconductor structure.

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