Image sensor

Abstract

An image sensor includes a pixel unit and a pixel reading circuit. The pixel unit includes an image pixel array and a bias circuit. The image pixel array includes a plurality of image pixels arranged in a plurality of image pixel columns and a plurality of image pixel rows. The bias circuit is coupled to the image pixel array to generate a plurality of row sensing signals at a plurality of nodes coupled to the plurality of image pixel rows according to a bias voltage. The pixel reading circuit is coupled to the image pixel array and the bias circuit in the pixel unit to generate a plurality of first sampling values according to the plurality of row sensing signals and generate a plurality of second sampling values according to adjacent row sensing signals of the plurality of row sensing signals. Wherein, the plurality of image pixels are generated by the difference between the plurality of first sampling values and the second sampling values.

Description

Technical Field

[0001] The present invention relates to image sensing, and more particularly to an image sensor including an optical fingerprint sensing module disposed under or embedded in a screen. Background Art

[0002] As Figure 1 shown, a conventional optical image sensor 10 includes a pixel unit 100, a pixel reading circuit 102, a control circuit 104, a column control circuit 106, a column decoder 108, a differential amplifier 110, an analog-to-digital converter (ADC) 112, and an image signal processor 114. Among them, the pixel unit 100 further includes an image pixel array 116 and a light-shielding pixel array 118, and optionally includes a reference pixel array 120, which is disposed at the end (or front end) of each column of the image pixel array 116.

[0003] The conventional optical image sensor 10 usually samples the reference sampling voltage of the light-shielding area or non-photosensitive pixels and the sampling voltage of the normal pixels simultaneously to eliminate common mode noise. However, since this method requires additional light-shielding areas or non-photosensitive pixels (such as Figure 1 the light-shielding pixel array 118 in Summary of the Invention

[0004] In view of this, the present invention provides an image sensor, whose pixel unit only needs an image pixel array and does not need to additionally include a light-shielding pixel array as a reference pixel array. When performing image sensing, its pixel reading circuit can simultaneously sample the difference (such as voltage difference) between the sampling values of two adjacent image pixel rows, so that the pixel reading circuit can eliminate dark current and random noise in an analog form, thereby achieving the effects of eliminating common mode noise and increasing the dynamic range of the input voltage, and thus effectively solving the above problems encountered in the prior art.

[0005] A specific embodiment according to the present invention is an image sensor. In this embodiment, the image sensor includes a pixel unit and a pixel reading circuit. The pixel unit includes an image pixel array and a bias circuit. The image pixel array includes a plurality of image pixels arranged in a plurality of image pixel columns and a plurality of image pixel rows. The bias circuit is coupled to the image pixel array. The bias circuit generates a plurality of row sensing signals at a plurality of nodes coupled to the plurality of image pixel rows according to a bias voltage. The pixel reading circuit is coupled to the image pixel array and the bias circuit in the pixel unit. The pixel reading circuit generates a plurality of first sampling values according to the plurality of row sensing signals and generates a plurality of second sampling values according to adjacent row sensing signals of the plurality of row sensing signals. Among them, the plurality of image pixels are generated by the difference between the plurality of first sampling values and the second sampling values.

[0006] In one embodiment, the pixel reading circuit includes a plurality of sampling and holding circuits corresponding to the plurality of row sensing signals respectively. The plurality of sampling and holding circuits sample and hold the plurality of row sensing signals and their adjacent row sensing signals respectively to generate one of the plurality of first sampling values and one of the plurality of second sampling values.

[0007] In one embodiment, one of the plurality of sampling and holding circuits includes: a first sampling switch having a first end and a second end, the first end being coupled to a corresponding one of the plurality of row sensing signals; a first sampling capacitor having a third end and a fourth end, the third end being coupled to the second end of the first sampling switch; a second sampling switch having a fifth end and a sixth end, the fifth end being coupled to a corresponding one of the plurality of row sensing signals adjacent thereto; a second sampling capacitor having a seventh end and an eighth end, the seventh end being coupled to the sixth end of the second sampling switch; a switching switch coupled between the third end of the first sampling capacitor and the seventh end of the second sampling capacitor; and a reference voltage signal switching switch group including: a first switch coupled between a reference voltage signal and the fourth end of the first sampling capacitor; and a second switch coupled between the reference voltage signal and the eighth end of the second sampling capacitor, wherein the fourth end of the first sampling capacitor and the eighth end of the second sampling capacitor are provided to generate one of the plurality of first sampling values and one of the plurality of second sampling values.

[0008] In one embodiment, one of the plurality of sampling and holding circuits includes: a first sampling switch having a ninth terminal and a tenth terminal, the ninth terminal being coupled to a corresponding row sensing signal among the plurality of row sensing signals; a first sampling capacitor having an eleventh terminal and a twelfth terminal, the eleventh terminal being coupled to the tenth terminal of the first sampling switch and the twelfth terminal being coupled to a reference voltage signal; a second sampling switch having a thirteenth terminal and a fourteenth terminal, the thirteenth terminal being coupled to a corresponding row sensing signal adjacent to the plurality of row sensing signals; and a second sampling capacitor having a fifteenth terminal and a sixteenth terminal, the fifteenth terminal being coupled to the fourteenth terminal of the second sampling switch and the sixteenth terminal being coupled to the reference voltage signal; wherein, the eleventh terminal of the first sampling capacitor and the fifteenth terminal of the second sampling capacitor are provided to generate a first sampling value among the plurality of first sampling values and a second sampling value among the plurality of second sampling values.

[0009] In one embodiment, the image sensor further includes: a differential amplifier for generating a plurality of analog pixel values corresponding to the difference between the plurality of first sampling values and the plurality of second sampling values; and an analog-to-digital converter (ADC) coupled to the differential amplifier for converting the plurality of analog pixel values into the plurality of digital pixel values.

[0010] In one embodiment, the image sensor is an optical image sensing device.

[0011] In one embodiment, the image sensor includes an optical fingerprint sensing module.

[0012] In one embodiment, the optical fingerprint sensing module is disposed under the screen.

[0013] In one embodiment, the optical fingerprint sensing module is embedded in the screen.

[0014] In one embodiment, the image sensor uses the voltage difference of simultaneously sampling adjacent pixel rows to eliminate common mode noise and increase the dynamic range of the input voltage.

[0015] Compared with the prior art, the image sensor of the present invention uses the voltage difference of simultaneously sampling adjacent pixel rows to eliminate common mode noise and increase the dynamic range of the input voltage, so no additional light shielding area or non-photosensitive pixels are required, and the area of the actual exposure area or the area of image sensing does not need to be reduced, which helps to improve the sensing efficiency of the image sensor.

[0016] The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings. Description of the Drawings

[0017] The accompanying drawings of the present invention are described as follows:

[0018] Figure 1 It is a schematic diagram of an image sensor of the prior art.

[0019] Figure 2 It is a schematic diagram of the image sensor of the present invention.

[0020] Figure 3 It is an embodiment of a pixel.

[0021] Figure 4 It is Figure 3 and Figure 5 The timing diagram of each signal in.

[0022] Figure 5 It is an embodiment of an image sensor.

[0023] Figure 6 It is the timing diagram of each signal when resetting the photosensitive pixel voltage.

[0024] Figure 7 It is a schematic diagram of a pixel when resetting the photosensitive pixel voltage.

[0025] Figure 8 It is the timing diagram of each signal when sampling the photosensitive pixel voltage.

[0026] Figure 9 It is a schematic diagram of a pixel when sampling the photosensitive pixel voltage.

[0027] Figure 10 It is a schematic diagram of an image sensor when sampling the photosensitive pixel voltage.

[0028] Figure 11 It is the timing diagram of each signal when subtracting the sampled voltages of photosensitive pixels located in adjacent image pixel rows C1 and C2.

[0029] Figure 12 It is a schematic diagram of a pixel when subtracting the sampled voltages of photosensitive pixels located in adjacent image pixel rows C1 and C2.

[0030] Figure 13 It is a schematic diagram of an image sensor when subtracting the sampled voltages of photosensitive pixels located in adjacent image pixel rows C1 and C2.

[0031] Figure 14 It is the timing diagram of each signal when subtracting the sampled voltages of photosensitive pixels located in adjacent image pixel rows C2 and C3.

[0032] Figure 15 It is a schematic diagram of a pixel when subtracting the sampled voltages of photosensitive pixels located in adjacent image pixel rows C2 and C3.

[0033] Figure 16 Schematic diagram of an image sensor for subtracting the sampling voltages of photosensitive pixels located adjacent to image pixel rows C2 and C3.

[0034] Figure 17 Another embodiment of a pixel.

[0035] Figure 18 For Figure 17 And Figure 19 Timing diagram of each signal in

[0036] Figure 19 Another embodiment of an image sensor.

[0037] Figure 20 Timing diagram of each signal when resetting the photosensitive pixel voltage.

[0038] Figure 21 Schematic diagram of a pixel when resetting the photosensitive pixel voltage.

[0039] Figure 22 Timing diagram of each signal when sampling the photosensitive pixel voltage.

[0040] Figure 23 Schematic diagram of a pixel when sampling the photosensitive pixel voltage.

[0041] Figure 24 Schematic diagram of an image sensor when sampling the photosensitive pixel voltage.

[0042] Figure 25 Timing diagram of each signal for subtracting the sampling voltages of photosensitive pixels located adjacent to image pixel rows C1 and C2.

[0043] Figure 26 Schematic diagram of a pixel for subtracting the sampling voltages of photosensitive pixels located adjacent to image pixel rows C1 and C2.

[0044] Figure 27 Schematic diagram of an image sensor for subtracting the sampling voltages of photosensitive pixels located adjacent to image pixel rows C1 and C2.

[0045] Figure 28 Timing diagram of each signal for subtracting the sampling voltages of photosensitive pixels located adjacent to image pixel rows C2 and C3.

[0046] Figure 29 Schematic diagram of a pixel for subtracting the sampling voltages of photosensitive pixels located adjacent to image pixel rows C2 and C3.

[0047] Figure 30Schematic diagram of an image sensor for subtracting the sampling voltages of photosensitive pixels located adjacent to image pixel rows C2 and C3.

[0048] Description of main component symbols:

[0049] 10... Optical image sensor

[0050] 100... Pixel unit

[0051] 102... Pixel reading circuit

[0052] 104... Control circuit

[0053] 106... Column control circuit

[0054] 108... Column decoder

[0055] 110... Differential amplifier

[0056] 112... Analog-to-digital converter

[0057] 114... Image signal processor

[0058] 116... Image pixel array

[0059] 118... Light-shielded area pixel array

[0060] 120... Reference pixel array

[0061] 200... Pixel reading circuit

[0062] 202... Pixel

[0063] R1~Rn... Image pixel columns

[0064] C1~Cm... Image pixel rows

[0065] 221~22(m - 1)... Sampling and storage circuit

[0066] 230... Bias circuit

[0067] BIAS... Bias reference voltage

[0068] VR... Reference voltage

[0069] SWS... Switch

[0070] SWR... Switch

[0071] SWC... Switch

[0072] CS... Capacitor

[0073] CR... Capacitor

[0074] AVS... Reference voltage signal switching switch group

[0075] SW1... Switch

[0076] SW2... Switch

[0077] CSC... Row selection circuit

[0078] Vout... Output voltage

[0079] V12, V23, V34, …, V(m-2)(m-1), V(m-1)m... Voltages

[0080] 204... Photodiode

[0081] 206... Sensing capacitor

[0082] 208... Transistor

[0083] 213... Column selection signal

[0084] N1... Node

[0085] N2... Node

[0086] N3... Node

[0087] N4... Node

[0088] RST... Pixel reset switch

[0089] VREF... Reference voltage

[0090] VDD... Operating voltage

[0091] VSS... Common ground voltage

[0092] VA... Voltage

[0093] Vth... Threshold voltage of the transistor

[0094] t0~t3... Time Detailed implementation manners

[0095] In the application documents of the present invention, the term "coupled" can refer to any direct or indirect connection means. For example, if it is described in the text that the first device is coupled to the second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or a certain connection means.

[0096] According to a specific embodiment of the present invention, there is an image sensor. As Figure 2 shown,Figure 2 Schematic diagram of an image sensor. As Figure 2 shown, the image sensor 10 includes a pixel reading circuit 102, a control circuit 104, a column control circuit 106, a differential amplifier 110, an analog-to-digital converter (ADC) 112, and an image pixel array 116. The control circuit 104 is respectively coupled to the pixel reading circuit 102 and the column control circuit 106. The pixel reading circuit 102 is coupled to the differential amplifier 110 and the image pixel array 116. The column control circuit 106 is coupled to the image pixel array 116. The differential amplifier 110 is coupled to the analog-to-digital converter 112.

[0097] Briefly, when the image sensor 10 performs image sensing, the photosensitive diodes of the pixels in the image pixel array 116 generate charges after being exposed to light and store them in the corresponding sensing capacitors. Then, the control circuit 104 controls the column control circuit 106 and the pixel reading circuit 102, so that the pixel reading circuit 102 samples each column of the image pixel array 116 to generate the sampling values of each pixel, and then the differential amplifier 110 amplifies the difference of the sampling values and the analog-to-digital converter 112 performs analog-to-digital conversion.

[0098] It should be noted that for the pixel unit of the present invention, only the image pixel array 116 is required, and there is no need to additionally include a light-shielding pixel array as a reference pixel array. When performing image sensing, the pixel reading circuit 102 can simultaneously sample the difference (such as the voltage difference) between the sampling values of two adjacent image pixel rows, so that the pixel reading circuit 102 can eliminate the dark current and random noise in an analog form, thereby achieving the effects of eliminating the common-mode noise and increasing the dynamic range of the input voltage.

[0099] As Figures 3 to 5 shown. Figure 3 An embodiment of a pixel. Figure 5 An embodiment of an image sensor. Figure 4 For Figure 3 and Figure 5 the timing diagram of each signal in Figures 3 to 5 shown, the image pixel array 116 includes image pixel columns R1 to Rn and image pixel rows C1 to Cm. The pixel 202 can be any pixel in the image pixel array 116 (such as a pixel at any intersection of the image pixel columns R1 to Rn and the image pixel rows C1 to Cm). The pixel reading circuit 200 includes (m - 1) sampling and storage circuits 221 to 22(m - 1), which respectively correspond to (m - 1) image pixel rows C1 to C(m - 1) and (m - 1) image pixel rows C2 to Cm, where m is a positive integer greater than 1.

[0100] Each sampling and storage circuit 221 to 22(m - 1) includes switches SWS, SWR, and SWC, capacitors CS and CR. The switch SWS is coupled to the capacitor CS and the switch SWR is coupled to the capacitor CR. One end of the switch SWC is coupled between the switch SWS and the capacitor CS, and the other end of the switch SWC is coupled between the switch SWR and the capacitor CR. When the switches SWS and SWR are turned on, the voltage values of adjacent pixel rows are sampled simultaneously and stored in the capacitors CS and CR; when the switch SWC is turned on, the difference Vout of the voltage values of the adjacent pixel rows is output to the differential amplifier 110 to eliminate common-mode noise and increase the dynamic range of the input voltage.

[0101] When performing image sensing in this structure, the photosensitive diode 204 generates charges after being exposed to light and stores them in the sensing capacitor 206 as sensing signals. When the bias reference voltage BIAS of the bias circuit 230 is at a high level and a column of switches RS is turned on by selecting the image pixel column where the pixel 202 is located, the pixel reset switch RST is first turned on to reset the voltage of the node N1 to the reference voltage VREF. Then the column selection signal 213 is sequentially pulled up and the sampling switch SWS is sequentially turned on to turn on the transistor 208 according to the sensing signals stored in the sensing capacitor 206, so as to store charges in the first sampling capacitor CS as the first sampling value, and at the same time, the pixels in the adjacent row of the image pixel row where the pixel 202 is located store charges in the second sampling capacitor CR as the second sampling value. Among them, when reading the first sampling value and the second sampling value, the reference voltage signal switching switch group AVS can control one end of the first sampling capacitor CS and the second sampling capacitor CR to be coupled to the reference voltage VR through the switches SW1 and SW2 respectively to eliminate non-ideal factors (such as dark current, etc.). Finally, the switching switch SWC is turned on and the corresponding row selection circuit CSC controls the switches of the corresponding columns to be turned on, so as to output the difference between the first sampling value and the second sampling value stored in the corresponding first sampling capacitor CS and the second sampling capacitor CR to the differential amplifier 110 for subsequent processing.

[0102] It should be noted that since the first sampling value and the second sampling value stored in the first sampling capacitor CS and the second sampling capacitor CR are the stored charges of the pixels in adjacent rows, and they have the same random noise disturbance, this embodiment can directly eliminate the influence of random noise disturbance in an analog form.

[0103] Next, the operations of resetting the photosensitive pixel voltage, sampling the photosensitive pixel voltage, subtracting the sampled voltages of the photosensitive pixels located in adjacent image pixel rows C1 and C2, and subtracting the sampled voltages of the photosensitive pixels located in adjacent image pixel rows C2 and C3 of the image sensor 10 will be described in detail respectively.

[0104] As Figure 6 and Figure 7 shown. Figure 6Timing diagram of each signal when resetting the photosensitive pixel voltage. Figure 7 Schematic diagram of a pixel when resetting the photosensitive pixel voltage.

[0105] As Figure 6 and Figure 7 shown, at time t0, the control signal of the pixel reset switch RST changes from the low-level common ground voltage VSS to the high-level operating voltage VDD and remains at the high-level operating voltage VDD during the period from t0 to t1. Therefore, the pixel reset switch RST conducts at time t0 and remains in the conducting state during the period from t0 to t1, so that the node N1 has the reference voltage VREF during the period from t0 to t1.

[0106] As Figures 8 to 10 shown. Figure 8 Timing diagram of each signal when sampling the photosensitive pixel voltage. Figure 9 Schematic diagram of a pixel when sampling the photosensitive pixel voltage. Figure 10 Schematic diagram of an image sensor when sampling the photosensitive pixel voltage.

[0107] As Figures 8 to 10 shown, at time t2, the column select signal 213 changes from the low-level common ground voltage VSS to the reference voltage VREF and remains at the reference voltage VREF during the period from t2 to t3. The control signal of the pixel reset switch RST remains at the low-level common ground voltage VSS during the period from t2 to t3. At time t2, the switch control signals of the switches SWS, SWR, SW1, and SW2 all change from low level to high level and remain at the high level during the period from t2 to t3. The switch control signal of the switch SWC remains at the low level during the period from t2 to t3. Therefore, during the period from t2 to t3, the switches SWS, SWR, SW1, and SW2 all conduct, but the switch SWC does not conduct, so that the node N1 has the voltage VA during the period from t2 to t3 and the node N2 has the voltage (VA - Vth) during the period from t2 to t3, where Vth is the threshold voltage value of the transistor 208.

[0108] As Figures 11 to 13 shown. Figure 11 Timing diagram of each signal for subtracting the sampled voltages of photosensitive pixels located in adjacent image pixel rows C1 and C2. Figure 12 Schematic diagram of a pixel for subtracting the sampled voltages of photosensitive pixels located in adjacent image pixel rows C1 and C2. Figure 13 Schematic diagram of an image sensor for subtracting the sampled voltages of photosensitive pixels located in adjacent image pixel rows C1 and C2.

[0109] As Figures 11 to 13As shown, at time t3, the control signal of the pixel reset switch RST is maintained at the low-level common ground voltage VSS, the column selection signal 213 changes from the reference voltage VREF to the low-level common ground voltage VSS, the switch control signal of the switch SWC changes from the low level to the high level, and the switch control signals of the switches SWS, SWR, SW1, and SW2 all change from the high level to the low level. Therefore, at time t3, the switch SWC is turned on, while the switches SWS, SWR, SW1, and SW2 are all not turned on, causing the voltage of node N1 to drop from voltage VA to the low level at time t3 and the voltage of node N2 to drop from voltage (VA - Vth) to the low level at time t3.

[0110] Similarly, as for the timing diagrams of the signals for subtracting the sampling voltages of the photosensitive pixels located in the adjacent image pixel rows C2 and C3, the schematic diagrams of the pixels and the image sensor are as Figures 14 to 16 , which will not be elaborated here.

[0111] As Figures 17 to 19 shown. Figure 17 is another embodiment of the pixel. Figure 19 is another embodiment of the image sensor. Figure 18 is Figure 17 and Figure 19 the timing diagram of the signals in

[0112] Comparing Figure 19 and Figure 5 it can be seen that Figure 19 and Figure 5 the differences between the image sensors are as follows: Figure 19 The sampling and storage circuits 221 to 22(m - 1) of

[0113] do not include the switching switch SWC, and the first end of the first sampling capacitor CS is respectively coupled to the sampling switch SWS and the row selection circuit CSC, and the first end of the second sampling capacitor CR is respectively coupled to the sampling switch SWR and the row selection circuit CSC. Therefore, under this circuit architecture, the difference between the first sampling value and the second sampling value can be directly provided by the first ends of the first sampling capacitor CS and the second sampling capacitor CR.

[0114] Next, operations such as resetting the photosensitive pixel voltage, sampling the photosensitive pixel voltage, subtracting the sampling voltages of the photosensitive pixels located in the adjacent image pixel rows C1 and C2, and subtracting the sampling voltages of the photosensitive pixels located in the adjacent image pixel rows C2 and C3 of the image sensor 20 will be described in detail. Figures 20 to 21 shown. Figure 20 is the timing diagram of the signals when resetting the photosensitive pixel voltage. Figure 21 is the schematic diagram of the pixel when resetting the photosensitive pixel voltage.

[0115] As Figure 20 and Figure 21 shown, at time t0, the control signal of the pixel reset switch RST changes from the low-level common ground voltage VSS to the high-level operating voltage VDD and remains at the high-level operating voltage VDD during the period from t0 to t1. Therefore, the pixel reset switch RST conducts at time t0 and remains in the conducting state during the period from t0 to t1, so that the node N1 has the reference voltage VREF during the period from t0 to t1.

[0116] As Figures 22 to 24 shown. Figure 22 is the timing diagram of each signal during the photosensitive pixel voltage sampling. Figure 23 is the schematic diagram of the pixel during the photosensitive pixel voltage sampling. Figure 24 is the schematic diagram of the image sensor during the photosensitive pixel voltage sampling.

[0117] As Figures 22 to 24 shown, at time t2, the column selection signal 213 changes from the low-level common ground voltage VSS to the reference voltage VREF and remains at the reference voltage VREF during the period from t2 to t3. The control signal of the pixel reset switch RST remains at the low-level common ground voltage VSS during the period from t2 to t3. At time t2, the switch control signals of the switches SWS and SWR both change from the low level to the high level and remain at the high level during the period from t2 to t3. The switch control signal of the row selection circuit CSC remains at the low level during the period from t2 to t3. Therefore, during the period from t2 to t3, both the switches SWS and SWR conduct, but a pair of switches in the row selection circuit CSC do not conduct, so that the node N1 has the voltage VA and the node N2 has the voltage (VA - Vth) during the period from t2 to t3, where Vth is the threshold voltage value of the transistor 208.

[0118] As Figures 25 to 27 . Figure 25 is the timing diagram of each signal for subtracting the sampled voltages of the photosensitive pixels located in the adjacent image pixel rows C1 and C2. Figure 26 is the schematic diagram of the pixel for subtracting the sampled voltages of the photosensitive pixels located in the adjacent image pixel rows C1 and C2. Figure 27 is the schematic diagram of the image sensor for subtracting the sampled voltages of the photosensitive pixels located in the adjacent image pixel rows C1 and C2.

[0119] As Figures 25 to 27As shown, at time t3, the control signal of the pixel reset switch RST is maintained at the low-level common ground voltage VSS, and the column selection signal 213 changes from the reference voltage VREF to the low-level common ground voltage VSS. The switch control signal of the row selection circuit CSC changes from the low level to the high level, while the switch control signals of the switches SWS and SWR both change from the high level to the low level. Therefore, at time t3, a pair of switches in the row selection circuit CSC are turned on, while the switches SWS and SWR are not turned on, causing the voltage of node N1 to drop from voltage VA to the low level at time t3 and the voltage of node N2 to drop from voltage (VA - Vth) to the low level at time t3.

[0120] Similarly, as for the signal timing diagrams, pixel diagrams, and image sensor diagrams for performing the subtraction of the sampling voltages of the photosensitive pixels located in the adjacent image pixel rows C2 and C3, they are as shown in Figures 28 to 30 , and will not be elaborated here.

[0121] Compared with the prior art, the image sensor of the present invention utilizes the simultaneous sampling of the voltage differences between adjacent pixel rows to eliminate common-mode noise and increase the dynamic range of the input voltage. Therefore, no additional light-shielding area or non-photosensitive pixels are required, and the area of the actual exposure area or the area of image sensing does not need to be reduced, which helps to improve the sensing performance of the image sensor.

Claims

1. An image sensor, characterized in that, Comprising a pixel unit and a pixel reading circuit: The pixel unit includes an image pixel array and a bias circuit: The image pixel array includes a plurality of image pixels arranged in a plurality of image pixel columns and a plurality of image pixel rows; the bias circuit is coupled to the image pixel array, and the bias circuit generates a plurality of row sensing signals at a plurality of nodes coupled to the plurality of image pixel rows according to a bias voltage; The pixel reading circuit is coupled to the image pixel array and the bias circuit in the pixel unit. The pixel reading circuit generates a plurality of first sampling values according to the plurality of row sensing signals and generates a plurality of second sampling values according to adjacent row sensing signals of the plurality of row sensing signals, and generates a plurality of image pixel values from the difference between the plurality of first sampling values and the plurality of second sampling values. The pixel reading circuit includes a plurality of sampling and storage circuits corresponding to the plurality of row sensing signals respectively. The plurality of sampling and storage circuits sample and store the plurality of row sensing signals and their adjacent row sensing signals respectively to generate one of the plurality of first sampling values and one of the plurality of second sampling values. One of the plurality of sampling and storage circuits includes: A first sampling switch having a first end and a second end, the first end being coupled to a corresponding row sensing signal among the plurality of row sensing signals; A first sampling capacitor having a third end and a fourth end, the third end being coupled to the second end of the first sampling switch; A second sampling switch having a fifth end and a sixth end, the fifth end being coupled to a corresponding row sensing signal among the plurality of row sensing signals, and the corresponding row sensing signal coupled to the fifth end among the plurality of row sensing signals being adjacent to the corresponding row sensing signal coupled to the first end of the first sampling switch; A second sampling capacitor having a seventh end and an eighth end, the seventh end being coupled to the sixth end of the second sampling switch; A switching switch coupled between the third end of the first sampling capacitor and the seventh end of the second sampling capacitor; And A reference voltage signal switching switch group includes: A first switch coupled between a reference voltage signal and the fourth end of the first sampling capacitor; And A second switch coupled between the reference voltage signal and the eighth end of the second sampling capacitor, wherein the fourth end of the first sampling capacitor and the eighth end of the second sampling capacitor are provided to generate one of the plurality of first sampling values and one of the plurality of second sampling values.

2. The image sensor according to claim 1, characterized in that, It further includes: A differential amplifier for generating a plurality of analog pixel values corresponding to the difference between the plurality of first sampling values and the plurality of second sampling values; and An analog-to-digital converter coupled to the differential amplifier for converting the plurality of analog pixel values into a plurality of digital pixel values.

3. The image sensor according to claim 1, characterized in that, The image sensor is an optical image sensing device.

4. The image sensor according to claim 3, characterized in that, Including an optical fingerprint sensing module.

5. The image sensor according to claim 4, characterized in that, The optical fingerprint sensing module is placed under the screen.

6. The image sensor according to claim 4, characterized in that, The optical fingerprint sensing module is embedded in the screen.

7. The image sensor according to claim 1, characterized in that Utilize the voltage difference of simultaneously sampling adjacent pixel rows to eliminate common-mode noise and increase the dynamic range of the input voltage.

8. An image sensor, characterized in that, Comprising a pixel unit and a pixel reading circuit: The pixel unit includes an image pixel array and a bias circuit: The image pixel array includes a plurality of image pixels arranged in a plurality of image pixel columns and a plurality of image pixel rows; the bias circuit is coupled to the image pixel array, and the bias circuit generates a plurality of row sensing signals at a plurality of nodes coupled to the plurality of image pixel rows according to a bias voltage. The pixel reading circuit is coupled to the image pixel array and the bias circuit in the pixel unit. The pixel reading circuit generates a plurality of first sampling values according to the plurality of row sensing signals and generates a plurality of second sampling values according to adjacent row sensing signals of the plurality of row sensing signals, and generates a plurality of image pixel values from the difference between the plurality of first sampling values and the plurality of second sampling values. The pixel reading circuit includes a plurality of sampling and holding circuits corresponding to the plurality of row sensing signals respectively. The plurality of sampling and holding circuits sample and hold the plurality of row sensing signals and their adjacent row sensing signals respectively to generate one of the plurality of first sampling values and one of the plurality of second sampling values. One of the plurality of sampling and holding circuits includes: A first sampling switch having a ninth terminal and a tenth terminal, and the ninth terminal is coupled to a corresponding row sensing signal among the plurality of row sensing signals. A first sampling capacitor having an eleventh terminal and a twelfth terminal, and the eleventh terminal is coupled to the tenth terminal of the first sampling switch, and the twelfth terminal is coupled to a reference voltage signal. A second sampling switch having a thirteenth terminal and a fourteenth terminal, and the thirteenth terminal is coupled to a corresponding row sensing signal among the plurality of row sensing signals, and the corresponding row sensing signal coupled to the thirteenth terminal is adjacent to the corresponding row sensing signal coupled to the ninth terminal of the first sampling switch among the plurality of row sensing signals; and A second sampling capacitor having a fifteenth terminal and a sixteenth terminal, and the fifteenth terminal is coupled to the fourteenth terminal of the second sampling switch, and the sixteenth terminal is coupled to the reference voltage signal. Wherein, the eleventh terminal of the first sampling capacitor and the fifteenth terminal of the second sampling capacitor are provided to generate one of the plurality of first sampling values and one of the plurality of second sampling values.

9. The image sensor according to claim 8, characterized in that, It further includes: A differential amplifier for generating a plurality of analog pixel values corresponding to the difference between the plurality of first sampling values and the plurality of second sampling values; and An analog-to-digital converter coupled to the differential amplifier for converting the plurality of analog pixel values into a plurality of digital pixel values.

10. The image sensor according to claim 8, wherein, The image sensor is an optical image sensing device.

11. The image sensor according to claim 10, wherein, It includes an optical fingerprint sensing module.

12. The image sensor according to claim 11, wherein, The optical fingerprint sensing module is placed under the screen.

13. The image sensor according to claim 11, wherein, The optical fingerprint sensing module is embedded in the screen.

14. The image sensor according to claim 8, wherein By simultaneously sampling the voltage difference between adjacent pixel rows, common-mode noise is eliminated and the dynamic range of the input voltage is increased.

Images