Storage test method, storage chip and related equipment based on serial interface

Abstract

The embodiment of the present application provides a storage test method and related equipment based on a serial interface, which realizes the rapid location of problems during the test process. The method includes: performing a read and write operation through a first circuit and obtaining corresponding first read and write information, the first circuit including a first simulation module for simulating a serial interface and an intermediate protocol layer, a storage control module, and a storage module; performing a read and write operation through a second circuit and obtaining corresponding second read and write information, the second circuit including a serial interface, an intermediate protocol layer, and a second simulation module for simulating a storage control module and a storage module; respectively determining whether the first read and write information and the second read and write information meet the preset read and write standards; if the first read and write information does not meet the preset read and write standards, determining that the data storage between the storage control module and the storage module is abnormal; if the second read and write information does not meet the preset read and write standards, determining that the data storage between the serial interface and the intermediate protocol layer is abnormal.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of testing technology, and in particular to a storage testing method based on a serial interface and related equipment. Background Art

[0002] When storing data via a serial interface, the data is typically sent through a serial interface SerDes (Serializer / DeSerializer) to an intermediate protocol module for parsing. The parsed data is then sent to the corresponding memory via a memory control module. A serial interface SerDes (SERializer / DESerializer, abbreviated as SerDes) is a generic term for a serializer / deserializer. It is typically used to convert multiple low-speed parallel signals at the transmitting end into high-speed serial signals, which are then converted back into low-speed parallel signals at the receiving end via a transmission medium such as optical cable or copper wire.

[0003] Currently, before performing storage operations based on a serial interface, it is generally necessary to test the transmission process. This involves testing the transmission links between the serial interface SerDes (SerDes), the intermediate protocol layer module, the memory control module, and the memory. This allows for analysis of the problematic link after any problems are detected. However, in practical applications, the data transmission process passes through multiple modules during testing. Consequently, when problems arise during the data storage process, it is necessary to identify the cause across multiple links corresponding to these modules, hindering rapid problem location. Summary of the Invention

[0004] The Summary of the Invention section introduces a series of simplified concepts that will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention section of the embodiments of the present application does not intend to limit the key features and essential technical features of the claimed technical solution, nor does it intend to determine the scope of protection of the claimed technical solution.

[0005] The embodiments of the present application provide a storage testing method and related equipment based on a serial interface to enable rapid location of problems during the testing process.

[0006] To at least partially address the above-mentioned issues, in a first aspect, embodiments of the present application provide a storage testing method based on a serial interface, comprising:

[0007] Performing a read / write operation through a first circuit and obtaining corresponding first read / write information, wherein the first circuit includes a first simulation module, a storage control module, and a storage module, the first simulation module is used to simulate a serial interface and an intermediate protocol layer, and the first read / write information is used to represent data transmission information when the read / write operation is performed through the first simulation module, the storage control module, and the storage module;

[0008] performing a read / write operation through a second line and obtaining corresponding second read / write information, wherein the second line includes a serial interface, an intermediate protocol layer, and a second simulation module, the second simulation module is used to simulate a storage control module and a storage module, and the second read / write information is used to represent data transmission information when performing the read / write operation through the serial interface, the intermediate protocol layer, and the second simulation module;

[0009] respectively determining whether the first read-write information and the second read-write information meet preset read-write standards;

[0010] If the first read / write information does not meet the preset read / write standard, determining that data storage between the storage control module and the storage module is abnormal;

[0011] If the second read / write information does not meet the preset read / write standard, it is determined that data storage between the serial interface and the intermediate protocol layer is abnormal.

[0012] Optionally, after respectively determining whether the first read-write information and the second read-write information meet preset read-write standards, the method further includes:

[0013] If both the first read-write information and the second read-write information meet the preset read-write standard, it is determined that data storage among the serial interface, the intermediate protocol layer, the storage control module, and the storage module is normal.

[0014] Optionally, the first simulation module includes a BIST self-test module;

[0015] The performing of the read and write operations through the first line and obtaining corresponding first read and write information includes:

[0016] Controlling the BIST self-test module to perform a first read and write operation on the storage module through the storage control module;

[0017] The read and write information during the first read and write operation is recorded as the first read and write information.

[0018] Optionally, the second simulation module includes a data memory and a data storage controller;

[0019] The performing of the read and write operations through the second line and obtaining corresponding second read and write information includes:

[0020] Performing a second read / write operation on the data storage via the data storage controller through the serial interface and the intermediate protocol layer;

[0021] The read and write information during the second read and write operation is recorded as the second read and write information.

[0022] Optionally, the second circuit includes a multiplexer;

[0023] Before performing the second read / write operation on the data storage through the serial interface and the intermediate protocol layer via the data storage controller, the method further includes:

[0024] By setting a multiplexer in the second circuit, the second circuit is divided into a first branch and a second branch, wherein the first branch includes the data storage controller and the data storage;

[0025] The performing a second read / write operation on the data storage via the data storage controller through the serial interface and the intermediate protocol layer includes:

[0026] controlling the multiplexing controller to turn on the first branch;

[0027] The second read and write operations are performed through the serial interface and the intermediate protocol layer and then through the multiplexing controller via the first branch.

[0028] Optionally, the second branch includes the storage module and the storage control module;

[0029] The method further comprises:

[0030] If both the first read / write information and the second read / write information meet a preset read / write standard, controlling the multiplexer to turn on the second branch;

[0031] The serial interface and the intermediate protocol layer are controlled to perform a data storage operation on the storage module through the second branch after passing through the multiplexer.

[0032] Optionally, the storage module includes a GDDR6 memory, and the storage control module includes a GDDR6 memory controller.

[0033] Optionally, the data memory includes an SRAM static random access memory, and the data storage controller includes an SRAM static random access controller.

[0034] In a second aspect, an embodiment of the present application provides a memory chip provided with a memory test device having a serial interface, wherein the memory test device having a serial interface includes:

[0035] a first acquiring unit, configured to perform a read / write operation through a first circuit and acquire corresponding first read / write information, wherein the first circuit includes a first simulation module, a storage control module, and a storage module, the first simulation module is configured to simulate a serial interface and an intermediate protocol layer, and the first read / write information is configured to represent data transmission information when the read / write operation is performed through the first simulation module, the storage control module, and the storage module;

[0036] a second acquiring unit, configured to perform a read / write operation through a second line and acquire corresponding second read / write information, wherein the second line includes a serial interface, an intermediate protocol layer, and a second simulation module, the second simulation module is configured to simulate a storage control module and a storage module, and the second read / write information is configured to represent data transmission information when the read / write operation is performed through the serial interface, the intermediate protocol layer, and the second simulation module;

[0037] a judging unit, configured to judge whether the first read-write information and the second read-write information meet preset read-write standards;

[0038] a first determining unit, configured to determine that data storage between the storage control module and the storage module is abnormal if the first read / write information does not meet the preset read / write standard;

[0039] The second determining unit is configured to determine that data storage between the serial interface and the intermediate protocol layer is abnormal if the second read / write information does not meet the preset read / write standard.

[0040] Optionally, the device further includes:

[0041] The third determining unit is configured to determine that data storage among the serial interface, the intermediate protocol layer, the storage control module, and the storage module is normal if both the first read-write information and the second read-write information meet the preset read-write standard.

[0042] Optionally, the first simulation module includes a BIST self-test module;

[0043] The first acquiring unit includes:

[0044] an execution module, configured to control the BIST self-test module to perform a first read and write operation on the storage module through the storage control module;

[0045] The recording module is used to record the read and write information during the first read and write operation as the first read and write information.

[0046] Optionally, the second simulation module includes a data memory and a data storage controller;

[0047] The second acquiring unit includes:

[0048] an execution module, configured to execute a second read / write operation on the data storage via the serial interface and the intermediate protocol layer and through the data storage controller;

[0049] The recording module is used to record the read and write information during the second read and write operation as the second read and write information.

[0050] Optionally, the second circuit includes a multiplexer;

[0051] The second acquiring unit further includes:

[0052] a setting module, configured to divide the second circuit into a first branch and a second branch by setting a multiplexer in the second circuit, wherein the first branch includes the data storage controller and the data storage;

[0053] The execution module includes:

[0054] a control submodule, configured to control the multiplexing controller to turn on the first branch;

[0055] An execution submodule is used to execute the second read and write operation through the serial interface and the intermediate protocol layer and through the first branch after passing through the multiplexing controller.

[0056] Optionally, the second branch includes the storage module and the storage control module;

[0057] The device further comprises:

[0058] a control unit, configured to control the multiplexer to turn on the second branch if both the first read / write information and the second read / write information meet a preset read / write standard;

[0059] An execution unit is used to control the serial interface and the intermediate protocol layer to perform a data storage operation on the storage module through the second branch after passing through the multiplexer.

[0060] Optionally, the storage module includes a GDDR6 memory, and the storage control module includes a GDDR6 memory controller.

[0061] Optionally, the data memory includes an SRAM static random access memory, and the data storage controller includes an SRAM static random access controller.

[0062] In a third aspect, an embodiment of the present invention further provides an electronic device comprising at least one processor, and at least one memory and a bus connected to the processor; wherein the processor and the memory communicate with each other through the bus; and the processor is used to call program instructions in the memory to execute any one of the serial interface-based storage test methods in the first aspect.

[0063] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium having a program stored thereon, which, when executed by a processor, implements the serial interface-based storage testing method described in any one of the first aspects.

[0064] Compared with the prior art, the logic chip capacitor circuit provided in the embodiment of the present invention has at least the following beneficial effects:

[0065] The embodiment of the present invention provides a storage test method and related equipment based on a serial interface, and the method includes: first, performing a read and write operation through a first line and obtaining corresponding first read and write information; then, performing a read and write operation through a second line and obtaining corresponding second read and write information; thereafter, respectively judging whether the first read and write information and the second read and write information meet the preset read and write standards; finally, if the first read and write information does not meet the preset read and write standards, determining that the data storage between the storage control module and the storage module is abnormal; at the same time, if the second read and write information does not meet the preset read and write standards, determining that the data storage between the serial interface and the intermediate protocol layer is abnormal, thereby realizing a storage test function based on a serial interface. In the above scheme, since the first circuit includes a first simulation module, a storage control module and a storage module, the second circuit includes a serial interface, an intermediate protocol layer and a second simulation module, and the first simulation module is used to simulate the serial interface and the intermediate protocol layer, and the second simulation module is used to simulate the storage control module and the storage module, this can ensure that when a problem is detected in any circuit during the test process, it can be directly determined whether the problem exists in the module that has not been simulated, so that during the test process, it can be quickly determined through the two circuits whether the problem exists in the serial interface and the intermediate protocol layer module, or in the memory control module and the memory, thereby realizing the rapid location of the problem during the test process.

[0066] Correspondingly, the computer storage medium and electronic device provided by the embodiments of the present invention also have the above technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0068] Figure 1 A flowchart of a serial interface-based storage test method provided by an embodiment of the present invention;

[0069] Figure 2 A schematic diagram of data transmission between modules in a first circuit and a second circuit during execution of a storage test method based on a serial interface provided by an embodiment of the present invention;

[0070] Figure 3 A schematic structural block diagram of a storage test device for a serial interface of a memory chip provided by an embodiment of the present invention;

[0071] Figure 4 A schematic structural block diagram of another storage test device for a serial interface of a memory chip provided by an embodiment of the present invention;

[0072] Figure 5 A schematic structural block diagram of an electronic device provided by an embodiment of the present invention;

[0073] Figure 6 A schematic structural block diagram of a computer-readable storage medium provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0074] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments so that those skilled in the art can implement the invention with reference to the description.

[0075] It should be understood that terms such as “having”, “including” and “comprising” used herein do not preclude the existence or addition of one or more other elements or combinations thereof.

[0076] Furthermore, it should be noted that, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be interpreted broadly. For example, they can refer to fixed or removable connections; direct or indirect connections through an intermediary; integral or internally connected components; or signal transmission and data communication between the two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0077] On the one hand, in order to realize the rapid location of problems in the storage test process of the serial interface, the embodiment of the present application provides a storage test method based on the serial interface, which solves the problem in the prior art that when a problem occurs in the storage test based on the serial interface, it is difficult to quickly locate the link where the problem occurs. The implementation steps of the specific solution can be as follows: Figure 1 shown, including:

[0078] 101. Perform a read / write operation through a first line and obtain corresponding first read / write information.

[0079] The first circuit includes a first simulation module, a storage control module, and a storage module. The first simulation module is used to simulate the serial interface and the intermediate protocol layer. The first read / write information is used to represent the data transmission information when performing read / write operations through the first simulation module, the storage control module, and the storage module. In practical applications, the first circuit can be understood as a circuit used to simulate the storage of data to the storage module. In this circuit, the serial interface and the intermediate protocol layer are simulated by the first simulation module, while the storage control module and the storage module are not simulated. This is actually equivalent to performing read / write operations on the storage module through the storage control module under the premise of replacing the serial interface and the intermediate protocol layer. Therefore, the read / write status of the storage control module and the storage module can be reflected based on the first read / write information.

[0080] 102. Perform a read / write operation through a second line, and obtain corresponding second read / write information.

[0081] The second circuit includes a serial interface, an intermediate protocol layer, and a second simulation module. The second simulation module is used to simulate the storage control module and the storage module. The second read / write information is used to represent data transmission information when performing read / write operations through the serial interface, the intermediate protocol layer, and the second simulation module. In this step, since the second circuit includes the second simulation module for simulating the storage control module and the storage module, it is equivalent to assuming that the second simulation module is operating normally, and the second read / write information corresponding to the read / write operations reflects the data storage status of the serial interface and the intermediate protocol layer.

[0082] 103. Determine whether the first read-write information and the second read-write information meet preset read-write standards.

[0083] Based on the description in the above steps 101 and 102, it can be seen that since the first read-write information and the second read-write information are respectively used to reflect the data read and write status of the module that is not simulated, in this step, the preset read-write standard can be used as a judgment basis to determine whether the first read-write information and the second read-write information are normal.

[0084] Therefore, based on the method described in this step, after judgment, the following steps can be performed based on the judgment results. First, if the first read / write information does not meet the preset read / write standard, step 104 is performed; second, if the second read / write information does not meet the preset read / write standard, step 105 is performed.

[0085] 104. If the first read / write information does not meet the preset read / write standard, determine that data storage between the storage control module and the storage module is abnormal.

[0086] Since the first read-write information is actually used to reflect whether the read and write conditions of the storage control module and the storage module when storing data are normal, when it is determined that the first read-write information does not meet the preset read-write standards, it means that there are problems with these two modules, and then it is determined that the data storage between the storage control module and the storage module is abnormal.

[0087] 105. If the second read / write information does not meet the preset read / write standard, determine that data storage between the serial interface and the intermediate protocol layer is abnormal.

[0088] Similar to step 104, since the second read-write information is actually used to reflect whether the read and write conditions of the serial interface and the intermediate protocol layer are normal when executing data storage, when it is determined that the second read-write information does not meet the preset read-write standards, it means that there are problems with these two modules, and then it is determined that the data transmission between the serial interface and the intermediate protocol layer is abnormal.

[0089] In the above steps, the order of execution of step 101 and step 102 can be selected according to actual needs. The steps described in this embodiment are only exemplary and are not limited here. At the same time, the first circuit and the second circuit respectively include a first simulation module for simulating the serial interface and the intermediate protocol layer, and a second simulation module for simulating the storage control module and the storage module. In this way, during the test process, any circuit can be used to test whether the module that has not been simulated can ensure normal data storage. For example, after performing a read and write operation through the first circuit, it can be determined based on the first read and write information corresponding to the read and write operation whether the storage module and the storage control module that have not been simulated in the circuit can ensure normal data storage. When it is detected that the first circuit fails to meet the preset read and write standards, it means that there is a problem with the module that has not been simulated, that is, there is a problem with the storage module and the storage control module, so that the link where the abnormal problem is located can be quickly determined in the storage test of the serial interface.

[0090] For example, in actual applications, after the judgment in step 103, there may be a situation where both the first read-write information and the second read-write information meet the preset read-write standard. In this case, the method of this embodiment may further include: if both the first read-write information and the second read-write information meet the preset read-write standard, then determining that the data storage between the serial interface, the intermediate protocol layer, the storage control module, and the storage module is normal. In this way, since the first read-write information can reflect whether the data storage between the storage control module and the storage module is normal, and the second read-write information can reflect whether the data storage between the serial interface and the intermediate protocol layer is normal, when both of these two pieces of information meet the preset read-write standard, it can be said that these modules are all normal, that is, the data storage between the serial interface, the intermediate protocol layer, the storage control module, and the storage module is normal, so that subsequent data storage operations can be performed.

[0091] Illustratively, in this embodiment, the aforementioned first analog module may include a BIST self-test module. The BIST self-test module is a technology in the art that implants relevant functional circuits into a circuit during design to provide a self-test function. This can reduce the reliance of device testing on automatic test equipment during the testing process. Therefore, in the aforementioned step 101, performing read and write operations through the first circuit and obtaining corresponding first read and write information may be performed in the following manner, including:

[0092] First, controlling the BIST self-test module to perform a first read and write operation on the storage module through the storage control module;

[0093] Then, the read and write information during the first read and write operation is recorded as the first read and write information.

[0094] Based on the above method, it can be seen that because the BIST self-test module can simulate the serial interface and intermediate protocol layer, it can perform data transmission and analysis. Therefore, in the above steps, the BIST module can replace the above modules to perform data transmission and analysis. At the same time, the BIST module is built into the processor chip and can be directly controlled and called, eliminating the need for additional devices to simulate the module and simplifying the testing process. In addition, based on the first read and write operation record corresponding to the first read and write information, data quantification can be used to lay the foundation for subsequent determination of whether the preset read and write standards are met.

[0095] For example, in this embodiment, since the second simulation module is used to simulate the storage control module and the storage module, the second simulation module may include a data memory and a data storage controller corresponding to the two modules, respectively. The data memory corresponds to the storage module, and the data storage controller corresponds to the storage control module. Based on this, in step 102, performing read and write operations via the second circuit and obtaining corresponding second read and write information may be performed in the following manner, including:

[0096] First, a second read / write operation is performed on the data memory via the serial interface and the intermediate protocol layer through the data storage controller; then, the read / write information during the second read / write operation is recorded as the second read / write information.

[0097] Through the above steps, it can be seen that by using the data memory to simulate the storage module and the data storage controller to simulate the storage control module, the functions of the above two modules can be simulated. In addition, the data storage controller and data memory are both located within the chip. This means that during the test process, they can be called and controlled only through functional statements or instructions, eliminating the need for additional test modules, thus simplifying the testing process.

[0098] For example, in practical applications, the second circuit in the aforementioned example may further include a multiplexer. A multiplexer (MUX, also known as a data selector) is a device that can select data conduction based on a control instruction. Therefore, before performing the second read / write operation on the data storage device via the serial interface and the intermediate protocol layer through the data storage controller in the aforementioned steps, the method may further include a process of setting a multiplexer in the second circuit, specifically, by setting a multiplexer in the second circuit to divide the second circuit into a first branch and a second branch, wherein the first branch includes the data storage controller and the data storage device.

[0099] Therefore, in the aforementioned steps, performing the second read / write operation on the data memory via the serial interface and the intermediate protocol layer through the data storage controller may specifically include:

[0100] First, the multiplexing controller is controlled to turn on the first branch.

[0101] Then, the second read and write operation is performed through the serial interface and the intermediate protocol layer and then through the multiplexing controller via the first branch.

[0102] In this way, since the multiplexer can play the function of line selection, and the first branch includes a data storage controller and the data storage device, that is to say, it can ensure the function of line selection based on the multiplexer, and ensure that the serial interface and the intermediate protocol layer can connect to other devices or apparatuses through the multiplexer to perform other functions.

[0103] For example, in actual applications, based on the above example, after a multiplexer is provided in the second circuit, the second branch formed can correspond to the storage module and the storage control module. Thus, in this embodiment, if it is determined that both the first read / write information and the second read / write information meet the preset read / write standards, that is, the data transmission from the serial interface to the intermediate protocol layer, and then to the storage control module and the storage module is normal, then the corresponding data storage operation can be directly performed based on the second branch formed by the multiplexer. Therefore, the method of this embodiment can also include:

[0104] First, if both the first read / write information and the second read / write information meet a preset read / write standard, the multiplexer is controlled to turn on the second branch.

[0105] Then, the serial interface and the intermediate protocol layer are controlled to perform a data storage operation on the storage module through the second branch after passing through the multiplexer.

[0106] Therefore, by controlling whether the second branch formed by the multiplexer is turned on, it can be ensured that when it is determined that the serial interface, the intermediate protocol layer, the storage control module and the storage module are all transmitting data normally, the data storage operation is directly executed to ensure the rapid switching of the test function and other storage functions after the test is passed.

[0107] In some embodiments, the storage module includes a GDDR6 memory, wherein the GDDR6 memory (Graphics Double Data Rate, version 6, abbreviated as GDDR6) is the sixth version of the graphics double data rate memory; the storage control module includes a GDDR6 memory controller, so that the test function of data storage of the GDDR6 memory can be realized through the method of the above example.

[0108] In some embodiments, the data memory includes an SRAM static random access memory (SRAM), and the data storage controller includes an SRAM static random access controller. Since SRAM static random access memory has the fastest read and write speeds of all memories, it can ensure that the execution time of read and write operations is reduced during the test process, thereby improving the overall execution efficiency of the serial interface-based storage testing method described in this embodiment.

[0109] In some embodiments, as a specific application scenario for executing the above method, this embodiment also provides a module-based execution process during the implementation of the above method, which can be combined with Figure 2 As shown, Line 1 is the first line, which includes BIST, GD6 CTRL IP, and GDDR6. Here, BIST is the BIST self-test module, GD6 CTRL IP is the GDDR6 memory controller, and GDDR6 is the GDDR6 memory. The first line can perform a first read and write operation on the GDDR6, thereby determining whether the data read and write between the GD6 CTRL IP and the GDDR6 is normal based on the corresponding first read and write information, and then determining whether there is a problem with the GD6 CTRL IP and the GDDR6. It should be noted that in this embodiment, the first line of Line 1 is mainly applicable in the testing process when the serial interface IO rate is above 10Gb / s. In this case, the handshake between the intermediate protocol layer (i.e., Protocol) and the other end is relatively complex, and the execution process of the communication protocol transport layer is relatively complex. Therefore, in testing scenarios under high-speed protocols such as PCIE, CXL, and CCIX, this method of using the BIST self-test module instead of the SerDes serial interface and Protocol intermediate protocol layer process test can be adopted. Among them, the PCIE protocol, also known as PCI-Express, is a high-speed serial computer expansion bus standard; CXL (ComputeExpress Lin, abbreviated as CXL) is a fast transmission protocol between the central processing unit and the graphics processor; the CCIX protocol, also known as the cache coherent interconnect protocol for accelerators, is a transmission protocol for faster access to memory in heterogeneous multi-processor systems.

[0110] Similarly, Line2 is the second line, where path1 is the first branch and path2 is the second branch. The first branch consists of SerDes, Protocol, MUX, SRAM, and SRAM CTRL. SerDes is a serial interface, Protocol is the intermediate protocol layer, MUX is a multiplexer, SRAM is a static random access memory, and SRAM CTRL is an SRAM static random access controller. Here, SRAM is used to simulate GDDR6, and SRAM CTRL is used to simulate the GD6 CTRL IP. In this way, a second read and write operation can be performed on the SRAM through the first branch in the second line. Since the SRAM and SRAM CTRL functions are normal, the second read and write information obtained from the second read and write operation can be used to determine whether the read and write process from the SerDes to the SRAM is normal, and then determine whether there is a data transmission problem between the SerDes and the Protocol. It should be noted that in the method described in this step, Line 2 is the second line and is mainly applicable when the memory IO transmission rate is above 3.2Gbps, such as when the static random access memory is manufactured using processes such as DDR4, DDR5, GDDR5, GDDR6, HBM, and 3D-Stacking Memory; or when the memory manufacturing process is complex, such as when the memory is manufactured using processes such as TSV and 3D-Stacking. DDR4, DDR5, GDDR5, GDDR6, HBM, 3D-Stacking Memory, TSV, and 3D-Stacking are all memory manufacturing processes of different generations and methods.

[0111] In addition, Line2 also includes a second branch, which is composed of SerDes, Protocol, MUX, GD6CTRL IP, and GDDR6. In this way, when the above steps determine that both the data transmission between the serial interface and the intermediate protocol layer, and the data reading and writing between the GD6 CTRL IP and GDDR6 are normal based on the first branch of the first line Line1 and the second line Line2, it means that the above-mentioned SerDes, Protocol, GD6 CTRL IP, and GDDR6 are all normal. At this time, the data storage behavior required by the user can be directly performed based on the second branch. Therefore, after the test is completed, when no problem is found, the MUX can be controlled to quickly switch to the second branch to complete the normal data storage behavior.

[0112] In the second aspect, based on the same inventive concept of the above-mentioned method, the embodiment of this specification further provides a memory chip provided with a storage test device of a serial interface, the functions and effects achieved by the storage test device of the serial interface are the same as those of the method of the first aspect mentioned above, and the execution process thereof will not be described one by one here. For example, the device is as follows Figure 3 shown, including:

[0113] A first acquisition unit 31 may be configured to perform a read / write operation through a first circuit and acquire corresponding first read / write information, wherein the first circuit includes a first simulation module, a storage control module, and a storage module, the first simulation module may be configured to simulate a serial interface and an intermediate protocol layer, and the first read / write information may be configured to represent data transmission information when performing the read / write operation through the first simulation module, the storage control module, and the storage module;

[0114] a second acquiring unit 32 configured to perform a read / write operation through a second circuit and acquire corresponding second read / write information, wherein the second circuit includes a serial interface, an intermediate protocol layer, and a second simulation module, the second simulation module being configured to simulate a storage control module and a storage module, and the second read / write information being configured to represent data transmission information when performing the read / write operation through the serial interface, the intermediate protocol layer, and the second simulation module;

[0115] The judging unit 33 may be configured to judge whether the first read / write information obtained by the first obtaining unit 31 and the second read / write information obtained by the second obtaining unit 32 meet preset read / write standards;

[0116] A first determining unit 34 may be configured to determine that data storage between the storage control module and the storage module is abnormal if the determining unit 33 determines that the first read / write information does not meet the preset read / write standard;

[0117] The second determining unit 35 may be configured to determine that data storage between the serial interface and the intermediate protocol layer is abnormal if the determining unit 33 determines that the second read / write information does not meet the preset read / write standard.

[0118] Optional, such as Figure 4 As shown, the device also includes:

[0119] The third determination unit 36 ​​can be used to determine that the data storage between the serial interface, the intermediate protocol layer, the storage control module and the storage module is normal if the determination unit 33 determines that the first read-write information and the second read-write information both meet the preset read-write standard.

[0120] Optional, such as Figure 4 As shown, the first analog module includes a BIST self-test module;

[0121] The first acquiring unit 31 includes:

[0122] An execution module 311 may be configured to control the BIST self-test module to perform a first read / write operation on the storage module through the storage control module;

[0123] The recording module 312 may be configured to record the read / write information of the first read / write operation performed by the execution module 311 as the first read / write information.

[0124] Optional, such as Figure 4 As shown, the second simulation module includes a data memory and a data storage controller;

[0125] The second acquiring unit 32 includes:

[0126] An execution module 321 may be configured to execute a second read / write operation on the data storage via the serial interface and the intermediate protocol layer via the data storage controller;

[0127] The recording module 322 may be configured to record the read / write information of the second read / write operation performed by the execution module 321 as the second read / write information.

[0128] Optional, such as Figure 4 As shown, the second circuit includes a multiplexer;

[0129] The second acquiring unit 32 further includes:

[0130] The setting module 323 may be configured to divide the second circuit into a first branch and a second branch by setting a multiplexer in the second circuit, wherein the first branch includes the data storage controller and the data storage;

[0131] The execution module 321 includes:

[0132] The control submodule 3211 may be configured to control the multiplexing controller to turn on the first branch;

[0133] The execution submodule 3212 can be used to perform the second read and write operation through the serial interface and the intermediate protocol layer, and after passing through the multiplexing controller and the first branch controlled by the control submodule 3211.

[0134] Optional, such as Figure 4 As shown, the second branch includes the storage module and the storage control module;

[0135] The device further comprises:

[0136] The control unit 37 may be configured to control the multiplexer to turn on the second branch if the judgment unit 33 judges that both the first read / write information and the second read / write information meet the preset read / write standard;

[0137] The execution unit 38 may be configured to control the serial interface and the intermediate protocol layer, and to execute a data storage operation on the storage module through the second branch controlled by the control unit 37 after passing through the multiplexer.

[0138] Optional, such as Figure 4 As shown, the storage module includes a GDDR6 memory, and the storage control module includes a GDDR6 memory controller.

[0139] Optional, such as Figure 4 As shown, the data memory includes an SRAM static random access memory, and the data storage controller includes an SRAM static random access controller.

[0140] For example, Figure 5 The present invention provides a schematic diagram of a portion of a serial interface-based storage test device according to an embodiment of the present invention. The serial interface-based storage test device includes a memory 501 for storing a program for executing the method described in the first embodiment. The serial interface-based storage test device also includes a processor 502 connected to the memory 501 and configured to execute the program stored in the memory 501.

[0141] When the processor 502 executes the computer program, it implements the steps of the method of the storage test device based on the serial interface in the first embodiment. Alternatively, when the processor executes the computer program, it implements the functions of each module / unit in the storage test device based on the serial interface in the second embodiment.

[0142] Illustratively, this embodiment also provides a computer-readable storage medium, such as Figure 6 As shown, a computer program 601 is stored thereon, and when the computer program 601 is executed by a processor, the storage test method based on the serial interface of any one of the embodiments of the first aspect mentioned above is implemented.

[0143] This embodiment provides a storage test method and related equipment based on a serial interface, which include: first, performing read and write operations through a first line and obtaining corresponding first read and write information; then, performing read and write operations through a second line and obtaining corresponding second read and write information; thereafter, respectively judging whether the first read and write information and the second read and write information meet preset read and write standards; finally, if the first read and write information does not meet the preset read and write standards, determining that data storage is abnormal between the storage control module and the storage module; at the same time, if the second read and write information does not meet the preset read and write standards, determining that data storage is abnormal between the serial interface and the intermediate protocol layer, thereby realizing a storage test function based on a serial interface. In the above scheme, since the first circuit includes a first simulation module, a storage control module and a storage module, the second circuit includes a serial interface, an intermediate protocol layer and a second simulation module, and the first simulation module is used to simulate the serial interface and the intermediate protocol layer, and the second simulation module is used to simulate the storage control module and the storage module, this can ensure that when a problem is detected in any circuit during the test process, it can be directly determined whether the problem exists in the module that has not been simulated, so that during the test process, it can be quickly determined through the two circuits whether the problem exists in the serial interface and the intermediate protocol layer module, or in the memory control module and the memory, thereby realizing the rapid location of the problem during the test process.

[0144] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection, or communication; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0145] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the description and implementation methods. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A storage test method based on a serial interface, characterized in that: include: Performing a read / write operation through a first circuit and obtaining corresponding first read / write information, wherein the first circuit includes a first simulation module, a storage control module, and a storage module, the first simulation module is used to simulate a serial interface and an intermediate protocol layer, and the first read / write information is used to represent data transmission information when the read / write operation is performed through the first simulation module, the storage control module, and the storage module; performing a read / write operation through a second line and obtaining corresponding second read / write information, wherein the second line includes a serial interface, an intermediate protocol layer, and a second simulation module, the second simulation module is used to simulate a storage control module and a storage module, and the second read / write information is used to represent data transmission information when performing the read / write operation through the serial interface, the intermediate protocol layer, and the second simulation module; respectively determining whether the first read-write information and the second read-write information meet preset read-write standards; If the first read / write information does not meet the preset read / write standard, determining that data storage between the storage control module and the storage module is abnormal; If the second read / write information does not meet the preset read / write standard, it is determined that data storage between the serial interface and the intermediate protocol layer is abnormal.

2. The method according to claim 1, characterized in that After respectively determining whether the first read-write information and the second read-write information meet preset read-write standards, the method further includes: If both the first read-write information and the second read-write information meet the preset read-write standard, it is determined that data storage among the serial interface, the intermediate protocol layer, the storage control module, and the storage module is normal.

3. The method according to claim 1, characterized in that The first analog module includes a BIST self-test module; The performing of the read and write operations through the first line and obtaining corresponding first read and write information includes: Controlling the BIST self-test module to perform a first read and write operation on the storage module through the storage control module; The read and write information during the first read and write operation is recorded as the first read and write information.

4. The method according to claim 1, wherein The second simulation module includes a data storage device and a data storage controller; The performing of the read and write operations through the second line and obtaining corresponding second read and write information includes: Performing a second read / write operation on the data storage via the data storage controller through the serial interface and the intermediate protocol layer; The read and write information during the second read and write operation is recorded as the second read and write information.

5. The method according to claim 4, characterized in that The second circuit includes a multiplexer; Before performing the second read / write operation on the data storage through the serial interface and the intermediate protocol layer via the data storage controller, the method further includes: By setting a multiplexer in the second circuit, the second circuit is divided into a first branch and a second branch, wherein the first branch includes the data storage controller and the data storage; The performing a second read / write operation on the data storage via the data storage controller through the serial interface and the intermediate protocol layer includes: controlling the multiplexer to turn on the first branch; The second read and write operations are performed through the serial interface and the intermediate protocol layer and through the first branch after passing through the multiplexer.

6. The method according to claim 5, characterized in that The second branch includes the storage module and the storage control module; The method further comprises: If both the first read / write information and the second read / write information meet a preset read / write standard, controlling the multiplexer to turn on the second branch; The serial interface and the intermediate protocol layer are controlled to perform a data storage operation on the storage module through the second branch after passing through the multiplexer.

7. The method according to any one of claims 1 to 6, characterized in that The storage module includes a GDDR6 memory, and the storage control module includes a GDDR6 memory controller.

8. The method according to any one of claims 1 to 6, characterized in that The data memory includes an SRAM static random access memory, and the data storage controller includes an SRAM static random access controller.

9. A memory chip provided with a memory test device having a serial interface, characterized in that: The storage test device of the serial interface comprises: a first acquiring unit, configured to perform a read / write operation through a first circuit and acquire corresponding first read / write information, wherein the first circuit includes a first simulation module, a storage control module, and a storage module, the first simulation module is configured to simulate a serial interface and an intermediate protocol layer, and the first read / write information is configured to represent data transmission information when the read / write operation is performed through the first simulation module, the storage control module, and the storage module; a second acquiring unit, configured to perform a read / write operation through a second line and acquire corresponding second read / write information, wherein the second line includes a serial interface, an intermediate protocol layer, and a second simulation module, the second simulation module is configured to simulate a storage control module and a storage module, and the second read / write information is configured to represent data transmission information when the read / write operation is performed through the serial interface, the intermediate protocol layer, and the second simulation module; a judging unit, configured to judge whether the first read-write information and the second read-write information meet preset read-write standards; a first determining unit, configured to determine that data storage between the storage control module and the storage module is abnormal if the first read / write information does not meet the preset read / write standard; The second determining unit is configured to determine that data storage between the serial interface and the intermediate protocol layer is abnormal if the second read / write information does not meet the preset read / write standard.

10. The memory chip provided with a memory test device having a serial interface according to claim 9, characterized in that: The device further comprises: The third determining unit is configured to determine that data storage among the serial interface, the intermediate protocol layer, the storage control module, and the storage module is normal if both the first read-write information and the second read-write information meet the preset read-write standard.

11. The memory chip of the memory test device provided with a serial interface according to claim 9, characterized in that: The first analog module includes a BIST self-test module; The first acquiring unit includes: an execution module, configured to control the BIST self-test module to perform a first read and write operation on the storage module through the storage control module; The recording module is used to record the read and write information during the first read and write operation as the first read and write information.

12. The memory chip provided with a memory test device having a serial interface according to claim 9, characterized in that: The second simulation module includes a data storage device and a data storage controller; The second acquiring unit includes: an execution module, configured to execute a second read / write operation on the data storage via the serial interface and the intermediate protocol layer and through the data storage controller; The recording module is used to record the read and write information during the second read and write operation as the second read and write information.

13. The memory chip provided with a memory test device having a serial interface according to claim 12, characterized in that: The second circuit includes a multiplexer; The second acquiring unit further includes: a setting module, configured to divide the second circuit into a first branch and a second branch by setting a multiplexer in the second circuit, wherein the first branch includes the data storage controller and the data storage; The execution module includes: a control submodule, configured to control the multiplexer to turn on the first branch; An execution submodule is used to perform the second read and write operation through the serial interface and the intermediate protocol layer and through the first branch after passing through the multiplexer.

14. The memory chip of the memory test device provided with a serial interface according to claim 13, characterized in that: The second branch includes the storage module and the storage control module; The device further comprises: a control unit, configured to control the multiplexer to turn on the second branch if both the first read / write information and the second read / write information meet a preset read / write standard; An execution unit is used to control the serial interface and the intermediate protocol layer to perform a data storage operation on the storage module through the second branch after passing through the multiplexer.

15. A memory chip provided with a memory test device having a serial interface according to any one of claims 9 to 14, characterized in that: The storage module includes a GDDR6 memory, and the storage control module includes a GDDR6 memory controller.

16. A memory chip provided with a memory test device having a serial interface according to any one of claims 9 to 14, characterized in that: The data memory includes an SRAM static random access memory, and the data storage controller includes an SRAM static random access controller.

17. An electronic device, characterized in that: It comprises a processor and a memory connected to the processor, wherein the processor is used to call program instructions in the memory to execute the storage test method based on the serial interface according to any one of claims 1 to 8.

18. A computer-readable storage medium, characterized in that A program is stored thereon, and when the program is executed by a processor, the storage test method based on the serial interface according to any one of claims 1 to 8 is implemented.

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