Pixel driving circuit and display panel

Abstract

The present invention provides a pixel driving circuit and a display panel, wherein the pixel driving circuit includes a data writing module, a data conversion module and a current driving module. The data writing module is electrically connected to a first node to transmit a data signal to the first node; the data conversion module is electrically connected to the first node, the second node and the modulation signal source to generate a current driving control signal according to the voltage difference between the modulation signal generated by the modulation signal source and the data signal received by the first node, and the current driving control signal is output to the second node; the current driving module is electrically connected to the second node, the light-emitting control line and the light-emitting device to control the light-emitting device to emit light according to the current driving control signal and the light-emitting control signal transmitted by the light-emitting control line. The pulse width of the effective pulse corresponding to the current driving control signal in different grayscale states is different.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel driving circuit and a display panel. Background Art

[0002] In existing display panels, when the grayscale of a sub-pixel is presented by a pulse amplitude modulation driving method, the wavelength and grayscale of the light emitted change simultaneously according to the amplitude of the driving current, so there is a problem of reduced color reproducibility of the image (ie, color shift). Summary of the invention

[0003] The embodiments of the present invention provide a pixel driving circuit and a display panel, which are beneficial to achieving the purpose of improving the problem of reduced image color reproducibility.

[0004] An embodiment of the present invention provides a pixel driving circuit, comprising a data writing module, a data conversion module and a current driving module. The data writing module is electrically connected to a first node to transmit a data signal to the first node; the data conversion module is electrically connected to the first node, a second node and a modulation signal source to generate a current driving control signal and output the current driving control signal to the second node; the current driving module is electrically connected to the second node, a light emitting control line and a light emitting device to control the light emitting device to emit light. The pulse width of the effective pulse corresponding to the current driving control signal in different grayscale states is different.

[0005] Optionally, in some embodiments of the present invention, the modulation signal generated by the modulation signal source is a triangular wave signal.

[0006] Optionally, in some embodiments of the present invention, within a first duration, the voltage value of the modulation signal is less than the voltage value of the data signal. Wherein, the pulse width is equal to the first duration.

[0007] Optionally, in some embodiments of the present invention, in a high grayscale state, the current drive control signal has a plurality of first effective pulses; in a low grayscale state, the current drive control signal has a plurality of second effective pulses, wherein the pulse width of the first effective pulse is greater than the pulse width of the second effective pulse, and the amplitude of the first effective pulse is equal to the amplitude of the second effective pulse.

[0008] Optionally, in some embodiments of the present invention, the data conversion module includes a current source unit, a current mirror unit and a signal correction unit. The current source unit is electrically connected to the third node; the current mirror unit is electrically connected to the third node, the first node, the modulation signal source and the fourth node, so as to generate a pulse width modulation signal and output the pulse width modulation signal to the fourth node; the signal correction unit is electrically connected to the fourth node and the second node, so as to generate the current drive control signal and transmit the current drive control signal to the second node.

[0009] Optionally, in some embodiments of the present invention, the current mirror unit includes: a first transistor, a second transistor, a third transistor and a fourth transistor.

[0010] The gate of the first transistor is electrically connected to the modulation signal source, and the source and drain of the first transistor are electrically connected between the third node and the fourth node; the gate of the second transistor is electrically connected to the first node, and one of the source and drain of the second transistor is electrically connected to the third node; the gate of the third transistor is electrically connected to the other of the source and drain of the second transistor, and the source and drain of the third transistor are electrically connected between the other of the source and drain of the second transistor and a first power supply terminal; the gate of the fourth transistor is electrically connected to the other of the source and drain of the second transistor, and the source and drain of the fourth transistor are electrically connected between the fourth node and the first power supply terminal.

[0011] Optionally, in some embodiments of the present invention, the current source unit includes a fifth transistor, a gate of the fifth transistor is electrically connected to the second power supply terminal, and a source and a drain of the fifth transistor are electrically connected between the second power supply terminal and the third node.

[0012] The signal correction unit includes a sixth transistor and a seventh transistor, the gate of the sixth transistor and the gate of the seventh transistor are both electrically connected to the fourth node, the source and the drain of the sixth transistor are electrically connected between the third power supply terminal and the second node, and the source and the drain of the seventh transistor are electrically connected between the fourth power supply terminal and the second node.

[0013] Among them, the volt value of the second power signal transmitted by the second power end is greater than the volt value of the first power signal transmitted by the first power end, and the volt value of the fourth power signal transmitted by the fourth power end is greater than the volt value of the third power signal transmitted by the third power end.

[0014] Optionally, in some embodiments of the present invention, the data writing module includes an eighth transistor and a first capacitor. The gate of the eighth transistor is electrically connected to the scan line, the source and drain of the eighth transistor are electrically connected between the first node and the data line, and the first capacitor is connected in series between the first node and the fifth power supply terminal.

[0015] Optionally, in some embodiments of the present invention, the current driving module includes a ninth transistor and a tenth transistor. The gate of the ninth transistor is electrically connected to the second node, and one of the source and the drain of the ninth transistor is electrically connected to the sixth power supply terminal; the gate of the tenth transistor is electrically connected to the light emitting control line, and the source and the drain of the tenth transistor are electrically connected between the other of the source and the drain of the ninth transistor and the anode of the light emitting device.

[0016] The cathode of the light emitting device is electrically connected to the fifth power supply terminal, and the volt value of the sixth power supply signal transmitted by the sixth power supply terminal is greater than the volt value of the fifth power supply signal transmitted by the fifth power supply terminal.

[0017] Optionally, in some embodiments of the present invention, the pixel driving circuit also includes a reset module, the reset module includes an eleventh transistor, the gate of the eleventh transistor is electrically connected to the reset control line, and the source and drain of the eleventh transistor are electrically connected between the first node and the fifth power supply terminal.

[0018] The present invention further provides a display panel, comprising any of the above-mentioned pixel driving circuits.

[0019] The present invention further provides a display panel, comprising a plurality of pixel driving circuits and a plurality of light emitting devices, wherein the plurality of pixel driving circuits are electrically connected to the plurality of light emitting devices. At least one of the pixel driving circuits comprises:

[0020] a first transistor, wherein a gate of the first transistor is electrically connected to a modulation signal source, and a source and a drain of the first transistor are electrically connected between a third node and a fourth node;

[0021] a second transistor, wherein a gate of the second transistor is electrically connected to the first node, and one of a source and a drain of the second transistor is electrically connected to a second power supply terminal through the third node;

[0022] a third transistor, wherein a gate of the third transistor is electrically connected to the other of the source and the drain of the second transistor, and a source and a drain of the third transistor are electrically connected between the other of the source and the drain of the second transistor and a first power supply terminal;

[0023] a fourth transistor, wherein a gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor, and a source and a drain of the fourth transistor are electrically connected between the fourth node and the first power supply terminal;

[0024] a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the fourth node, and a source and a drain of the sixth transistor are electrically connected between the third power supply terminal and the second node,

[0025] a seventh transistor, a gate of the seventh transistor being electrically connected to the fourth node, a source and a drain of the seventh transistor being electrically connected between a fourth power supply terminal and the second node; an eighth transistor, a gate of the eighth transistor being electrically connected to the scan line, a source and a drain of the eighth transistor being electrically connected between the first node and the data line;

[0026] a ninth transistor, a gate of the ninth transistor being electrically connected to the second node, and one of a source and a drain of the ninth transistor being electrically connected to a sixth power supply terminal; and

[0027] A tenth transistor, wherein the gate of the tenth transistor is electrically connected to the light-emitting control line, the source and the drain of the tenth transistor are electrically connected between the other of the source and the drain of the ninth transistor and the corresponding anode of the light-emitting device, and the cathode of the light-emitting device is electrically connected to the fifth power supply terminal.

[0028] Optionally, in some embodiments of the present invention, at least one of the pixel driving circuits further comprises:

[0029] a fifth transistor, wherein a gate of the fifth transistor is electrically connected to the second power supply terminal, and a source and a drain of the fifth transistor are electrically connected between the second power supply terminal and the third node; and

[0030] The first capacitor is connected in series between the first node and the fifth power supply terminal.

[0031] The present invention provides a pixel driving circuit and a display panel, wherein the pixel driving circuit includes a data writing module, a data conversion module and a current driving module. The data writing module is electrically connected to a first node to transmit a data signal to the first node; the data conversion module is electrically connected to the first node, the second node and the modulation signal source to generate a current driving control signal according to the voltage difference between the modulation signal generated by the modulation signal source and the data signal received by the first node, and the current driving control signal is output to the second node; the current driving module is electrically connected to the second node, the light-emitting control line and the light-emitting device to control the light-emitting device to emit light according to the current driving control signal and the light-emitting control signal transmitted by the light-emitting control line. The pulse width of the effective pulse corresponding to the current driving control signal in different grayscale states is different, so as to change the light-emitting time of the light-emitting device in the corresponding different grayscale states, so as to realize the grayscale difference during display, which is conducive to achieving the purpose of improving the problem of reduced image color reproducibility. The display panel includes a pixel driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1A It is a graph showing the change of the central wavelength of the light-emitting device with the current;

[0034] Figure 1B It is a schematic diagram of the structure of a pixel driving circuit in the prior art;

[0035] Figure 2A to Figure 2C is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0036] Figure 3 is a driving timing diagram provided by an embodiment of the present invention;

[0037] Figure 4 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0038] Figure 5A to Figure 5B Schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device.

[0040] Specifically, Figure 1A is a graph showing the change of the central wavelength of the light-emitting device with the current; taking the light-emitting device as an example, the light color of red is Figure 1A It can be seen that under different driving currents I, the light emitting center wavelength λ of the light emitting device will shift, which is reflected in the display screen as a problem of reduced color reproducibility of the image (ie, color shift).

[0041] Figure 1B It is a schematic diagram of the structure of a pixel driving circuit in the prior art. In the existing pixel driving circuit, a driving transistor Tdr, a data transistor Tda and a capacitor C are included. By controlling the voltage value of the data signal Data transmitted by the data line DaL, the gate-source voltage difference Vgs of the driving transistor Tdr is changed, thereby controlling the size of the driving current, thereby changing the light-emitting brightness of the light-emitting device, and then making the displayed picture have grayscale differences.

[0042] Figure 2A to Figure 2C is a structural schematic diagram of a pixel driving circuit provided by an embodiment of the present invention. The present invention provides a pixel driving circuit, including a data writing module 100, a data conversion module 200 and a current driving module 300.

[0043] The data writing module 100 is electrically connected to the first node Q1 to transmit a data signal Data to the first node Q1.

[0044] Optionally, the data writing module 100 includes an eighth transistor T8. The gate of the eighth transistor T8 is electrically connected to the scan line SL, the source and the drain of the eighth transistor T8 are electrically connected between the first node Q1 and the data line DaL, and the eighth transistor T8 is used to transmit the data signal Data transmitted by the data line DaL to the first node according to the scan signal Scan(n) transmitted by the scan line SL.

[0045] Optionally, the eighth transistor T8 is a P-type transistor or an N-type transistor. The eighth transistor T8 is a silicon transistor or an oxide transistor.

[0046] Optionally, the data writing module 100 further includes a first capacitor C1. The first capacitor C1 is connected in series between the first node Q1 and the fifth power supply terminal Vss, and the first capacitor C1 is used to maintain the potential of the first node Q1.

[0047] The data conversion module 200 is electrically connected to the first node Q1, the second node Q2 and the modulation signal source Sweep, so as to generate a current drive control signal Ic according to the voltage difference between the modulation signal Sw generated by the modulation signal source Sweep and the data signal Data received by the first node Q1, and output the current drive control signal Ic to the second node Q2.

[0048] Optionally, the data conversion module 200 includes a current mirror unit 201. The current mirror unit 201 is electrically connected to the third node Q3, the first node Q1, the modulation signal source Sweep and the fourth node Q4, so as to output a pulse width modulation signal according to the voltage difference between the modulation signal Sw and the data signal Data, and output the pulse width modulation signal to the fourth node Q4.

[0049] Optionally, the current mirror unit 201 includes: a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4.

[0050] The gate of the first transistor T1 is electrically connected to the modulation signal source Sweep, and the source and drain of the first transistor T1 are electrically connected between the third node Q3 and the fourth node Q4.

[0051] A gate of the second transistor T2 is electrically connected to the first node Q1 , and one of a source and a drain of the second transistor T2 is electrically connected to the third node Q3 .

[0052] The gate of the third transistor T3 is electrically connected to the other of the source and the drain of the second transistor T2 , and the source and the drain of the third transistor T3 are electrically connected between the other of the source and the drain of the second transistor T2 and the first power supply terminal Switch_L.

[0053] The gate of the fourth transistor T4 is electrically connected to the other of the source and the drain of the second transistor T2 , and the source and the drain of the fourth transistor T4 are electrically connected between the fourth node Q4 and the first power supply terminal Switch_L.

[0054] Optionally, the third node Q3 may be connected to a constant power source. Optionally, the data conversion module 200 further includes a current source unit 202, and the current source unit 202 is electrically connected to the third node Q3.

[0055] Optionally, the current source unit 202 includes a fifth transistor T5, a gate of the fifth transistor T5 is electrically connected to the second power supply terminal Switch_H, a source and a drain of the fifth transistor T5 are electrically connected between the second power supply terminal Switch_H and the third node Q3, and the fifth transistor T5 is used to transmit the second power supply signal transmitted by the second power supply terminal Switch_H to the third node Q3.

[0056] Optionally, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are P-type transistors or N-type transistors. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are silicon transistors or oxide transistors.

[0057] Optionally, the data conversion module 200 further includes a signal correction unit 203. The signal correction unit 203 is electrically connected to the fourth node Q4 and the second node Q2, so as to generate the current drive control signal Ic according to the pulse width modulation signal, and transmit the current drive control signal Ic to the second node Q2.

[0058] The pulse widths of effective pulses corresponding to different grayscale states of the current driving control signal Ic are different, so that the light-emitting device D can achieve different brightness differences when emitting light, thereby realizing display grayscale differences.

[0059] Optionally, the pulse width of the effective pulse of the current drive control signal Ic is positively correlated with the grayscale value. Optionally, in the high grayscale state, the current drive control signal Ic has a plurality of first effective pulses; in the low grayscale state, the current drive control signal Ic has a plurality of second effective pulses. The pulse width of the first effective pulse is greater than the pulse width of the second effective pulse, and the amplitude of the first effective pulse is equal to the amplitude of the second effective pulse, so that the light-emitting duration of the light-emitting device D in the high grayscale state is longer than the light-emitting duration of the light-emitting device D in the low grayscale state.

[0060] Optionally, the signal correction unit 203 includes a sixth transistor T6 and a seventh transistor T7.

[0061] The gate of the sixth transistor T6 is electrically connected to the fourth node Q4, the source and drain of the sixth transistor T6 are electrically connected between the third power supply terminal DL and the second node Q2, and the sixth transistor T6 is used to transmit the third power supply signal transmitted by the third power supply terminal DL to the second node Q2 according to the pulse width modulation signal.

[0062] The gate of the seventh transistor T7 is electrically connected to the fourth node Q4, the source and drain of the seventh transistor T7 are electrically connected between the fourth power terminal DH and the second node Q2, and the seventh transistor T7 is used to transmit the fourth power signal transmitted by the fourth power terminal DH to the second node Q2 according to the pulse width modulation signal.

[0063] Since the sixth transistor T6 and the seventh transistor T7 respectively transmit the third power signal transmitted by the third power terminal DL and the fourth power signal transmitted by the fourth power terminal DH to the second node Q2 according to the pulse width modulation signal to form the current drive control signal Ic, the pulse width of the effective pulse of the current drive control signal Ic can be controlled more accurately.

[0064] Optionally, the sixth transistor T6 and the seventh transistor T7 are P-type transistors or N-type transistors. The sixth transistor T6 and the seventh transistor T7 are silicon transistors or oxide transistors. To avoid the sixth transistor T6 and the seventh transistor T7 being turned on at the same time, the sixth transistor T6 is one of a P-type transistor and an N-type transistor, and the seventh transistor T7 is the other of a P-type transistor and an N-type transistor.

[0065] Please continue reading Figure 2A to Figure 2C The current driving module 300 is electrically connected to the second node Q2, the light-emitting control line EML and the light-emitting device D, so as to control the light-emitting device D to emit light according to the current driving control signal Ic and the light-emitting control signal Em(n) transmitted by the light-emitting control line EML.

[0066] Optionally, the current driving module 300 includes a ninth transistor T9 and a tenth transistor T10.

[0067] The gate of the ninth transistor T9 is electrically connected to the second node Q2, and one of the source and the drain of the ninth transistor T9 is electrically connected to the sixth power supply terminal Vdd.

[0068] The gate of the tenth transistor T10 is electrically connected to the light emitting control line EML, the source and the drain of the tenth transistor T10 are electrically connected between the other of the source and the drain of the ninth transistor T9 and the anode of the light emitting device, and the cathode of the light emitting device D is electrically connected to the fifth power supply terminal Vss.

[0069] The ninth transistor T9 and the tenth transistor T10 respectively generate a driving current Id for driving the light emitting device D to emit light in the path from the sixth power supply terminal Vdd to the fifth power supply terminal Vss under the action of the current driving control signal Ic and the light emitting control signal Em(n).

[0070] In addition, since the source and drain of the tenth transistor T10 are electrically connected between the ninth transistor T9 and the light-emitting device D, the tenth transistor T10 can be used to control the current path from the sixth power supply terminal Vdd to the fifth power supply terminal Vss, while also avoiding display abnormalities caused by the light-emitting device D erroneously emitting light during the writing of the data signal Data.

[0071] Optionally, see Figure 2C The pixel driving circuit further includes a reset module 400, and the reset module 400 is used to reset the first node Q1.

[0072] Optionally, the reset module 400 includes an eleventh transistor T11, a gate of the eleventh transistor T11 is electrically connected to the reset control line InL, and a source and a drain of the eleventh transistor T11 are electrically connected between the first node Q1 and a fifth power supply terminal Vss.

[0073] Optionally, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 are P-type transistors or N-type transistors. The eighth transistor T8, the ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 are silicon transistors or oxide transistors.

[0074] Optionally, the first power signal, the second power signal, the third power signal, the fourth power signal, the fifth power signal and the sixth power signal are all DC signals. The voltage value of the second power signal transmitted by the second power terminal Switch_H is greater than the voltage value of the first power signal transmitted by the first power terminal Switch_L, the voltage value of the fourth power signal transmitted by the fourth power terminal DH is greater than the voltage value of the third power signal transmitted by the third power terminal DL, and the voltage value of the sixth power signal transmitted by the sixth power terminal Vdd is greater than the voltage value of the fifth power signal transmitted by the fifth power terminal Vss, so as to ensure that the pixel driving circuit can work normally.

[0075] Optionally, the modulation signal Sw is a triangular wave signal. Accordingly, with the change of the modulation signal Sw, the data signal Data may be greater than the modulation signal Sw, or the data signal Data may be equal to the modulation signal Sw, or the data signal Data may be less than the modulation signal Sw. The branch current flowing through the first transistor T1 and the fourth transistor T4 and the branch current flowing through the second transistor T2 and the third transistor T3 are respectively determined by the modulation signal Sw and the potential of the first node Q1. Therefore, if the first transistor T1 and the second transistor T2 are both P-type transistors, when the potential of the first node Q1 is greater than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is greater than the branch current flowing through the second transistor T2 and the third transistor T3. Since the resistance of the branch where the first transistor T1 and the fourth transistor T4 are located and the resistance of the branch where the second transistor T2 and the third transistor T3 are located and the first power signal transmitted by the first power terminal Switch_L are fixed, when the branch current flowing through the first transistor T1 and the fourth transistor T4 increases, the voltage drop across the source and the drain of the fourth transistor T4 increases, so that the potential of the fourth node Q4 increases, the sixth transistor T6 is turned on as the potential of the fourth node Q4 increases, and the third power signal transmitted by the third power terminal DL is transmitted to the second node Q2. On the contrary, when the potential of the first node Q1 is less than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is less than the branch current flowing through the second transistor T2 and the third transistor T3. Since the resistances of the branch where the first transistor T1 and the fourth transistor T4 are located and the branch where the second transistor T2 and the third transistor T3 are located, and the first power signal transmitted by the first power terminal Switch_L are fixed, when the branch current flowing through the first transistor T1 and the fourth transistor T4 decreases, the voltage across the source and the drain of the fourth transistor T4 decreases, thereby reducing the potential of the fourth node Q4, and the seventh transistor T7 is turned on as the potential of the fourth node Q4 decreases, and the fourth power signal transmitted by the fourth power terminal DH is transmitted to the second node Q2.

[0076] It can be understood that if the first transistor T1 and the second transistor T2 are both N-type transistors, when the potential of the first node Q1 is less than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is greater than the branch current flowing through the second transistor T2 and the third transistor T3, so that the potential of the fourth node Q4 increases, the sixth transistor T6 is turned on as the potential of the fourth node Q4 increases, and the third power signal transmitted by the third power terminal DL is transmitted to the second node Q2. When the potential of the first node Q1 is greater than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is less than the branch current flowing through the second transistor T2 and the third transistor T3, so that the potential of the fourth node Q4 decreases, the seventh transistor T7 is turned on as the potential of the fourth node Q4 decreases, and the fourth power signal transmitted by the fourth power terminal DH is transmitted to the second node Q2.

[0077] Figure 3 : is a driving timing diagram provided by an embodiment of the present invention, taking the first transistor T1, the second transistor T2, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 as P-type transistors, and the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 as N-type transistors as an example, Figure 2B The working principle of the pixel driving circuit shown in the figure is described. Among them, V1-V6 represent the voltage values ​​of the first power signal to the sixth power signal respectively; V7 represents a high potential, and V8 represents a low potential; TB and TD both represent pulse widths; Vsh represents the maximum value of the modulation signal Sw, and Vsl represents the minimum value of the modulation signal Sw.

[0078] In the first frame Frame1, when the scan signal Scan(n) transmitted by the scan line SL is at a low potential and the light control signal Em(n) transmitted by the light control line EML is at a high potential, the eighth transistor T8 is turned on, and the data signal Data transmitted by the data line DaL is transmitted to the first node Q1. At this time, the data signal Data has a first voltage value VB.

[0079] After the scanning signal Scan(n) changes from a low potential to a high potential and the light emitting control signal Em(n) changes from a high potential to a low potential, the tenth transistor T10 is turned on. When the potential of the first node Q1 is greater than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is greater than the branch current flowing through the second transistor T2 and the third transistor T3. Since the resistance of the branch where the first transistor T1 and the fourth transistor T4 are located and the resistance of the branch where the second transistor T2 and the third transistor T3 are located and the first power signal transmitted by the first power terminal Switch_L are fixed, when the branch current flowing through the first transistor T1 and the fourth transistor T4 increases, the voltage drop across the source and drain of the fourth transistor T4 increases, so that the potential of the fourth node Q4 increases, the sixth transistor T6 is turned on as the potential of the fourth node Q4 increases, the third power signal transmitted by the third power terminal DL is transmitted to the second node Q2 (i.e., corresponding to the effective pulse of the current drive control signal Ic), the ninth transistor T9 is turned on, and the light emitting device D enters the light emitting state. When the potential of the first node Q1 is less than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is less than the branch current flowing through the second transistor T2 and the third transistor T3. Since the resistance of the branch where the first transistor T1 and the fourth transistor T4 are located and the branch where the second transistor T2 and the third transistor T3 are located and the first power signal transmitted by the first power terminal Switch_L are fixed, when the branch current flowing through the first transistor T1 and the fourth transistor T4 decreases, the voltage across the source and drain of the fourth transistor T4 decreases, thereby reducing the potential of the fourth node Q4, and the seventh transistor T7 is turned on as the potential of the fourth node Q4 decreases, and the fourth power signal transmitted by the fourth power terminal DH is transmitted to the second node Q2 (i.e., the invalid pulse between the two valid pulses corresponding to the current drive control signal Ic), the ninth transistor T9 is turned off, and the light-emitting device D enters a non-light-emitting state. Until the light-emitting control signal EM(n) changes from a low potential to a high potential, the light-emitting state of the light-emitting device D enters a cyclic state as the difference between the modulation signal Sw and the potential of the first node Q1.

[0080] In the second frame Frame2: when the scan signal Scan(n) transmitted by the scan line SL is at a low potential and the light emitting control signal Em(n) transmitted by the light emitting control line EML is at a high potential, the eighth transistor T8 is turned on, and the data signal Data transmitted by the data line DaL is transmitted to the first node Q1. At this time, the data signal Data has a second voltage value VD different from the first voltage value VB.

[0081] After the scanning signal Scan(n) changes from a low potential to a high potential and the light emitting control signal Em(n) changes from a high potential to a low potential, the tenth transistor T10 is turned on. When the potential of the first node Q1 is greater than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is greater than the branch current flowing through the second transistor T2 and the third transistor T3, so that the potential of the fourth node Q4 increases, the sixth transistor T6 is turned on as the potential of the fourth node Q4 increases, the third power signal transmitted by the third power terminal DL is transmitted to the second node Q2, the ninth transistor T9 is turned on, and the light emitting device D enters a light emitting state. When the potential of the first node Q1 is less than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is less than the branch current flowing through the second transistor T2 and the third transistor T3, so that the potential of the fourth node Q4 decreases, the seventh transistor T7 is turned on as the potential of the fourth node Q4 decreases, the fourth power signal transmitted by the fourth power terminal DH is transmitted to the second node Q2, the ninth transistor T9 is turned off, and the light-emitting device D enters a non-light-emitting state. Until the light-emitting control signal EM(n) changes from a low potential to a high potential, the light-emitting state of the light-emitting device D enters a cyclic state as the difference between the modulation signal Sw and the potential of the first node Q1.

[0082] By controlling the voltage value of the data signal Data transmitted by the data line DaL in different frames, the effective pulse of the current drive control signal Ic can have different pulse widths in different frames according to the voltage difference between the data signal Data and the modulation signal, and thus the effective pulse of the drive current Id can also have different pulse widths in different frames, so that the light-emitting device D has different light-emitting durations in different grayscale states, and grayscale differences can be displayed. The light-emitting brightness of the light-emitting device D is proportional to the product of time and the drive current Id.

[0083] In addition, since the light emitting device D enters a cycle state of a light emitting state and a non-light emitting state according to the difference between the modulation signal Sw and the potential of the first node Q1 during the effective stage of the light emitting control signal Em(n), the brightness attenuation problem of the light emitting device D when it continues to emit light for a long time can be improved, and the flicker problem can also be improved. The effective stage of the light emitting control signal Em(n) refers to the stage in which the tenth transistor T10 can be turned on.

[0084] It can be understood that the frequency and amplitude of the modulation signal Sw can be set according to actual needs.

[0085] In order to enable the eighth transistor T8 to work normally, the voltage value of the data signal Data is greater than the voltage value corresponding to the low potential V8 of the scan signal Scan(n) and less than the voltage value corresponding to the high potential V7 of the scan signal Scan(n).

[0086] To ensure that the ninth transistor T9 can be effectively turned off, the difference between the voltage value of the fourth power signal V4 transmitted by the fourth power terminal DH and the threshold voltage of the ninth transistor T9 is greater than or equal to the voltage value of the second power signal V2 transmitted by the second power terminal Vdd.

[0087] In order to enable the tenth transistor T10 to operate normally, the voltage value corresponding to the high potential V7 of the light-emitting control signal Em(n) is greater than the voltage value of the second power signal V2 transmitted by the second power terminal Vdd, and the voltage value corresponding to the low potential V8 of the light-emitting control signal Em(n) is less than the voltage value of the first power signal V1 transmitted by the first power terminal Vss.

[0088] Optionally, within a first time duration t1, the voltage value of the modulation signal Sw is less than the voltage value of the data signal Data. Wherein, the pulse width of the effective pulse of the current drive control signal Ic is equal to the first time duration t1.

[0089] It can be understood that the first time duration t1 can be calculated according to Vsh, Vsl and Data. Specifically, taking the data signal Data as VB as an example, t=t1 / 2=(VB-Vsl)*T / (Vsh-Vsl).

[0090] Optionally, the grayscale state corresponding to the first frame Frame1 is a high grayscale state, and the grayscale state corresponding to the second frame Frame2 is a low grayscale state, and the current drive control signal Ic has a plurality of first valid pulses in the first frame Frame1, and a plurality of second valid pulses in the second frame Frame2. The pulse width of the first valid pulse is TB, and the pulse width of the second valid pulse is TD, TB>TD; and the amplitude of the first valid pulse is equal to the amplitude of the second valid pulse, so that the light-emitting duration of the light-emitting device D corresponding to the high grayscale state is longer than the light-emitting duration of the light-emitting device D corresponding to the low grayscale state.

[0091] Optionally, the first transistor T1 and the second transistor T2 are both N-type transistors, and within the second duration, the voltage value of the modulation signal Sw is greater than the voltage value of the data signal Data. The pulse width of the effective pulse of the current drive control signal Ic is equal to the second duration.

[0092] Optionally, the reset module 400 may reset the first node Q1 before the data signal Data is transmitted to the first node Q1. That is, the reset control signal transmitted by the reset control line InL turns on the eleventh transistor T11 before the scan signal Scan(n) enters the effective phase, thereby resetting the first node Q1. The scan signal Scan(n) entering the effective phase refers to the phase in which the eighth transistor T8 can be turned on.

[0093] In addition, the first node Q1 can be reset by setting a virtual frame before the first frame Frame1. That is, before the first frame Frame1, the eighth transistor T8 is turned on according to the scan signal Scan(n), and at this time, the data signal Data transmits a voltage value with a reset function to reset the first node Q1.

[0094] The present invention further provides a display panel, comprising any of the above-mentioned pixel driving circuits.

[0095] Figure 4 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention, Figure 5A to Figure 5B Schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present invention.

[0096] The present invention further provides a display panel, comprising a plurality of pixel driving circuits and a plurality of light emitting devices D, wherein the plurality of pixel driving circuits are electrically connected to the plurality of light emitting devices. At least one of the pixel driving circuits comprises:

[0097] The first transistor T1 has a gate electrically connected to the modulation signal source Sweep, and a source and a drain electrically connected between the third node Q3 and the fourth node Q4.

[0098] The second transistor T2 has a gate electrically connected to the first node Q1 , and one of a source and a drain of the second transistor T2 is electrically connected to the first power supply terminal Switch_H through the third node Q3 .

[0099] A third transistor T3, wherein a gate of the third transistor T3 is electrically connected to the other of the source and the drain of the second transistor T2, and a source and a drain of the third transistor T3 are electrically connected between the other of the source and the drain of the second transistor T2 and a first power supply terminal Switch_L.

[0100] A fourth transistor T4, wherein a gate of the fourth transistor T4 is electrically connected to the other of the source and the drain of the second transistor T2, and a source and a drain of the fourth transistor T4 are electrically connected between the fourth node Q4 and the first power supply terminal Switch_L.

[0101] A sixth transistor T6, a gate of the sixth transistor T6 is electrically connected to the fourth node Q4, and a source and a drain of the sixth transistor T6 are electrically connected between the third power supply terminal DL and the second node Q2.

[0102] A seventh transistor T7, a gate of the seventh transistor T7 is electrically connected to the fourth node Q4, and a source and a drain of the seventh transistor T7 are electrically connected between the fourth power terminal DH and the second node Q2.

[0103] An eighth transistor T8, wherein a gate of the eighth transistor T8 is electrically connected to the scan line, and a source and a drain of the eighth transistor T8 are electrically connected between the first node Q1 and the data line DaL.

[0104] A ninth transistor T9, wherein a gate of the ninth transistor T9 is electrically connected to the second node Q2, and one of a source and a drain of the ninth transistor T9 is electrically connected to a sixth power supply terminal Vdd.

[0105] A tenth transistor T10, a gate of the tenth transistor T10 is electrically connected to the light emitting control line EML, a source and a drain of the tenth transistor T10 are electrically connected between the other of the source and the drain of the ninth transistor T9 and the corresponding anode of the light emitting device D, and a cathode of the light emitting device is electrically connected to the fifth power supply terminal Vss.

[0106] Optionally, at least one of the pixel driving circuits further includes a fifth transistor T5, a gate of the fifth transistor T5 is electrically connected to the first power terminal Switch_H, and a source and a drain of the fifth transistor T5 are electrically connected between the first power terminal Switch_H and the third node Q3.

[0107] Optionally, at least one of the pixel driving circuits further includes a first capacitor C1 connected in series between the first node Q1 and the fifth power supply terminal Vss.

[0108] Optionally, the plurality of light-emitting devices D include a first light-emitting device, a second light-emitting device, and a third light-emitting device with different light-emitting colors, and the plurality of pixel driving circuits include a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit. The first pixel driving circuit is used to drive the first light-emitting device to emit light, the second pixel driving circuit is used to drive the second light-emitting device to emit light, and the third pixel driving circuit is used to drive the third light-emitting device to emit light. By controlling the difference in data signals transmitted by the data line DaL electrically connected to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit, the light-emitting durations of the first light-emitting device, the second light-emitting device, and the third light-emitting device corresponding to the same grayscale state can be different, thereby realizing the display of grayscale differences and improving the problem of reduced color reproducibility of the image.

[0109] Optionally, the light emitting device D includes a sub-millimeter light emitting diode, a micro light emitting diode and an organic light emitting diode.

[0110] The present invention further provides a display device, comprising any one of the above-mentioned driving circuits or any one of the above-mentioned display panels.

[0111] It can be understood that the display device includes a movable display device (such as a laptop computer, a mobile phone, etc.), a fixed terminal (such as a desktop computer, a television, etc.), a measuring device (such as a sports bracelet, a thermometer, etc.), etc.

[0112] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A pixel driving circuit, characterized in that: include: A data writing module, electrically connected to the first node, and configured to transmit a data signal to the first node; a data conversion module, electrically connected to the first node, the second node and the modulation signal source, for generating a current drive control signal, and outputting the current drive control signal to the second node; as well as a current driving module, electrically connected to the second node, the light-emitting control line and the light-emitting device, and configured to control the light-emitting device to emit light according to the current driving control signal and the light-emitting control signal transmitted by the light-emitting control line; Wherein, the pulse width of the effective pulse of the current driving control signal corresponding to different grayscale states is different; Wherein, the data conversion module includes: a current source unit, electrically connected to the third node, and configured to provide a second power signal to the third node; a current mirror unit, electrically connected to the third node, the first node, the modulation signal source and the fourth node, for generating a pulse width modulation signal, and outputting the pulse width modulation signal to the fourth node; a signal correction unit, electrically connected to the fourth node and the second node, configured to generate the current drive control signal and transmit the current drive control signal to the second node; In which, the signal correction unit includes a sixth transistor and a seventh transistor, the gate of the sixth transistor and the gate of the seventh transistor are both electrically connected to the fourth node, the source and drain of the sixth transistor are electrically connected between the third power supply terminal and the second node, and the source and drain of the seventh transistor are electrically connected between the fourth power supply terminal and the second node.

2. The pixel driving circuit according to claim 1, characterized in that: The modulation signal generated by the modulation signal source is a triangular wave signal.

3. The pixel driving circuit according to claim 2, characterized in that: During a first time period, the voltage value of the modulation signal is less than the voltage value of the data signal; Wherein, the pulse width is equal to the first duration.

4. The pixel driving circuit according to claim 1, characterized in that: In the high grayscale state, the current driving control signal has a plurality of first effective pulses; in the low grayscale state, the current driving control signal has a plurality of second effective pulses; The pulse width of the first effective pulse is greater than the pulse width of the second effective pulse, and the amplitude of the first effective pulse is equal to the amplitude of the second effective pulse.

5. The pixel driving circuit according to claim 1, characterized in that: The current mirror unit comprises: a first transistor, wherein a gate of the first transistor is electrically connected to the modulation signal source, and a source and a drain of the first transistor are electrically connected between the third node and the fourth node; a second transistor, wherein a gate of the second transistor is electrically connected to the first node, and one of a source and a drain of the second transistor is electrically connected to the third node; a third transistor, a gate of the third transistor being electrically connected to the other of the source and the drain of the second transistor, and a source and a drain of the third transistor being electrically connected between the other of the source and the drain of the second transistor and a first power supply terminal; and A fourth transistor, wherein a gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor, and a source and a drain of the fourth transistor are electrically connected between the fourth node and the first power supply terminal.

6. The pixel driving circuit according to claim 5, characterized in that: The current source unit includes a fifth transistor, a gate of the fifth transistor is electrically connected to the second power supply terminal, and a source and a drain of the fifth transistor are electrically connected between the second power supply terminal and the third node; Among them, the volt value of the second power signal transmitted by the second power end is greater than the volt value of the first power signal transmitted by the first power end, and the volt value of the fourth power signal transmitted by the fourth power end is greater than the volt value of the third power signal transmitted by the third power end.

7. The pixel driving circuit according to claim 1, characterized in that: The data writing module comprises: an eighth transistor, a gate of the eighth transistor being electrically connected to the scan line, and a source and a drain of the eighth transistor being electrically connected between the first node and the data line; and The first capacitor is connected in series between the first node and the fifth power supply terminal.

8. The pixel driving circuit according to claim 1, characterized in that: The current driving module comprises: a ninth transistor, a gate of the ninth transistor being electrically connected to the second node, and one of a source and a drain of the ninth transistor being electrically connected to a sixth power supply terminal; and a tenth transistor, wherein a gate of the tenth transistor is electrically connected to the light emitting control line, and a source and a drain of the tenth transistor are electrically connected between the other of the source and the drain of the ninth transistor and an anode of the light emitting device; The cathode of the light emitting device is electrically connected to the fifth power supply terminal, and the volt value of the sixth power supply signal transmitted by the sixth power supply terminal is greater than the volt value of the fifth power supply signal transmitted by the fifth power supply terminal.

9. The pixel driving circuit according to claim 1, characterized in that: It also includes a reset module, the reset module including: An eleventh transistor, a gate of the eleventh transistor is electrically connected to the reset control line, and a source and a drain of the eleventh transistor are electrically connected between the first node and a fifth power supply terminal.

10. A display panel, characterized in that: It includes a plurality of pixel driving circuits and a plurality of light emitting devices, wherein the plurality of pixel driving circuits are electrically connected to the plurality of light emitting devices; At least one of the pixel driving circuits comprises: a first transistor, wherein a gate of the first transistor is electrically connected to a modulation signal source, and a source and a drain of the first transistor are electrically connected between a third node and a fourth node; a second transistor, wherein a gate of the second transistor is electrically connected to the first node, and one of a source and a drain of the second transistor is electrically connected to a second power supply terminal through the third node; a third transistor, wherein a gate of the third transistor is electrically connected to the other of the source and the drain of the second transistor, and a source and a drain of the third transistor are electrically connected between the other of the source and the drain of the second transistor and a first power supply terminal; a fourth transistor, wherein a gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor, and a source and a drain of the fourth transistor are electrically connected between the fourth node and the first power supply terminal; a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the fourth node, and a source and a drain of the sixth transistor are electrically connected between the third power supply terminal and the second node, a seventh transistor, a gate of the seventh transistor being electrically connected to the fourth node, and a source and a drain of the seventh transistor being electrically connected between a fourth power supply terminal and the second node; an eighth transistor, a gate of the eighth transistor being electrically connected to the scan line, and a source and a drain of the eighth transistor being electrically connected between the first node and the data line; a ninth transistor, a gate of the ninth transistor being electrically connected to the second node, and one of a source and a drain of the ninth transistor being electrically connected to a sixth power supply terminal; and A tenth transistor, wherein the gate of the tenth transistor is electrically connected to the light-emitting control line, the source and the drain of the tenth transistor are electrically connected between the other of the source and the drain of the ninth transistor and the corresponding anode of the light-emitting device, and the cathode of the light-emitting device is electrically connected to the fifth power supply terminal.

11. The display panel according to claim 10, characterized in that: At least one of the pixel driving circuits further comprises: a fifth transistor, wherein a gate of the fifth transistor is electrically connected to the second power supply terminal, and a source and a drain of the fifth transistor are electrically connected between the second power supply terminal and the third node; and The first capacitor is connected in series between the first node and the fifth power supply terminal.

Images