P-type GaN-based high electron mobility transistor and manufacturing method thereof

Abstract

The present invention relates to a P-type GaN-based high electron mobility transistor and a method for manufacturing the same. The method comprises: obtaining a substrate; the substrate comprising a channel layer, a primary epitaxial barrier layer on the channel layer, and a gate structure on the primary epitaxial barrier layer, wherein the gate structure is made of P-type doped GaN; forming a source recess and a drain recess on either side of the gate structure, wherein the source recess and the drain recess extend downward from the upper surface of the primary epitaxial barrier layer to the channel layer; performing secondary epitaxy on the substrate to form a secondary epitaxial barrier layer, wherein the secondary epitaxial barrier layer is made of the same material as the primary epitaxial barrier layer; forming a source electrode, a drain electrode, and a gate electrode; the source electrode forms an ohmic contact with the epitaxial layer in the source recess, and the drain electrode forms an ohmic contact with the epitaxial layer in the drain recess. The present invention can simultaneously meet the device's high threshold voltage and low sheet resistance requirements for the active area.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, in particular to a P-type GaN-based high electron mobility transistor, and also to a method for manufacturing the P-type GaN-based high electron mobility transistor. Background Art

[0002] The safety of power electronic systems requires that the threshold voltage of power devices is generally above 2V. For P-GaN HEMT (High Electron Mobility Transistor) devices, we hope that they have a sufficiently high threshold voltage. Summary of the Invention

[0003] Based on this, it is necessary to provide a P-type GaN-based high electron mobility transistor with a sufficiently high threshold voltage and a manufacturing method thereof.

[0004] A method for manufacturing a P-type GaN-based high electron mobility transistor comprises: obtaining a substrate; the substrate comprising a GaN channel layer, a primary epitaxial AlGaN barrier layer on the GaN channel layer, and a gate structure on the primary epitaxial barrier layer, wherein the gate structure is made of P-type doped GaN; forming a source recess and a drain recess on both sides of the gate structure, wherein the source recess and the drain recess extend downward from the upper surface of the primary epitaxial AlGaN barrier layer to the GaN channel layer; forming a secondary epitaxial AlGaN barrier layer on the substrate by secondary epitaxy, wherein the material of the secondary epitaxial AlGaN barrier layer is the same as that of the primary epitaxial AlGaN barrier layer; forming a source electrode, a drain electrode, and a gate electrode; the source electrode forms an ohmic contact with the secondary epitaxial AlGaN barrier layer in the source recess, and the drain electrode forms an ohmic contact with the secondary epitaxial AlGaN barrier layer in the drain recess.

[0005] The above-mentioned method for manufacturing a P-type GaN-based high-electron mobility transistor is to form a secondary epitaxial AlGaN barrier layer made of the same material as the primary epitaxial AlGaN barrier layer on the primary epitaxial AlGaN barrier layer after forming the gate structure. Therefore, the primary epitaxial AlGaN barrier layer below the gate structure can be made thinner, making the two-dimensional electron gas below the gate structure more easily depleted and the threshold voltage of the device higher. At the same time, the sheet resistance of the active region is affected by the thickness of the AlGaN barrier layer. The secondary epitaxy of the active region thickens the AlGaN barrier layer to a certain thickness, so the secondary epitaxial AlGaN barrier layer can reduce the sheet resistance of the active region. In other words, the thickness of the primary epitaxial AlGaN barrier layer below the gate structure and the thickness of the secondary epitaxial AlGaN barrier layer in the active region can be adjusted independently of each other. When the barrier layer below the gate structure is thin, the barrier layer in the active region can be made sufficiently thick, thereby simultaneously meeting the high threshold voltage of the device and the low sheet resistance requirements of the active region.

[0006] In one embodiment, the substrate further includes an insertion layer formed between the channel layer and the barrier layer, and the material of the insertion layer includes AlN; the step of forming the source groove and the drain groove adopts an etching process to etch the barrier layer, the insertion layer and the channel layer on both sides of the gate structure to form the source groove and the drain groove.

[0007] In one embodiment, the thickness of the insertion layer is 1 nm.

[0008] In one embodiment, in the step of etching the barrier layer, the insertion layer, and the channel layer to form the source groove and the drain groove, the thickness of the channel layer etched and removed is less than 20 nanometers.

[0009] In one embodiment, the thickness of the channel layer removed by etching is 0 to 20 nanometers.

[0010] In one embodiment, the barrier layer and the epitaxial layer are made of AlGaN.

[0011] In one embodiment, in the step of forming an epitaxial layer on the substrate by epitaxial growth, the thickness of the grown epitaxial layer is 1 to 10 nanometers.

[0012] In one embodiment, the substrate further includes a buffer layer, and the channel layer and the primary epitaxial barrier layer are formed on the buffer layer.

[0013] In one embodiment, the material of the buffer layer includes GaN.

[0014] In one embodiment, the material of the channel layer includes GaN.

[0015] In one embodiment, the step of forming the epitaxial layer on the substrate is to form the epitaxial layer by metal organic chemical vapor deposition technology.

[0016] In one embodiment, the method further includes forming a dielectric layer on the epitaxial layer.

[0017] A P-type GaN-based high electron mobility transistor comprises: a GaN channel layer; a primary epitaxial AlGaN barrier layer, disposed on the GaN channel layer; a gate structure, disposed on the primary epitaxial AlGaN barrier layer, the material of the gate structure comprising P-type doped GaN; source grooves and drain grooves are formed on both sides of the gate structure, the source grooves and drain grooves extending downward through the primary epitaxial AlGaN barrier layer to the GaN channel layer; a secondary epitaxial AlGaN barrier layer, disposed on the primary epitaxial AlGaN barrier layer and also disposed on the bottom and sidewalls of the source grooves and drain grooves; a source electrode, filled in the source groove, forming an ohmic contact with the secondary epitaxial AlGaN barrier layer; a drain electrode, filled in the drain groove, forming an ohmic contact with the secondary epitaxial AlGaN barrier layer; and a gate electrode, disposed on the gate structure.

[0018] The above-mentioned P-type GaN-based high-electron mobility transistor has a secondary epitaxial AlGaN barrier layer made of the same material as the primary epitaxial AlGaN barrier layer, which allows the primary epitaxial AlGaN barrier layer below the gate structure to be made thinner, making the two-dimensional electron gas below the gate structure more easily depleted and the threshold voltage of the device higher. At the same time, the sheet resistance of the active region is affected by the thickness of the AlGaN barrier layer. The secondary epitaxy of the active region thickens the AlGaN barrier layer to a certain thickness, so the secondary epitaxial AlGaN barrier layer can reduce the sheet resistance of the active region. In other words, the thickness of the primary epitaxial AlGaN barrier layer below the gate structure and the thickness of the secondary epitaxial AlGaN barrier layer in the active region can be adjusted independently of each other. When the barrier layer below the gate structure is thin, the barrier layer in the active region can be made sufficiently thick, thereby simultaneously meeting the high threshold voltage of the device and the low sheet resistance requirements of the active region.

[0019] In one embodiment, an insertion layer is further included between the GaN channel layer and the primary epitaxial AlGaN barrier layer, the source groove and the drain groove pass through the insertion layer, and the material of the insertion layer includes AlN.

[0020] In one embodiment, the thickness of the insertion layer is 1 nm.

[0021] In one embodiment, the secondary epitaxial AlGaN barrier layer has a thickness of 1 to 10 nanometers.

[0022] In one embodiment, the source groove and the drain groove have a depth of less than 20 nanometers in the channel layer.

[0023] In one embodiment, the depth is 5 to 15 nanometers.

[0024] In one embodiment, the P-type GaN-based high electron mobility transistor further includes a buffer layer; and the channel layer is formed on the buffer layer.

[0025] In one embodiment, the material of the buffer layer includes GaN.

[0026] In one embodiment, the P-type GaN-based high electron mobility transistor further includes a dielectric layer disposed on the epitaxial layer.

[0027] In one embodiment, the P-type doped GaN is in direct contact with the barrier layer.

[0028] In one embodiment, the source electrode is made of metal and / or alloy.

[0029] In one embodiment, the material of the drain electrode includes metal and / or alloy.

[0030] In one embodiment, the gate electrode is made of metal and / or alloy. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0032] Figures 1a-1d In one embodiment, Figure 3 A schematic cross-sectional view of a device during the process of manufacturing a P-GaN HEMT according to the method shown;

[0033] Figure 2 is a cross-sectional schematic diagram of a P-type GaN-based high electron mobility transistor in one embodiment;

[0034] Figure 3 FIG. 1 is a flow chart of a method for manufacturing a P-type GaN-based high electron mobility transistor in one embodiment. DETAILED DESCRIPTION

[0035] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0038] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0041] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0042] The AlGaN barrier layer of an exemplary P-GaN HEMT device is approximately 15nm thick. Normally-off operation is only possible when holes in the P-GaN gate deplete the two-dimensional electron gas beneath the gate. Power electronics system safety requirements generally require a threshold voltage of 2V or higher for power devices. A thin AlGaN barrier layer makes the two-dimensional electron gas beneath the gate more easily depleted, leading to a higher threshold voltage for the P-GaN device. However, the thinner AlGaN active region also increases the sheet resistance, leading to a higher on-resistance for the device.

[0043] Based on this, the present application provides a P-type GaN-based high electron mobility transistor with a sufficiently high threshold voltage and a small sheet resistance of the active region and a manufacturing method thereof. Figure 3 FIG. 1 is a flow chart of a method for manufacturing a P-type GaN-based high electron mobility transistor in one embodiment, comprising the following steps:

[0044] S310, obtaining a substrate.

[0045] The substrate includes a channel layer 120, a primary epitaxial barrier layer 140 on the channel layer 120, and a gate structure 150 on the primary epitaxial barrier layer 140. The gate structure 150 is made of P-type doped GaN.

[0046] In one embodiment of the present application, the thickness of the primary epitaxial barrier layer 140 is 5-15 nm.

[0047] In one embodiment of the present application, the gate structure 150 may be formed by photolithography and etching the P-GaN layer 152 on the primary epitaxial barrier layer 140, see Figure 1a and Figure 1b , the P-type doped GaN (ie, the gate structure 150 ) is in direct contact with the primary epitaxial barrier layer 140 .

[0048] In one embodiment of the present application, the substrate further includes an insertion layer 130 formed between the channel layer 120 and the primary epitaxial barrier layer 140. In one embodiment of the present application, the insertion layer 130 is an AlN spacer. Providing an insertion layer 130 made of AlN material can improve the confinement of the two-dimensional electron gas, thereby improving the current collapse effect of the device and improving the device reliability. The process of the source and drain grooves can make the ohmic contact process of the AlN spacer better realized. In one embodiment of the present application, the thickness of the insertion layer 130 is 0.2 to 1.5 nm; further, it can be 1 nm.

[0049] In one embodiment of the present application, the substrate further includes a buffer layer 110. The channel layer 120 and the primary epitaxial barrier layer 140 are formed on the buffer layer 110. It is understood that other structures of HEMT devices known in the art, such as a substrate, may also be provided under the buffer layer 110.

[0050] In one embodiment of the present application, the buffer layer 110 is a GaN buffer.

[0051] In one embodiment of the present application, the channel layer 120 is a GaN layer.

[0052] In one embodiment of the present application, the primary epitaxial barrier layer 140 is an AlGaN layer.

[0053] S320 , forming a source groove and a drain groove on both sides of the gate structure.

[0054] The source groove 141 and the drain groove 143 extend downward from the upper surface of the primary epitaxial barrier layer 140 to the channel layer 120, see Figure 1cIn one embodiment of the present application, a source recess 141 and a drain recess 143 are formed by etching downward from the upper surface of the primary epitaxial barrier layer 140 to the channel layer 120 through a photolithography and etching process. The primary epitaxial barrier layer 140 is completely recessed, and after etching through the insertion layer 130, the channel layer 120 is continuously overetched by zero to twenty nanometers, that is, the thickness of the channel layer 120 etched away at the source recess 141 and the drain recess 143 can be zero to twenty nanometers. Furthermore, the thickness of the channel layer 120 etched away is 0 to 20 nanometers.

[0055] S330 , epitaxially forming a secondary epitaxial barrier layer on the substrate.

[0056] The material of the secondary epitaxial barrier layer 142 is the same as that of the primary epitaxial barrier layer 140. Figure 1d In the embodiment shown, the secondary epitaxial barrier layer 142 is an AlGaN layer formed by secondary epitaxy. In one embodiment of the present application, the thickness of the secondary epitaxial barrier layer 142 grown by secondary epitaxy is 1 to 10 nanometers.

[0057] In one embodiment of the present application, after step S320 and before step S330, the structure obtained in step S320 (ie Figure 1c The corresponding structure) is cleaned.

[0058] In one embodiment of the present application, the secondary epitaxial barrier layer 142 is formed by using MOCVD (Metal Organic Chemical Vapor Deposition) equipment.

[0059] S340 , forming a source electrode, a drain electrode, and a gate electrode.

[0060] Electrode windows are opened to form electrodes. Gate electrode 172 is formed on gate structure 150. Source electrode 171 forms an ohmic contact with secondary epitaxial barrier layer 142 in the source groove, and drain electrode 173 forms an ohmic contact with secondary epitaxial barrier layer 142 in the drain groove. The processes after step S330 can adopt conventional processes known in the art. Figure 2 FIG3 is a schematic cross-sectional view of the device after step S340 is completed in one embodiment. In this embodiment, a dielectric layer 160 is further formed on the secondary epitaxial barrier layer 142. The dielectric layer 160 can be formed first, and then the gate electrode 172, source electrode 171, and drain electrode 173 can be formed through contact hole photolithography and etching processes, and metal sputtering processes.

[0061] In the above-mentioned method for manufacturing a P-type GaN-based high electron mobility transistor, after forming the gate structure 150, a secondary epitaxial barrier layer 142 made of the same material as the primary epitaxial barrier layer 140 is epitaxially formed on the primary epitaxial barrier layer 140. Therefore, the primary epitaxial barrier layer 140 below the gate structure 150 can be made thinner, making it easier to deplete the two-dimensional electron gas under the gate structure 150, and the threshold voltage of the device will also be higher; at the same time, the sheet resistance of the active area is affected by the thickness of the AlGaN barrier layer. The secondary epitaxy of the active area thickens the AlGaN barrier layer to a certain thickness, so the secondary epitaxial AlGaN barrier layer can reduce the sheet resistance of the active area. That is to say, the thickness of the primary epitaxial barrier layer 140 under the gate structure 150 and the thickness of the secondary epitaxial barrier layer 142 in the active area can be adjusted independently of each other. When the primary epitaxial barrier layer 140 under the gate structure 150 is relatively thin, the AlGaN barrier layer in the active area can be made thick enough, thereby simultaneously meeting the high threshold voltage of the device and the low sheet resistance requirements of the active area.

[0062] For an exemplary P-GaN HEMT device with an AlN Spacer layer, Recess technology is required to form a low-ohmic contact structure for the source and drain electrodes. However, the intra-chip etching uniformity of the Recess process of the currently commonly used six-inch line equipment is poor. For P-GaN HEMT devices with an AlN Spacer layer, the high aluminum component of the AlN Spacer layer makes the ohmic contact of the structure difficult to make and the process uniformity is poor, which places high demands on the process equipment. Specifically, etching to form the source and drain grooves requires etching through the AlN Spacer layer and then continuing to etch down the channel layer to a very shallow depth (exemplarily 5nm, depending on the design of the channel layer). Therefore, it is difficult for general etching equipment to meet the requirements of etching endpoint control and etching uniformity. The above-mentioned method for manufacturing a P-type GaN-based high electron mobility transistor further forms a secondary epitaxial barrier layer 142 on the inner surface of the source groove 141 and the drain groove 143. Therefore, even if the etching depth of the source groove 141 and the drain groove 143 is not well controlled (the etching is too deep), an AlGaN layer with good thickness uniformity and repeatability can be obtained through the secondary epitaxial barrier layer 142. The thickness of the secondary epitaxial barrier layer 142 can be precisely controlled, that is, the thickness of the AlGaN in the ohmic contact can be precisely controlled, so the uniformity and stability of the ohmic contact when forming the source electrode and the drain electrode can be guaranteed. Therefore, the secondary epitaxial barrier layer 142 can reduce the requirements for Resess etching uniformity and precisely control the thickness of the AlGaN in the ohmic contact, thereby improving the uniformity of the ohmic contact with the AlN spacer structure, solving the problems of wafer batch-to-wafer repeatability and intra-wafer uniformity of the ohmic contact of the P-GaN HEMT with the AlN spacer structure.

[0063] The present application accordingly provides a P-type GaN-based high electron mobility transistor, see Figure 2 , including a channel layer 120, a primary epitaxial barrier layer 140, a gate structure 150, a secondary epitaxial barrier layer 142, a source electrode 171, a drain electrode 173 and a gate electrode 172. The primary epitaxial barrier layer 140 is provided on the channel layer 120. The gate structure 150 is provided on the primary epitaxial barrier layer 140. The material of the gate structure 150 is P-type doped GaN, and the P-type doped GaN is in direct contact with the primary epitaxial barrier layer 140. Source grooves and drain grooves are formed on both sides of the gate structure, and the source grooves and drain grooves extend downward through the primary epitaxial barrier layer 140 to the channel layer 120. The secondary epitaxial barrier layer 142 is provided on the primary epitaxial barrier layer 140, and is also provided at the bottom and sidewalls of the source grooves and the drain grooves. The material of the secondary epitaxial barrier layer 142 is the same as that of the primary epitaxial barrier layer 140. The source electrode 171 is filled in the source groove and forms an ohmic contact with the secondary epitaxial barrier layer 142. The drain electrode 173 is filled in the drain groove and forms an ohmic contact with the secondary epitaxial barrier layer 142. The gate electrode 172 is disposed on the gate structure 150.

[0064] In the aforementioned P-type GaN-based high-electron-mobility transistor, a secondary epitaxial barrier layer 142 made of the same material as the primary epitaxial barrier layer 140 is provided on the primary epitaxial barrier layer 140. Therefore, the primary epitaxial barrier layer 140 below the gate structure 150 can be made thinner, making the two-dimensional electron gas below the gate structure 150 more easily depleted and the threshold voltage of the device higher. At the same time, the sheet resistance of the active region is affected by the thickness of the AlGaN barrier layer. The secondary epitaxial growth of the active region thickens the AlGaN barrier layer to a certain thickness, so the secondary epitaxial barrier layer 142 can reduce the sheet resistance of the active region. In other words, the thickness of the primary epitaxial barrier layer 140 below the gate structure 150 and the thickness of the secondary epitaxial barrier layer 142 in the active region can be adjusted independently of each other. This allows the AlGaN barrier layer in the active region to be sufficiently thick even when the primary epitaxial barrier layer 140 below the gate structure 150 is thin, thereby simultaneously meeting the device's high threshold voltage and low sheet resistance requirements for the active region.

[0065] exist Figure 2 In the embodiment shown, the P-type GaN-based high electron mobility transistor also includes an insertion layer 130 provided between the channel layer 120 and the primary epitaxial barrier layer 140, and the source groove and the drain groove pass downward through the insertion layer 130. In one embodiment of the present application, the insertion layer 130 is an AlN spacer. Providing an insertion layer 130 of AlN material can improve the confinement of the two-dimensional electron gas, thereby improving the current collapse effect of the device and improving the device reliability. In one embodiment of the present application, the thickness of the insertion layer 130 is 0.2 to 1.5 nm; further, it can be 1 nm.

[0066] In one embodiment of the present application, the P-type GaN-based high electron mobility transistor further includes a buffer layer 110. A channel layer 120 and a primary epitaxial barrier layer 140 are formed on the buffer layer 110. It is understood that other structures of HEMT devices known in the art, such as a substrate, may also be provided below the buffer layer 110.

[0067] In one embodiment of the present application, the buffer layer 110 is a GaN buffer.

[0068] In one embodiment of the present application, the channel layer 120 is a GaN layer.

[0069] In one embodiment of the present application, the primary epitaxial barrier layer 140 is an AlGaN layer.

[0070] In one embodiment of the present application, the thickness of the secondary epitaxial barrier layer is 1 to 10 nanometers.

[0071] In one embodiment of the present application, the depth of the source groove and the drain groove in the channel layer 120 is 0 to 20 nanometers.

[0072] exist Figure 2 In the illustrated embodiment, the P-type GaN-based high electron mobility transistor further includes a dielectric layer 160 disposed on the secondary epitaxial barrier layer 142 .

[0073] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0074] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0075] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A method for manufacturing a p-type GaN-based high electron mobility transistor, comprising: Obtaining a substrate; The substrate includes a channel layer, a primary epitaxial barrier layer on the channel layer, and a gate structure on the primary epitaxial barrier layer, wherein the channel layer is made of GaN, the primary epitaxial barrier layer is made of AlGaN, and the gate structure is made of P-type doped GaN; forming a source groove and a drain groove on both sides of the gate structure, wherein the source groove and the drain groove extend downward from the upper surface of the primary epitaxial barrier layer to the channel layer; After forming source grooves and drain grooves on both sides of the gate structure, forming a secondary epitaxial barrier layer on the substrate by secondary epitaxy, wherein the material of the secondary epitaxial barrier layer is the same as that of the primary epitaxial barrier layer; forming a source electrode, a drain electrode, and a gate electrode; wherein the source electrode forms an ohmic contact with the secondary epitaxial barrier layer in the source groove, and the drain electrode forms an ohmic contact with the secondary epitaxial barrier layer in the drain groove; Among them, the thickness of the barrier layer under the gate structure is the thickness of the primary epitaxial barrier layer under the gate structure, the thickness of the barrier layer under the source electrode is the thickness of the secondary epitaxial barrier layer under the source electrode, and the thickness of the barrier layer under the drain electrode is the thickness of the secondary epitaxial barrier layer under the drain electrode.

2. The method for manufacturing a P-type GaN-based high electron mobility transistor according to claim 1, wherein: The substrate also includes an insertion layer formed between the channel layer and the primary epitaxial barrier layer, and the material of the insertion layer includes AlN; the step of forming the source groove and the drain groove adopts an etching process to etch the primary epitaxial barrier layer, the insertion layer and the channel layer on both sides of the gate structure to form the source groove and the drain groove.

3. The method for manufacturing a P-type GaN-based high electron mobility transistor according to claim 2, wherein: In the step of etching the primary epitaxial barrier layer, the insertion layer and the channel layer to form the source groove and the drain groove, the thickness of the channel layer etched and removed is no more than 20 nanometers.

4. The method for manufacturing a P-type GaN-based high electron mobility transistor according to claim 2, wherein: In the step of forming a secondary epitaxial barrier layer on the substrate by secondary epitaxy, the thickness of the formed secondary epitaxial barrier layer is 1 to 10 nanometers.

5. The method for manufacturing a P-type GaN-based high electron mobility transistor according to claim 1, wherein: The substrate further includes a buffer layer, and the channel layer is formed on the buffer layer.

6. The method for manufacturing a P-type GaN-based high electron mobility transistor according to claim 1, wherein: The step of forming a secondary epitaxial barrier layer on the substrate by secondary epitaxy is achieved by metal organic compound chemical vapor deposition technology.

7. A P-type GaN-based high electron mobility transistor, characterized in that: include: GaN channel layer; a primary epitaxial AlGaN barrier layer, disposed on the GaN channel layer; A gate structure is provided on the primary epitaxial AlGaN barrier layer, wherein the material of the gate structure includes P-type doped GaN; a source groove and a drain groove are formed on both sides of the gate structure, and the source groove and the drain groove extend downward through the primary epitaxial AlGaN barrier layer to the GaN channel layer; A secondary epitaxial AlGaN barrier layer is provided on the primary epitaxial AlGaN barrier layer and is also provided on the bottom and sidewalls of the source groove and the drain groove; A source electrode is filled in the source groove and forms an ohmic contact with the secondary epitaxial AlGaN barrier layer; a drain electrode, filled in the drain groove, and forming an ohmic contact with the secondary epitaxial AlGaN barrier layer; a gate electrode, disposed on the gate structure; Among them, the thickness of the barrier layer under the gate structure is the thickness of the primary epitaxial barrier layer under the gate structure, the thickness of the barrier layer under the source electrode is the thickness of the secondary epitaxial barrier layer under the source electrode, and the thickness of the barrier layer under the drain electrode is the thickness of the secondary epitaxial barrier layer under the drain electrode.

8. The P-type GaN-based high electron mobility transistor according to claim 7, characterized in that: The system further includes an insertion layer disposed between the GaN channel layer and the primary epitaxial AlGaN barrier layer. The source groove and the drain groove pass through the insertion layer. The material of the insertion layer includes AlN.

9. The P-type GaN-based high electron mobility transistor according to claim 7, characterized in that: The thickness of the secondary epitaxial AlGaN barrier layer is 1 to 10 nanometers.

10. The P-type GaN-based high electron mobility transistor according to claim 7, characterized in that: The depth of the source groove and the drain groove in the channel layer is no more than 20 nanometers.

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