Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention relates to a solar cell and a preparation method thereof, and a photovoltaic module, and the solar cell comprises a substrate which is provided with a first surface and a second surface, and the first surface and the second surface are opposite to each other; the first surface is provided with a groove; the first tunneling oxide layer is arranged in the groove of the first surface; the first doped polycrystalline silicon layer is arranged on one side, far away from the first surface, of the first tunneling oxide layer in the groove; the doping type of the first doped polycrystalline silicon layer is the same as that of the substrate; the first passivation anti-reflection layer is arranged on one side, far away from the first doped polycrystalline silicon layer, of the first surface; the first electrode grid line is arranged in the groove of the first surface, and the first electrode grid line penetrates through the first passivation anti-reflection layer to be in contact with the first doped polycrystalline silicon layer; the solar cell is capable of parasitic absorption; transmission channels of carriers are increased; and the ohmic contact between the electrode grid line and the doped polycrystalline silicon layer can be enhanced.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, including solar cells and their preparation methods, and photovoltaic modules. Background Technology

[0002] TOPCon (Tunnel Oxide Passivated Contact) solar cells are favored in the market due to their high efficiency and excellent surface passivation characteristics. To further improve the conversion efficiency of TOPCon solar cells, the passivation effect can be optimized.

[0003] Traditional methods often improve passivation by using high concentrations of doping, but this method leads to an increase in carrier concentration in the polysilicon layer, resulting in more light being absorbed by the polysilicon layer and causing parasitic absorption loss. Summary of the Invention

[0004] Therefore, it is necessary to provide a solar cell and its preparation method, as well as a photovoltaic module, that can reduce parasitic absorption.

[0005] In a first aspect, this application provides a solar cell, comprising:

[0006] A substrate having a first surface and a second surface disposed opposite to each other; the first surface is provided with a groove.

[0007] A first tunneling oxide layer is disposed in a groove on the first surface;

[0008] A first doped polysilicon layer is disposed in the groove on the side of the first tunneling oxide layer away from the first surface; the doping type of the first doped polysilicon layer is the same as the doping type of the substrate.

[0009] The first passivation anti-reflection layer is disposed on the side of the first surface away from the first doped polysilicon layer;

[0010] The first electrode gate line is disposed in the groove of the first surface, and the first electrode gate line passes through the first passivation antireflection layer and contacts the first doped polysilicon layer.

[0011] In one embodiment, it further includes:

[0012] A groove provided on the second surface;

[0013] The second tunneling oxide layer is disposed in the groove of the second surface;

[0014] A second doped polysilicon layer is disposed within the groove on the side of the second tunneling oxide layer away from the second surface; the doping type of the second doped polysilicon layer is different from the doping type of the substrate.

[0015] The second passivation anti-reflection layer is disposed on the side of the second surface away from the second doped polysilicon layer;

[0016] The second electrode gate line is disposed in the groove of the second surface, and the second electrode gate line passes through the second passivation antireflection layer and contacts the second doped polysilicon layer.

[0017] In one embodiment, the groove on the second surface is disposed opposite to the groove on the first surface in the thickness direction of the substrate.

[0018] In one embodiment, the depth of the groove is 5 to 8 micrometers.

[0019] In one embodiment, the height of the electrode grid line is greater than the depth of the groove.

[0020] In one embodiment, the width of the groove on the first surface is greater than the width of the first electrode grid line, and the width of the groove on the second surface is greater than the width of the second electrode grid line.

[0021] In one embodiment, the width of the first electrode grid line is greater than the width of the second electrode grid line, and the width of the groove on the first surface is greater than the width of the groove on the second surface.

[0022] In one embodiment, the first passivation antireflection layer has a smooth surface structure, and the first tunneling oxide layer, the first doped polysilicon layer, the second tunneling oxide layer, the second doped polysilicon layer, and the second passivation antireflection layer all have a textured surface structure.

[0023] Secondly, this application also provides a method for preparing a solar cell, comprising:

[0024] A substrate is provided, the substrate having a first surface and a second surface disposed opposite to each other;

[0025] A groove is formed within the first surface of the substrate;

[0026] A first tunneling oxide layer is formed within the groove on the first surface;

[0027] A first polysilicon layer is formed on the side of the first surface away from the first tunneling oxide layer, and the first polysilicon layer outside the groove is removed;

[0028] The first polysilicon layer within the groove is doped to form a first doped polysilicon layer; the doping type of the first doped polysilicon layer is the same as the doping type of the substrate.

[0029] A first passivation and antireflection layer is formed on the side of the first surface away from the substrate;

[0030] A first electrode gate line is formed within the groove, passing through the first passivation antireflection layer and contacting the first doped polysilicon layer.

[0031] In one embodiment, a groove is formed within the second surface of the substrate;

[0032] A second tunneling oxide layer is formed within the groove on the second surface;

[0033] A second polysilicon layer is formed on the side of the second surface away from the second tunneling oxide layer, and the second polysilicon layer outside the groove is removed;

[0034] The second polysilicon layer within the groove is doped to form a second doped polysilicon layer; the doping type of the second doped polysilicon layer is different from the doping type of the substrate.

[0035] A second passivation antireflection layer is formed on the side of the second surface away from the substrate;

[0036] A second electrode gate line is formed within the groove, passing through the second passivation antireflection layer and contacting the second doped polysilicon layer.

[0037] In one embodiment, after forming the groove and before forming the polysilicon layer, the method further includes:

[0038] The first surface, the second surface, and the groove are subjected to a flocking process to form a flocked structure.

[0039] In one embodiment, before forming the first passivation antireflection layer, after forming the first doped polysilicon layer, the textured structure of the first surface is alkaline polished to form a smooth structure.

[0040] Thirdly, this application also provides a photovoltaic module, including at least one battery string, the battery string including at least two of the above-described solar cells or solar cells prepared using the above-described solar cell preparation method.

[0041] The aforementioned solar cell, by setting a doped polycrystalline silicon layer, can adsorb metal impurities in the substrate to the doped polycrystalline silicon layer through the getter effect, reducing defect recombination in the substrate and helping to improve minority carrier lifetime. Moreover, the doped polycrystalline silicon layer can form ohmic contacts, reducing contact resistance and thus improving carrier transport efficiency. Furthermore, the doped polycrystalline silicon layer is only set in the groove, which can reduce parasitic absorption and improve the utilization rate of incident light. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the structure of a solar cell according to one embodiment;

[0044] Figure 2 This is a schematic diagram of the structure of a solar cell according to another embodiment;

[0045] Figure 3 A flowchart illustrating a method for fabricating a solar cell according to one embodiment;

[0046] Figure 4 This is a flowchart illustrating a solar cell fabrication method according to another embodiment.

[0047] Explanation of reference numerals in the attached figures:

[0048] Substrate: 100; First tunneling oxide layer: 200; First doped polysilicon layer: 300; First passivation antireflection layer: 400; First passivation layer: 410; First antireflection layer: 420; First electrode gate line: 500; Second tunneling oxide layer: 600; Second doped polysilicon layer: 700; Second passivation antireflection layer: 800; Second passivation layer: 810; Second antireflection layer: 820; Second electrode gate line: 900. Detailed Implementation

[0049] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0051] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

[0052] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0053] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0054] TOPCon (Tunnel Oxide Passivated Contact) is a high-efficiency crystalline silicon solar cell technology. Through its unique back-side passivated contact structure, it significantly improves the open-circuit voltage (Voc) and conversion efficiency. A highly doped polycrystalline silicon layer forms a strong electric field beneath the ultra-thin tunnel oxide layer. This field effectively repels minority carriers, preventing them from reaching the back surface interface, thereby significantly reducing the surface recombination rate and achieving excellent field-effect passivation. However, the highly doped polycrystalline silicon layer exhibits strong absorption of incident infrared light. This absorption does not generate electrical energy but instead converts light energy into heat loss, i.e., parasitic absorption, leading to a decrease in the cell's conversion efficiency. To reduce the impact of parasitic absorption caused by high-concentration doping, this application provides a solar cell, see reference. Figure 1 include:

[0055] The substrate 100 has a first surface and a second surface disposed opposite to each other; the first surface is a backlight surface, and the second surface is a light-receiving surface; the first surface is provided with a groove. The substrate 100 can be made of N-type single crystal silicon or P-type single crystal silicon; the thickness of the substrate 100 can be 120 to 150 micrometers. In this embodiment, 130 micrometers of N-type single crystal silicon is used as an example.

[0056] A first tunneling oxide layer 200 is disposed within a groove on the first surface. The first tunneling oxide layer 200 allows specific types of charge carriers (such as electrons) to tunnel from the silicon substrate to the first doped polysilicon layer 300 via a tunneling effect, while blocking another type of charge carrier (such as holes). This selective transport mechanism is highly effective for achieving efficient charge separation and collection, reducing carrier recombination losses, and improving the fill factor and conversion efficiency of the battery. Since the first tunneling oxide layer 200 primarily provides a carrier transport channel between the doped polysilicon layer and the substrate, reducing the area of ​​the first tunneling oxide layer 200, which would reduce the area of ​​the first doped polysilicon layer 300, can save material.

[0057] The first tunneling oxide layer 200 can be deposited within the groove, at least on the bottom surface of the groove; wherein, the bottom surface of the groove is a relative position, in Figure 1 The "middle" refers to the top of the groove. It is understandable that, due to process reasons, some of the material of the first tunneling oxide layer 200 may also be deposited on the sidewall of the groove. This method can increase the area between the first tunneling oxide layer 200 and the first doped polysilicon layer 300, thereby increasing the carrier transport channel.

[0058] The first doped polysilicon layer 300 is disposed in the groove on the side of the first tunneling oxide layer 200 away from the first surface; the doping type of the first doped polysilicon layer 300 is the same as the doping type of the substrate; in this embodiment, the substrate 100 is N-type single crystal silicon, so the first doped polysilicon layer 300 is an N-type doped layer; both are high-concentration phosphorus doped.

[0059] In TOPCON cells, the first doped polysilicon layer 300 and the first tunneling oxide layer 200 together form a passivation contact structure, creating a charge-selective contact. Taking an N-type TOPCon cell as an example, the first doped polysilicon layer 300 is N-type, allowing electrons to pass through the first tunneling oxide layer 200 from the substrate 100 into the first doped polysilicon layer 300, while blocking hole recombination, thus achieving selective electron transport and improving carrier collection efficiency. However, high doping concentrations cause a redshift in the optical absorption edge of the polysilicon layer, i.e., a shift towards longer wavelengths. This means that photons that could originally penetrate the polysilicon layer and be absorbed by the substrate may now be absorbed by the polysilicon layer, thus being converted into heat energy and unable to be used for power generation, thereby increasing parasitic absorption. Reducing the doping concentration will decrease the conductivity of the polysilicon layer, increase the contact resistance, and thus reduce the photoelectric conversion efficiency. In this embodiment, by placing the first doped polysilicon layer 300 in the groove of the back surface of the solar cell, the incident light can reach the substrate 100 without passing through the first doped polysilicon layer 300, thus reducing photon loss. In this embodiment, the area of ​​the first doped polysilicon layer 300 on the back surface is also reduced, further reducing the absorption of reflected light by the first doped polysilicon layer 300.

[0060] A first passivation antireflection layer 400 is disposed on the side of the first surface away from the first doped polysilicon layer 300; the first passivation antireflection layer 400 includes a first passivation layer 410 and a first antireflection layer 420 disposed sequentially; the first passivation layer 410 may be made of aluminum oxide, titanium oxide, zirconium oxide, etc.; the first passivation layer 410 may be 3 to 20 nanometers; the first passivation layer 410 may be set to 3 nanometers, 10 nanometers, 15 nanometers or 20 nanometers depending on the material or requirements of the first passivation layer 410; the first antireflection layer 420 may be made of silicon nitride, magnesium fluoride, titanium dioxide, etc. In one embodiment, the first passivation layer 410 is made of alumina and has a thickness of 3 nanometers, while the first antireflection layer 420 is made of silicon nitride and has a thickness of 100 nanometers. Alumina exhibits excellent chemical and field passivation effects, effectively reducing surface recombination rates and increasing open-circuit voltage. Furthermore, alumina contains a large number of fixed negative charges, attracting holes and repelling electrons, reducing electron-hole recombination, extending carrier lifetime, and improving battery efficiency. Silicon nitride reduces light reflection and improves light absorption efficiency. Its refractive index is similar to that of silicon, effectively reducing interface reflectivity, allowing more photons to enter the silicon substrate, increasing the number of photogenerated carriers, and improving short-circuit current.

[0061] A first electrode gate line 500 is disposed within a groove on the first surface, and the first electrode gate line 500 passes through the first passivation antireflection layer 400 and contacts the first doped polysilicon layer 300. The contact between the first electrode gate line 500 and the first doped polysilicon layer 300 enables efficient collection of charge carriers (electrons or holes) in the first doped polysilicon layer 300 and their transfer to external circuitry. This ensures that the current generated by the battery can be effectively extracted and utilized, improving the battery's output performance.

[0062] In this embodiment, only the structures disposed on the first surface of the substrate are limited, namely the first tunneling oxide layer 200 and the first doped polysilicon layer 300 disposed in the groove, as well as the first passivation antireflection layer 400 and the first electrode gate line 500; the structures disposed on the second surface are not limited; for example, a doped polysilicon layer, an aluminum oxide layer and a silicon nitride layer may be disposed sequentially on the second surface; and an electrode gate line that passes through the aluminum oxide layer and the silicon nitride layer and contacts the doped polysilicon layer is disposed.

[0063] The aforementioned solar cell reduces the area of ​​the first doped polycrystalline silicon layer 300 by placing it in the groove, thereby further reducing the absorption of incident light by the first doped polycrystalline silicon layer 300 and thus reducing parasitic absorption.

[0064] In one embodiment, the solar cell is described in reference to... Figure 2 It includes a substrate 100, a first tunneling oxide layer 200, a first doped polysilicon layer 300, a first passivation antireflection layer 400, and a first electrode gate line 500; it also includes:

[0065] A groove is provided on the second surface.

[0066] The second tunneling oxide layer 600 is disposed in the groove of the second surface.

[0067] The second doped polysilicon layer 700 is disposed in the groove on the side of the second tunneling oxide layer 600 away from the second surface; the doping type of the second doped polysilicon layer 700 is different from the doping type of the substrate 100; in this example, the substrate 100 is N-type single crystal silicon and the doping element is phosphorus, then the second doped polysilicon layer 700 is a P-type doped layer and the doping element is boron.

[0068] In this embodiment, both the first and second surfaces are provided with a tunneling oxide layer and a doped polysilicon layer, which can effectively achieve selective transport of charge carriers. The tunneling oxide layer allows specific types of charge carriers to enter the doped polysilicon layer through the tunneling effect, while blocking other types of charge carriers. Specifically, the first doped polysilicon layer 300 is an N-type doped layer, and the corresponding first tunneling oxide layer 200 allows electrons to pass through, which can efficiently collect photogenerated electrons from the N-type substrate, while blocking holes from reaching the first electrode gate line. The second doped polysilicon layer 700 is a P-type doped layer, and the corresponding second tunneling oxide layer 600 allows holes to pass through, which can efficiently collect photogenerated holes from the substrate, while blocking electrons from reaching the second electrode gate line 900. This selective mechanism greatly reduces the loss of charge carriers due to recombination near the metal contact point.

[0069] A second passivation and antireflection layer 800 is disposed on the side of the second surface away from the second doped polycrystalline silicon layer 700. The second passivation and antireflection layer 800 includes a second passivation layer 810 and a second antireflection layer 820. The second passivation layer 810 can be made of alumina, titanium oxide, zirconium oxide, etc. The second passivation layer 810 can be 3 to 20 nanometers in size. The second passivation layer 810 can be set to 3 nanometers, 10 nanometers, 15 nanometers, or 20 nanometers depending on the material or requirements. The second antireflection layer 820 can be made of silicon nitride, magnesium fluoride, titanium dioxide, etc. In one embodiment, the second passivation layer 810 is made of alumina and has a thickness of 3 nanometers, and the second antireflection layer 820 is made of silicon nitride and has a thickness of 100 nanometers. By providing passivation layers on both the first and second surfaces, surface recombination on both surfaces can be significantly reduced, thereby extending the carrier lifetime and improving the open-circuit voltage and short-circuit current of the battery. By setting antireflection layers on both the first and second surfaces, the reflectivity of both surfaces can be effectively reduced, and the light absorption rate can be increased, thereby further improving the short-circuit current of the battery.

[0070] The second electrode gate line 900 is disposed within a groove on the second surface, and the second electrode gate line 900 passes through the second passivation antireflection layer 800 and contacts the second doped polysilicon layer 700. By placing the second electrode gate line 900 inside the groove, it can penetrate deep into the PN junction, resulting in faster electron extraction and better current extraction.

[0071] The aforementioned solar cell has a tunneling oxide layer and a doped polycrystalline silicon layer disposed in the grooves on both the first and second surfaces, which can reduce parasitic absorption on both sides; and due to the selective transport of the tunneling oxide layer, the surface recombination rate is reduced, and the open-circuit voltage of the cell is further improved due to the reduction of recombination loss.

[0072] In one embodiment, the groove on the second surface is disposed opposite to the groove on the first surface in the thickness direction of the substrate 100; since the electrode grid lines are disposed in the grooves; the opposite arrangement of the grooves on the first surface and the second surface ensures that the first electrode grid lines 500 and the second electrode grid lines 900 are disposed opposite to each other in the thickness direction of the substrate 100.

[0073] The relative arrangement of grid lines helps to form a more uniform electric field distribution inside the battery, avoids electric field distortion, and improves carrier mobility. Furthermore, the relative arrangement of grid lines can ensure that the carrier transport path is optimized to be the shortest, thereby achieving efficient collection from inside the battery to the electrodes. It can also reduce current loss during the transmission process.

[0074] In one embodiment, the depth of the groove is 5-8 micrometers. Since the thickness of the substrate 100 is greater than 100 micrometers, setting the groove depth to 5-8 micrometers has almost no impact on the battery. Furthermore, since the tunneling oxide layer and the doped polysilicon layer are very thin, with thicknesses in the nanometer range, not only are the tunneling oxide layer and the doped polysilicon layer disposed inside the groove, but also the passivation layer and the antireflection layer are deposited because the tunneling oxide layer and the doped polysilicon layer cannot fill the groove. At the same time, the passivation layer and the antireflection layer are also deposited on the surface of the substrate (non-groove). Figure 1 and Figure 2 This is only a general structural diagram and does not constitute a limitation on the structure of this application.

[0075] In one embodiment, the depth of the groove is 5-8 micrometers, and the height of the electrode grid line is greater than the depth of the groove. The reason for the electrode grid line being greater than the depth of the groove is to lead the electrode grid line out of the groove for easy connection to the outside.

[0076] In one embodiment, the width of the groove on the first surface is greater than the width of the first electrode gate line 500, and the width of the groove on the second surface is greater than the width of the second electrode gate line 900.

[0077] The width of the groove can be controlled between 50 and 100 micrometers. Specifically, the groove width can be set to 50, 60, 80 or 100 micrometers according to the requirements. By controlling the groove width, the area of ​​the doped polysilicon layer can be further controlled, thereby controlling the absorption of incident light by the doped polysilicon layer. The groove width is greater than the electrode gate line width so that the electrode gate line can make good contact with the doped polysilicon layer inside the groove.

[0078] In one embodiment, the width of the first electrode gate line 500 is greater than the width of the second electrode gate line 900, and the width of the groove on the first surface is greater than the width of the groove on the second surface. Since sunlight shines on the side of the second surface, the second electrode gate line 900 is designed to be relatively thin, which can reduce the obstruction of incident light. Since the first surface is located on the backlight side, setting the first electrode gate line 500 on the backlight side to be relatively wide can provide a larger contact area and effectively collect carriers transported from the back of the substrate. Furthermore, the first electrode gate line 500 can also work with an antireflection layer to achieve better reflection, increase the light path length, and thus improve the light absorption efficiency. The width of the groove on the first surface is greater than the width of the groove on the second surface, which facilitates the control of the widths of the first electrode gate line 500 and the second electrode gate line 900.

[0079] In one embodiment, the first passivation antireflection layer 400 is a smooth structure, and the first tunneling oxide layer 200, the first doped polysilicon layer 300, the second tunneling oxide layer 600, the second doped polysilicon layer 700, and the second passivation antireflection layer 800 are all textured structures. The textured structure can form multiple reflections, increase the propagation path of light, and allow the incident light to be absorbed by the substrate after multiple reflections on the surface, thereby improving light utilization. Since the passivation layer includes silicon nitride, setting the first passivation antireflection layer 400 as a smooth surface can provide a more uniform reflection effect.

[0080] Secondly, this application also provides a method for preparing a solar cell, see below. Figure 3 ,include:

[0081] Step S110: Provide a substrate 100, the substrate 100 having a first surface and a second surface disposed opposite to each other; the substrate 100 may be N-type single crystal silicon or P-type single crystal silicon; the thickness of the substrate 100 may be 120 to 150 micrometers.

[0082] Step S120: A groove is formed in the first surface of the substrate 100; the groove can be formed by laser etching, with a laser wavelength of 355 nanometers, a power of 5 watts, a pulse frequency of 1 kHz to 40 kHz, and a scanning speed of 30 nanometers per second to 100 millimeters per second. Before forming the groove, the substrate 100 needs to be cleaned to remove surface contaminants, organic matter, and metallic impurities to ensure the cleanliness of the groove.

[0083] Step S130: A first tunneling oxide layer 200 is formed in the groove of the first surface. The first tunneling oxide layer 200 can be prepared by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced atomic layer deposition (PEALD). By setting the first tunneling oxide layer 200, selective transport of charge carriers can be achieved.

[0084] Step S140: A first polycrystalline silicon layer is formed on the side of the first surface away from the first tunneling oxide layer 200, and the first polycrystalline silicon layer outside the groove is removed. The first polycrystalline silicon layer can be deposited, specifically by plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition. The polycrystalline silicon layer can generate a gettering effect, absorbing impurities in the substrate 100. Depositing a polycrystalline silicon layer on the first surface and removing the polycrystalline silicon layer outside the groove can reduce impurities inside the finally formed solar cell.

[0085] Step S150: Doping is performed on the first polysilicon layer within the groove to form a first doped polysilicon layer 300; the doping type of the first doped polysilicon layer 300 is the same as the doping type of the substrate 100; when the substrate 100 is N-type single-crystal silicon, phosphorus doping is performed on the first polysilicon layer. By forming a first tunneling oxide layer 200 and a first doped polysilicon layer 300 within the groove, parasitic absorption of incident light can be reduced, and carrier transport channels can be increased.

[0086] Preparing the first polycrystalline silicon layer allows for impurity absorption before removing some of the polycrystalline silicon, thus removing some impurities and retaining only the polycrystalline silicon within the groove. Subsequently, doping the polycrystalline silicon within the groove can increase the doping concentration while reducing parasitic absorption.

[0087] Step S160: A first passivation antireflection layer 400 is formed on the side of the first surface away from the substrate; the first passivation antireflection layer 400 includes a first passivation layer 410 and a first antireflection layer 420; the first passivation layer 410 is formed by physical vapor deposition (ALD), and the first antireflection layer 420 is formed by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced atomic layer deposition (PEALD); the first passivation layer 410 reduces surface traps by bonding with dangling bonds on the semiconductor surface, thereby reducing non-equilibrium recombination of charge carriers and improving minority carrier lifetime and quantum efficiency; the first antireflection layer 420 helps to reduce light reflection and improve light absorption.

[0088] Step S170: A first electrode gate line 500 is formed in the groove, passing through the first passivation antireflection layer 400 and contacting the first doped polysilicon layer 300; the first electrode gate line 500 can be set by screen printing.

[0089] By preparing solar cells through the above steps, we can obtain solar cells with fewer impurities, less parasitic absorption, and higher photoelectric conversion efficiency.

[0090] In one embodiment, see [reference] Figure 4 In addition to steps S110-S170, the solar cell fabrication method also includes:

[0091] Step S210: A groove is formed in the second surface of the substrate 100; the groove is created by laser etching.

[0092] Step S220: A second tunneling oxide layer 600 is formed in the groove of the second surface; it can be prepared by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced atomic layer deposition (PEALD).

[0093] Step S230: A second polysilicon layer is formed on the side of the second surface away from the second tunneling oxide layer 600, and the second polysilicon layer outside the groove is removed; this can be done by deposition, specifically by plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition, etc.

[0094] Step S240: Doping is performed on the second polysilicon layer within the groove to form a second doped polysilicon layer 700; the doping type of the second doped polysilicon layer 700 is different from the doping type of the substrate 100; when the substrate 100 is N-type single crystal silicon, boron doping is performed on the second polysilicon layer.

[0095] Step S250: A second passivation antireflection layer 800 is formed on the side of the second surface away from the substrate; the second passivation antireflection layer 800 includes a second passivation layer 810 and a second antireflection layer 820; the second passivation layer 810 is formed by physical vapor deposition (ALD), and the second antireflection layer 820 is formed by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced atomic layer deposition (PEALD).

[0096] Step S260: A second electrode gate line 900 is formed in the groove, passing through the second passivation antireflection layer 800 and contacting the second doped polysilicon layer 700. The second electrode gate line 900 is formed by screen printing.

[0097] The above preparation method can form a tunneling oxide layer and a doped polycrystalline silicon layer in the grooves on both sides of the solar cell, thereby reducing the parasitic absorption effect on both sides and improving the cell performance.

[0098] In one embodiment, the grooves on the second surface and the grooves on the first surface are disposed opposite to each other in the thickness direction of the substrate 100; this arrangement ensures that the first electrode gate line 500 and the second electrode gate line 900 are disposed opposite to each other in the thickness direction of the substrate 100, which can reduce current loss during transmission.

[0099] In one embodiment, the depth of the groove is 5-8 micrometers; the thickness of the substrate 100 is greater than 100 micrometers. The groove depth is much smaller than the thickness of the substrate 100. Setting the groove depth to 5-8 micrometers will hardly affect the structure of the substrate 100, while also controlling the parasitic absorption effect of the doped polycrystalline silicon layer.

[0100] In one embodiment, the height of the electrode grid line is greater than the depth of the groove, which ensures that the electrode grid line is led out from the groove.

[0101] In one embodiment, the width of the groove on the first surface is greater than the width of the first electrode grid line, and the width of the groove on the second surface is greater than the width of the second electrode grid line.

[0102] The width of the groove can be controlled between 50 and 100 micrometers. By controlling the width of the groove, the area of ​​the polycrystalline silicon layer inside the groove can be further controlled, thereby controlling the parasitic absorption effect of the polycrystalline silicon layer.

[0103] In one embodiment, the width of the first electrode grid line 500 is greater than the width of the second electrode grid line 900; the width of the groove on the first surface is greater than the width of the groove on the second surface; by controlling the groove width, the width of the electrode grid line can be controlled, thereby improving the photoelectric conversion efficiency.

[0104] In one embodiment, after forming the groove and before forming the polysilicon layer, the method further includes:

[0105] The first and second surfaces, as well as the groove, are subjected to a texturing process to form a texturing structure; the inside of the groove is also texturing to remove various defects caused by the grooving.

[0106] In one embodiment, before forming the first passivation antireflection layer 400, after forming the first doped polysilicon layer 300, the textured structure of the first surface is alkaline polished to form a smooth structure; that is, in this way, the first passivation antireflection layer 400 is a smooth structure; the rest are textured structures. Specifically, the first tunneling oxide layer 200, the first doped polysilicon layer 300, the second tunneling oxide layer 600, the second doped polysilicon layer 700, and the second passivation antireflection layer 800 are all textured structures. The textured structure can increase the light propagation path and improve light utilization; the smooth structure can provide a more uniform reflection effect.

[0107] Thirdly, this application also provides a photovoltaic module, including at least one battery string. The battery string includes at least two solar cells as described above or solar cells prepared by the solar cell preparation method described above. The solar cells can be connected together by string welding, thereby collecting the electrical energy generated by each individual solar cell for subsequent transmission. Of course, the solar cells can be arranged at intervals or stacked together in a shingled manner.

[0108] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0109] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0110] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A solar cell, characterized in that, include: A substrate having a first surface and a second surface disposed opposite to each other; the first surface is provided with a groove. A first tunneling oxide layer is disposed in a groove on the first surface; A first doped polysilicon layer is disposed in the groove on the side of the first tunneling oxide layer away from the first surface; the doping type of the first doped polysilicon layer is the same as the doping type of the substrate. The first passivation anti-reflection layer is disposed on the side of the first surface away from the first doped polysilicon layer; The first electrode gate line is disposed in the groove of the first surface, and the first electrode gate line passes through the first passivation antireflection layer and contacts the first doped polysilicon layer.

2. The solar cell according to claim 1, characterized in that, Also includes: A groove provided on the second surface; The second tunneling oxide layer is disposed in the groove of the second surface; A second doped polysilicon layer is disposed within the groove on the side of the second tunneling oxide layer away from the second surface; the doping type of the second doped polysilicon layer is different from the doping type of the substrate. The second passivation anti-reflection layer is disposed on the side of the second surface away from the second doped polysilicon layer; The second electrode gate line is disposed in the groove of the second surface, and the second electrode gate line passes through the second passivation antireflection layer and contacts the second doped polysilicon layer.

3. The solar cell according to claim 2, characterized in that, The groove on the second surface is disposed opposite to the groove on the first surface in the thickness direction of the substrate.

4. The solar cell according to any one of claims 1 to 3, characterized in that, The depth of the groove is 5 to 8 micrometers.

5. The solar cell according to claim 4, characterized in that, The height of the electrode grid line is greater than the depth of the groove.

6. The solar cell according to claim 2 or 3, characterized in that, The width of the groove on the first surface is greater than the width of the first electrode grid line, and the width of the groove on the second surface is greater than the width of the second electrode grid line.

7. The solar cell according to claim 6, characterized in that, The width of the first electrode grid line is greater than the width of the second electrode grid line, and the width of the groove on the first surface is greater than the width of the groove on the second surface.

8. The solar cell according to claim 2, characterized in that, The first passivation antireflection layer has a smooth surface structure, while the first tunneling oxide layer, the first doped polysilicon layer, the second tunneling oxide layer, the second doped polysilicon layer, and the second passivation antireflection layer all have a textured surface structure.

9. A method for preparing a solar cell, characterized in that, include: A substrate is provided, the substrate having a first surface and a second surface disposed opposite to each other; A groove is formed within the first surface of the substrate; A first tunneling oxide layer is formed within the groove on the first surface; A first polysilicon layer is formed on the side of the first surface away from the first tunneling oxide layer, and the first polysilicon layer outside the groove is removed; The first polysilicon layer within the groove is doped to form a first doped polysilicon layer; the doping type of the first doped polysilicon layer is the same as the doping type of the substrate. A first passivation and antireflection layer is formed on the side of the first surface away from the substrate; A first electrode gate line is formed within the groove, passing through the first passivation antireflection layer and contacting the first doped polysilicon layer.

10. The method for preparing a solar cell according to claim 9, characterized in that, A groove is formed within the second surface of the substrate; A second tunneling oxide layer is formed within the groove on the second surface; A second polysilicon layer is formed on the side of the second surface away from the second tunneling oxide layer, and the second polysilicon layer outside the groove is removed; The second polysilicon layer within the groove is doped to form a second doped polysilicon layer; the doping type of the second doped polysilicon layer is different from the doping type of the substrate. A second passivation antireflection layer is formed on the side of the second surface away from the substrate; A second electrode gate line is formed within the groove, passing through the second passivation antireflection layer and contacting the second doped polysilicon layer.

11. The method for preparing a solar cell according to claim 10, characterized in that, After the groove is formed and before the polysilicon layer is formed, the process also includes: The first surface, the second surface, and the groove are subjected to a flocking process to form a flocked structure.

12. The method for preparing a solar cell according to claim 11, characterized in that, Before forming the first passivation antireflection layer, after forming the first doped polysilicon layer, the textured structure of the first surface is alkaline polished to form a smooth structure.

13. A photovoltaic module, characterized in that, It includes at least one battery string, the battery string comprising at least two solar cells as described in any one of claims 1-8 or solar cells prepared using the preparation method as described in any one of claims 9-12.

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