Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes: a stacked structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers alternately stacked; a channel plug at least partially passing through the stacked structure over a cell region; and a plurality of support structures at least partially passing through the stacked structure over a contact region.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] A non-volatile memory element is a memory element that can maintain stored data even when power is cut off. In recent years, as the improvement in the integration degree of two-dimensional non-volatile memory elements in which memory cells are formed in a single layer on a substrate has reached its limit, three-dimensional non-volatile memory elements in which memory cells are vertically stacked on a substrate have been proposed.

[0003] The three-dimensional non-volatile memory element includes an interlayer insulating layer and a gate electrode that are alternately stacked, and a channel layer that penetrates the interlayer insulating layer and the gate electrode, and memory cells are stacked along the channel layer. In order to improve the reliability of the non-volatile memory element having such a three-dimensional structure, various structures and manufacturing methods have been developed. Summary of the Invention

[0004] According to an embodiment of the present disclosure, a semiconductor device may include: a stacked structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers that are alternately stacked; a channel plug that at least partially penetrates the stacked structure on a cell region; and a plurality of support structures that at least partially penetrate the stacked structure on a contact region. The plurality of support structures include a linear first support structure and a hole-shaped second support structure.

[0005] According to an embodiment of the present disclosure, a semiconductor device may include: a stacked structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers that are alternately stacked; a first channel plug and a second channel plug formed on a cell region by vertically penetrating a part or all of the stacked structure; a plurality of support structures formed on a contact region by vertically penetrating a part or all of the stacked structure; and an auxiliary support structure disposed on the stacked structure and the plurality of support structures.

[0006] According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include: forming a stacked structure in which a plurality of interlayer insulating layers and a plurality of sacrificial layers are alternately stacked on a substrate including a cell region and a contact region; etching the stacked structure on the contact region to together form a first hole for forming a contact plug passing through a part or all of the stacked structure, a trench for forming a first support structure, and a second hole for forming a second support structure; forming the contact plug by filling the first hole with a barrier layer and a conductive layer; filling the trench and the second hole with the barrier layer and the conductive layer; forming an auxiliary support structure on the stacked structure, the auxiliary support structure including a plurality of opening regions overlapping with a part of the trench and a part of the second hole; removing the barrier layer and the conductive layer for the gate remaining in the trench and the second hole exposed through the plurality of opening regions of the auxiliary support structure; and forming the first support structure and the second support structure by filling the trench and the second hole with an insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A and Figure 1B is a block diagram schematically showing a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 is a cross-sectional view schematically showing a peripheral circuit structure.

[0009] Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D are a plan view and a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7 、 Figure 8A 、 Figure 8B 、 Figure 9 、 Figure 10A 、 Figure 10B and Figure 11 are a cross-sectional view and a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 12A and Figure 12B is a plan view showing a semiconductor device according to another embodiment of the present disclosure.

[0012] Figure 13 is an illustration showing a memory block included in a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 14 is a block diagram showing the configuration of a storage system according to an embodiment of the present disclosure.

[0014] Figure 15 is a block diagram showing the configuration of a storage system according to an embodiment of the present disclosure.

[0015] Figure 16 is a block diagram showing the configuration of a computing system according to an embodiment of the present disclosure.

[0016] Figure 17 is a block diagram showing the computing system according to an embodiment of the present disclosure. Detailed Embodiments

[0017] The specific structural or functional descriptions of the embodiments according to the concepts disclosed in this specification or this application are only shown to describe the embodiments according to the concepts of the present disclosure. The embodiments according to the concepts of the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0018] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0019] Embodiments of the present disclosure provide a semiconductor device having a stable structure and improved characteristics, and a method of manufacturing the same.

[0020] According to the present technology, a semiconductor device having a stable structure can be manufactured, and thus the characteristics of the semiconductor device can be improved.

[0021] Figure 1A and Figure 1B is a block diagram schematically showing a semiconductor device according to an embodiment of the present disclosure.

[0022] Referring to Figure 1A and Figure 1B , each of the semiconductor devices according to the embodiments of the present disclosure may include a peripheral circuit structure PC and a cell array CAR disposed on a substrate SUB.

[0023] The substrate SUB may be a single crystal semiconductor layer. For example, the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin layer formed by a selective epitaxial growth method.

[0024] The cell array CAR may include a plurality of memory blocks. Each of the memory blocks may include a plurality of cell strings. Each of the cell strings is electrically connected to a bit line, a source line, a word line, and a select line. Each of the cell strings may include memory cells and select transistors connected in series. Each of the select lines is used as a gate electrode of its corresponding select transistor, and each of the word lines is used as a gate electrode of its corresponding memory cell.

[0025] The peripheral circuit structure PC may include NMOS transistors, PMOS transistors, resistors, and capacitors electrically connected to the cell array CAR. The NMOS transistors, PMOS transistors, resistors, and capacitors may be used as elements for configuring a row decoder, a column decoder, a page buffer, and a control circuit.

[0026] As Figure 1A shown, the peripheral circuit structure PC may be disposed on a partial area of the substrate SUB that does not overlap with the cell array CAR.

[0027] Alternatively, as Figure 1B shown, the peripheral circuit structure PC may be disposed between the cell array CAR and the substrate SUB. In this case, since the peripheral circuit structure PC overlaps with the cell array CAR, the area of the substrate SUB occupied by the cell array CAR and the peripheral circuit structure PC can be reduced.

[0028] Figure 2 is a cross-sectional view schematically showing the peripheral circuit structure.

[0029] Figure 2 The peripheral circuit structure PC shown may be included in Figure 1A the peripheral circuit structure shown, or may be included in Figure 1B the peripheral circuit structure shown.

[0030] Referring to Figure 2 , the peripheral circuit structure PC may include a peripheral gate electrode PEG, a peripheral gate insulating layer PGI, a junction Jn, a peripheral circuit line PCL, and a peripheral contact plug PCP. The peripheral circuit structure PC may be covered with a peripheral circuit insulating layer PIL formed on the substrate SUB.

[0031] Each of the peripheral gate electrodes PEG may be used as a gate electrode of the NMOS transistors and PMOS transistors of the peripheral circuit structure PC. The peripheral gate insulating layer PGI is disposed between each of the peripheral gate electrodes PEG and the substrate SUB.

[0032] Jn is a region defined by implanting n-type or p-type impurities into the active region of a substrate SUB. The junction Jn is disposed on both sides of each of the peripheral gate electrodes PEG and serves as a source junction or a drain junction. The active region of the substrate SUB may be separated by a separation layer ISO formed in the substrate SUB. The separation layer ISO is formed of an insulating material.

[0033] The peripheral circuit lines PCL can be electrically connected to transistors, resistors, and capacitors of the circuits constituting the peripheral circuit structure PC through the peripheral contact plugs PCP.

[0034] The peripheral circuit insulating layer PIL may include insulating layers stacked in multiple layers.

[0035] Figures 3A to 3D are a plan view and a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0036] Referring to Figure 3A , of the semiconductor device Figure 1A and Figure 1B , the cell array CAR may include a cell region Cell and a contact region CT. A plurality of channel plugs CP1 and CP2 may be regularly arranged on the cell region Cell. In addition, a linear first vertical structure VS1 disposed between the plurality of channel plugs CP1 and CP2 may be arranged in the central portion of the cell region Cell, and a second vertical structure VS2 may be disposed at both ends of the cell region Cell. A plurality of channel plugs CP1 and CP2 may be arranged between the second vertical structures VS2. Each of the plurality of channel plugs CP1 and CP2 may include a channel layer 112 and a storage layer 111 surrounding the channel layer 112. The first vertical structure VS1 and the second vertical structure VS2 may be insulating layers and may be formed of, for example, an oxide layer.

[0037] A plurality of contact plugs CT1 and CT2 may be regularly arranged on the contact region CT. In addition, at least one support structure 119 and the second vertical structure VS2 may be arranged in the space between the plurality of contact plugs CT1 and CT2 on the contact region CT. The support structure 119 may be formed of the same material as the first vertical structure VS1. The support structure 119 may be an insulating layer and may be formed of, for example, an oxide layer. The support structure 119 may include a linear first support structure 119A and a second support structure 119B and a hole-shaped third support structure 119C. The width X1 of the first support structure 119A may be wider than the width X2 of the second support structure 119B. That is, the support structure 119 may include a linear support structure and a hole-shaped support structure having different widths. The linear first support structure 119A, the second support structure 119B, and the hole-shaped third support structure 119C are arranged parallel to the second vertical structure VS2 and do not intersect and overlap with each other.

[0038] Referring to Figure 3B , cross-section A-A’ is the cross-section of the cell region, while cross-section B-B’ is the cross-section of the contact region CT.

[0039] On the cell region Cell of the semiconductor device, a source line layer 101, a stacked structure SS stacked on the source line layer 101, channel plugs CP1 and CP2 that contact the source line layer 101 by passing through a part or all of the stacked structure SS in the vertical direction, a second vertical structure VS2 vertically disposed at both ends of the stacked structure SS and contacting the source line layer 101, and a first vertical structure VS1 disposed by passing through the part of the stacked structure SS disposed between the channel plugs CP1 and CP2 may be included and configured.

[0040] The source line layer 101 may be a doped semiconductor layer. For example, the source line layer 101 may be a semiconductor layer doped with n-type impurities. As an implementation, the source line layer 101 may be formed by implanting impurities into Figure 1A the surface of the substrate SUB shown, or may be formed by depositing at least one doped silicon layer on the substrate SUB. As an implementation, the source line layer 101 may be formed by forming an insulating layer on Figure 1B the peripheral circuit structure PC shown, and then depositing at least one doped silicon layer on the insulating layer.

[0041] The stacked structure SS may include a structure in which a plurality of gate conductive layers 123 and interlayer insulating layers 105 are alternately stacked, and in some embodiments, has a structure in which the interlayer insulating layer 105 is disposed at the lowermost and uppermost ends of the stacked structure SS. At least one gate conductive layer disposed at the lowermost end of the gate conductive layer 123 may be a source select line SSL, at least one gate conductive layer disposed at the uppermost end of the gate conductive layer 123 is a drain select line DSL, and the remaining gate conductive layers may be word lines WL.

[0042] The channel plugs CP1 and CP2 may be vertically arranged by passing through the stacked structure SS, and may include a channel layer 112 and a storage layer 111 surrounding the channel layer 112.

[0043] The first vertical structure VS1 may be disposed to pass through at least one gate conductive layer 123 serving as the drain select line DSL, and is disposed at the uppermost part of the stacked structure SS disposed between the channel plugs CP1 and CP2. That is, the first vertical structure VS1 electrically separates the gate conductive layer 123 of the drain select line DSL for connecting to the first channel plug CP1 from the gate conductive layer 123 of the drain select line DSL for connecting to the second channel plug CP2.

[0044] On the contact region CT of a semiconductor device, there may be included and configured a source line layer 101, a contact pad layer 103, an insulating layer 102 disposed between the source line layer 101 and the contact pad layer 103, a stacked structure SS stacked on the insulating layer 102 and the contact pad layer 103, contact plugs CT1 and CT2 that contact the contact pad layer 103 by vertically passing through a part or all of the stacked structure SS, a second vertical structure VS2 that contacts the source line layer 101 by vertically passing through a part or all of the stacked structure SS, and at least one support structure 119.

[0045] The source line layer 101 and the contact pad layer 103 are formed on the same layer, and the source line layer 101 and the contact pad layer 103 are electrically separated from each other by the insulating layer 102 disposed between the source line layer 101 and the contact pad layer 103. The insulating layer 102 may be formed of an insulating layer such as an oxide layer. The contact pad layer 103 may be electrically connected to Figure 1A and Figure 1B the peripheral circuit structure PC shown in

[0046] Each of the contact plugs CT1 and CT2 may include a conductive layer 116 for the contact plug and a barrier layer 115 surrounding the conductive layer 116 for the contact plug. The barrier layer 115 may also be formed on the sidewalls of the support structure 119.

[0047] Figure 3C and Figure 3D are a plan view and a cross-sectional view of the semiconductor device, showing a structure in which an auxiliary support structure 117 is disposed on the stacked structure SS in the contact region CT of the semiconductor device shown in the above Figure 3A and Figure 3B shown.

[0048] Referring to Figure 3C and Figure 3D, the auxiliary support structure 117 may be disposed on the stacked structure SS and the support structure 119 formed in the contact region CT of the semiconductor device. The auxiliary support structure 117 may have a plurality of opening regions OP, and the plurality of opening regions OP may overlap with the support structure 119. For example, the plurality of opening regions OP may be arranged to overlap with the first support structure 119A, the second support structure 119B, and the third support structure 119C. The plurality of opening regions OP may have a dash structure. The auxiliary support structure 117 may be formed as a mesh structure. The plurality of opening regions OP may be arranged in a matrix structure. At least one of the plurality of opening regions OP may be arranged to overlap with the first support structure 119A. At least one of the plurality of opening regions OP may be arranged to overlap with the second support structure 119B. At least one of the plurality of third support structures 119C may overlap with one opening region OP. That is, at least one of the third support structures 119C may overlap with one opening region OP.

[0049] The auxiliary support structure 117 may include the same material as the mask pattern of the first vertical structure VS1 used to form Figure 3A and Figure 3B on the cell region of the semiconductor device.

[0050] In the semiconductor device according to the embodiment of the present disclosure described above, the support structure 119 for supporting the stacked structure SS may be disposed in the contact region CT, and the support structure 119 is formed of a linear and hole-shaped structure. Therefore, in some embodiments, the problem that the support structure 119 expands and tilts in one direction due to heat generated during subsequent processes can be suppressed. In addition, in some embodiments, by forming the auxiliary support structure 117 on the support structure 119, the expansion of the upper part of the support structure 119 can be suppressed.

[0051] Figures 4 to 11 are a cross-sectional view and a plan view showing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0052] Referring to Figure 4 , a source line layer 101 is formed on the cell region Cell and the contact region CT of the semiconductor device. The source line layer 101 may be a doped semiconductor layer, for example, a semiconductor layer doped with an n-type impurity. As an embodiment, the source line layer 101 may be formed by implanting impurities into Figure 1A the surface of the substrate SUB shown, or by depositing at least one doped silicon layer on the substrate SUB. As an embodiment, the source line layer 101 may be formed by Figure 1BAn insulating layer is formed on the peripheral circuit structure PC shown, and then at least one doped silicon layer is deposited on the insulating layer to form it.

[0053] After that, a part of the source line layer 101 formed on the contact region CT is etched to form a region where the contact pad layer is to be formed. The region where the contact pad layer is to be formed can be defined as being electrically connected to Figure 1A and Figure 1B the region of the peripheral circuit structure PC shown in. Thereafter, the contact pad layer 103 is formed in the portion where the source line layer 101 is etched and removed. The insulating layer 102 is formed between the contact pad layer 103 and the source line layer 101 to electrically isolate the contact pad layer 103 and the source line layer 101. The insulating layer 102 can be formed of an insulating layer such as an oxide layer.

[0054] Thereafter, a stack 105 and 107 in which the first material layer 105 and the second material layer 107 are alternately stacked is formed on the cell region Cell and the contact region CT. The second material layer 107 can be used to form conductive layers such as word lines, selection lines, and pads, and the first material layer 105 can be used to insulate the stacked conductive layers from each other.

[0055] The first material layer 105 is formed of a material having a high etching selectivity with respect to the second material layer 107. For example, the first material layer 105 can include an insulating material such as an oxide, and the second material layer 107 can include a sacrificial material such as a nitride.

[0056] Referring to Figure 5A and Figure 5B , a first mask pattern 109 is formed on the stack 105 and 107 of the cell region Cell and the contact region CT. The first mask pattern 109 is formed such that a first opening OP1 is provided in the portion of the cell region Cell where the channel plug is to be formed.

[0057] Referring to Figure 6A and Figure 6B , the stack 105 and 107 is etched by using the first mask pattern as a barrier to form a first hole H1 passing through a part or all of the stack 105 and 107. At this time, the contact region CT is not etched due to the first mask pattern, so no hole is formed.

[0058] Thereafter, the first mask pattern is removed.

[0059] Thereafter, channel plugs CP1 and CP2 including a channel layer 112 and a storage layer surrounding the channel layer 112 are formed in the first hole H1. For example, the storage layer 111 is formed on the sidewall of the first hole H1. The storage layer 111 may include at least one of a charge blocking layer, a data storage layer, and a tunnel insulating layer, and the data storage layer may include a floating gate such as silicon, a charge trapping material such as nitride, a phase change material, nanodots, etc. Thereafter, the channel plugs CP1 and CP2 are formed by completely filling the first hole H1 with the channel layer 112 up to the central region. As another embodiment, the channel layer 112 may be formed in such a structure that the central region of the first hole H1 is open, and a gap filling layer may be formed in the open central region.

[0060] Thereafter, a second mask pattern 113 is formed on the channel plugs CP1 and CP2 and the stacks 105 and 107 in the cell region Cell and on the stacks 105 and 107 in the contact region CT. The second mask pattern 113 is formed such that the portions where contact plugs are to be formed and the portions where support structures are to be formed in the contact region CT have second openings OP21 to OP24. For example, the second opening OP21 corresponding to the contact plug may have a hole shape, while the second openings OP22 and OP23 corresponding to the support structures may have a linear shape. The widths X1 and X2 of the linear second openings OP22 and OP23 may be different from each other.

[0061] In an embodiment of the present disclosure, an example is described in which the support structure is formed in a linear shape and the quadrilateral structure is in a hole shape, but the present disclosure is not limited thereto, and the support structure may be formed in various patterns such as circular, elliptical, rhombic, etc.

[0062] Refer to Figure 7 , using the second mask pattern as a barrier to etch the stacks 105 and 107 on the contact region CT to form second holes H2 and third holes H3 passing through part or all of the stacks 105 and 107 and linear first trenches T1 and second trenches T2. At this time, the cell region Cell is prevented or reduced from being etched by the second mask pattern. The widths of the first trench T1 and the second trench T2 may be different from each other.

[0063] Thereafter, the second mask pattern may be removed.

[0064] Thereafter, a barrier layer 115 is formed on the sidewall of the second hole H2, and contact plugs CT1 and CT2 connected to the contact pad layer 103 are formed by filling the inside of the second hole H2 with the conductive layer 116 of the contact plug. At this time, the barrier layer 115 and the conductive layer 116 for the contact plug may be formed inside the third hole H3 and the linear first trenches T1 and second trenches T2.

[0065] Refer toFigure 8A and Figure 8B ,an auxiliary support structure 117 is formed on the channel plugs CP1 and CP2 of the cell region Cell and the laminates 105 and 107, and on the contact plugs CT1 and CT2 of the contact region CT and the laminates 105 and 107. The auxiliary support structure 117 can be used as a third mask pattern for forming the first vertical structure. The auxiliary support structure 117 is formed to have a third opening OP3, in which a partial region between the region between the channel plugs CP1 and CP2 in the cell region Cell and the region where the support structure for the contact region CT to be formed is located is opened. That is, the auxiliary support structure 117 is formed to have a third opening OP3, through which the region where the first vertical structure between the channel plugs CP1 and CP2 to be formed and a part of the region where the support structure to be formed is located are opened. The third opening OP3 of the region where the first vertical structure is to be formed can be formed linearly, as Figure 8B shown.

[0066] The auxiliary support structure 117 formed on the contact region CT can be formed as a mesh structure. That is, the third openings OP3 on the contact region CT can be arranged in a matrix structure. Each of the third openings OP3 on the contact region CT can have a baffle structure. Each of the third openings OP3 on the contact region CT can be arranged to overlap with the first trench T1 where the first support structure is to be formed, the second trench T2 where the second support structure is to be formed, and the third hole H3 where the third support structure is to be formed. At least one of the third openings OP3 on the contact region CT can be arranged to overlap with a part or all of the first trench T1, at least one of the third openings OP3 on the contact region CT can be arranged to overlap with a part or all of the second trench T2, and at least one of the third openings OP3 on the contact region CT can be arranged to overlap with a part or all of at least one of the plurality of third holes H3. That is, at least one third hole H3 can overlap with one third opening OP3.

[0067] Referring to Figure 9 ,using the auxiliary support structure 117 as a mask pattern, a part of the upper ends of the laminates 105 and 107 between the channel plugs CP1 and CP2 in the cell region Cell is etched to form a first slit, and an insulating layer is filled in the first slit to form a first vertical structure VS1. The first vertical structure VS1 is formed to pass through at least one second material layer 107 provided at the uppermost end of the laminate 105 and 107 where the drain selection line is to be formed.

[0068] Thereafter, in the contact region CT, the Figure 8A and Figure 8BThe conductive layer 116 and the barrier layer 115 for contact plugs are formed in the first trench, the second trench, and the third hole exposed by the third opening OP3. Thereafter, the insulating layer is filled in the first trench, the second trench, and the third hole to form the first support structure 119A, the second support structure 119B, and the third support structure 119C.

[0069] The process of removing the conductive layer 116 and the barrier layer 115 for contact plugs described above can be performed after the etching process of forming the first slit in the cell region Cell using the auxiliary support structure 117 as a mask pattern. In addition, the process of filling the insulating layer in the first trench, the second trench, and the third hole can be performed together with the process of filling the insulating layer in the first slit. The first vertical structure VS1 and the support structure 119 can be formed of an oxide layer.

[0070] Refer to Figure 10A and Figure 10B , a fourth mask pattern 121 is formed on the auxiliary support structure 117 on the cell region Cell and the contact region CT. The fourth mask pattern 121 is formed to have a fourth opening OP4, through which the channel plugs CP1 and CP2 are opened at both ends of the set region in the cell region Cell and in the region between the support structures 119 in the contact region CT. That is, the fourth mask pattern 121 is formed to have a fourth opening OP4, through which the regions where the second vertical structure is to be formed at both ends of the set regions of the channel plugs CP1 and CP2 and the regions where the second vertical structure is to be formed between the support structures 119 are opened. The fourth opening OP4 of the region where the second vertical structure is to be formed can be formed in a linear shape as shown in Figure 10B and can be set to be parallel or perpendicular to each other. In addition, according to an embodiment, the fourth opening OP4 can be formed in various shapes.

[0071] Thereafter, the auxiliary support structure 117 and the laminates 105 and 107 formed at both ends of the set regions of the channel plugs CP1 and CP2 in the cell region Cell and the auxiliary support structure 117 and the laminates 105 and 107 formed between the support structures 119 in the contact region CT are etched to form the second slit SI2. The second slit SI2 etches Figure 9 the laminates 105 and 107 to expose the sidewalls of Figure 9 the first material layer 105 and the second material layer 107. Figure 9 the laminates 105 and 107 to expose Figure 9 the sidewalls of the first material layer 105 and the second material layer 107.

[0072] Thereafter, the second material layer 107 is removed, the sidewall of which is exposed through the second slit SI2, and after the removal of Figure 9 the second material layer 107, Figure 9A gate conductive layer 123 is formed in the space of the second material layer 107. At least one gate conductive layer 123 disposed at the lowermost end of the gate conductive layer 123 is a lower select line (source select line), at least one gate conductive layer 123 disposed at the uppermost end and separated by the first vertical structure VS1 is an upper select line (drain select line), and the remaining gate conductive layers 123 are word lines.

[0073] Referring to Figure 11 , a second vertical structure VS2 is formed by filling the second slit with an insulating layer. The second vertical structure VS2 may be formed of an oxide layer.

[0074] As described above, according to the method of manufacturing a semiconductor device according to an embodiment of the present disclosure, since the support structure 119 is formed of the same material as the first vertical structure VS1, that is, formed of an oxide layer, problems such as oxidation and expansion of the support structure 119 due to heat generated during subsequent processes can be suppressed. In addition, by forming the support structure 119 in a linear shape and a hole shape, the problem of the support structure 119 tilting in one direction can be suppressed. In addition, in some embodiments, by forming an auxiliary support structure 117 on the support structure 119, expansion of the upper part of the support structure 119 can be suppressed.

[0075] Figure 12A and Figure 12B is a plan view of a semiconductor device, showing a semiconductor device according to another embodiment of the present disclosure.

[0076] Referring to Figure 12A , a linear support structure 119D including protrusions P and a hole-shaped support structure 119C may be provided. In an embodiment, the linear support structure 119D including protrusions P may suppress the expansion of the insulating layer constituting the support structure 119D in one direction due to heat. In addition, the hole-shaped support structure 119C may be arranged in a row adjacent to the second vertical structure VS2 as shown in the figure, and may also be provided in the space between the contact plugs (that is, between the contact plugs CT1 and CT1 and between the contact plugs CT2 and CT2).

[0077] In addition, as another embodiment, the hole-shaped support structure 119C may be formed and provided in various shapes other than a quadrilateral shape, such as a circular shape, an oval shape, and a cross shape (+).

[0078] Referring to Figure 12B , the linear support structures 119D and 119E including protrusions P may be arranged adjacent to each other. At this time, the protrusions P of each of the adjacent linear support structures 119D and 119E may be arranged so as not to face each other.

[0079] Figure 13It is a diagram showing a memory block included in a semiconductor device according to an embodiment of the present disclosure.

[0080] The semiconductor device may include a plurality of memory blocks BLK1 to BLKz. The memory blocks BLK1 to BLKz may be arranged to be spaced apart from each other along the direction Y in which the bit lines BLK to BLM extend. For example, the first memory block BLK1 to the Zth memory block BLKz may be arranged to be spaced apart from each other along the second direction Y and may include a plurality of memory cells stacked along the third direction Z. At this time, the first memory block BLK1 to the Zth memory block BLKz may be spaced apart from each other using slits.

[0081] Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of channel plugs, contact plugs, and support structures, as Figure 3A and Figure 3B or Figure 12A and Figure 12B shown.

[0082] Figure 14 It is a block diagram showing the configuration of a memory system according to an embodiment of the present invention.

[0083] Referring to Figure 14 , a memory system 1000 according to an embodiment of the present disclosure includes a storage device 1200 and a controller 1100.

[0084] The storage device 1200 is used to store data information having various data types, such as text, graphics, and software code. The storage device 1200 may be the semiconductor device described with reference to Figure 1A , Figure 1B , Figure 2 , Figures 3A to 3D , Figure 12A or Figure 12B and may be manufactured according to the manufacturing method described with reference to Figures 4 to 11 . Since the structure of the storage device 1200 and the method of manufacturing the storage device 1200 are the same as those described above, a detailed description thereof will be omitted.

[0085] The controller 1100 is connected to the host and the storage device 1200 and is configured to access the storage device 1200 in response to a request from the host. For example, the controller 1100 is configured to control read, write, erase, and background operations of the storage device 1200, etc.

[0086] The controller 1100 includes a random access memory (RAM) 1110, a central processing unit (CPU) 1120, a host interface 1130, an error correction code circuit 1140, a storage interface 1150, etc.

[0087] Here, the RAM 1110 can be used as an operating memory for the CPU 1120, a cache memory between the storage device 1200 and the host, a buffer memory between the storage device 1200 and the host, etc. For reference, the RAM 1110 can be replaced with a static random access memory (SRAM), a read-only memory (ROM), etc.

[0088] The CPU 1120 is configured to control the overall operation of the controller 1100. For example, the CPU 1120 is configured to operate firmware, such as a flash translation layer (FTL) stored in the RAM 1110.

[0089] The host interface 1130 is configured to perform docking with the host. For example, the controller 1100 communicates with the host through at least one of various interface protocols, such as a Universal Serial Bus (USB) protocol, a Multimedia Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a proprietary protocol.

[0090] The ECC circuit 1140 is configured to detect and correct errors included in data read from the storage device 1200 using an error correction code (ECC).

[0091] The storage interface 1150 is configured to perform docking with the storage device 1200. For example, the storage interface 1150 includes a NAND interface or a NOR interface.

[0092] For reference, the controller 1100 may further include a buffer memory (not shown) for temporarily storing data. Here, the buffer memory can be used to temporarily store data transmitted to the outside through the host interface 1130, or temporarily store data transmitted from the storage device 1200 through the storage interface 1150. In addition, the controller 1100 may further include a ROM that stores code data for engaging with the host.

[0093] As described above, since the storage system 1000 according to an embodiment of the present disclosure includes a storage device 1200 having improved integration and improved characteristics, the integration and characteristics of the storage system 1000 can also be improved.

[0094] Figure 15 is a block diagram showing the configuration of a storage system according to an embodiment of the present disclosure. Hereinafter, descriptions that are repeated with the above description will be omitted.

[0095] Refer to Figure 15, the storage system 1000' according to an embodiment of the present disclosure includes a storage device 1200' and a controller 1100. Additionally, the controller 1100 includes a RAM 1110, a CPU 1120, a host interface 1130, an ECC circuit 1140, a storage interface 1150, etc.

[0096] The storage device 1200' may be a non-volatile memory. The storage device 1200' may be the semiconductor device described above with reference to Figure 1A , Figure 1B , Figure 2 , Figures 3A to 3D , Figure 12A or Figure 12B described, and may be manufactured according to the manufacturing method described with reference to Figures 4 to 11 described. Since the structure of the storage device 1200' and the method of manufacturing the storage device 1200' are the same as those described above, a detailed description thereof will be omitted.

[0097] Additionally, the storage device 1200' may be a multi-chip package configured by a plurality of memory chips. The plurality of memory chips are divided into a plurality of groups, and the plurality of groups are configured to communicate with the controller 1100 through the first to k-th channels CH1 to CHk. Additionally, the memory chips belonging to one group are configured to communicate with the controller 1100 through a common channel. As a reference, the storage system 1000' may be modified such that one memory chip is connected to one channel.

[0098] As described above, since the storage system 1000' according to an embodiment of the present disclosure includes a storage device 1200' having improved integration and improved characteristics, the integration and characteristics of the storage system 1000' can also be improved. Specifically, by configuring the storage device 1200' in a multi-chip package, the data storage capacity of the storage system 1000' can be increased, and the driving speed can be improved.

[0099] Figure 16 is a block diagram showing the configuration of a computing system according to an embodiment of the present disclosure. Hereinafter, descriptions that are repeated with the above description will be omitted.

[0100] Referring to Figure 16 , the computing system 2000 according to an embodiment of the present disclosure includes a storage device 2100, a CPU 2200, a RAM 2300, a user interface 2400, a power supply 2500, a system bus 2600, etc.

[0101] The storage device 2100 stores data provided through the user interface 2400, data processed by the CPU 2200, and the like. In addition, the storage device 2100 is electrically connected to the CPU 2200, the RAM 2300, the user interface 2400, the power supply 2500, etc. via the system bus 2600. For example, the storage device 2100 may be connected to the system bus 2600 through a controller (not shown) or may be directly connected to the system bus 2600. When the storage device 2100 is directly connected to the system bus 2600, the functions of the controller may be executed by the CPU 2200, the RAM 2300, etc.

[0102] Here, the storage device 2100 may be a non-volatile memory. The storage device 2100 may be the semiconductor device described above with reference to Figure 1A , Figure 1B , Figure 2 , Figures 3A to 3D , Figure 12A or Figure 12B and may be manufactured according to the manufacturing method described with reference to Figures 4 to 11 . Since the structure of the storage device 2100 and the method of manufacturing the storage device 2100 are the same as those described above, its detailed description will be omitted.

[0103] In addition, the storage device 2100 may be a multi-chip package including a plurality of memory chips as described with reference to Figure 15 .

[0104] A computing system having such a configuration may be a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3D TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, an RFID device, etc.

[0105] As described above, since the computing system 2000 according to an embodiment of the present disclosure includes the storage device 2100 having improved integration and improved characteristics, the characteristics of the computing system 2000 can also be improved.

[0106] Figure 17 is a block diagram showing a computing system according to an embodiment of the present disclosure.

[0107] Refer to Figure 17, the computing system 3000 according to an embodiment of the present disclosure includes a software layer, which includes an operating system 3200, applications 3100, a file system 3300, a conversion layer 3400, etc. Additionally, the computing system 3000 includes a hardware layer such as a storage device 3500.

[0108] The operating system 3200 is used to manage the software, hardware resources, etc. of the computing system 3000, and can control the program execution of the central processing unit. The applications 3100 can be various application programs executed on the computing system 3000, and can be utilities executed by the operating system 3200.

[0109] The file system 3300 refers to the logical structure for managing data, files, etc. existing in the computing system 3000, and organizes the files or data to be stored in the storage device 3500 according to rules. The file system 3300 can be determined according to the operating system 3200 used in the computing system 3000. For example, when the operating system 3200 is the Windows system of Microsoft Corporation, the file system 3300 can be the File Allocation Table (FAT), NT File System (NTFS), etc. Additionally, when the operating system 3200 is the Unix / Linux system, the file system 3300 can be the Extended File System (EXT), Unix File System (UFS), Journaled File System (JFS), etc.

[0110] Although the operating system 3200, applications 3100, and file system 3300 are shown as separate blocks in this drawing, the applications 3100 and file system 3300 can be included in the operating system 3200.

[0111] In response to a request from the file system 3300, the conversion layer 3400 converts the address into a form suitable for the storage device 3500. For example, the conversion layer 3400 converts the logical address generated by the file system 3300 into the physical address of the storage device 3500. Here, the mapping information between the logical address and the physical address can be stored in the address translation table. For example, the conversion layer 3400 can be a Flash Translation Layer (FTL), Universal Flash Storage Link Layer (ULL), etc.

[0112] The storage device 3500 can be a non-volatile memory. The storage device 3500 can be the semiconductor device described above with reference to Figure 1A , Figure 1B , Figure 2 , Figures 3A to 3D , Figure 12A or Figure 12B described, and can be according to the reference Figures 4 to 11It is manufactured by the described manufacturing method. Since the structure of the storage device 3500 and the method of manufacturing the storage device 3500 are the same as those described above, a detailed description thereof will be omitted.

[0113] The computing system 3000 having such a configuration can be divided into an operating system layer that executes in a higher-level area and a controller layer that executes in a lower-level area. Here, the application 3100, the operating system 3200, and the file system 3300 can be included in the operating system layer and can be driven by the operation memory of the computing system 3000. Additionally, the conversion layer 3400 can be included in the operating system layer or the controller layer.

[0114] As described above, since the computing system 3000 according to an embodiment of the present disclosure includes the storage device 3500 having improved integration and improved characteristics, the characteristics of the computing system 3000 can also be improved.

[0115] Cross-reference to related applications

[0116] This application claims priority to Korean Patent Application No. 10-2021-0077473, filed on June 15, 2021, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, the semiconductor device comprising: A stacked structure, the stacked structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers stacked alternately; A channel plug, the channel plug at least partially passing through the stacked structure on the unit region; A plurality of support structures, the plurality of support structures at least partially passing through the stacked structure on the contact region, the plurality of support structures including a linear first support structure and a hole-shaped second support structure; And An auxiliary support structure, the auxiliary support structure being formed on the stacked structure, the first support structure, and the second support structure on the contact region, Wherein, the auxiliary support structure includes a plurality of opening regions, Wherein, the plurality of opening regions are spaced apart from each other in a first direction, and Wherein, the first support structure overlaps at least two opening regions spaced apart from each other in the first direction.

2. The semiconductor device according to claim 1, wherein, The plurality of opening regions are arranged in a matrix structure.

3. The semiconductor device according to claim 1, wherein, The auxiliary support structure has a mesh structure.

4. The semiconductor device according to claim 1, the semiconductor device further comprising: A linear vertical structure, the vertical structure passing through an upper portion of the stacked structure at a central portion of the unit region.

5. The semiconductor device according to claim 4, wherein, The auxiliary support structure extends to the unit region and has an opening region overlapping with the vertical structure to expose a part of the vertical structure.

6. The semiconductor device according to claim 4, wherein, The vertical structure passes through at least one gate conductive layer among the plurality of gate conductive layers that serves as a drain select line.

7. A semiconductor device, the semiconductor device comprising: A stacked structure, the stacked structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers stacked alternately; A first channel plug and a second channel plug, the first channel plug and the second channel plug being formed on the unit region by vertically passing through a part or all of the stacked structure; A plurality of support structures, the plurality of support structures being formed on the contact region by vertically passing through a part or all of the stacked structure; And An auxiliary support structure, the auxiliary support structure being provided on the stacked structure and the plurality of support structures, Wherein, the plurality of support structures include a linear first support structure, Wherein, the auxiliary support structure includes a plurality of opening regions, the plurality of opening regions are spaced apart from each other in a first direction, and Wherein, the first support structure overlaps at least two opening regions spaced apart from each other in the first direction.

8. The semiconductor device according to claim 7, wherein, The plurality of support structures further include a hole-shaped second support structure.

9. The semiconductor device according to claim 7, wherein, The auxiliary support structure is formed as a mesh structure including the opening regions.

10. The semiconductor device according to claim 7, the semiconductor device further comprising: A linear vertical structure, the vertical structure passing through an upper portion of the stacked structure at a central portion of the unit region.

11. The semiconductor device according to claim 10, wherein, The auxiliary support structure includes an opening region exposing the vertical structure.

12. A method of manufacturing a semiconductor device, the method comprising the following steps: Forming a stacked structure, in which a plurality of interlayer insulating layers and a plurality of sacrificial layers are alternately stacked on a substrate including a unit region and a contact region; Etch the stacked structure on the contact region to together form a first hole for forming a contact plug passing through a part or all of the stacked structure, a trench for forming a first support structure, and a second hole for forming a second support structure; Form the contact plug by filling the first hole with a barrier layer and a conductive layer; Fill the trench and the second hole with the barrier layer and the conductive layer; Form an auxiliary support structure on the stacked structure, the auxiliary support structure including a plurality of opening regions overlapping a part of the trench and a part of the second hole; Remove the barrier layer and the conductive layer for the gate remaining in the trench and the second hole exposed through the plurality of opening regions of the auxiliary support structure; And Form the first support structure and the second support structure by filling the trench and the second hole with an insulating layer, wherein the plurality of opening regions are spaced apart from each other in a first direction, and wherein each of the first support structures overlaps at least two opening regions spaced apart from each other in the first direction.

13. The method according to claim 12, wherein, The step of forming the auxiliary support structure includes forming the auxiliary support structure such that the auxiliary support structure extends above the stacked structure on the cell region to expose a part of the cell region.

14. The method according to claim 13, the method further comprising, before removing the barrier layer and the conductive layer for the gate remaining in the trench and the second hole: Form a slit by partially etching the upper end of the stacked structure on the cell region exposed through the auxiliary support structure.

15. The method according to claim 14, wherein, When forming the first support structure and the second support structure, fill the slit with the insulating layer to form a vertical structure.

16. The method according to claim 12, wherein, The first support structure is formed in a linear shape, and the widths of each of the first support structures are different from each other.

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