Semiconductor equipment

Abstract

To provide a device capable of reducing gate resistance. [Solution] The semiconductor device includes first to fourth electrodes, a semiconductor layer, a first contact, and a first conductive layer. The second electrode is located above the first electrode. The semiconductor layer is provided between the first electrode and the second electrode. The semiconductor layer includes first to third semiconductor regions. Multiple third electrodes are provided side by side in a cell region. The third electrode faces the first semiconductor region via a first insulating portion. The fourth electrode includes a portion located between two adjacent third electrodes. The fourth electrode includes a first extending portion and a wide portion. The fourth electrode faces the second semiconductor region via a second insulating portion. The first contact is located above the fourth electrode and is connected to the wide portion of the fourth electrode. The first conductive layer is located above the fourth electrode and is connected to the fourth electrode by the first contact.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] In a semiconductor device including a transistor such as a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), by reducing the gate resistance of the transistor, for example, the switching speed can be improved.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a semiconductor device capable of reducing gate resistance.

Means for Solving the Problems

[0005] According to embodiments of the present invention, a semiconductor device includes a first electrode, a second electrode, a semiconductor layer, a plurality of third electrodes, a fourth electrode, a first contact, and a first conductive layer. The second electrode is located above the first electrode. The semiconductor layer is provided between the first electrode and the second electrode. The semiconductor layer includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of a first conductivity type. The second semiconductor region is provided on top of the first semiconductor region. The third semiconductor region is provided on top of the second semiconductor region and is electrically connected to the second electrode. The plurality of third electrodes are provided side by side in a cell region where the second electrode is provided. The third electrodes face the first semiconductor region via a first insulating portion. The fourth electrode includes a portion located between two adjacent third electrodes. The fourth electrode includes a first extension portion and a wide portion. The first extension portion is located in the cell region. The wide portion is located in the cell region and has a width wider than the width of the first extension. The fourth electrode faces the second semiconductor region via the second insulating portion. The first contact is located above the fourth electrode and is connected to the wide portion of the fourth electrode. The first conductive layer is located above the fourth electrode and is connected to the fourth electrode by the first contact. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a schematic plan view illustrating a semiconductor device according to an embodiment. [Figure 2] Figure 2 is a schematic diagram illustrating a semiconductor device according to an embodiment. [Figure 3] Figure 3 is a schematic diagram illustrating a semiconductor device according to an embodiment. [Figure 4] Figure 4 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. [Figure 5] Figure 5 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. [Figure 6] Figure 6 is a schematic diagram illustrating a semiconductor device according to a modified embodiment. [Figure 7]Figure 7 is a schematic diagram illustrating a semiconductor device according to a modified embodiment. [Figure 8] Figures 8(a) and 8(b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] Figures 9(a) and 9(b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] Figure 10 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] Figure 11 is a schematic diagram illustrating another semiconductor device according to the embodiment. [Figure 12] Figure 12 is a schematic diagram illustrating another semiconductor device according to the embodiment. [Figure 13] Figure 13 is a schematic cross-sectional view illustrating another semiconductor device according to the embodiment. [Figure 14] Figure 14 is a schematic cross-sectional view illustrating another semiconductor device according to the embodiment. [Modes for carrying out the invention]

[0007] The embodiments of the present invention will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. In this specification and in each figure, elements similar to those described above are denoted by the same reference numerals with respect to previously shown figures, and detailed explanations are omitted as appropriate. In the following explanation, n + , n -The notations represent the relative levels of the respective impurity concentrations. That is, a notation with a "+" indicates that the impurity concentration is relatively higher than a notation without either a "+" or a "-", and a notation with a "-" indicates that the impurity concentration is relatively lower than a notation without any notations. These notations represent the relative levels of the net impurity concentration after the impurities have compensated for each other when both p-type impurities and n-type impurities are included in each region. In the following examples, the first conductivity type is n-type and the second conductivity type is p-type. However, for each embodiment described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

[0008] FIG. 1 is a schematic plan view illustrating a semiconductor device according to an embodiment. In the description of the embodiment, the X direction, the Y direction, and the Z direction that are perpendicular to each other are used. For example, as shown in FIG. 1, when viewed from above (when viewed along the Z direction), the semiconductor device 100 according to the embodiment has a rectangular shape having sides extending in the X direction and the Y direction.

[0009] The semiconductor device 100 is, for example, a MOSFET. On the upper surface side of the semiconductor device 100, a source electrode 12, a gate pad 13, and a gate wiring 14 are provided. The source electrode 12, the gate pad 13, and the gate wiring 14 are arranged side by side, for example, in the same X-Y plane.

[0010] In the semiconductor device 100, a cell region RC in which the source electrode 12 is arranged and a peripheral region RE located around the cell region RC in the X-Y plane are set. As will be described later, the cell region RC is a region in which transistors are formed in the semiconductor layer. The source electrode 12 extends in the X-Y plane and covers the entire cell region RC. The gate pad 13 and the gate wiring 14 are not arranged in the cell region RC. The source electrode 12 is insulated from the gate pad 13 and the gate wiring 14.

[0011] The peripheral region RE is aligned with the cell region RC in the X-Y plane direction. The peripheral region RE may include, for example, the terminal region of the semiconductor device 100. The terminal region includes the outer edge in the plan view of the semiconductor layer and is the region along the outer edge. The gate wiring 14 and the gate pad 13 are disposed in the peripheral region RE and may surround, for example, the source electrode 12. The gate wiring 14 extends in the X direction or the Y direction and is electrically connected to the gate pad 13. In this example, the gate pad 13 is disposed at the rectangular corner of the semiconductor device 100. The source electrode 12 is not disposed in the peripheral region RE.

[0012] FIGS. 2 to 5 are schematic diagrams illustrating a semiconductor device according to an embodiment. FIGS. 2 to 5 show the structure within the cell region RC (region R1 shown in FIG. 1). FIGS. 2 and 3 show the planar layout. The hatching in FIG. 2 corresponds to the cross section along the line A1 - A1' shown in FIG. 4, and the hatching in FIG. 3 corresponds to the cross section along the line A2 - A2' shown in FIG. 4. FIG. 4 shows the cross section along the line A3 - A3' shown in FIGS. 2 and 3. FIG. 5 shows the cross section along the line A4 - A4' shown in FIGS. 2 and 3.

[0013] For example, as shown in FIG. 4, the semiconductor device 100 has a drain electrode 11 (first electrode), a source electrode 12 (second electrode), and a semiconductor layer 20. The semiconductor layer 20 is located between the drain electrode 11 and the source electrode 12.

[0014] In the description of the embodiment, the direction from the drain electrode 11 to the source electrode 12 is defined as the Z direction. The upper and lower surfaces of the semiconductor layer 20 (semiconductor substrate) are along the X-Y plane perpendicular to the Z direction. Also, for convenience, the direction from the drain electrode 11 to the source electrode 12 is referred to as "up", and the opposite direction is referred to as "down". These directions are based on the relative positional relationship between the drain electrode 11 and the source electrode 12 and are independent of the direction of gravity.

[0015] The semiconductor layer 20 includes a drain region 24, a drift region 21 (first semiconductor region), a base region 22 (second semiconductor region), and a source region 23 (third semiconductor region). The drain region 24 is the first conductivity type (n + This is a semiconductor region of the shape ( ). The drain region 24 is provided on the drain electrode 11 and is electrically connected to the drain electrode 11. The drift region 21 is provided above the drain region 24 and has a first conductivity type (n - This is the semiconductor region of the n-type impurity. The concentration of n-type impurity in the drift region 21 is (atoms / cm³). 3 ) is the concentration of n-type impurities in the drain region 24 (atoms / cm³). 3 It is lower than ). The base region 22 is a second conductivity type (p-type) semiconductor region located on a portion of the drift region 21. The source region 23 is provided on a part of the base region 22 and has a first conductive type (n + This is a semiconductor region of n-type impurities. The upper end of the source region 23 is located on the upper surface 20U of the semiconductor layer 20 (the surface on the source electrode 12 side). The concentration of n-type impurities in the source region 23 is (atoms / cm³). 3 ) is higher than the concentration of n-type impurities in the drift region 21. For example, the drift region 21 and the drain region 24 are provided across the cell region RC and the peripheral region RE, while the base region 22 and the source region 23 are provided in the cell region RC.

[0016] For example, as shown in Figure 4, the upper surface 20U of the semiconductor layer 20 is provided with a plurality of FP trenches TR1 (first trenches) and gate trenches TR2 (second trenches).

[0017] The FP trench TR1 extends in the Z direction from the upper surface 20U to the drift region 21. An FP insulating portion 41 (first insulating portion) and an FP electrode 31 (third electrode) are provided inside the FP trench TR1. The FP insulating portion 41 covers the inner wall (side and bottom surface) of the FP trench TR1. The FP insulating portion 41 is in contact with the drift region 21 and the base region 22.

[0018] The FP electrode 31 is a field plate. The FP electrode 31 is located inside the FP insulating portion 41 within the FP trench TR1. In other words, the FP insulating portion 41 is provided between the FP electrode 31 and the semiconductor layer 20. The lower surface and side surfaces of the FP electrode 31 are in contact with the FP insulating portion 41. The FP electrode 31 is insulated from the semiconductor layer 20 by the FP insulating portion 41. The FP electrode 31 has a portion that aligns with a part of the drift region 21 in the direction of the XY plane. That is, the FP electrode 31 faces a part of the drift region 21 via the FP insulating portion 41.

[0019] The gate trench TR2 includes a portion located between two adjacent FP trenches TR1 (the closest FP trenches TR1 to each other among multiple FP trenches TR1). In the Z direction, the gate trench TR2 extends from the upper surface 20U of the semiconductor layer 20 to the drift region 21. The gate trench TR2 is shallower than the FP trenches TR1.

[0020] A gate insulator 42 (second insulator) and a gate electrode 32 (fourth electrode) are provided inside the gate trench TR2. The gate insulator 42 covers the inner wall (side and bottom) of the gate trench TR2. The gate insulator 42 is in contact with the drift region 21, the base region 22, and the source region 23.

[0021] The gate electrode 32 is located inside the gate insulator 42 within the gate trench TR2. In other words, the gate insulator 42 is provided between the gate electrode 32 and the semiconductor layer 20. The lower and side surfaces of the gate electrode 32 are in contact with the gate insulator 42. The gate electrode 32 is insulated from the semiconductor layer 20 by the gate insulator 42. In the direction of the XY plane, the gate electrode 32 has portions that align with a part of the drift region 21, a base region 22, and a part of the source region 23. That is, the gate electrode 32 faces the drift region 21, the base region 22, and the source region 23 via the gate insulator 42. The FP electrode 31 extends to a deeper position than the gate electrode 32.

[0022] Furthermore, as shown in Figure 4, for example, an insulating layer 51 extending along the XY plane is provided on the upper surface 20U of the semiconductor layer 20. A gate conductive layer 70 (first conductive layer) and an insulating layer 52 are provided on the insulating layer 51. The gate conductive layer 70 is located between the insulating layer 51 and the insulating layer 52. The source electrode 12 is provided on the insulating layer 52.

[0023] The gate conductive layer 70 is located above the gate trench TR2 and the gate electrode 32. Within the cell region RC, a portion of the gate conductive layer 70 is located directly above the gate electrode 32. For example, as shown in Figure 5, the gate conductive layer 70 is electrically connected to the gate electrode 32 by a gate contact 37 (first contact). The gate contact 37 penetrates the insulating layer 51 and is located between the gate electrode 32 and the gate conductive layer 70. In other words, the gate contact 37 is provided within a contact hole that penetrates the insulating layer 51. The gate contact 37 is in contact with the upper surface of the gate electrode 32 and the lower surface of the gate conductive layer 70.

[0024] The sides and top surface of the gate conductive layer 70 are covered by the insulating layer 52. The gate conductive layer 70 is insulated from the source electrode 12 by the insulating layer 52.

[0025] As shown in Figure 5, a source conductive layer 35 (second conductive layer) is provided on the FP electrode 31 and the base region 22. The source conductive layer 35 electrically connects the FP electrode 31 and the source region 23. The source conductive layer 35 extends along the XY plane and is in contact with the upper surface of the FP electrode 31, the upper surface of the FP insulating portion 41, and the upper surface of the base region 22.

[0026] More specifically, the source conductive layer 35 has a central portion 35a located in the center of the source conductive layer 35 in the XY plane, and an outer portion 35b located outside the central portion 35a. The source region 23 (and part of the base region 22) is positioned between the outer portion 35b and the gate trench TR2. The outer portion 35b is in contact with the source region 23 and the base region 22. The central portion 35a covers and is in contact with the entire upper surface of the FP electrode 31. The upper end portion 41a of the FP insulating portion 41 is located between the outer portion 35b and the central portion 35a. The entire upper surface of the FP insulating portion 41 (upper end portion 41a) is covered by the source conductive layer 35.

[0027] The upper surface of the source conductive layer 35 is located higher than the upper end of the gate electrode 32. The lower surface of the source conductive layer 35 is located higher than the lower end of the gate electrode 32.

[0028] The source conductive layer 35 is formed as a separate conductive layer from the gate conductive layer 70 and the source electrode 12. For example, an insulating layer 51 is provided on top of the source conductive layer 35. In other words, the insulating layer 51 is placed between the source conductive layer 35 and the gate conductive layer 70, and the source conductive layer 35 is insulated from the gate conductive layer 70. Furthermore, the source conductive layer 35 is located below the insulating layer 51 and insulating layer 52, which are below the source electrode 12.

[0029] A source contact 36 (second contact) is provided between the source electrode 12 and the source conductive layer 35, penetrating the insulating layer 51 and the insulating layer 52. In other words, the source contact 36 is located within a contact hole that penetrates the insulating layer 51 and the insulating layer 52. The source contact 36 is in contact with the lower surface of the source electrode 12 and the center of the upper surface of the source conductive layer 35 (central portion 35a). As a result, the source contact 36 electrically connects the source electrode 12 and the source conductive layer 35.

[0030] The source contact 36 is located directly above the FP electrode 31. The source conductive layer 35 (central portion 35a) is located between the FP electrode 31 and the source contact 36, electrically connecting the FP electrode 31 and the source contact 36.

[0031] Furthermore, as shown in Figure 3, the source region 23 (and a part of the base region 22) surrounds the outer circumferential surface of the outer portion 35b of the source conductive layer 35 in the XY plane and is in contact with the outer circumferential surface of the outer portion 35b. The outer portion 35b surrounds the outer circumferential surface of the upper end portion 41a of the FP insulating portion 41 in the XY plane and is in contact with the outer circumferential surface of the upper end portion 41a. The upper end portion 41a surrounds the outer circumferential surface of the central portion 35a of the source region 23 and is in contact with the central portion 35a.

[0032] In Figure 2, the positions of the FP electrode 31, FP insulating portion 41, FP trench TR1, source conductive layer 35, and gate trench TR2 are shown by dotted lines in a plan view from above. For example, as shown in Figure 2, in the cell region RC, multiple FP trenches TR1 are arranged in the XY plane. More specifically, the multiple FP trenches TR1 are arranged in a first alignment direction D1 and a second alignment direction D2. The first alignment direction D1 is the direction that connects one FP trench TR1 to the FP trench TR1 closest to it by the shortest distance. In a plan view, the multiple FP electrodes 31 (FP trenches TR1) are located at the intersections of a grid or mesh where lines extending in the first alignment direction D1 and lines extending in the second alignment direction D2 intersect. In this example, the first alignment direction D1 is the X direction, and the second alignment direction D2 is the Y direction. Therefore, in a plan view, the multiple FP electrodes 31 are located at the vertices of a square. In this embodiment, the first array direction D1 and the second array direction D2 do not necessarily have to be orthogonal.

[0033] For example, the planar shape of the FP electrode 31 and the FP insulating part 41 is circular. The planar shape of the FP electrode 31 and the FP insulating part 41 may also be a regular polygon such as a square or a regular hexagon. Note that a regular polygon includes a regular polygon with rounded corners. An FP electrode 31 is provided in the center of each FP trench TR1. The source contact 36 is cylindrical and located in the center of the FP electrode 31.

[0034] As shown in Figure 3, in the cell region RC, the gate trench TR2 has a first extended portion 61, a second extended portion 62, and a wide portion 65. The first extension portion 61 is located between two adjacent FP trenches TR1 in the first array direction D1 and extends in a direction perpendicular to the first array direction D1. The first extension portion 61 has, for example, a constant width W61 (length in the direction perpendicular to the first array direction D1). The second extension portion 62 is located between two adjacent FP trenches TR1 in the second array direction D2 and extends in a direction perpendicular to the second array direction D2. The second extension portion 62 has, for example, a constant width W62 (length in the direction perpendicular to the second array direction D2). The width W62 may be the same as the width W61.

[0035] The wide portion 65 is aligned with the first extending portion 61 in the Y direction (a direction perpendicular to the first alignment direction D1) and is continuous with the first extending portion 61. The wide portion 65 is the portion that widens the gate trench TR2 from the first extending portion 61 or the second extending portion 62. That is, the width W65 of the wide portion 65 (length in the direction perpendicular to the first alignment direction D1) is wider than the width W61 of the first extending portion 61. The width W65 of the wide portion 65 is wider than the width W62 of the second extending portion 62. The width of the wide portion 65 in the second alignment direction D2 may be the same as the width W65 in the first alignment direction D1. The wide portion 65 and the first extending portion 61 are aligned alternately in the Y direction (a direction perpendicular to the first alignment direction D1).

[0036] The wide portion 65 connects the end of the first extending portion 61 and the end of the second extending portion 62. For example, the planar shape of the gate trench TR2 is mesh-like. In this example, the gate trench TR2 is a grid in which a portion extending in the first alignment direction D1 and a portion extending in the second alignment direction D2 intersect at the wide portion 65. That is, a wide portion 65 is located at each vertex of the square, and two first extending portions 61 and two second extending portions 62 are located on the four sides of the square. Inside the square, one FP trench TR1 is arranged, and the FP electrode 31 is located at the center of the square.

[0037] For example, the width of the wide portion 65 gradually increases in a continuous manner from the first extended portion 61 or the second extended portion 62. Therefore, the planar shape of the region enclosed by the first extended portion 61, the second extended portion 62, and the wide portion 65 is a polygon with rounded corners (a square in this example).

[0038] In a plan view, the thickness of the gate insulating portion 42 within the gate trench TR2 may be substantially constant. The gate electrode 32 includes an extending portion (first extending portion) provided within the first extending portion 61 and extending similarly to the first extending portion 61, an extending portion (second extending portion) provided within the second extending portion 62 and extending similarly to the second extending portion 62, and a portion provided within the wide portion 65. The gate electrode 32, like the gate trench TR2, is mesh-like or grid-like. The gate electrode 32 within the wide portion 65 may be a wide portion having a width wider than the gate electrode 32 within the first extending portion 61 or the second extending portion 62. By making the gate trench TR2 and the gate electrode 32 inside it mesh-like or grid-like, a large area for operation as a transistor can be secured.

[0039] Furthermore, the width of the gate trench TR2 (width W61 of the first extension portion 61, width W62 of the second extension portion 62) may be narrower than the width of the FP trench TR1 (length in the first or second arrangement direction D1 or D2). Also, the width of the gate electrode 32 within the first or second extension portion 61 may be narrower than the width of the FP electrode 31.

[0040] As shown in Figure 3, the gate contact 37 is, for example, a cylindrical shape with a circular planar shape. The gate contact 37 is located in the center of the wide section 65 of the gate trench TR2. The gate contact 37 is provided only in the wide section 65 and does not need to be provided in the first extended section 61 or the second extended section 62. The diameter of the gate contact 37 may be larger than the width W61 of the first extended section 61 or the width W62 of the second extended section 62.

[0041] As shown in Figure 2, the gate conductive layer 70 includes a plurality of first wiring sections 71. The first wiring sections 71 extend above and along the first extending section 61 of the gate trench TR2. For example, the first wiring sections 71 are located above the plurality of first extending sections 61 and the plurality of wide sections 65 and extend in the second alignment direction D2. For example, the first wiring sections 71 are connected to a plurality of gate contacts 37 located directly below the first wiring sections 71.

[0042] Furthermore, the gate conductive layer 70 includes a plurality of second wiring sections 72. The second wiring sections 72 extend along the second extending section 62 above the second extending section 62 of the gate trench TR2. That is, in this example, the gate conductive layer 70 is a grid in which the first wiring sections 71 and the second wiring sections 72 intersect each other. For example, the gate conductive layer 70 overlaps with the entire gate trench TR2 in the vertical direction. The gate contact 37 is connected to the intersection 75 of the first wiring section 71 and the second wiring section 72.

[0043] In a plan view, one FP electrode 31 is surrounded by a square formed by two adjacent first wiring sections 71 and two adjacent second wiring sections 72, with the source contact 36 positioned at the center of the square.

[0044] The first wiring section 71 and the second wiring section 72 extend from the cell region RC to the peripheral region RE, and are electrically connected to the gate wiring 14 (see Figure 1) located above the first wiring section 71 and the second wiring section 72 in the peripheral region RE.

[0045] An example of the materials used for each element of the semiconductor device 100 will be described below. Each semiconductor region of the semiconductor layer 20 contains silicon (Si), silicon carbide, gallium nitride, or gallium arsenide as the semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity. The semiconductor layer 20 is a semiconductor substrate, such as a silicon substrate. The FP electrode 31 and the gate electrode 32 include a conductive material such as polysilicon or metal. The FP insulating portion 41, the gate insulating portion 42, the insulating layer 51, and the insulating layer 52 each contain an insulating material such as silicon oxide or silicon nitride. The gate contact 37 and source contact 36 contain metals such as W (tungsten) and Ti (titanium). The drain electrode 11, source electrode 12, gate wiring 14, and gate pad 13 contain a metal such as Al (aluminum). The gate conductive layer 70 includes at least one of polysilicon, silicide, and metallic material. The source conductive layer 35 includes at least one of polysilicon, silicide, and metallic material. The silicide includes at least one selected from the group consisting of Co (cobalt), W, Ti, and Ni (nickel). As the silicide, metallic silicides such as CoSi, WSi, TiSi, and NiSi are used. The metallic material includes at least one selected from the group consisting of Ti, TiN (titanium nitride), W, Cu (copper), and Al. By using a metallic material, a conductive layer with lower resistance can be obtained. For example, the electrical resistivity of the gate conductive layer 70 or the source conductive layer 35 may be lower than the electrical resistivity of the gate electrode 32 or the FP electrode 31. By using polysilicon or silicide, the formation of the gate conductive layer 70 and the source conductive layer 35 becomes easier.

[0046] The operation of the semiconductor device 100 will be described. With a positive voltage applied to the source electrode 12 and the drain electrode 11, a positive voltage is applied to the gate pad 13. This applies a voltage to the gate electrode 32 via the gate wiring 14, gate conductive layer 70, and gate contact 37 from the gate pad 13. When a voltage greater than the threshold is applied to the gate electrode 32, an inversion layer is formed in the base region 22, and the transistor turns on. That is, an on-current flows from the drain electrode 11 to the source electrode 12 via the drift region 21, base region 22, source region 23, source conductive layer 35, and source contact 36. When the voltage at the gate pad 13 decreases and the voltage at the gate electrode 32 falls below the threshold, the transistor turns off and no on-current flows.

[0047] As described above, in the semiconductor device 100 according to this embodiment, a gate conductive layer 70 electrically connected to the gate electrode 32 is provided above the gate electrode 32 within the cell region RC. This makes it possible to reduce the gate resistance in the semiconductor device 100.

[0048] For example, in the reference example semiconductor device, a configuration is conceivable in which the gate conductive layer 70 and gate contact 37 are not provided within the cell region RC, and the gate wiring 14 and gate electrode 32 are connected in the peripheral region RE. In contrast, in the embodiment, by providing the gate conductive layer 70, for example, current flows within the cell region RC through a path in which the gate conductive layer 70 and gate electrode 32 are connected in parallel. Therefore, according to the embodiment, the gate resistance can be reduced compared to the reference example.

[0049] Furthermore, in the example, one possible method to reduce gate resistance is to improve the chip layout design and increase the number of gate traces 14. However, increasing the number of gate traces 14 reduces the effective device area for the same chip size, thus worsening area efficiency. Another possible method to reduce gate resistance is to use a metal gate, where the gate electrode is formed from a metal material. However, in the case of a metal gate, there is a risk that characteristics such as withstand voltage, leakage current, and defect density may deteriorate due to damage to the gate insulating film during the manufacturing process. In addition, the manufacturing process for metal gates can be complex.

[0050] In contrast, in this embodiment, the gate resistance can be reduced by providing a gate conductive layer 70, as described above. For example, by using polysilicon as the material for the gate electrode 32 and providing a gate conductive layer 70, the gate resistance can be reduced while avoiding performance degradation and increased complexity of the manufacturing process caused by a metal gate. However, in this embodiment, it is also possible to use a metal material for the gate electrode 32.

[0051] Furthermore, widening the gate electrode 32 reduces the gate resistance. However, widening the gate electrode 32 can increase capacitance between the gate electrode 32 and the drain electrode 11, which may increase the feedback capacitance of the transistor. For example, in a structure where the gate electrode 32 and the FP electrode 31 are provided in separate trenches, the feedback capacitance tends to increase when the gate electrode 32 is widened compared to a configuration where the gate electrode 32 and the FP electrode are provided in the same trench. In contrast, in a configuration where the gate electrode 32 and the FP electrode 31 are provided in separate trenches, providing a gate conductive layer 70 can reduce the gate resistance while suppressing the increase in feedback capacitance.

[0052] As explained with reference to Figure 4 or Figure 5, the source electrode 12 is provided on the insulating layer 52 on top of the gate conductive layer 70. By providing the gate conductive layer 70 and the source electrode 12 on separate layers in this way, the gate conductive layer 70 can be arranged to extend more widely within the cell region RC.

[0053] Furthermore, the gate contact 37 is positioned in the wide portion 65 of the gate trench TR2. This ensures that the gate contact 37 is more reliably connected to the gate electrode 32, even if misalignment occurs due to variations in the manufacturing process. For example, the width W37 (diameter) of the gate contact 37 may be wider than the width W61 of the first extension portion 61 of the gate trench TR2. A wider gate contact 37 allows for a further reduction in electrical resistance.

[0054] Furthermore, as shown in Figure 3, one wide section 65 is surrounded by four FP trenches TR1 that are closest to the wide section 65. In other words, the wide section 65 is located equidistant from each of the multiple FP electrodes 31 (or source contacts 36) surrounding it. The gate contact 37, located in the center of the wide section 65, is also located equidistant from each of the multiple FP electrodes 31 (or source contacts 36) surrounding it. That is, the gate contact 37 is positioned at the maximum distance from the FP electrodes or source contacts 36. This ensures sufficient space for the wide section 65 and the gate contact 37. This also suppresses interference between the gate contact 37 and the source contacts 36.

[0055] Furthermore, a source conductive layer 35 is provided as a separate layer from the source electrode 12, which electrically connects the source region 23 and the FP electrode 31. The source conductive layer 35 suppresses interference between the contact connecting the source region 23 and the source electrode 12 and the gate conductive layer 70. For example, as shown in Figure 4 or Figure 5, a source conductive layer 35 is provided extending laterally from the source region 23, and a source contact 36 is connected directly above the FP electrode 31. This allows the source region 23 and the source electrode 12 to be electrically connected, so the source contact 36 does not need to be provided directly above the source region 23. In this way, the source contact 36 can be positioned while avoiding the location of the gate conductive layer 70, and interference between the source contact 36 and the gate conductive layer 70 can be suppressed.

[0056] In this example, as shown in Figure 3, the planar shape of the region enclosed by the gate trench TR2 is a square with rounded corners, and the planar shape of the source conductive layer 35 is also a square with rounded corners. That is, in a plan view, the outer edge of the source conductive layer 35 extends along the gate trench TR2 (gate electrode 32) such that the distance from the gate trench TR2 (gate electrode 32) is constant. In other words, the width of the source region 23 is approximately constant. This suppresses bias in the transistor characteristics within the plane.

[0057] Furthermore, as explained with respect to Figure 2, the gate conductive layer 70 has a first wiring section 71 that is connected to a plurality of gate contacts 37 located directly beneath it. The first wiring section 71 leads the gate conductive layer 70 to the peripheral region RE, avoiding the source contact 36. Moreover, in this example, the gate conductive layer 70 is a grid in which the first wiring section 71 and the second wiring section 72 intersect along the gate trench TR2 and the gate electrode 32. This further reduces the gate resistance and allows the gate conductive layer 70 to be led in two directions.

[0058] For example, as shown in Figure 2, the width W71 of the first wiring section 71 (length in the direction perpendicular to the second arrangement direction D2) is wider than the width W61 of the first extension section 61 of the gate trench TR2 (see Figure 3). The width W71 of the first wiring section 71 may also be wider than the width W65 of the wide section 65 (see Figure 3). For example, the first wiring section 71 covers the entirety of multiple first extension sections 61. The first wiring section 71 (intersection section 75) covers the entirety of multiple wide sections 65 from above. In this way, the wider width of the gate conductive layer 70 allows for more reliable placement of the gate conductive layer 70 on the gate contact 37, even if there are variations in the manufacturing process.

[0059] For example, the gate conductive layer 70 (the end of the first wiring section 71 or the end of the second wiring section 72) may overlap with the outer portion 35b of the source conductive layer 35 and the end of the FP insulating section 41 in the vertical direction.

[0060] Figures 6 and 7 are schematic diagrams illustrating a semiconductor device according to a modified embodiment. Figure 6 shows a planar layout of a modified semiconductor device, similar to Figure 2. Figure 7 shows a planar layout of a modified semiconductor device, similar to Figure 3. This modified example is a configuration in which the second extension portion 62 of the gate trench TR2, the gate electrode 32 within the second extension portion 62, and the gate insulating portion 42 within the second extension portion 62 are omitted, as described in Figures 1 to 5.

[0061] In other words, in this example, multiple gate trenches TR2 are arranged in a stripe pattern. Multiple gate trenches TR2 are aligned in the first alignment direction D1. Each gate trench TR2 extends in the second alignment direction D2. Each gate trench TR2 has a shape in which the first extending portion 61 and the wide portion 65 are arranged alternately in the second alignment direction D2. Multiple FP electrodes 31 are arranged in the second alignment direction D2 between two adjacent gate trenches TR2.

[0062] When the gate trench TR2 and gate electrode 32 are in a stripe shape, compared to when they are in a grid shape, the capacitance between the gate electrode 32 and the drain electrode 11 can be reduced, and the feedback capacitance of the transistor can be reduced.

[0063] In this example as well, a gate contact 37 and a gate conductive layer 70 are provided. For example, as shown in Figure 6, in this example as well, the gate conductive layer 70 may be in a grid shape having a first wiring section 71 and a second wiring section. The first wiring section 71 extends along the gate trench above the gate trench TR2. The gate contact 37 is connected to the intersection 75 of the first wiring section 71 and the second wiring section 72. Similar to the semiconductor device 100 described in Figures 1 to 5, gate resistance can be suppressed. In addition, the source conductive layer 35 can suppress interference between the gate conductive layer 70 and the source contact 36.

[0064] Figures 8(a), 8(b), 9(a), 9(b), and 10 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. As shown in Figure 8(a), for example, an FP trench TR1 and a gate trench TR2 are formed on the upper surface 20U of the semiconductor layer 20 by RIE (reactive ion etching). An FP insulating portion 41 is formed in the FP trench TR1, and an FP electrode 31 is formed inside it. A gate insulating portion 42 is formed in the gate trench TR2, and a gate electrode 32 is formed inside it. Before (or after) the formation of the FP trench TR1 and gate trench TR2, a base region 22 and a source region 23 are formed by ion implantation.

[0065] Subsequently, as shown in Figure 8(b), a resist 80 is formed on the semiconductor layer 20. An opening 80e is formed in the resist 80 above the FP trench TR1 by photolithography. Then, RIE is performed using this resist 80 as a mask, and a portion of the semiconductor layer 20 and the FP insulating portion 41 is removed on the upper surface 20U side. This exposes the upper surface, base region 22 and source region 23 of the FP electrode 31. After that, the resist 80 is removed.

[0066] Subsequently, as shown in Figure 9(a), a source conductive layer 35 is formed on the upper surface of the FP electrode 31 exposed on the upper surface 20U side, the base region 22, the source region 23, and the FP insulating portion 41. For example, the source conductive layer 35 is formed by depositing a multilayer film of Ti, TiN, and W on the upper surface 20U side and planarizing it by CMP (chemical mechanical polishing). On the upper surface 20U side, the gate insulating portion 42, the source region 23, and the upper surface of the source conductive layer 35 are exposed.

[0067] Subsequently, as shown in Figure 9(b), an insulating layer 51 is formed on the gate insulating portion 42, the source region 23, and the source conductive layer 35. A gate contact 37 (not shown in Figure 9(b)) is formed directly above the gate electrode 32, penetrating the insulating layer 51 and connecting to the gate electrode 32. Then, a gate conductive layer 70 is formed on the insulating layer 51, connecting to the gate contact 37. For example, a metal film such as W is deposited on the insulating layer 51, and a portion of the metal film is removed by RIE directly above the FP electrode 31 to form the gate conductive layer 70.

[0068] Subsequently, as shown in Figure 10, an insulating layer 52 is formed on the insulating layer 51 and the gate conductive layer 70. A source contact 36 is formed directly above the FP electrode 31, penetrating the insulating layer 51 and the insulating layer 52 and connecting to the source conductive layer 35. Then, a source electrode 12 is formed on the insulating layer 52, connecting to the source contact 36.

[0069] Figures 11 to 14 are schematic diagrams illustrating another semiconductor device according to the embodiment. Although not shown in the diagram, this semiconductor device also has a cell region RC where the source electrode 12 is provided, and a peripheral region RE where the gate wiring 14 and gate pad 13 are provided, similar to Figure 1 described above.

[0070] Figures 11 to 14 show the structure within the RC cell region. Figures 11 and 12 show the planar layout. The hatching in Figure 11 corresponds to the cross-section along line A5-A5' shown in Figure 13, and the hatching in Figure 12 corresponds to the cross-section along line A6-A6' shown in Figure 13. Figure 13 shows the cross-section along line A7-A7' shown in Figures 11 and 12. Figure 14 shows the cross-section along line A8-A8' shown in Figures 11 and 12.

[0071] As shown in Figure 11, in the cell region RC, multiple FP trenches TR1 are aligned in the first and second alignment directions D1 and D2 in the XY plane. In this example, the first alignment direction D1 is the X direction. The second alignment direction D2 is inclined relative to the first alignment direction D1. For example, the angle between the first alignment direction D1 and the second alignment direction D2 is 60°. In this example, in a plan view, the multiple FP electrodes 31 are arranged to be at the vertices of a triangle (e.g., an equilateral triangle).

[0072] As shown in Figure 12, the gate trench TR2 has a first extension portion 61, a second extension portion 62, and a third extension portion 63. The first extension portion 61 extends in the Y direction (a direction perpendicular to the first alignment direction D1). The second extension portion 62 extends in a direction perpendicular to the second alignment direction D2. The third extension portion 63 extends in a direction different from that of the first extension portion 61 and the second extension portion 62.

[0073] The planar shape of the gate trench TR2 is a mesh made up of hexagons (for example, regular hexagons). That is, two first extensions 61, two second extensions 62, and two third extensions 63 are located on the six sides of the hexagon. At each vertex of the hexagon, the first extensions 61, the second extensions 62, and the third extensions 63 are connected. One FP trench TR1 is placed inside the hexagon, and the FP electrode 31 is located at the center of the hexagon. Note that the hexagon formed by the gate trench TR2 may be a hexagon with rounded corners (vertices). In this case, the vertices of the hexagon (the connection points of the three extensions) become widened sections that are wider than each extension. For example, the planar shape of the region enclosed by the first extension portion 61, the second extension portion 62, the third extension portion 63, and the wide portion is a regular hexagon with rounded corners.

[0074] The gate contact 37 is located at the connection point between the first extension portion 61, the second extension portion 62, and the third extension portion 63. In other words, the gate contact 37 is located at the vertices of the hexagon. The gate electrode 32, like the gate trench TR2, has a mesh structure in which hexagons are repeated.

[0075] As shown in Figure 11, the gate conductive layer 70 includes a first wiring section 71, a second wiring section 72, and a third wiring section 73. The first wiring section 71 extends above and along the first extending section 61 of the gate trench TR2. The second wiring section 72 extends above and along the second extending section 62 of the gate trench TR2. The third wiring section 73 extends above and along the third extending section 63 of the gate trench TR2.

[0076] In other words, the planar shape of the gate conductive layer 70 is a mesh made up of hexagons. Two first wiring sections 71, two second wiring sections 72, and two third wiring sections 73 are located on the six sides of the hexagon. The gate contact 37 is connected to the intersections of the first wiring sections 71, the second wiring sections 72, and the third wiring sections 73, i.e., the vertices of the hexagon.

[0077] In this way, multiple FP electrodes 31 may be arranged in a triangular shape. In this example as well, the gate resistance can be reduced by providing a gate conductive layer 70, similar to the semiconductor device described above. In this case, by providing a source conductive layer 35, a contact can be formed connecting the source region 23 and the source electrode 12, avoiding the position of the gate conductive layer 70.

[0078] According to this embodiment, a semiconductor device capable of reducing gate resistance can be provided.

[0079] In this specification, "electrically connected" includes not only cases where the connection is made by direct contact, but also cases where the connection is made via other conductive members or the like.

[0080] The relative levels of impurity concentrations between semiconductor regions can be confirmed, for example, using an SCM (Scanning Capacitive Microscope). Furthermore, the carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between semiconductor regions can also be confirmed using an SCM. Additionally, the impurity concentration in each semiconductor region can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry).

[0081] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of Symbols]

[0082] 11: Drain electrode 12: Source electrode 13: Gate Pad 14: Gate wiring 20: Semiconductor layer 20U:Top surface 21: Drift Region 22: Base area 23: Source area 24: Drain area 31:FP electrode 32: Grid gate 35: Source conductive layer 35a: Central part 35b:Outer part 36: Source Contact 37: Gate Contact 41: FP insulation section 41a: Upper end 42: Gate insulation 51, 52: Insulating layer 61~63: 1st~3rd extension part 65: Wide section 70: Gate conductive layer 71~73: 1st~3rd wiring section 75: Intersection 80: Resist 80e:Aperture 100: Semiconductor Devices D1: First alignment direction D2: Second alignment direction R1: area RC: Cell area RE: Peripheral Area TR1: FP Trench TR2: Gate Trench

Claims

1. First electrode and A second electrode located above the first electrode, Provided between the first electrode and the second electrode, The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on the second semiconductor region and electrically connected to the second electrode, A semiconductor layer containing, A plurality of third electrodes are provided side by side in the cell region where the second electrode is provided, and face the first semiconductor region via a first insulating portion, A fourth electrode facing the second semiconductor region via a second insulating portion, including a portion located between two adjacent third electrodes and a first extended portion located in the cell region and a wider portion located in the cell region and having a width wider than the width of the first extended portion, A first contact located above the fourth electrode and connected to the wide portion of the fourth electrode, A first conductive layer located above the fourth electrode and connected to the fourth electrode by the first contact, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the second electrode is provided on an insulating layer provided on the first conductive layer.

3. The semiconductor layer further comprises an insulating layer provided on the semiconductor layer, The semiconductor device according to claim 1, further comprising a second conductive layer that is insulated from the first conductive layer, electrically connects the third semiconductor region and the third electrode, is electrically connected to the second electrode, and is located below the insulating layer.

4. First electrode and A second electrode located above the first electrode, Provided between the first electrode and the second electrode, The first semiconductor region of the first conductivity type, A second semiconductor region of a second conductivity type is provided on the first semiconductor region, A third semiconductor region of a first conductivity type is provided on the second semiconductor region and electrically connected to the second electrode, A semiconductor layer containing, A plurality of third electrodes are provided side by side in the cell region where the second electrode is provided, and face the first semiconductor region via a first insulating portion, A fourth electrode, which includes a portion located between two adjacent third electrodes and faces the second semiconductor region via a second insulating portion, The cell region includes a portion located directly above the fourth electrode, and a first conductive layer electrically connected to the fourth electrode by a first contact, A second conductive layer is insulated from the first conductive layer, electrically connects the third semiconductor region and the third electrode, and electrically connects to the second electrode. An insulating layer located above the second conductive layer and below the second electrode, A semiconductor device equipped with the following features.

5. The semiconductor device according to claim 3 or 4, wherein the outer edge of the second conductive layer extends along the fourth electrode such that the distance from the fourth electrode is constant.

6. The semiconductor device according to claim 3 or 4, further comprising a second contact located directly above the third electrode, penetrating the insulating layer, and electrically connecting the second conductive layer and the second electrode.

7. The semiconductor device according to any one of claims 1 to 4, wherein the first contact is located equidistant from each of the plurality of third electrodes surrounding the first contact.

8. Multiple third electrodes are arranged in a first and second arrangement direction that intersect each other. The first extension is located between two of the third electrodes that are adjacent to each other in the first alignment direction. The fourth electrode further includes a second extension located between two of the third electrodes adjacent to each other in the second arrangement direction, The semiconductor device according to any one of claims 1 to 3, wherein the wide portion connects the end of the first extension portion and the end of the second extension portion.

9. The second arrangement direction is a direction perpendicular to the first arrangement direction, The semiconductor device according to claim 8, wherein the fourth electrode is arranged in a grid pattern.

10. The first conductive layer includes a first wiring portion extending in the second arrangement direction, The semiconductor device according to claim 8, wherein the first wiring portion is connected to a plurality of first contacts located directly below the first wiring portion.

11. The first conductive layer has a grid-like structure in which a first wiring portion extending along the first extending portion above the first extending portion and a second wiring portion extending along the second extending portion above the second extending portion intersect each other. The semiconductor device according to claim 9, wherein the first contact is connected to the intersection of the first wiring portion and the second wiring portion.

12. The semiconductor device according to any one of claims 1 to 3, wherein a plurality of the fourth electrodes are arranged in a stripe pattern.

13. The first conductive layer includes a first wiring portion extending along the fourth electrode above the fourth electrode, and a second wiring portion intersecting the first wiring portion. The semiconductor device according to claim 12, wherein the first contact is connected to the intersection of the first wiring portion and the second wiring portion.

14. The semiconductor device according to claim 10, wherein the width of the first wiring portion is wider than the width of the first extension portion of the fourth electrode.

15. The semiconductor device according to claim 3 or 4, wherein a portion of the first conductive layer overlaps with a portion of the second conductive layer in the vertical direction.

16. The semiconductor device according to any one of claims 1 to 4, wherein the plurality of third electrodes are located at the vertices of a square or at the vertices of an equilateral triangle.

17. The first conductive layer comprises at least one of polysilicon, silicide, and a metallic material. The silicide comprises at least one selected from the group consisting of Co, W, Ti, and Ni. The semiconductor device according to any one of claims 1 to 4, wherein the metal material comprises at least one selected from the group consisting of Ti, TiN, W, Cu, and Al.

18. The second conductive layer comprises at least one of polysilicon, silicide, and a metallic material. The silicide comprises at least one selected from the group consisting of Co, W, Ti, and Ni. The semiconductor device according to claim 3 or 4, wherein the metal material comprises at least one selected from the group consisting of Ti, TiN, W, Cu, and Al.

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