Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The semiconductor structure includes: a substrate, comprising a memory cell region, the memory cell region including sub-cell regions extending along a first direction and adjacent to each other along a second direction, the first direction being perpendicular to the second direction; the sub-cell regions including: a first channel structure and a second channel structure located on the substrate and extending along the first direction and arranged parallel to each other along the second direction; a first gate structure spanning the first channel structure and the second channel structure, the first gate structure and the first channel structure forming a pull-down transistor, and the first gate structure and the second channel structure forming a pull-up transistor; and a second gate structure discretely located on both sides of the first channel structure, the second gate structure and the first channel structure forming a transmission gate transistor, and the second gate structure and the first gate structure being arranged parallel to each other along the first direction. The read and write operating ranges of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory, and analog circuits, with memory devices accounting for a significant proportion. With the development of semiconductor technology and the wider application of memory devices, it is necessary to integrate these memory devices with other components onto a single chip to form embedded semiconductor memory devices. For example, if the memory device is embedded within a central processing unit (CPU), it is necessary to ensure compatibility between the memory device and the embedded CPU platform while maintaining the original specifications and corresponding electrical performance of the memory device.

[0003] Generally, the memory device needs to be compatible with embedded standard logic devices. Embedded semiconductor devices are typically divided into a logic region and a memory region. The logic region usually includes logic devices, while the memory region includes storage devices. With the development of storage technology, various types of semiconductor memories have emerged, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash memory. Due to its advantages such as low power consumption and fast operating speed, SRAM and its fabrication methods have received increasing attention.

[0004] However, the performance of SRAM devices still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to improving the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate including a memory cell region, the memory cell region including sub-cell regions extending along a first direction and adjacent to each other along a second direction, the first direction being perpendicular to the second direction; the sub-cell regions including: a first channel structure and a second channel structure located on the substrate and extending along the first direction and arranged parallel to each other along the second direction; a first gate structure spanning the first channel structure and the second channel structure, the first gate structure and the first channel structure forming a pull-down transistor, the first gate structure and the second channel structure forming a pull-up transistor; and a second gate structure disposed on both sides of the first channel structure, the second gate structure and the first channel structure forming a transmission gate transistor, and the second gate structure and the first gate structure being arranged parallel to each other along the first direction.

[0007] Optionally, the semiconductor structure further includes: a first source / drain doped layer located in the first channel structure on both sides of the first gate structure and on both sides of the second gate structure; a second source / drain doped layer located in the second channel structure on both sides of the first gate structure; and the first source / drain doped layer of the pull-down transistor is electrically connected to the second source / drain doped layer of the pull-up transistor.

[0008] Optionally, the semiconductor structure further includes: a shared plug located on top of the first source / drain doped layer between the first gate structure and the second gate structure, and extending along the second direction on top of the second source / drain doped layer on the same side as the first gate structure; a source / drain plug located on top of the second source / drain doped layer on the other side of the first gate structure, and on top of the remaining first source / drain doped layer; and a gate plug located on top of the first gate structure, wherein the first gate structure is electrically connected to the gate plug.

[0009] Optionally, the gate plug is also located on top of the shared plug of the adjacent sub-cell region, and the gate plug is electrically connected to the shared plug of the adjacent sub-cell region.

[0010] Optionally, the source / drain plug located on top of the second source / drain doped layer on the other side of the first gate structure is used to access VDD; the source / drain plug located on top of the first source / drain doped layer on the other side of the first gate structure is used to access VSS.

[0011] Optionally, the semiconductor structure further includes: a first word line located on top of the second gate structure on one side of the first channel structure, and the first word line is electrically connected to the second gate structure; and a second word line located on top of the second gate structure on the other side of the first channel structure, and the second word line is electrically connected to the second gate structure.

[0012] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a memory cell region, the memory cell region including sub-cell regions extending along a first direction and adjacent along a second direction, the first direction being perpendicular to the second direction; forming a first channel structure and a second channel structure extending along the first direction and arranged parallel to each other along the second direction on the substrate in the sub-cell regions; forming a first gate structure spanning the first channel structure and the second channel structure, the first gate structure and the first channel structure constituting a pull-down transistor, the first gate structure and the second channel structure constituting a pull-up transistor; forming a second gate structure discrete on both sides of the first channel structure, the second gate structure and the first channel structure constituting a transmission gate transistor, and the second gate structure and the first gate structure being arranged parallel to each other along the first direction.

[0013] Optionally, after forming the first gate structure and the second gate structure, the forming method further includes: forming a first source / drain doped layer in the first channel structure on both sides of the first gate structure and on both sides of the second gate structure; forming a second source / drain doped layer in the second channel structure on both sides of the first gate structure; and electrically connecting the first source / drain doped layer of the pull-down transistor to the second source / drain doped layer of the pull-up transistor.

[0014] Optionally, the steps of forming the first gate structure and the second gate structure include: forming a first dielectric layer covering the first channel structure and the second channel structure on the top of the substrate of the sub-cell region; forming a first opening in the first dielectric layer that exposes a portion of the top and sidewalls of the first channel structure and the second channel structure; forming a second opening in the first dielectric layer that exposes a portion of the top and sidewalls of the first channel structure; the first opening and the second opening extending along a second direction and arranged parallel to a first direction; forming a gate material layer in the first opening and the second opening; performing a planarization process on the gate material layer located in the second opening, so that the top of the remaining gate material layer in the second opening is flush with the top of the first channel structure; using the gate material layer located in the first opening as the first gate structure; and using the remaining gate material layer located in the second opening as the second gate structure.

[0015] Optionally, after forming the first source / drain doped layer and the second source / drain doped layer, the method for forming the semiconductor structure further includes: forming a shared plug on the top of the first source / drain doped layer located between the first gate structure and the second gate structure, and on the top of the second source / drain doped layer extending along the second direction and located on the same side of the first gate structure; forming a source / drain plug on the top of the second source / drain doped layer located on the other side of the first gate structure, and on the top of the remaining first source / drain doped layer; forming a gate plug on the top of the first gate structure, and the first gate structure is electrically connected to the gate plug.

[0016] Optionally, in the step of forming the gate plug, the gate plug is also located on top of the shared plug of the adjacent sub-cell region, and the gate plug is electrically connected to the shared plug of the adjacent sub-cell region.

[0017] Optionally, in the step of forming the source / drain plug, the source / drain plug formed on top of the second source / drain doped layer on the other side of the first gate structure is used to access VDD; the source / drain plug formed on top of the first source / drain doped layer on the other side of the first gate structure is used to access VSS.

[0018] Optionally, after forming the second gate structures discrete on both sides of the first channel structure, the method for forming the semiconductor structure further includes: forming a first word line on the top of the second gate structure on one side of the first channel structure, and electrically connecting the first word line to the second gate structure; forming a second word line on the top of the second gate structure on the other side of the first channel structure, and electrically connecting the second word line to the second gate structure.

[0019] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0020] The semiconductor structure provided in this embodiment of the invention includes a second gate structure disposed on both sides of a first channel structure. The second gate structure and the first channel structure constitute a transmission gate transistor, and the second gate structure and the first gate structure are arranged parallel to each other along a first direction. By disposing of the second gate structure on both sides of the first channel structure, voltage signals can be applied to the second gate structures on both sides of the first channel structure individually or simultaneously. This allows the current of the transmission gate transistor to be reduced or increased, that is, the read and write operating ranges of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0021] Figures 1 to 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0022] Figures 3 to 9 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0023] The performance of current semiconductor structures needs improvement. Specifically, the read operating range of SRAM devices is determined by the beta ratio (I0). pd / I pg It is determined that the write operating range of an SRAM device is determined by the gamma ratio (Ipg / Ipu). However, when the SRAM device is in operation, the Ipg value remains constant, which means that the read and write operating ranges of the SRAM device cannot be expanded or reduced.

[0024] To address the technical problem, embodiments of the present invention provide a semiconductor structure, comprising: a substrate, including a memory cell region, the memory cell region including sub-cell regions extending along a first direction and adjacent to each other along a second direction, the first direction being perpendicular to the second direction, the sub-cell regions including: a first channel structure and a second channel structure located on the substrate and extending along the first direction and arranged parallel to each other along the second direction; a first gate structure spanning the first channel structure and the second channel structure, the first gate structure and the first channel structure forming a pull-down transistor, the first gate structure and the second channel structure forming a pull-up transistor; and a second gate structure disposed on both sides of the first channel structure, the second gate structure and the first channel structure forming a transmission gate transistor, and the second gate structure and the first gate structure being arranged parallel to each other along the first direction.

[0025] In the semiconductor structure provided by this embodiment of the invention, a second gate structure is disposed on both sides of a first channel structure. The second gate structure and the first channel structure constitute a transmission gate transistor, and the second gate structure and the first gate structure are arranged parallel to each other along a first direction. By disposing of the second gate structure on both sides of the first channel structure, voltage signals can be applied to the second gate structures on both sides of the first channel structure individually or simultaneously. This allows the current of the transmission gate transistor to be reduced or increased, that is, the read and write operating ranges of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.

[0026] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Figures 1 to 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 1 This is a top view of the semiconductor structure. Figure 2 yes Figure 1 A cross-sectional view along the BB direction.

[0028] The semiconductor structure includes: a substrate 201, including a memory cell region 200A, the memory cell region 200A including a region along a first direction (e.g., ...). Figure 1 Extending along the X direction (as shown in the middle) and along the second direction (as shown in the middle X direction) Figure 1(As shown in the Y direction) Adjacent sub-cell regions 200B, with the first direction perpendicular to the second direction, the sub-cell region 200B includes: a first channel structure 202 and a second channel structure 203 located on the substrate 201 and extending along the first direction and arranged parallel to the second direction; a first gate structure 210 spanning the first channel structure 202 and the second channel structure 203, the first gate structure 210 and the first channel structure 202 forming a pull-down transistor, the first gate structure 210 and the second channel structure 203 forming a pull-up transistor; and a second gate structure 212 disposed on both sides of the first channel structure 202, the second gate structure 212 and the first channel structure 202 forming a transmission gate transistor, and the second gate structure 212 and the first gate structure 210 arranged parallel to each other along the first direction.

[0029] It should be noted that by setting the second gate structures 212 discretely on both sides of the first channel structure 202, voltage signals can be applied to the second gate structures 212 on both sides of the first channel structure 202 individually or simultaneously. This allows the current of the transmission gate transistor to be reduced or increased, that is, the read and write operating ranges of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.

[0030] Substrate 201 provides a process platform for setting up semiconductor structures.

[0031] In this embodiment, the substrate 201 includes a substrate.

[0032] The substrate material is silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0033] In this embodiment, the semiconductor structure is an SRAM device, which includes multiple memory cell regions 200A.

[0034] Specifically, in an SRAM device, multiple memory cell regions 200A are arranged in a matrix along a first direction and a second direction.

[0035] In this embodiment, the storage cell area 200A includes a sub-cell area 200B that extends along a first direction and is adjacent along a second direction, wherein the first direction is perpendicular to the second direction.

[0036] Specifically, each sub-unit region 200B includes a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region.

[0037] Specifically, the transmission gate transistor region is used to form transmission gate transistors, the pull-down transistor region is used to form pull-down transistors, and the pull-up transistor region is used to form pull-up transistors. The transmission gate transistors and pull-down transistors are both N-type transistors, while the pull-up transistors are P-type transistors.

[0038] The first channel structure 202 is used to provide a conductive channel for pull-down transistors and transmission gate transistors, and the second channel structure 203 is used to provide a conductive channel for pull-up transistors.

[0039] In this embodiment, both the first channel structure 202 and the second channel structure 203 are made of silicon. In other embodiments, the materials of the first channel structure 202 and the second channel structure 203 may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the first channel structure 202 may also be different from the material of the substrate.

[0040] It should be noted that the first gate structure 210 is used to control the opening and closing of the conductive channels of the pull-down transistor and the pull-up transistor, and the second gate structure 212 is used to control the opening and closing of the conductive channel of the transmission gate transistor.

[0041] The first gate structure 210 spans the first channel structure 202 and the second channel structure 203, meaning that the first gate structure 210 covers the top and sidewalls of the fin.

[0042] It should also be noted that by setting the second gate structures 212 discretely on both sides of the first channel structure 202, voltage signals can be applied to the second gate structures 212 on both sides of the first channel structure 202 individually or simultaneously. This allows the current of the transmission gate transistor to be reduced or increased, that is, the read and write operating ranges of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.

[0043] Specifically, the read operating range of an SRAM device is determined by the beta ratio (I0). pd / I pg The write operating range of an SRAM device is determined by the gamma ratio (Igamma). pg / I pu It is determined that by controlling the increase or decrease of the current of the transmission gate transistor, the beta ratio and gamma ratio of the SRAM device can be increased or decreased, thereby reducing or increasing the read and write operating ranges of the SRAM device.

[0044] In this embodiment, both the first gate structure 210 and the second gate structure 212 are metal gate structures. The first gate structure 210 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, and the second gate structure 212 also includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0045] The gate dielectric layer is used for the electrically isolated gate electrode layer and the first channel structure 202, and for the electrically isolated gate electrode layer and the second channel structure 203.

[0046] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0047] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Here, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0048] It should be noted that the gate dielectric layer may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the first channel structure 202, and between the high-k gate dielectric layer and the second channel structure 203. Specifically, the material of the gate oxide layer may be silicon oxide.

[0049] In this embodiment, the gate electrode layer is made of one or more of the following materials: TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0050] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0051] In other embodiments, depending on process requirements, the first gate structure and the second gate structure may also be polysilicon gate structures.

[0052] It should be noted that, as an example, the transmission gate transistor and the pull-down transistor share the same first channel structure 202 to meet the operating requirements of the SRAM device.

[0053] As an example, the pull-down transistor and the pull-up transistor share the first gate structure 210 to meet the operating requirements of the SRAM device.

[0054] In this embodiment, the semiconductor structure further includes a first source / drain doped layer (not shown), located in the first channel structure 202 on both sides of the first gate structure 210 and on both sides of the second gate structure 212.

[0055] The first source and drain doped layer is used as the source and drain regions of a pull-down transistor, and as the source and drain regions of a transmission gate transistor.

[0056] The doping type of the first source / drain doped layer is the same as the channel conductivity type of the corresponding transistor.

[0057] Since both the transmission gate transistor and the pull-down transistor are N-type transistors, the doping type of the first source / drain doping layer is N-type.

[0058] It should be noted that, as an example, in the formation process of the first channel structure 202, the first channel structure 202 has doped ions, and the doping type is the same as that of the first source / drain doped layer.

[0059] If the first channel structure 202 has doped ions and the doping type is the same as that of the first source / drain doped layer, then both the transmission gate transistor and the pull-down transistor are junctionless field-effect transistors (JLTs), which helps to simplify the formation process and steps of SRAM devices.

[0060] In this embodiment, the semiconductor structure further includes a second source / drain doped layer (not shown), located in the second channel structure 203 on both sides of the first gate structure 210.

[0061] The second source / drain doped layer is used as the source and drain regions of the pull-up transistor.

[0062] The doping type of the second source / drain doped layer is the same as the channel conductivity type of the corresponding transistor.

[0063] Since the pull-up transistor is a P-type transistor, the doping type of the second source / drain doping layer is also P-type.

[0064] It should be noted that, as an example, in the formation process of the second channel structure 203, the second channel structure 203 has doped ions, and the doping type is the same as that of the second source / drain doped layer.

[0065] If the second channel structure 203 has doped ions and the doping type is the same as that of the second source / drain doped layer, then the pull-up transistor adopts a junctionless field effect transistor (JLT), which is beneficial to simplify the formation process and steps of SRAM devices.

[0066] In other words, after forming the first channel structure 202 and the second channel structure 203 with doped ions, there is no need to perform source and drain doping. Instead, the first channel structure 202 on both sides of the first gate structure 210 and the second gate structure 212 can be used as the first source and drain doping layer, and the second channel structure 203 on both sides of the first gate structure 210 can be used as the second source and drain doping layer to form a junctionless field-effect transistor, which greatly reduces the difficulty of forming semiconductor structures.

[0067] In this embodiment, the second source / drain doped layer of the pull-up transistor is electrically connected to the first source / drain doped layer of the pull-down transistor.

[0068] Specifically, in each sub-cell region 200B, the drain region of the pull-up transistor is connected to the drain region of the pull-down transistor. The pull-up transistor and the pull-down transistor share the first gate structure 210. In two adjacent sub-cell regions 200B, the pull-up transistor and the pull-down transistor respectively constitute the first CMOS transistor and the second CMOS transistor. The input terminal of the first CMOS transistor is connected to the output terminal of the second CMOS transistor, and the output terminal of the first CMOS transistor is connected to the input terminal of the second CMOS transistor.

[0069] In this embodiment, the semiconductor structure further includes a shared plug 228, which is located on top of the first source / drain doped layer between the first gate structure 210 and the second gate structure 212, and extends along the second direction to be located on top of the second source / drain doped layer on the same side as the first gate structure 210.

[0070] It should be noted that the shared plug 228 enables the first source-drain doped layer between the first gate structure 210 and the second gate structure 212 to be electrically connected to the second source-drain doped layer extending along the second direction and located on the same side of the first gate structure 210, thereby realizing that in each sub-cell region 200B, the drain region of the pull-up transistor is electrically connected to the drain region of the pull-down transistor.

[0071] In this embodiment, the shared plug 228 is made of tungsten. In other embodiments, the shared plug may also be made of cobalt or ruthenium.

[0072] In this embodiment, the semiconductor structure further includes: source / drain plugs 226, located on top of the second source / drain doped layer on the other side of the first gate structure 210, and on top of the remaining first source / drain doped layer.

[0073] Source-drain plugs 226 are used to bring out the electrical properties of the first and second source-drain doped layers, thereby enabling the source regions of pull-up transistors to be connected to the power supply voltage in each sub-cell region 200B, the source regions of pull-down transistors to be connected to the power supply voltage, and the source region of the transmission gate transistor to be connected to the bit line BL.

[0074] In this embodiment, the source / drain plug 226 on the top of the second source / drain doped layer on the other side of the first gate structure 210 is used to connect to VDD.

[0075] Specifically, VDD represents the connected positive operating voltage.

[0076] In this embodiment, the source / drain plug 226 on the top of the first source / drain doped layer on the other side of the first gate structure 210 is used to connect to the VSS.

[0077] Specifically, VSS represents the negative operating voltage.

[0078] In this embodiment, the source / drain plug 226 is made of tungsten. In other embodiments, the source / drain plug may also be made of cobalt or ruthenium.

[0079] In this embodiment, the semiconductor structure further includes a gate plug 230, located on top of the first gate structure 210, and the first gate structure 210 is electrically connected to the gate plug 230.

[0080] The gate plug 230 is used to bring out the electrical properties of the first gate structure 210, thereby enabling control of the conductive channels of the first channel structure 202 and the second channel structure 203.

[0081] In this embodiment, the gate plug 230 is also located on top of the shared plug 228 of the adjacent sub-cell region 200B, and the gate plug 230 is electrically connected to the shared plug 228 of the adjacent sub-cell region 200B.

[0082] It should be noted that in two adjacent sub-cell regions 200B, the pull-up transistor and the pull-down transistor respectively constitute the first CMOS transistor and the second CMOS transistor. The gate plug 230 is electrically connected to the shared plug 228 of the adjacent sub-cell region 200B, thereby connecting the input terminal of the first CMOS transistor to the output terminal of the second CMOS transistor, and connecting the output terminal of the first CMOS transistor to the input terminal of the second CMOS transistor.

[0083] In this embodiment, the semiconductor structure further includes: a first word line 261, located on top of the second gate structure 212 on one side of the first channel structure 202, and electrically connected to the second gate structure 212; and a second word line 260, located on top of the second gate structure 212 on the other side of the first channel structure 202, and electrically connected to the second gate structure 212.

[0084] It should be noted that the first word line 261 and the second word line 260 are used to control the read and write operations of the SRAM device.

[0085] It should also be noted that by providing a first word line 261 and a second word line 260 on both sides of the first channel structure 202, voltage signals can be applied to the first word line 261 and the second word line 260 respectively, or simultaneously, so that the current of the transmission gate transistor can be reduced or increased, that is, the read operating range and write operating range of the semiconductor structure can be reduced or increased, thereby improving the performance of the SRAM device.

[0086] In this embodiment, the materials of the first word line 261 and the second word line 260 both include one or more of TiN, Cu and W.

[0087] Figures 3 to 9 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure fabrication method of the present invention.

[0088] refer to Figure 3 A substrate 101 is provided, the substrate 101 includes a storage cell region 100A, the storage cell region 100A including a region along a first direction (e.g., ...). Figure 3 Extending along the X direction (as shown in the middle) and along the second direction (as shown in the middle X direction) Figure 3 (As shown in the Y direction) The adjacent sub-unit region 100B, the first direction is perpendicular to the second direction.

[0089] Substrate 101 provides a process platform for the formation of semiconductor structures.

[0090] In this embodiment, the substrate 101 includes a substrate.

[0091] The substrate material is silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0092] In this embodiment, the semiconductor structure is an SRAM device, which includes multiple memory cell regions 100A.

[0093] Specifically, in an SRAM device, multiple memory cell regions 100A are arranged in a matrix along a first direction and a second direction.

[0094] In this embodiment, the storage cell area 100A includes a sub-cell area 100B that extends along a first direction and is adjacent along a second direction, wherein the first direction is perpendicular to the second direction.

[0095] Specifically, each sub-unit region 100B includes a transmission gate transistor region, a pull-down transistor region, and a pull-up transistor region.

[0096] Specifically, the transmission gate transistor region is used to form transmission gate transistors, the pull-down transistor region is used to form pull-down transistors, and the pull-up transistor region is used to form pull-up transistors. The transmission gate transistors and pull-down transistors are both N-type transistors, while the pull-up transistors are P-type transistors.

[0097] refer to Figure 4 In the sub-unit region 100B, a first channel structure 102 and a second channel structure 103 extending in a first direction and arranged in parallel in a second direction are formed on the substrate 101.

[0098] Specifically, the first channel structure 102 is used to provide a conductive channel for the pull-down transistor and the transmission gate transistor, and the second channel structure 103 is used to provide a conductive channel for the pull-up transistor.

[0099] In this embodiment, both the first channel structure 102 and the second channel structure 103 are made of silicon. In other embodiments, the materials of the first channel structure 102 and the second channel structure 103 may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the first channel structure 102 may also be different from the material of the substrate.

[0100] In this embodiment, the steps of forming the first channel structure 102 and the second channel structure 103 include: forming a channel material layer (not shown) on a substrate 101; forming a first mask layer (not shown) and a second mask layer (not shown) on top of the channel material layer, wherein the first mask layer and the second mask layer both extend along a first direction and are arranged in parallel at intervals along a second direction; using the first mask layer and the second mask layer as masks, performing patterning processing on the channel material layer to form the first channel structure 102 and the second channel structure 103 extending along the first direction and arranged in parallel along the second direction on the substrate 101.

[0101] In this embodiment, the process for patterning the channel material layer includes a dry etching process.

[0102] refer to Figure 5 and Figure 6 ,in, Figure 5 It is a top view. Figure 6 yes Figure 5 A cross-sectional view along the AA direction shows a first gate structure 110 spanning the first channel structure 102 and the second channel structure 103. The first gate structure 110 and the first channel structure 102 constitute a pull-down transistor, and the first gate structure 110 and the second channel structure 103 constitute a pull-up transistor. A second gate structure 112 is formed on both sides of the first channel structure 102. The second gate structure 112 and the first channel structure 102 constitute a transmission gate transistor, and the second gate structure 112 and the first gate structure 110 are arranged parallel to each other along the first direction.

[0103] It should be noted that the first gate structure 110 is used to control the opening and closing of the conductive channels of the pull-down transistor and the pull-up transistor, and the second gate structure 112 is used to control the opening and closing of the conductive channel of the transmission gate transistor.

[0104] It should also be noted that by setting the second gate structures 112 discretely on both sides of the first channel structure 102, voltage signals can be applied to the second gate structures 112 on both sides of the first channel structure 102 individually or simultaneously. This allows the current of the transmission gate transistor to be reduced or increased, that is, the read and write operating ranges of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.

[0105] Specifically, the read operating range of an SRAM device is determined by the beta ratio (I0). pd / I pg The write operating range of an SRAM device is determined by the gamma ratio (Igamma). pg / I pu It is determined that by controlling the increase or decrease of the current of the transmission gate transistor, the beta ratio and gamma ratio of the SRAM device can be increased or decreased, thereby reducing or increasing the read and write operating ranges of the SRAM device.

[0106] In this embodiment, the steps of forming the first gate structure 110 and the second gate structure 112 include: forming a first dielectric layer (not shown) covering the first channel structure 102 and the second channel structure 103 on the top of the substrate 101 of the sub-cell region 100B; forming a first opening (not shown) in the first dielectric layer that exposes the top and sidewalls of the first channel structure 102 and the second channel structure 103; forming a second opening (not shown) in the first dielectric layer that exposes the top and sidewalls of the first channel structure 102; the first opening and the second opening extending along a second direction and arranged parallel to each other along a first direction; forming a gate material layer (not shown) in the first opening and the second opening; performing planarization on the gate material layer located in the second opening, so that the top of the remaining gate material layer in the second opening is flush with the top of the first channel structure 102; using the gate material layer located in the first opening as the first gate structure 110; and using the remaining gate material layer located in the second opening as the second gate structure 112.

[0107] The first opening provides a spatial location for forming the first gate structure 110.

[0108] In this embodiment, the process for forming the first opening includes an anisotropic dry etching process.

[0109] Specifically, the anisotropic dry etching process has the characteristics of anisotropic etching, with a longitudinal etching rate greater than the transverse etching rate, resulting in better pattern transfer accuracy. This improves the morphological quality of the first opening sidewall. Furthermore, in the anisotropic dry etching process, the etching selectivity between the first dielectric layer and the first channel structure 102 can be utilized to remove the first dielectric layer and reduce the probability of damage to the first channel structure 102.

[0110] The second opening provides space for forming the first gate structure 110.

[0111] In this embodiment, the process for forming the second opening includes an anisotropic dry etching process.

[0112] As an example, the process of forming a gate material layer in the first opening and the second opening includes atomic layer deposition or chemical vapor deposition.

[0113] It should be noted that by planarizing the gate material layer located in the second opening, the top of the remaining gate material layer in the second opening can be made flush with the top of the first channel structure 102, so that gate material layers are separated on both sides of the first channel structure 102, and the gate material layers separated on both sides of the first channel structure 102 are used as the second gate structure 112, thereby achieving the purpose of applying voltage signals to the second gate structure 112 on both sides of the first channel structure 102 respectively, or applying voltage signals to the second gate structure 112 on both sides of the first channel structure 102 simultaneously.

[0114] It should also be noted that the first gate structure 110 and the second gate structure 112 are formed in the same step, reducing process steps and lowering process costs. In other embodiments, the first gate structure 110 and the second gate structure 112 may also be formed in different steps.

[0115] In this embodiment, both the first gate structure 110 and the second gate structure 112 are metal gate structures. The first gate structure 110 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, and the second gate structure 112 also includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0116] The gate dielectric layer is used for the electrically isolated gate electrode layer and the first channel structure 102, and for the electrically isolated gate electrode layer and the second channel structure 103.

[0117] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0118] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Here, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0119] It should be noted that the gate dielectric layer may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the first channel structure 102, and between the high-k gate dielectric layer and the second channel structure 103. Specifically, the material of the gate oxide layer may be silicon oxide.

[0120] In this embodiment, the gate electrode layer is made of one or more of the following materials: TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0121] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0122] In other embodiments, depending on process requirements, the first gate structure 110 and the second gate structure 112 may also be polysilicon gate structures.

[0123] It should be noted that, as an example, the transmission gate transistor and the pull-down transistor share the same first channel structure 102 to meet the operating requirements of the SRAM device.

[0124] As an example, the pull-down transistor and the pull-up transistor share the first gate structure 110 to meet the operating requirements of the SRAM device.

[0125] refer to Figure 7 After forming the first gate structure 110 and the second gate structure 112, the forming method further includes: forming a first source / drain doped layer 120 in the first channel structure 102 on both sides of the first gate structure 110 and the second gate structure 112, forming a second source / drain doped layer 122 in the second channel structure 103 on both sides of the first gate structure 110, and electrically connecting the first source / drain doped layer 120 of the pull-down transistor with the second source / drain doped layer 122 of the pull-up transistor.

[0126] The first source-drain doped layer 120 is used as the source and drain regions of a pull-down transistor, and as the source and drain regions of a transmission gate transistor.

[0127] The doping type of the first source / drain doped layer 120 is the same as the channel conductivity type of the corresponding transistor.

[0128] Since both the transmission gate transistor and the pull-down transistor are N-type transistors, the first source / drain doping layer 120 is doped with N-type material.

[0129] It should be noted that, as an example, in the step of forming the first channel structure 102, the first channel structure 102 has doped ions and the same doping type as the first source / drain doped layer 120.

[0130] If the first channel structure 102 has doped ions and the doping type is the same as that of the first source / drain doped layer 120, then both the transmission gate transistor and the pull-down transistor are junctionless field-effect transistors (JLTs), which helps to simplify the formation process and steps of SRAM devices.

[0131] The second source / drain doped layer 122 is used as the source and drain regions of the pull-up transistor.

[0132] The doping type of the second source / drain doped layer 122 is the same as the channel conductivity type of the corresponding transistor.

[0133] Since the pull-up transistor is a P-type transistor, the doping type of the second source / drain doped layer 122 is P-type.

[0134] It should be noted that, as an example, in the step of forming the second channel structure 103, the second channel structure 103 has doped ions and the same doping type as the second source / drain doped layer 122.

[0135] If the second channel structure 103 has doped ions and the doping type is the same as that of the second source / drain doped layer 122, then the pull-up transistor adopts a junctionless field effect transistor (JLT), which is beneficial to simplify the formation process and steps of SRAM devices.

[0136] In other words, after forming the first channel structure 102 and the second channel structure 103 with doped ions, there is no need to perform source and drain doping. Instead, the first channel structure 102 on both sides of the first gate structure 110 and the second gate structure 112 can be used as the first source and drain doping layer 120, and the second channel structure 103 on both sides of the first gate structure 110 can be used as the second source and drain doping layer 122 to form a junctionless field-effect transistor, which greatly reduces the difficulty of forming semiconductor structures.

[0137] In this embodiment, the second source / drain doped layer 122 of the pull-up transistor is electrically connected to the first source / drain doped layer 120 of the pull-down transistor.

[0138] Specifically, in each sub-cell region 100B, the drain region of the pull-up transistor is connected to the drain region of the pull-down transistor. The pull-up transistor and the pull-down transistor share the first gate structure 110. In two adjacent sub-cell regions 100B, the pull-up transistor and the pull-down transistor respectively constitute the first CMOS transistor and the second CMOS transistor. The input terminal of the first CMOS transistor is connected to the output terminal of the second CMOS transistor, and the output terminal of the first CMOS transistor is connected to the input terminal of the second CMOS transistor.

[0139] refer to Figure 8 After forming the first source / drain doped layer 120 and the second source / drain doped layer 122, and before forming the shared plug, gate plug and source / drain plug, the method further includes forming a second dielectric layer (not shown) on top of the first dielectric layer, the first gate structure 110 and the second gate structure 112.

[0140] The second dielectric layer provides the technological basis for the subsequent formation of shared plugs, source-drain plugs, and gate plugs.

[0141] In this embodiment, the material of the second dielectric layer is an insulating material. Specifically, the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide.

[0142] Continue to refer to Figure 8 After forming the first source / drain doped layer 120 and the second source / drain doped layer 122, the method for forming the semiconductor structure further includes: forming a shared plug 128 on the top of the first source / drain doped layer 120 located between the first gate structure 110 and the second gate structure 112, and on the top of the second source / drain doped layer 122 extending along the second direction and located on the same side as the first gate structure 110; forming a source / drain plug 126 on the top of the second source / drain doped layer 122 located on the other side of the first gate structure 110, and on the top of the remaining first source / drain doped layer 120; forming a gate plug 130 on the top of the first gate structure 110, and the first gate structure 110 is electrically connected to the gate plug 130.

[0143] It should be noted that the shared plug 128 enables the first source-drain doped layer 120 between the first gate structure 110 and the second gate structure 112 to be electrically connected to the second source-drain doped layer 122 extending along the second direction and located on the same side of the first gate structure 110, thereby realizing that in each sub-cell region 100B, the drain region of the pull-up transistor is electrically connected to the drain region of the pull-down transistor.

[0144] In this embodiment, the shared plug 128 is made of tungsten. In other embodiments, the shared plug may also be made of cobalt or ruthenium.

[0145] The source / drain plug 126 is used to electrically lead out the first source / drain doped layer 120 and the second source / drain doped layer 122, thereby realizing that in each sub-cell region 100B, the source regions of the pull-up transistors are all connected to the power supply voltage, the source regions of the pull-down transistors are all connected to the power supply voltage, and the source region of the transmission gate transistor is connected to the bit line BL.

[0146] In this embodiment, during the step of forming the source / drain plug 126, the source / drain plug 126 formed on top of the second source / drain doped layer 122 on the other side of the first gate structure 110 is used to access VDD.

[0147] Specifically, VDD represents the connected positive operating voltage.

[0148] In this embodiment, in the step of forming the source / drain plug 126, the source / drain plug 126 formed on the top of the first source / drain doped layer 120 on the other side of the first gate structure 110 is used to access the VSS.

[0149] Specifically, VSS represents the negative operating voltage.

[0150] In this embodiment, the source / drain plug 126 is made of tungsten. In other embodiments, the source / drain plug may also be made of cobalt or ruthenium.

[0151] The gate plug 130 is used to bring out the electrical properties of the first gate structure 110, thereby enabling control of the conductive channels of the first channel structure 102 and the second channel structure 103.

[0152] In this embodiment, during the step of forming the gate plug 130, the gate plug 130 is also located on top of the shared plug 128 of the adjacent sub-cell region 100B, and the gate plug 130 is electrically connected to the shared plug 128 of the adjacent sub-cell region 100B.

[0153] It should be noted that in two adjacent sub-cell regions 100B, the pull-up transistor and the pull-down transistor respectively constitute the first CMOS transistor and the second CMOS transistor. The gate plug 130 is electrically connected to the shared plug 128 of the adjacent sub-cell region 100B, thereby connecting the input terminal of the first CMOS transistor to the output terminal of the second CMOS transistor, and connecting the output terminal of the first CMOS transistor to the input terminal of the second CMOS transistor.

[0154] refer to Figure 9After forming the second gate structure 112 discretely on both sides of the first channel structure 102, the method for forming the semiconductor structure further includes: forming a first word line 161 on the top of the second gate structure 112 on one side of the first channel structure 102, and the first word line 161 is electrically connected to the second gate structure 112; forming a second word line 160 on the top of the second gate structure 112 on the other side of the first channel structure 102, and the second word line 160 is electrically connected to the second gate structure 112.

[0155] It should be noted that the first word line 161 and the second word line 160 are used to control the read and write operations of the SRAM device.

[0156] It should also be noted that by providing a first word line 161 and a second word line 160 on both sides of the first channel structure 102, voltage signals can be applied to the first word line 161 and the second word line 160 respectively, or simultaneously, so that the current of the transmission gate transistor can be reduced or increased, that is, the read operating range and write operating range of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.

[0157] In this embodiment, the materials of the first word line 161 and the second word line 160 both include one or more of TiN, Cu and W.

[0158] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate includes a storage cell region, the storage cell region including sub-cell regions extending along a first direction and adjacent along a second direction, the first direction being perpendicular to the second direction, the sub-cell regions including: A first channel structure and a second channel structure located on the substrate and extending along the first direction and arranged in parallel along the second direction; A first gate structure spanning the first channel structure and the second channel structure, wherein the first gate structure and the first channel structure constitute a pull-down transistor, and the first gate structure and the second channel structure constitute a pull-up transistor. The second gate structure is discrete on both sides of the first channel structure. The second gate structure and the first channel structure constitute a transmission gate transistor, and the second gate structure and the first gate structure are arranged parallel to each other along the first direction. The first word line is located on the top of the second gate structure on one side of the first channel structure, and the first word line is electrically connected to the second gate structure. The second word line is located on top of the second gate structure on the other side of the first channel structure, and the second word line is electrically connected to the second gate structure.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a first source / drain doped layer located in the first channel structure on both sides of the first gate structure and on both sides of the second gate structure; The second source / drain doped layer is located in the second channel structure on both sides of the first gate structure; The first source / drain doped layer of the pull-down transistor is electrically connected to the second source / drain doped layer of the pull-up transistor.

3. The semiconductor structure as described in claim 2, characterized in that, The semiconductor structure further includes: a shared plug, located on top of the first source / drain doped layer between the first gate structure and the second gate structure, and extending along the second direction on top of the second source / drain doped layer on the same side as the first gate structure; The source / drain plugs are located on top of the second source / drain doped layer on the other side of the first gate structure, and on top of the remaining first source / drain doped layer. A gate plug is located on top of the first gate structure, and the first gate structure is electrically connected to the gate plug.

4. The semiconductor structure as described in claim 3, characterized in that, The gate plug is also located on top of a shared plug adjacent to the sub-cell region, and the gate plug is electrically connected to the shared plug of the adjacent sub-cell region.

5. The semiconductor structure as described in claim 3, characterized in that, The source / drain plug located on top of the second source / drain doped layer on the other side of the first gate structure is used to connect to VDD; The source / drain plug located on top of the first source / drain doped layer on the other side of the first gate structure is used to access the VSS.

6. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a storage cell region, the storage cell region including sub-cell regions extending along a first direction and adjacent along a second direction, the first direction being perpendicular to the second direction; In the sub-unit region, a first channel structure and a second channel structure extending along the first direction and arranged in parallel along the second direction are formed on the substrate. A first gate structure is formed that spans the first channel structure and the second channel structure. The first gate structure and the first channel structure constitute a pull-down transistor, and the first gate structure and the second channel structure constitute a pull-up transistor. A second gate structure is formed on both sides of the first channel structure. The second gate structure and the first channel structure constitute a transmission gate transistor, and the second gate structure and the first gate structure are arranged parallel to each other along the first direction. A first word line is formed on the top of the second gate structure on one side of the first channel structure, and the first word line is electrically connected to the second gate structure. A second word line is formed on top of a second gate structure on the other side of the first channel structure, and the second word line is electrically connected to the second gate structure.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, After forming the first gate structure and the second gate structure, the forming method further includes: forming a first source / drain doped layer in the first channel structure on both sides of the first gate structure and on both sides of the second gate structure; A second source / drain doped layer is formed in the second channel structure on both sides of the first gate structure; The first source / drain doped layer of the pull-down transistor is electrically connected to the second source / drain doped layer of the pull-up transistor.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The steps of forming the first gate structure and the second gate structure include: forming a first dielectric layer covering the first channel structure and the second channel structure on top of the substrate of the sub-cell region; A first opening is formed in the first dielectric layer to expose the top and sidewalls of the first and second channel structures, and a second opening is formed in the first dielectric layer to expose the top and sidewalls of the first channel structure. The first and second openings extend along the second direction and are arranged in parallel along the first direction. A gate material layer is formed in the first opening and the second opening; The gate material layer located in the second opening is planarized so that the top of the remaining gate material layer in the second opening is flush with the top of the first channel structure. The gate material layer located in the first opening is used as the first gate structure, and the remaining gate material layer located in the second opening is used as the second gate structure.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, After forming the first source / drain doped layer and the second source / drain doped layer, the method of forming the semiconductor structure further includes: forming a shared plug on the top of the first source / drain doped layer located between the first gate structure and the second gate structure, and on the top of the second source / drain doped layer extending along the second direction and located on the same side of the first gate structure. Source / drain plugs are formed on top of the second source / drain doped layer located on the other side of the first gate structure and on top of the remaining first source / drain doped layer; A gate plug is formed on top of the first gate structure, and the first gate structure is electrically connected to the gate plug.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the gate plug, the gate plug is also located on top of a shared plug of the adjacent sub-cell region, and the gate plug is electrically connected to the shared plug of the adjacent sub-cell region.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the source / drain plug, the source / drain plug formed on top of the second source / drain doped layer on the other side of the first gate structure is used to access VDD; The source / drain plug formed on top of the first source / drain doped layer on the other side of the first gate structure is used to access the VSS.

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