METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

Method for manufacturing a semiconductor device (100) comprising the following: (a) Preparing a semiconductor substrate (SUB) of a first conductivity type, wherein the semiconductor substrate (SUB) has an upper surface (TS) and a lower surface (BS); (b) Forming a first trench (TR1) in the upper surface (TS) of the semiconductor substrate (SUB); (c) Forming a first insulating film (IF1) in the first trench (TR1) and on the upper surface (TS) of the semiconductor substrate (SUB); (d) Performing a first ion implantation on the first insulating film (IF1); (e) following (d) reducing the thickness of the first insulating film (IF1) by performing an etching treatment on the first insulating film (IF1); and (f) according to (e) forming a first conductive film (CF1) in the first trench (TR1) over the first insulating film (IF1), wherein in the top view the first trench (TR1) extends in a first direction, wherein in (d) the first ion implantation is carried out from a direction which is inclined by a first angle from a normal direction (10) with reference to the upper surface (TS) of the semiconductor substrate (SUB) in the cross-sectional view, where a second ion implantation is performed after the first ion implantation at (d), wherein the first ion implantation is performed from a direction inclined at a first angle from the first direction in the top view, wherein the second ion implantation is performed from a direction that is inclined to the first direction by a second angle that differs from the first angle in the top view, wherein the semiconductor device (100) comprises a cell region (CR) in which several MOSFETs are formed and an outer circumferential region (OR) that surrounds the cell region (CR) in a top view, where each of the multiple MOSFETs comprises: the first trench (TR1); the first insulating film (IF1); and a field plate electrode (FP) consisting of the first conductive film (CF1), wherein (b) a second trench (TR2) is formed in the upper surface (TS) of the semiconductor substrate (SUB) which is arranged in the outer circumferential region (OR), wherein the second trench (TR2) extends in the first direction and a second direction perpendicular to the first direction in the plan view, so that it surrounds the cell area (CR) in the plan view, and wherein each of the first ion implantation and the second ion implantation is performed from directions other than the first and directions other than directions inclined from the first direction by angles that are multiples of 90 degrees in the top view.

Description

BACKGROUND

[0001] The present invention relates to a semiconductor device and a method for its manufacture, and in particular relates to a semiconductor device comprising a gate electrode and a field plate electrode in a trench and a method for its manufacture.

[0002] In a semiconductor device with a semiconductor element such as a power MOSFET (metal-oxide-semiconductor field-effect transistor), a trench-gate structure is used, in which a gate electrode is embedded in a trench. One type of trench-gate structure is a split-gate structure, in which a field-plate electrode is formed at the lower part of the trench and a gate electrode is formed at the upper part. The field-plate electrode is electrically connected to a source electrode. A depletion layer is extended through this field-plate electrode in a drift region, making it possible to increase the concentration in the drift region and to decrease its resistance.

[0003] A technique listed below is disclosed. [Patent Document 1] Japanese Unexamined Patent Application Publication No. JP 2011-199109A [Patent document 2] US 2006 / 0 166 419 A1 [Patent document 3] US 2016 / 0 093 719 A1 [Patent document 4] US 2012 / 0 241 849 A1 [Patent document 5] US 2016 / 0 329 423 A1 [Patent document 6] US 2016 / 0 079 375 A1

[0004] Patent document 1, for example, discloses a semiconductor device to which a split gate structure with a gate electrode and a field plate electrode is applied. Patent document 2 discloses a manufacturing process for a semiconductor device. A thick silicon oxide layer is first formed in a trench. Then, obliquely implanted argon ions create a selective, damaged area on the sidewalls through shading. During wet casting, in which the damaged areas are removed more quickly, the oxide is selectively removed from the affected areas, leaving a thick residual oxide film on the bottom and lower sidewall of the trench.

[0005] Patent document 3 discloses a semiconductor device consisting of a first semiconductor region, a second semiconductor region selectively arranged on the first semiconductor region, and a third semiconductor region selectively arranged on the second semiconductor region. A first electrode lies on the third semiconductor region and is connected to it. A second electrode is electrically connected to the first semiconductor region. A third electrode is arranged across the first, second, and third semiconductor regions via an insulating layer. A fourth electrode is arranged on the side of the second electrode, relative to the third electrode, across the insulating layer on the first semiconductor region. The insulating layer has three or more regions between the fourth electrode and the first semiconductor region, the widths of which differ in a direction that intersects the direction from the third to the second electrode.

[0006] Patent document 4 discloses a semiconductor device comprising a first, a second, and a third semiconductor region. It also includes a control electrode in the trench, a first main electrode conductively connected to the third semiconductor region, and an internal electrode in the trench conductively connected to the first main electrode. An insulating region is located between the inner trench wall and the internal electrode. The internal electrode comprises a first part in a first trench region and a second part in a second trench region between the first region and the first main electrode. The distance between the first part and the inner trench wall is greater than the distance between the second part and the inner trench wall.

[0007] Patent document 5 discloses a semiconductor device with a vertical MOS transistor whose trenches with trench gate extend through a vertical drift region to a drain region. Field plates with multiple segments are arranged in the trenches below the gate. A dielectric liner separates the field plates from the drift region. It is thicker than the gate dielectric between the gate and body. The liner is thicker at the lower field plate segment than at the upper segment directly below the gate. The trench gate can be electrically isolated from the field plates or connected to the upper segment. The field plate segments can be isolated from each other or connected to each other.

[0008] Patent document 6 discloses electrodes in a first semiconductor layer extending in a first direction, as well as gate electrodes arranged thereon, which also extend in the first direction. A circuit located outside the ends of the gate electrodes extends in a second direction intersecting the first direction and is connected to the electrodes. Gate contacts are located on the gate electrodes and are connected to them. SUMMARY

[0009] According to the investigations conducted by the inventors of this application, it was found that during the deposition of a conductive film as the base of the field plate electrode, a void, called a seam, likely occurs in the conductive film, and this void causes a variety of problems. Fig. 25, Fig. 26 to Fig. Figure 27 shows a semiconductor device in an investigated example examined by the inventors of this application and shows states before and after the fabrication step for forming a field plate electrode. With reference to the Fig. 25, Fig. 26 to Fig. 27. Problems arising in the investigated example are described below. The investigated example and its problems are not previously known findings, but rather findings newly discovered by the inventors of this application.

[0010] As in Fig. As shown in Figure 25, in the split-gate structure, a trench TR1 is first formed in a semiconductor substrate SUB. Next, an insulating film IF1 is formed in the trench TR1 to insulate the semiconductor substrate SUB and the field plate electrode. The insulating film IF1 is a silicon oxide film formed by the CVD process (chemical vapor deposition).

[0011] When the insulating film IF1 is formed by the CVD process, the thickness of the insulating film IF1 at the topmost section (opening) of the trench TR1 is usually large, and the insulating film IF1 is likely to overhang. For example, the thickness T4 of the insulating film IF1 at a position on the top surface of the semiconductor substrate SUB is greater than the thickness T3 of the insulating film IF1 at half the depth from the top surface of the semiconductor substrate SUB to the deepest section of the trench TR1. The "thickness" mentioned here is based on a side surface (inner wall surface) of the trench TR1 rather than a thickness based on a bottom surface of the trench TR1.

[0012] As in Fig. As shown in Figure 26, the conductive film CF1 for the field plate electrode in trench TR1 is deposited using the CVD process. The conductive film CF1 is, for example, a polycrystalline silicon film of the n type. If the insulating film IF1 overhangs, a filling defect in the conductive film CF1 is likely to occur. That is, a void 20 is likely to occur in the conductive film CF1.

[0013] Fig. Figure 27 shows a state in which the conductive film CF1 is processed to form a field plate electrode FP when the vacancy 20 is present. First, the conductive film CF1 formed outside the trench TR1 is removed, and then the conductive film CF1 is retracted by an etching treatment, thus forming the field plate electrode FP. Next, the insulating film IF1 formed outside the trench TR1 is removed by the wet etching treatment, and the insulating film IF1 within the trench TR1 is retracted. Finally, a gate insulating film GI is formed on top of the insulating film IF1 within the trench TR1 by a thermal oxidation process, and an insulating film IF2 is formed on a surface of the field plate electrode FP exposed by the insulating film IF1.

[0014] Here, the etching treatment on the conductive film CF1 is performed in a state where the vacancy 20 is present, and therefore the shape of an upper section of the field plate electrode FP is likely to be anomalous. Furthermore, the insulating film IF2 is formed along the vacancy 20. Then, a volume within the field plate electrode FP expands, and a voltage is applied from the insulating film IF2 to the outside of the trench TR1. In particular, the voltage is likely to be applied in the vicinity of corner sections of the trench TR1. Therefore, crystal defects 30 are likely to occur in the semiconductor substrate SUB, located in the vicinity of the corner sections of the trench TR1. If a large number of crystal defects 30 occur, they will form a creepage path, causing a decrease in the MOSFET's withstand voltage.

[0015] After the manufacturing step in Fig. Furthermore, a gate electrode is formed on the field plate electrode FP over the insulating film IF2. If the vacancy 20 is present, the upper section of the field plate electrode FP is likely to be processed like a protruding section. An electric field is likely to be concentrated at such a protruding section, and therefore the insulating resistance between the field plate electrode FP and the gate electrode is likely to be degraded.

[0016] A primary objective of this application is to solve the problems of the investigated example and to improve the reliability of the semiconductor device by suppressing the occurrence of the vacancy 20. Other objectives and novel features are evident from the description in this patent specification and the accompanying drawings.

[0017] Outlines of representative embodiments disclosed in this application are briefly described below.

[0018] A method for manufacturing a semiconductor device according to one embodiment comprises: (a) preparing a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate has an upper surface and a lower surface; (b) forming a first trench in the upper surface of the semiconductor substrate; (c) forming a first insulating film in the first trench and on the upper surface of the semiconductor substrate; (d) performing a first ion implantation on the first insulating film; (e) after (d) reducing the thickness of the first insulating film by performing an etching treatment on the first insulating film; and (f) after (e) forming a first conductive film in the first trench over the first insulating film.Here, in a top view, the first trench extends in a first direction, and at (d) the first ion implantation is carried out from a direction inclined by a first angle from a normal direction with reference to the top surface of the semiconductor substrate in a cross-sectional view.

[0019] A semiconductor device according to one embodiment comprises: a semiconductor substrate with an upper surface and a lower surface; a first trench formed in the upper surface of the semiconductor substrate such that it extends in a first direction in a top view; a field plate electrode formed within the first trench at a lower section of the first trench; and a gate electrode formed within the first trench at an upper section of the first trench and electrically insulated from the field plate electrode. Here, a portion of the field plate electrode is formed not only at the lower section of the first trench but also at the upper section of the first trench, forming a contact section of the field plate electrode.In a cross-sectional view, the width of the contact section at a position on the upper surface of the semiconductor substrate is also greater than the width of the contact section at half the depth from the upper surface of the semiconductor substrate to the deepest section of the first trench.

[0020] According to one embodiment, the reliability of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a top view showing a semiconductor device in a first embodiment. Fig. Figure 2 is an enlarged top view showing a main section of the semiconductor device in the first embodiment. Fig. Figure 3 is an enlarged top view showing the main section of the semiconductor device in the first embodiment. Fig. Figure 4 shows cross-sectional views of the semiconductor device in the first embodiment. Fig. Figure 5 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. Fig. 6 is a cross-sectional view showing a manufacturing step following Fig. 5 shows. Fig. 7 is a cross-sectional view showing a manufacturing step following Fig. 6 shows. Fig. 8 a cross-sectional view showing a manufacturing step following Fig. 7 shows. Fig. 9 is a cross-sectional view showing a manufacturing step following Fig. 8 shows. Fig. 10 is a cross-sectional view showing a manufacturing step following Fig. 9 shows. Fig. 11 a cross-sectional view showing a manufacturing step following Fig. 10 shows. Fig. 12 is a cross-sectional view showing a manufacturing step following Fig. 11 shows. Fig. 13 is a cross-sectional view showing a manufacturing step following Fig. 12 shows. Fig. 14 is a cross-sectional view showing a manufacturing step following Fig. 13 shows. Fig. 15 is a cross-sectional view showing a manufacturing step following Fig. 14 shows. Fig. 16 is a cross-sectional view showing a manufacturing step following Fig. 15 shows. Fig. 17 is a cross-sectional view showing a manufacturing step following Fig. 16 shows. Fig. 18 is a cross-sectional view showing a manufacturing step following Fig. 17 shows. Fig. 19 is a cross-sectional view showing a manufacturing step following Fig. 18 shows. Fig. Figure 20 is a cross-sectional view showing a manufacturing step following Fig. 19 shows. Fig. Figure 21 is an enlarged top view showing a manufacturing step of a semiconductor device in a second embodiment. Fig. Figure 22 is a cross-sectional view showing a manufacturing step of a semiconductor device in a third embodiment. Fig. Figure 23 is a cross-sectional view showing a manufacturing step of a semiconductor device in one modification. Fig. 24 is a cross-sectional view showing a manufacturing step following Fig. 23 shows. Fig. Figure 25 is a cross-sectional view showing a manufacturing step of a semiconductor device in an investigated example. Fig. 26 is a cross-sectional view showing a manufacturing step following Fig. 25 shows. Fig. 27 is a cross-sectional view showing a manufacturing step following Fig. 26 shows. DETAILED DESCRIPTION

[0021] The embodiments are described in detail below with reference to the drawings. It should be noted that in all drawings used to describe the embodiments, elements with the same function are designated by the same reference numerals, and repeated descriptions are omitted. Furthermore, in the following embodiments, the description of the same or similar sections is generally not repeated unless specifically required.

[0022] Furthermore, the X, Y, and Z directions described in this application intersect and are perpendicular to each other. In this application, the Z direction is described as the upward-downward direction, height direction, or thickness direction of a particular structure. Furthermore, an expression such as "top view" or "in plan view" for use in this application means that a plane formed by the X and Y directions is defined as a "flat plane" and that this "flat plane" is viewed from the Z direction. First embodiment structure of the semiconductor device

[0023] A semiconductor device 100 in the first embodiment is described below with reference to Fig. 1, Fig. 2, Fig. 3 to Fig. 4 described. The semiconductor device 100 comprises a MOSFET with a trench-gate structure as the semiconductor element. Furthermore, the MOSFET of the first embodiment forms a split gate structure with a gate electrode GE and a field plate electrode (electrode with fixed potential) FP.

[0024] Fig. Figure 1 is a top view of a semiconductor chip, which is the semiconductor device 100. Fig. Figure 1 mainly shows a wiring pattern formed on top of the semiconductor substrate SUB. Fig. 2 is a main section top view, in which an area 1A, which is in Fig. The image shown in 1 is enlarged. Fig. Figure 3 shows a structure under Fig. 2 and shows a structure of a trench gate formed in the semiconductor substrate SUB.

[0025] As in Fig. As shown in Figure 1, most of the semiconductor device 100 is covered with a source electrode (a fixed-potential supply wire) SE. A gate wire GW is provided along an outer circumference of the semiconductor device 100 and surrounds the source electrode SE in the top view. Although not shown here, the source electrode SE and the gate wire GW are covered with a protective film, such as a polyimide film. A portion of the protective film has openings, and the source electrode SE and the gate wire GW exposed at these openings serve as the source contact SP and gate contact GP, respectively. External connecting elements, such as wires or terminals (copper plates), are connected to the source contact SP and the gate contact GP, thus electrically connecting the semiconductor device 100 to other semiconductor chips or wiring boards.

[0026] Furthermore, the semiconductor device 100 comprises a cell area CR and an outer circumferential area OR that surrounds the cell area CR in a top view. The main semiconductor elements, such as several MOSFETs, are formed within the cell area CR. The outer circumferential area OR is used to connect the gate wiring GW to the gate electrode GE, to form trenches TR2 that act as termination areas, and so on.

[0027] Positions of holes CH1 to CH4, which are in Fig. The 3 shown correspond to the positions of holes CH1 to CH4, which are in Fig. The two shown are consistent. As in Fig. As shown in Figure 3, several trenches TR1 extend in the Y-direction within cell CR and are adjacent to each other in the X-direction. For example, the width of each of the trenches TR1 in the X-direction is 1.5 µm or more and 1.8 µm or less. Furthermore, each of the trenches TR1 is separated from others in the X-direction by an interval of 0.7 µm or more and 1.0 µm or less.

[0028] Within trench TR1, the field plate electrode FP is formed on a lower section (a lower part) of trench TR1, and the gate electrode GE is formed on an upper section (an upper part) of trench TR1. The field plate electrode FP and the gate electrode GE extend along trench TR1 in the Y direction.

[0029] Part of the field plate electrode FP forms a contact section FPa. Within the trench TR1 in the cell area CR, the field plate electrode FP, which forms the contact section FPa, is formed not only at the lower section of the trench TR1, but also at the upper section of the trench TR1.

[0030] In the outer perimeter area OR, the trenches (enclosure trenches) TR2 are formed. The trenches TR2 extend in the Y and X directions to surround the cell area CR. The width of the trenches TR2 is similar to that of the trenches TR1. Within each of the trenches TR2, the field plate electrode FP is formed.

[0031] As in Fig. As shown in Figure 3, the gate electrode GE, the contact section FPa, and the field plate electrode FP are exposed in the trench TR2. In the outer circumferential region OR, holes CH2 are formed on the gate electrodes GE, and the gate electrodes GE are electrically connected to the gate wiring GW via the holes CH2. In the cell region CR, holes CH3 are formed on the contact sections FPa, and the contact sections FPa are electrically connected to the source electrode SE via the holes CH3. In the outer circumferential region OR, holes CH4 are formed on a portion of the field plate electrodes FP, and the field plate electrodes FP are electrically connected to the source electrode SE via the holes CH4.

[0032] With reference to Fig. 4 A cross-sectional structure of the semiconductor device 100 is described below. Fig. Figure 4 shows cross-sectional views along line AA and line BB, which are in Fig. 2 and Fig. 3 are shown.

[0033] First, with reference to the AA cross-section in Fig. 4 describes a basic structure of the MOSFET. The semiconductor device 100 comprises the semiconductor substrate SUB with an upper surface TS and a lower surface BS. The semiconductor substrate SUB has a low-concentration n-type drift region NV. Here, the n-type semiconductor substrate SUB itself forms the drift region NV. It should be noted that the drift region NV can be an n-type semiconductor layer that is grown while phosphorus (P) is introduced into an n-type silicon substrate by epitaxial growth. In this application, a description is given under the assumption that a stacked body consisting of such an n-type silicon substrate and an n-type semiconductor layer is also the semiconductor substrate SUB.

[0034] In the upper surface TS of the semiconductor substrate SUB, several grooves TR1 are formed, reaching a predetermined depth from the upper surface TS of the semiconductor substrate SUB. The depth of each of the grooves TR1 is, for example, 5 µm or more and 7 µm or less. Furthermore, a depth of the grooves TR2, which are in Fig. Figure 3 shows similarities to those of each of the trenches TR1. Within the trench TR1, the field plate electrode FP is formed on the lower section of the trench TR1 over the insulating film IF1, and the gate electrode GE is formed on the upper section of the trench TR1 over the gate insulating film GI.

[0035] The position of an upper surface of the insulating film IF1 is lower than the position of an upper surface of the field plate electrode FP. The gate insulating film GI is formed on the insulating film IF1 in the groove TR1. The insulating film IF2 is formed on the upper and side surfaces of the field plate electrode FP that are exposed by the insulating film IF1. The gate electrode GE is also formed between the field plate electrode FP, which is exposed by the insulating film IF1, and the semiconductor substrate SUB, via the gate insulating film GI and the insulating film IF2.

[0036] The insulating film IF1 is formed between the semiconductor substrate SUB and the field plate electrode FP. The insulating film IF2 is formed between the gate electrode GE and the field plate electrode FP. The gate insulating film GI is formed between the semiconductor substrate SUB and the gate electrode GE. These insulating films electrically isolate the semiconductor substrate SUB, the gate electrode GE, and the field plate electrode FP from each other.

[0037] An upper surface of the gate electrode GE is slightly recessed from the upper surface TS of the semiconductor substrate SUB. An insulating film IF3 is formed on an upper surface of a portion of the gate electrode GE such that it is in contact with the gate insulating film GI.

[0038] Each of the gate electrode GE and the field plate electrode FP, for example, consists of a polycrystalline silicon film into which n-type defects are introduced. Each of the insulating film IF1, insulating film IF2, insulating film IF3, and gate insulating film GI, for example, consists of a silicon oxide film.

[0039] The thickness of insulating film IF1 is greater than the thickness of each of insulating films IF2, IF3, and GI. For example, the thickness of insulating film IF1 is 400 nm or more and 600 nm or less. The thickness of each of insulating film IF2 and the gate insulating film is, for example, 50 nm or more and 80 nm or less. The thickness of insulating film IF3 is, for example, 30 nm or more and 80 nm or less.

[0040] In the semiconductor substrate SUB (specifically in a position closer to the upper surface of the semiconductor substrate SUB than to its lower surface BS), a p-type body region PB is formed such that it is shallower than the trench TR1. An n-type source region NS is formed within the body region PB. The source region NS exhibits a higher impurity concentration than that of the drift region NV.

[0041] On a side closer to the lower surface BS of the semiconductor substrate SUB, an n-type drain region ND is formed within the semiconductor substrate SUB. The drain region ND exhibits a higher concentration of impurities than that of the drift region NV. A drain electrode DE is formed beneath the lower surface BS of the semiconductor substrate SUB. The drain electrode DE consists, for example, of a single metal film such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film, or of a stacked film, optionally formed by depositing these metal films.

[0042] On the upper surface TS of the semiconductor substrate SUB, an intermediate insulating film IL is formed such that it covers the trench TR1. The intermediate insulating film IL consists, for example, of a silicon oxide film. The thickness of the intermediate insulating film IL is, for example, 700 nm or more and 900 nm or less. It should be noted that the intermediate insulating film IL can be a stacked film of a thin silicon oxide film and a thick silicon oxide film containing phosphorus (PSG: phosphosilicate glass film).

[0043] In the intermediate insulating film IL, a hole CH1 is formed, reaching both the source region NS and the body region PB. At the bottom of hole CH1, a diffusion region PR with a high concentration of impurities in the body region PB is formed. This high-concentration diffusion region PR exhibits an impurity concentration that is higher than that of the body region PB.

[0044] The source electrode SE is formed on the intermediate insulating film IL. The source electrode SE is embedded in the hole CH1. Furthermore, the source electrode SE is electrically connected to the source region NS, the body region PB, and the diffusion region PR with high concentrations and supplies a source potential (a fixed potential) to them.

[0045] Although not shown here, the hole CH2, which is located in the interlayer insulating film IL, is also present, although not shown here. Fig. 2 and Fig. As shown in Figure 3, the gate wiring GW is formed on the intermediate insulating film IL. The hole CH2 reaches the gate electrode GE, and the gate wiring GW is embedded in the hole CH2. The gate wiring GW is electrically connected to the gate electrode GE and supplies a gate potential to the gate electrode GE.

[0046] As in the BB cross-section of Fig. As shown in Figure 4, part of the field plate electrode FP forms the contact section FPa of the field plate electrode FP. A position of an upper surface of the insulating film IF1 that is in contact with the field plate electrode FP, apart from the contact section FPa, is lower than a position of an upper surface of the insulating film IF1 that is in contact with the contact section FPa. Specifically, a position of an upper surface of the insulating film IF1 in the AA cross-section is located at a depth of 1.2 µm or more and 1.5 µm or less from the upper surface TS of the semiconductor substrate SUB. A position of an upper surface of the insulating film IF1 in the BB cross-section is located at a depth of 50 nm or more and 500 nm or less from the upper surface TS of the semiconductor substrate SUB.

[0047] Furthermore, a position of an upper surface of the contact section FPa is higher than a position of the upper surface TS of the semiconductor substrate SUB and is located at a height of 200 nm or more and 400 nm or less from the upper surface TS of the semiconductor substrate SUB.

[0048] The hole CH3, which reaches the contact section FPa, is formed in the intermediate insulating film IL. The source electrode SE is embedded in the hole CH3. The source electrode SE is electrically connected to the field plate electrode FP and supplies the source potential to the field plate electrode FP.

[0049] Although not shown here, the field plate electrode FP is also located in trench TR2, which is in Fig. Figure 3 shows the component formed over the insulating film IF1. The hole CH4, which reaches part of the field plate electrode FP in the trench TR2, is formed in the intermediate insulating film IL. The source electrode SE is embedded in the hole CH4. The source electrode SE is electrically connected to the field plate electrode FP in the trench TR2 and supplies the source potential to the field plate electrode FP in the trench TR2. A cross-sectional view of the part is shown in Figure 3. Fig. 3, in which the hole CH4 is located, is the same as that of a structure of the BB cross-section in Fig. 4.

[0050] Each of the source electrode (SE) and gate wiring (GW) also consists, for example, of a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium nitride film, and the conductive film is, for example, an aluminum film.

[0051] It should be noted that each of the source electrode SE and the gate wiring GW can consist of a plug layer filling the interior of each of the holes CH1 to CH4, and a wiring layer formed on the intermediate insulating film IL. In this case, the wiring layer consists of the barrier metal film and the conductive film mentioned above. The plug layer consists, for example, of a stacked film of a barrier metal film, such as a titanium nitride film, and a conductive film, such as a tungsten film. Method for manufacturing the semiconductor device

[0052] With reference to Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 to Fig. The respective manufacturing steps contained in the process for manufacturing the semiconductor device 100 are described below. In the following description, the AA cross-section and the BB cross-section are described in Fig. 4 used. It should be noted that the cross-sectional structures of the trenches TR2, the holes CH4 and their surroundings in the outer perimeter area OR are essentially the same as the structure of the BB cross-section in Fig. 4 are as mentioned above. Since the description of the manufacturing steps for these cross-sectional structures is essentially the same as the description of the manufacturing steps for the BB cross-section, a detailed description of these steps is omitted.

[0053] Furthermore, the main feature of the method for manufacturing the semiconductor device 100 in the first embodiment lies in the manufacturing steps for forming the insulating film IF1 and the field plate electrode FP. Such a feature will be described, if necessary, while being compared with the aforementioned investigated example.

[0054] As in Fig. As shown in Figure 5, the n-type semiconductor substrate SUB with the upper surface TS and the lower surface BS is prepared first. Although the n-type semiconductor substrate SUB itself forms the drift region NV here, as mentioned above, the drift region NV can be such an n-type semiconductor layer that is grown while phosphorus (P) is introduced into an n-type silicon substrate by epitaxial growth.

[0055] Next, the trench TR1 is formed in the upper surface TS of the semiconductor substrate SUB. To form the trench TR1, a silicon oxide film is formed on the semiconductor substrate SUB, for example, by the CVD process. Next, a resist pattern with an opening is formed on the oxide film using photolithography. Next, an etching treatment (for example, dry etching) is performed using the resist pattern as a mask, thus structuring the silicon oxide film to form a hard mask HM. Next, the resist pattern is removed by an ashing treatment. Next, an etching treatment (for example, dry etching) is performed using the hard mask HM as a mask, thus forming the trench TR1 in the semiconductor substrate SUB.Afterwards, the hard mask HM is removed by an etching treatment (for example, wet etching) using a solution containing, for example, hydrofluoric acid.

[0056] It should be noted that in the outer perimeter area OR, the trenches TR2 are formed using the same steps as those used to form the trenches TR1.

[0057] As in Fig. As shown in Figure 6, the insulating film IF1, which consists, for example, of a silicon oxide film, is formed in the trench TR1 and on the semiconductor substrate SUB. First, a first silicon oxide film IF1a is formed in the trench TR1 and on the semiconductor substrate SUB by thermal oxidation. Next, a second silicon oxide film IF1b is formed on top of the first silicon oxide film IF1a by CVD. The insulating film IF1 is configured to encompass both the first silicon oxide film IF1a and the second silicon oxide film IF1b. The thickness of the first silicon oxide film IF1a is, for example, 100 nm or more and 200 nm or less. The thickness of the second silicon oxide film IF1b is, for example, 300 nm or more and 400 nm or less.

[0058] Although it is also possible to form the entire insulating film IF1 by the thermal oxidation process, stress from the insulating film IF1 would likely cause the semiconductor substrate SUB in a wafer state to warp, which would have a detrimental effect on subsequent manufacturing steps. Meanwhile, to improve the interface condition between the insulating film IF1 and the semiconductor substrate SUB, the silicon oxide film in contact with the semiconductor substrate SUB is preferably formed by the thermal oxidation process. Therefore, in the first embodiment, the insulating film IF1 consists of a stacked film of the first silicon oxide film IF1a, formed by the thermal oxidation process and relatively thin, and the second silicon oxide film IF1b, formed by the CVD process and relatively thick.

[0059] When the CVD method is used to form the insulating film IF1, the thickness of the insulating film IF1 on the uppermost section (opening) of the trench TR1 is usually large, as shown in relation to Fig. 25 in the investigated example, and the insulating film IF1 is likely to be overhanging. As with reference to Fig. As described in the investigated example 26, the vacancy 20 probably occurs in the conductive film CF1 at the time of the formation of the conductive film CF1. Ion implantation process on insulating film IF1

[0060] To solve the problem described above, the inventors of this application therefore developed a technique to suppress the overhang of the insulating film by performing ion implantation on the insulating film IF1 at the upper section of the trench TR1 and partially changing the etch rate of the etching treatment.

[0061] In particular, first, as in Fig. Figure 6 shows the ion implantation performed on the insulating film IF1. This ion implantation is carried out from a direction inclined at a predetermined angle to the direction of a normal line 10 (hereinafter referred to as the "normal direction") with respect to the upper surface TS of the semiconductor substrate SUB. Here, the case of performing the ion implantation twice is shown. The first ion implantation is carried out from a direction inclined at an angle θ1 to the normal direction, and the second ion implantation is carried out from a direction inclined at an angle θ2 to the normal direction. The angles θ1 and θ2 are different from each other.

[0062] Since such an implantation angle is larger, it becomes easier to implant ions into the insulating film IF1 near the uppermost section (opening) of the trench TR1. By decreasing the implantation angle, the ions can be implanted not only into the vicinity of the uppermost section of the trench TR1, but also into the insulating film IF1 located further away from the uppermost section of the trench TR1.

[0063] For example, arsenic (As), phosphorus (P), or boron difluoride (BF2) can be used as the ion species for ion implantation. The total implantation quantity for ion implantation is preferably 1 x 10 13 / cm 2 or more. Furthermore, the implantation angle (angle θ1 and angle θ2) during ion implantation is preferably set to a range of 20 degrees or more and 60 degrees or less.

[0064] It should be noted that, although the case of performing ion implantation twice is shown here, ion implantation can be performed three or more times at different angles. Furthermore, ion implantation does not necessarily have to be performed multiple times and only needs to be performed at least once.

[0065] The etching rate of the treatment differs between the point where ions are implanted and the point where they are not. At the point where ions are implanted, the etching rate is faster compared to the point where they are not. The faster the etching rate is at the point where a larger number of ions are implanted.

[0066] After the aforementioned ion implantation has been performed on the insulating film IF1, an etching treatment is carried out on the insulating film IF1 to reduce its thickness. It is important to note that an etching treatment with a greater isotropic component than an anisotropic component is used for the etching treatment performed on the insulating film IF1 after the ion implantation. Specifically, for example, a wet etching treatment using a solution containing hydrofluoric acid is employed. This ensures that the etching action on the insulating film IF1 does not only work in one thickness direction (Z-direction, which is defined in the ion implantation process). Fig. 7 shown) of the semiconductor substrate SUB, but also in a direction along the upper surface TS (or the lower surface BS) of the semiconductor substrate SUB (X-direction shown in Fig., the horizontal direction).

[0067] Fig. Figure 7 shows the state of the insulating film IF1 after the etching treatment. The insulating film IF1 is generally thinned, and its thickness is further reduced in the vicinity of the uppermost section (the opening) TOP of the trench TR1, into which the ions are implanted. In the Fig. In the X-direction shown in Figure 7, for example, the thickness T2 of the insulating film IF1 at the position of the upper surface TS of the semiconductor substrate SUB is smaller than the thickness T1 of the insulating film IF1 at half the depth from the upper surface TS of the semiconductor substrate SUB to the deepest section of the trench TR1. Therefore, the overhang of the insulating film IF1 is eliminated, its aspect ratio is improved, and thus the vacancy 20 is less likely to occur in the conductive film CF1 during the formation of the conductive film CF1 in the next step.

[0068] In other words, the characteristics regarding the thickness T1 and the thickness T2 of the insulating film IF1 are, for example, as follows. The trench TR has a bottom surface TR1b and a side surface (an inner wall surface) TR1s in the cross-sectional view. It should be noted that the deepest section of the trench TR1 is located within a portion of the bottom surface TR1b. Specifically, the bottom surface TR1b and the side surface TR1s do not intersect at a right angle, but are, strictly speaking, rounded, as shown in Fig. Figure 7 shows that in the cross-sectional view, the insulating film IF1 has a first section formed on the side surface TR1s and located at the top section (opening) TOP of the trench TR1, and a second section formed on the side surface TR1s and located closer to the bottom surface TR1b than the top section TOP of the trench TR1. The thickness of the first section is less than the thickness of the second section. It should be noted that the "thickness" mentioned here refers to a thickness based on the side surface TR1s (thickness in the Fig. 7 shown X-direction) as a thickness based on the ground surface TR1b.

[0069] The thickness of the first section corresponds, for example, to the thickness T2 of the insulating film IF1. Furthermore, the thickness of the second section includes the thickness T1 of the insulating film IF1. Training step of the field plate electrode FP

[0070] After the etching treatment on the insulating film IF1, which has undergone ion implantation, the field plate electrode FP is formed such that it fills the interior of the trench TR1 above the insulating film IF1, as shown in Fig. 8, Fig. 9, Fig. 10 to Fig. 11 shown.

[0071] As in Fig. As shown in Figure 8, the conductive film CF1 is first formed on the insulating film IF1, for example, by the CVD process. The conductive film CF1 is, for example, a polycrystalline silicon film of the n type. At this stage, the interior of the trench TR1 is not completely filled with the conductive film CF1. The thickness of the conductive film CF1 is, for example, 200 nm or more and 300 nm or less.

[0072] As in Fig. As shown in Figure 9, the next step is to perform an etching treatment on the conductive film CF1, thus reducing its thickness. It is important to note that the etching treatment used on the conductive film CF1 employs a larger anisotropic component than an isotropic component. Because the conductive film CF1 is machined into a sidewall shape within the trench TR1, its thickness decreases as it approaches the uppermost section of the trench TR1.

[0073] As in Fig. As shown in Figure 10, a conductive film CF2 is next formed, for example, by the CVD process, such that it fills the interior of the trench TR1 over the insulating film IF1 and the conductive film CF1. The conductive film CF2 is also formed on the insulating film IF1 outside the trench TR1. The conductive film CF2 is, for example, an n-type polycrystalline silicon film. A thickness of the conductive film CF2 is, for example, 800 nm or more and 1200 nm or less. Since in the manufacturing step in Fig. 9. As the thickness of the conductive film CF1 decreases as it approaches the uppermost section of the trench TR1, the vacancy 20 is less likely to occur in the conductive film CF2 at the time of the formation of the conductive film CF2.

[0074] As in Fig. As shown in Figure 11, the conductive film CF2, which forms outside the trench TR1, is next removed by, for example, a polishing treatment using the CMP (chemical-mechanical polishing) process or an etching treatment. This forms the field plate electrode FP, which comprises the conductive films CF1 and CF2 that form in the trench TR1. At this point, the position of the upper surface of the field plate electrode FP is higher than the position of the upper surface TS of the semiconductor substrate SUB.

[0075] As described above, the field plate electrode FP, in which the occurrence of the vacancy 20 is suppressed, can be formed. It should be noted that even if each of the ion implantation and etching treatment in Fig. 6 is not carried out and the thickness of the insulating film IF1 determines the relationship (“T2 < T1”) in Fig. 7 not fulfilled, the training procedure of the field plate electrode FP, which refers to Fig. 8, Fig. 9, Fig. 10 to Fig. 11 is described as a method for suppressing the occurrence of the vacancy 20.

[0076] As in Fig. As shown in Figure 12, the next step is to selectively retract part of the field plate electrode FP (the BB cross-section) so that part of the electrode remains as the contact section FPa (the AA cross-section). First, a resist pattern RP1 is formed, selectively covering an area that serves as the contact section FPa. Next, the etching treatment (for example, the dry etching treatment) is performed using the resist pattern RP1 as a mask. This selectively retracts the electrode FP except for the contact section FPa. Afterward, the resist pattern RP1 is removed by the ashing treatment.

[0077] As in Fig. As shown in Figure 13, a portion of the insulating film IF1 is subsequently removed by the etching process (for example, wet etching). This removes the insulating film IF1 from the semiconductor substrate SUB, and furthermore, the position of the upper surface of the insulating film IF1 becomes lower than the position of the upper surface of the field plate electrode FP in the trench TR1. The insulating film IF1 is thus retracted. In the area where the field plate electrode FP is retracted (the AA cross-section), a portion of the insulating film IF1 is also exposed in the trench TR1, and therefore the etching on the insulating film IF1 progresses rapidly.

[0078] At this point, the position of the upper surface of the insulating film IF1, which is in contact with the field plate electrode FP except for the contact section FPa, is lower than the position of the upper surface of the insulating film IF1 that is in contact with the contact section FPa. Furthermore, since the insulating film IF1 is removed from the semiconductor substrate SUB, the position of the upper surface of the contact section FPa is higher than the position of the upper surface TS of the semiconductor substrate SUB.

[0079] Since the field plate electrode FP is formed along the shape of the insulating film IF1, the width W2 of the upper section of the contact section FPa is also greater than the width W1 of the lower section of the contact section FPa, as shown in the BB cross-section. In the X-direction, for example, the width W2 of the contact section FPa at the position of the upper surface TS of the semiconductor substrate SUB is greater than the width W1 of the contact section FPa at half the depth from the upper surface TS of the semiconductor substrate SUB to the deepest section of the trench TR1.

[0080] As in Fig. As shown in Figure 14, the gate insulating film GI, which consists, for example, of a silicon oxide film, is formed next by the thermal oxidation process in trench TR1 on the insulating film IF1 and on the semiconductor substrate SUB. Simultaneously, the insulating film IF2 is formed on the upper surface and the side surface of the field plate electrode FP, which are exposed by the insulating film IF1.

[0081] On the field plate electrode FP, which is used in the manufacturing step in Fig. After the 12-phase process is withdrawn, a conductive film CF3 is formed in the trench TR1 and on the semiconductor substrate SUB, for example by CVD, to fill the interior of the trench TR1 (the AA cross-section). Here, the conductive film CF3 is also formed in the trench TR1 where the contact section FPa is formed (the BB cross-section). The conductive film CF3 is, for example, an n-type polycrystalline silicon film. The thickness of the conductive film CF3 is, for example, 800 nm or more and 1200 nm or less.

[0082] As in Fig. As shown in Figure 15, the next step is to perform an etching treatment (for example, a dry etching treatment) on the conductive film CF3, so that the conductive film CF3 formed outside the trench TR1 is removed, and the gate electrode GE is formed in the trench TR1 (the AA cross-section). This etching treatment removes the conductive film CF3 in the trench TR1 where the contact section FPa is formed (the BB cross-section).

[0083] It should be noted that, in order to completely remove the conductive film CF3 in trench TR1, where the contact section FPa is formed, and the conductive film CF3 outside of trench TR1, over-etching of the conductive film CF3 is implemented in this etching treatment. As shown in the AA cross-section of Fig. As shown in Figure 15, the position of the upper surface of the gate electrode GE is therefore slightly lower than the position of the upper surface TS of the semiconductor substrate SUB.

[0084] As in Fig. As shown in Figure 16, the insulating film IF3 is next formed on the upper surface TS of the semiconductor substrate SUB, for example by the CVD process, to cover the trench TR1. The insulating film IF3 is formed, for example, from a silicon oxide film or a silicon nitride film.

[0085] As in Fig. As shown in Figure 17, the next step is to perform the etching treatment (for example, the dry etching treatment) on the insulating film IF3. This leaves the insulating film IF3 on the upper surface of part of the gate electrode GE, so that it is in contact with the gate insulating film GI (the AA cross-section). Furthermore, the insulating film IF3 is left over the insulating film IF2 on the side surface of the contact section FPa (the BB cross-section).

[0086] As in Fig. As shown in Figure 17, boron (B) is next introduced by ion implantation at a position closer to the upper surface TS of the semiconductor substrate SUB than to the lower surface BS of the semiconductor substrate SUB, forming the p-type body region PB in the semiconductor substrate SUB. The body region PB is formed to be shallower than the trench TR1. After covering the perimeter of the contact section FPa with the resist pattern, arsenic (As) is next introduced by ion implantation, forming the n-type source region NS in the body region PB. Next, the resist pattern is removed by ashing. A heat treatment is then applied to the semiconductor substrate SUB to diffuse any defects present in the source region NS and the body region PB.

[0087] It should be noted that a thin silicon oxide film can be pre-formed as a through-film on the semiconductor substrate SUB prior to ion implantation into the source region NS and the body region PB. This through-film can be removed after ion implantation or can remain as part of the interlayer insulating film IL.

[0088] As in Fig. As shown in Figure 18, the intermediate insulating film IL is next formed, for example, by the CVD process on the upper surface TS of the semiconductor substrate SUB to cover the trench TR1. The intermediate insulating film IL consists, for example, of a silicon oxide film. It should be noted that the intermediate insulating film IL can be a stacked film of a thin silicon oxide film formed by the CVD process and a PSG film formed by the deposition process.

[0089] As in Fig. As shown in Figure 19, the holes CH1 to CH4 are formed next in the interlayer insulating film IL. Although holes CH2 and CH4 are not shown, they are formed in the same step as in the step for forming hole CH3.

[0090] First, a resist pattern is formed on the intermediate insulating film IL, creating a pattern that opens the semiconductor substrate SUB, where the source region NS is formed. Next, the etching treatment (e.g., dry etching) is performed using the resist pattern described above as a mask, so that the hole CH1, which reaches the interior of the source region NS and the interior of the body region PB, is formed in the intermediate insulating film IL. The bottom of the hole CH1 is located in the body region PB. Next, boron (B), for example, is introduced into the body region PB at the bottom of the hole CH1 by the ion implantation process, so that the p-type diffusion region PR is formed at a high concentration. Afterward, the resist pattern is removed by the ashing treatment.

[0091] Next, a resist pattern is formed on the intermediate insulating film IL, with a pattern that opens the gate electrode GE in the outer circumferential region OR, the contact section FPa in the cell region CR, and the field plate electrode FP in the outer circumferential region OR. The etching treatment (e.g., dry etching) is then performed using the resist pattern as a mask, so that the hole CH2, reaching the gate electrode GE, the hole CH3, reaching the contact section FPa, and the hole CH4, reaching the field plate electrode FP of the outer circumferential region OR, are formed in the intermediate insulating film IL. Afterward, the resist pattern is removed by an ashing treatment.

[0092] It should be noted that either the step to form hole CH1 or the step to form holes CH2 to CH4 can be performed first.

[0093] As in Fig. As shown in Figure 20, the next steps involve forming the source electrode SE and the gate wiring GW, which surrounds the source electrode SE in a top view, on the intermediate insulating film IL. First, a stacked film of a barrier metal film, for example, a titanium nitride film, and a conductive film, for example, an aluminum film, is formed on the intermediate insulating film IL by sputtering or CVD. Next, the source electrode SE and the gate wiring GW are formed by structuring the stacked film.

[0094] The gate wiring GW is embedded in hole CH2 and electrically connected to the gate electrode GE. The source electrode SE is embedded in holes CH1, CH3, and CH4 and electrically connected to the source region NS, the body region PB, the high-concentration diffusion region PR, and the field plate electrode FP.

[0095] Although not shown here, a protective film, for example made of a polyimide film, is next formed on the source electrode SE and the gate wiring GW, for example by a coating process. Areas that are to be the source contact point SP and the gate contact point GP in the source electrode SE and the gate wiring GW are exposed by opening up a portion of the protective film.

[0096] The following manufacturing steps then produce the in Fig. 4 Semiconductor device 100 shown is fabricated. First, the lower surface BS of the semiconductor substrate SUB is polished according to requirements. Next, for example, arsenic (As) or the like is introduced into the lower surface BS of the semiconductor substrate SUB by the ion implantation method, so that the drain region ND of n-type is formed. Next, the drain electrode DE is formed under the lower surface BS of the semiconductor substrate SUB by the sputtering method. Structural feature of the semiconductor device

[0097] As with reference to Fig. 8, Fig. 9, Fig. 10 to Fig. As described in Figure 11, in the first embodiment the vacancy 20 in the field plate electrode FP is not formed. Therefore, even if the insulating film IF2 is formed, the problem of volume expansion occurring within the field plate electrode FP and the appearance of crystal defects 30 in the semiconductor substrate SUB, which are located in the vicinity of the corner sections of the trench TR1, as in the investigated example, is less likely to occur.

[0098] The presence of the vacancy 20 also causes the problem that the upper section of the field plate electrode FP is likely to be machined like a protruding section, an electric field is concentrated on such a protruding section, and the insulation resistance between the field plate electrode FP and the gate electrode GE is likely to be degraded. In the first embodiment, this problem is also suppressed. Therefore, according to the first embodiment, the problem of reducing the MOSFET's withstand voltage can be suppressed, and the reliability of the semiconductor device 100 can be improved.

[0099] As with reference to Fig. As described in section 13, the width W2 of the upper section of the contact section FPa is also greater than the width W1 of the lower section of the contact section FPa. This relationship also applies to Fig. 4, which shows the final structure.

[0100] With regard to the insulating film IF1, the thickness T2 of the insulating film IF1 at the position of the upper surface TS of the semiconductor substrate SUB is also smaller than the thickness T1 of the insulating film IF1 at half the depth from the upper surface TS of the semiconductor substrate SUB to the deepest section of the trench TR1 in the step of Fig. 7. Although the insulating film IF1 in Fig. When 4 is withdrawn, a portion of the insulating film IF1 remains and maintains this relationship. As in the BB cross-section of Fig. As shown in Figure 4, for example, the thickness of the insulating film IF1, which is in contact with the contact section FPa, is smallest at the part of the insulating film IF1 that is closest to the upper surface of the contact section FPa.

[0101] Since the width W2 of the upper section of the contact section FPa is large in the first embodiment, the tolerance for misalignment during the formation of the hole CH3 is increased. This makes it easier to position the hole CH3 on the contact section FPa. Second embodiment

[0102] A semiconductor device in a second embodiment is described below with reference to Fig. 21. It should be noted that the following description mainly describes differences from the first embodiment and omits descriptions of points that overlap with the first embodiment.

[0103] In the second embodiment, the ions are implanted into the insulating film IF1 from directions inclined at predetermined angles to the normal direction during the ion implantation process. Fig. 6 as in the first embodiment. Furthermore, in the second embodiment, as in Fig. Figure 21 shows the multiple ion implantations being carried out from directions inclined at different angles in plan view to the direction of the trench TR1 (the Y direction). Fig. Figure 21 shows the case in which twelve ion implantations IMP1 to IMP12 are each performed from directions inclined at angles that are different from each other in the top view.

[0104] If ion implantation is performed from the same direction as the orientation of trench TR1 (the Y-direction) in the top view, the ions will also be implanted into the insulating film IF1 located at the bottom of trench TR1. Consequently, the etch rate of the insulating film IF1 located at the bottom of trench TR1 will increase due to the etching treatment (e.g., wet etching) in the next step, and a localized area of ​​reduced insulating film thickness IF1 will form. Therefore, there is a concern that this could lead to a deterioration of the insulation resistance.

[0105] If the semiconductor device 100 includes the trenches TR2 as termination regions in the outer circumferential region OR, such a problem can also occur in the trenches TR2. As in Fig. As shown in Figure 3, the trenches TR2 are designed to surround the cell area CR in the top view and to include the part extending in the Y direction and the part extending in the X direction.

[0106] Therefore, the multiple ion implantations IMP1 to IMP12 must be performed in Fig. 21 are each performed from directions other than the Y-direction and directions other than the X-direction. In other words, the multiple ion implantations IMP1 to IMP12 are each performed from directions other than the direction of travel of trench TR1 and from directions other than those inclined to the direction of travel of trench TR1 at angles that are multiples of 90 degrees.

[0107] As in Fig. As shown in Figure 3, the trenches TR2 are sometimes provided with corner sections TR2a that couple the parts extending in the Y direction and those extending in the X direction. The corner sections TR2a extend in directions inclined at 45 degrees from the Y direction or the X direction in the plan view. Although it is not essential to provide the corner sections TR2a, the parts extending in the Y direction and those extending in the X direction are coupled at a right angle if such corner sections TR2a are not provided. Consequently, the thickness of the insulating film IF1 is likely to vary, and the filling defect of the conductive film CF1 is likely to occur at the right-angled part. Therefore, it is preferred that the trenches TR2 be provided with the corner sections TR2a to make such defects less likely to occur.

[0108] If the corner sections TR2a are located in the grooves TR2, it is also necessary to prevent the ions from being implanted into the insulating film IF1, which is located on the undersides of the corner sections TR2a. Therefore, the multiple ion implantations IMP1 to IMP12 must be in Fig. 21 each from directions other than the Y-direction, directions other than the X-direction, and directions other than those inclined at 45 degrees to the Y-direction or the Y-direction. In other words, the multiple ion implantations IMP1 to IMP12 are each performed from directions other than the direction of travel of trench TR1 and directions other than those inclined at angles multiples of 45 degrees to the direction of travel of trench TR1.

[0109] The depth of the ion implants IMP1 to IMP12 is described in the case where the multiple ion implants IMP1 to IMP12 are viewed in the cross-sectional view of the second embodiment. For example, it is assumed that the implantation angle of the ion implants IMP1 to IMP12 in the cross-sectional view is the same angle as the implantation angle θ1 in Fig. 6 are. In this case, for ion implantations that are inclined by 180 degrees to each other, such as the ion implantation IMP2 and the ion implantation IMP8, the depths of the ions implanted into the insulating film IF1 become the same depth.

[0110] Furthermore, ion implantation procedures IMP1, IMP2, and IMP3 are performed at angles that differ from each other when viewed from above, and therefore the depths of these ion implantations differ. In ion implantation IMP1, where the angle of inclination from the direction of the trench TR1 is small, the depth of the ions implanted into the insulating film IF1 is greatest. In ion implantation IMP3, where the angle of inclination from the direction of the trench TR1 is close to 90 degrees, the depth of the ions implanted into the insulating film IF1 is smallest. In ion implantation IMP2, the depth of the ions implanted into the insulating film IF1 is the depth between that of ion implantation IMP1 and that of ion implantation IMP3.

[0111] As described above, even if the implantation angles in the cross-sectional view are the same as θ1, the depth distribution of the ions implanted into the insulating film IF1 can be controlled by making the implantation angles different from each other in the top view. In contrast to the multiple ion implantations IMP1 to IMP12, which are located at the implantation angle θ1 in Fig. 6. The multiple ion implantations IMP1 to IMP12 can also be performed at a variety of other implantation angles, such as at implantation angle θ2 in Fig. 6. This allows for more precise control of the depth distribution of the ions.

[0112] Although the second embodiment represents the case of performing twelve ion implantations IMP1 to IMP12, the number of ion implantations in the second embodiment is not limited to twelve and can be set to the required number of times if necessary. Third embodiment

[0113] A semiconductor device in a third embodiment is described below with reference to Fig. 22. It should be noted that the following description mainly describes differences from the first embodiment and omits descriptions of points that overlap with the first embodiment.

[0114] The case in which the ion implantations are carried out on the insulating film IF1 was described in the first embodiment, but in the third embodiment the ion implantations are carried out on the conductive film CF1.

[0115] Fig. Figure 22 shows a state of the execution of the ion implantations on the conductive film CF1 after the formation of the conductive film CF1 in Fig. 8 and before carrying out the etching treatment in Fig. 9. Impurities exhibiting an n-type conductivity are preferred for ion species in this ion implantation, and examples of such ion species are arsenic (As) or phosphorus (P). Specifically, the ion species in this ion implantation are preferably impurities of the same conductivity type as the conductivity type of the field plate electrode FP (of the conductive film CF1, of the conductive film CF2).

[0116] The ion implantations on the conductive film CF1 are performed in the same way as the ion implantations on the insulating film IF1. As in Fig. As shown in Figure 22, ion implantation on the conductive film CF1 is also carried out from directions inclined at predetermined angles (angle θ1, angle θ2, and the like) from the normal direction with respect to the upper surface TS of the semiconductor substrate SUB, just as ion implantation is carried out on the insulating film IF1. As the implantation angle increases, it becomes easier to implant the ions into the conductive film CF1 near the uppermost section of the trench TR1. By decreasing the implantation angle, the ions can be implanted not only into the vicinity of the uppermost section of the trench TR1, but also into the conductive film CF1 located further away from the uppermost section of the trench TR1.

[0117] The etch rate of the etching treatment in Fig. The etch rate differs between the point where ions are implanted and the point where they are not. At the point where ions are implanted, the etch rate is faster compared to the point where ions are not implanted. The etch rate increases at this point when a larger number of ions are implanted.

[0118] In the third embodiment, therefore, after the etching treatment in Fig. 9 The conductive film CF1, which is arranged at the uppermost section of the trench TR1, is thinner compared to that in the first embodiment. By forming the conductive film CF2 in Fig. 10 In this state, the conductive film CF2 can be satisfactorily embedded in the trench TR1 and the occurrence of the vacancy 20 can be further suppressed.

[0119] In the third embodiment, the multiple ion implantations can also be carried out using the technical idea similar to that in the second embodiment, from directions inclined at different angles to the direction of the trench TR1 (the Y-direction) in the top view.

[0120] As described in the first embodiment, even if each of the ion implantations and the etching treatment in Fig. 6 is not carried out on the insulating film IF1, moreover the formation procedure of the field plate electrode FP, which is carried out with reference to Fig. 8, Fig. 9, Fig. 10 to Fig. 11 is described as a method for suppressing the occurrence of the vacancy 20. This also applies to the third embodiment. modification

[0121] A semiconductor device in a modification of the third embodiment is described below with reference to Fig. 23 and Fig. 24 described. Fig. 23 and Fig. Figures 24 show a state of oxide film formation on the surface of the conductive film CF1 and the removal of this oxide film after ion implantation in Fig. 22 and before carrying out the etching treatment in Fig. 9.

[0122] As in Fig. As shown in Figure 23, the thermal oxidation treatment is performed on the conductive film CF1. This thermal oxidation treatment forms an oxide film OX1 on the surface of the conductive film CF1. At that time, ion implantation in Fig. 22. The thermal oxidation treatment was performed on an upper section of the conductive film CF1. Specifically, a larger quantity of n-type defects is present in the upper section of the conductive film CF1 than in the lower section. When the thermal oxidation treatment is performed in this state, the accelerated oxidation process accelerates the oxidation in the region containing the higher concentration of defects. Therefore, the oxide film OX1 forms thicker in the upper section of the conductive film CF1 than in the lower section.

[0123] As in Fig. As shown in Figure 24, the oxide film OX1 is subsequently removed by the etching treatment. The thickness of the conductive film CF1, which is left in place, is less at the upper part of the trench TR1 than at the lower part of the trench TR1. Wet etching using a solution containing hydrofluoric acid is used, for example, for this etching treatment.

[0124] By performing the etching treatment (for example, the dry etching treatment) on the conductive film CF1 in this state, the thickness of the conductive film CF1 located in the vicinity of the upper section of the trench TR1 can be reduced more than that in Fig. 9. Therefore, the conductive film CF2 can be embedded more satisfactorily in the trench TR1 and the occurrence of the vacancy 20 can be further suppressed.

Claims

[1] Method for manufacturing a semiconductor device (100) comprising the following: (a) Preparing a semiconductor substrate (SUB) of a first conductivity type, wherein the semiconductor substrate (SUB) has an upper surface (TS) and a lower surface (BS); (b) Forming a first trench (TR1) in the upper surface (TS) of the semiconductor substrate (SUB); (c) Forming a first insulating film (IF1) in the first trench (TR1) and on the upper surface (TS) of the semiconductor substrate (SUB); (d) Performing a first ion implantation on the first insulating film (IF1); (e) following (d) reducing the thickness of the first insulating film (IF1) by performing an etching treatment on the first insulating film (IF1); and (f) according to (e) forming a first conductive film (CF1) in the first trench (TR1) over the first insulating film (IF1), wherein in the top view the first trench (TR1) extends in a first direction, wherein in (d) the first ion implantation is carried out from a direction which is inclined by a first angle from a normal direction (10) with reference to the upper surface (TS) of the semiconductor substrate (SUB) in the cross-sectional view, where a second ion implantation is performed after the first ion implantation at (d), wherein the first ion implantation is performed from a direction inclined at a first angle from the first direction in the top view, wherein the second ion implantation is performed from a direction that is inclined to the first direction by a second angle that differs from the first angle in the top view, wherein the semiconductor device (100) comprises a cell region (CR) in which several MOSFETs are formed and an outer circumferential region (OR) that surrounds the cell region (CR) in a top view, where each of the multiple MOSFETs comprises: the first trench (TR1); the first insulating film (IF1); and a field plate electrode (FP) consisting of the first conductive film (CF1), wherein (b) a second trench (TR2) is formed in the upper surface (TS) of the semiconductor substrate (SUB) which is arranged in the outer circumferential region (OR), wherein the second trench (TR2) extends in the first direction and a second direction perpendicular to the first direction in the plan view, so that it surrounds the cell area (CR) in the plan view, and wherein each of the first ion implantation and the second ion implantation is performed from directions other than the first and directions other than directions inclined from the first direction by angles that are multiples of 90 degrees in the top view. [2] Method for manufacturing the semiconductor device (100) according to claim 1, wherein in the cross-sectional view the first trench (TR1) comprises: a ground surface (TR1b); and a side surface (TR1s) comprising the first insulating film (IF1) in the cross-sectional view: a first section formed on the side surface (TR1s) of the first trench (TR1) and arranged at an opening of the first trench (TR1); and a second section formed on the side surface (TR1s) of the first trench (TR1) and located closer to the bottom surface (TR1b) of the first trench (TR1) than to the opening of the first trench (TR1), wherein according to (e) a thickness of the first section is less than a thickness of the second section, and where the thickness of each of the first section and the second section is rather a thickness based on the side surface (TR1s) of the first trench (TR1) than a thickness based on the bottom surface (TR1b) of the first trench (TR1). [3] Method for manufacturing the semiconductor device (100) according to claim 1, wherein the second trench (TR2) has a corner section (TR2a) that couples a part extending in the first direction and a part extending in the second direction, wherein the corner section (TR2a) extends in a direction inclined at an angle of 45 degrees from the first direction or the second direction in the top view, and wherein each of the first ion implantation and the second ion implantation is performed from directions other than the first direction and directions other than directions inclined from the first direction by angles which are multiples of 45 degrees in the top view. [4] Method for manufacturing a semiconductor device comprising: (a) Preparing a semiconductor substrate (SUB) of a first conductivity type, wherein the semiconductor substrate (SUB) has an upper surface (TS) and a lower surface (BS); (b) Forming a first trench (TR1) in the upper surface (TS) of the semiconductor substrate (SUB); (c) Forming a first insulating film (IF1) in the first trench (TR1) and on the upper surface (TS) of the semiconductor substrate (SUB); (d) Performing a first ion implantation on the first insulating film (IF1); (e) following (d) reducing the thickness of the first insulating film (IF1) by performing an etching treatment on the first insulating film (IF1); and (f) according to (e) forming a first conductive film (CF1) in the first trench (TR1) over the first insulating film (IF1), wherein in the top view the first trench (TR1) extends in a first direction, wherein in (d) the first ion implantation is carried out from a direction which is inclined by a first angle from a normal direction (10) with reference to the upper surface (TS) of the semiconductor substrate (SUB) in the cross-sectional view, where (f) includes: (f1) after (e) forming the first conductive film (CF1) on the first insulating film (IF1), (f2) after (f1) reducing the thickness of the first conductive film (CF1) by performing an etching treatment on the first conductive film (CF1); and (f3) after (f2) forming a second conductive film (CF2) in the first trench (TR1) over the first insulating film (IF1) and the first conductive film (CF1) to fill the first trench (TR1), where (f) further includes: (f4) between (f1) and (f2) Performing an ion implantation on the first conductive film (CF1) from a direction inclined by a fifth angle from the normal direction (10) with reference to the upper surface (TS) of the semiconductor substrate (SUB). [5] Method for manufacturing the semiconductor device (100) according to claim 4, wherein (f) further comprises: (f5) between (f4) and (f2) Formation of an oxide film (OX1) on a surface of the first conductive film (CF1) by thermal oxidation treatment; and (f6) between (f5) and (f2) Removal of the oxide film (OX1) by etching treatment. [6] Method for manufacturing the semiconductor device (100) according to claim 4, further comprising: (g) according to (f) selectively withdrawing sections of a field plate electrode (FP) consisting of the first conductive film (CF1) and the second conductive film (CF2) formed in the first trench (TR1) according to (f3) so that part of the field plate electrode (FP) is left as a contact section; (h) after (g) retracting the first insulating film (IF1) such that a position of an upper surface (TS) of the first insulating film (IF1) is lower than a position of an upper surface (TS) of the field plate electrode (FP) in the first trench (TR1); (i) after (h) forming a gate insulating film (GI) in the first trench (TR1) on the first insulating film (IF1) and forming a second insulating film (IF2) on the top surface (TS) and a side surface of the field plate electrode (FP) that are exposed by the insulating film; and (j) after (i) forming a gate electrode (GE) on the field plate electrode (FP), which is withdrawn at (g) to fill the first trench (TR1). [7] Method for manufacturing the semiconductor device (100) according to claim 6, wherein according to (g) a width of the contact section in the cross-sectional view in a position of the upper surface (TS) of the semiconductor substrate (SUB) is greater than a width of the contact section at half depth from the upper surface (TS) of the semiconductor substrate (SUB) to a deepest section of the first trench (TR1). [8] Method for manufacturing the semiconductor device (100) according to claim 6, further comprising: (k) after (j) forming a body region (PB) of a second conductivity type opposite to the first conductivity type in the semiconductor substrate (SUB), such that in cross-sectional view it is shallower than the first trench (TR1); (l) after (k) forming a source area (NS) of the first conductivity type in the body area (PB); (m) after (l) forming an intermediate insulating film (IL) on the upper surface (TS) of the semiconductor substrate (SUB) to cover the first trench (TR1); (n) after (m) forming a first hole (CH1) reaching the source region (NS) and the body region (PB), a second hole (CH2) reaching the gate electrode (GE), and a third hole (CH3) reaching the contact section in the interlayer insulating film (IL); (o) after (n) forming a source electrode (SE) and a gate wiring (GW) surrounding the source electrode (SE) in plan view on the interlayer insulating film (IL); and (p) according to (o) forming a drain electrode (DE) below the lower surface (BS) of the semiconductor substrate (SUB), wherein the gate wiring (GW) is embedded in the second hole (CH2) and electrically connected to the gate electrode (GE), and wherein the source electrode (SE) is embedded in the first hole (CH1) and the third hole (CH3) and electrically connected to the source region (NS), the body region (PB) and the field plate electrode (FP). [9] Method for manufacturing the semiconductor device (100) according to claim 1, wherein (c) comprises: (c1) Forming a first silicon oxide film in the first trench (TR1) and on the upper surface (TS) of the semiconductor substrate (SUB) by a thermal oxidation process; and (c2) Forming a second silicon oxide film on the first silicon oxide film by a CVD process, wherein the first insulating film (IF1) comprises the first silicon oxide film and the second silicon oxide film. [10] Method for producing the semiconductor device (100) according to claim 9, wherein in (c1) the first silicon oxide film is formed such that the thickness of the first silicon oxide film is less than the thickness of the second silicon oxide film.

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