Deposition mask and deposition apparatus

Abstract

Deposition masks and deposition apparatuses are provided. A deposition mask includes a substrate including a plurality of cell regions and a rim region dividing the plurality of cell regions; a mask septum disposed on the plurality of cell regions of the substrate; a first line and a second line disposed on the rim region of the substrate, wherein the first line and the second line extend between adjacent cell regions of the plurality of cell regions, a first pad connected to the first line and configured to provide a first value of voltage to the first line from an outer edge of the substrate; and a second pad connected to the second line and configured to provide a second value of voltage to the second line from the outer edge of the substrate.

Description

Technical Field

[0001] This disclosure relates to a deposition mask and a deposition apparatus including the deposition mask. Background Technology

[0002] Wearable devices in the form of glasses or helmets have been developed, in which the focal point is formed at a distance close to the user's eyes. For example, the wearable device can be a head-mounted display (HMD) or augmented reality (hereinafter referred to as "AR") glasses. Such wearable devices can provide users with AR or virtual reality (referred to as "VR") visuals.

[0003] Some wearable devices (such as HMDs or AR glasses) may require display specifications of approximately 3000 PPI (pixels per inch) or higher, allowing users to use the devices for extended periods without experiencing dizziness. For this purpose, organic light-emitting diodes on silicon (OLEDoS) technology has emerged, enabling the provision of high-resolution, small organic light-emitting displays. OLEDoS technology involves placing organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which complementary metal-oxide-semiconductor (CMOS) semiconductors are disposed.

[0004] To fabricate high-resolution display panels with approximately 3000 ppi or higher, high-resolution deposition masks can be implemented. In this paper, for simplicity, "deposition mask" is also referred to as "mask". As deposition masks used for manufacturing OLEDoS display panels, masks are being investigated that deposit inorganic films on a silicon substrate and pattern the deposited inorganic films to form mask septa. However, in some cases, the gap between the mask and the deposition surface of the substrate may increase due to the weight of the mask septa formed by the inorganic film. This gap can lead to shading defects or color mixing defects. Utility Model Content

[0005] This disclosure provides a deposition mask capable of reducing shading or color mixing defects by reducing the gap between the deposition substrate and the mask, and a deposition apparatus including the deposition mask.

[0006] According to an aspect of this disclosure, a deposition mask includes: a substrate including a plurality of cell regions and edge regions dividing the plurality of cell regions; a mask diaphragm disposed on the plurality of cell regions of the substrate; a first line and a second line disposed on the edge regions of the substrate, wherein the first line and the second line extend between adjacent cell regions in the plurality of cell regions; a first pad connected to the first line and configured to provide a first value of voltage to the first line from an outer edge of the substrate; and a second pad connected to the second line and configured to provide a second value of voltage to the second line from the outer edge of the substrate.

[0007] In one embodiment, the first line and the second line are configured such that the first line and the second line are parallel to each other between the adjacent cell regions.

[0008] In an embodiment, when the substrate is viewed on a plane, each of the first line and the second line extends in a straight line.

[0009] In one embodiment, when the substrate is viewed on a plane, each of the first line and the second line extends according to an irregular shape.

[0010] In one embodiment, the first line and the second line generate electrostatic forces based on the voltage of the first value applied to the first line and the voltage of the second value applied to the second line to clamp the deposited substrate.

[0011] According to an aspect of this disclosure, a deposition apparatus includes a deposition source and a mask disposed between the deposition source and a deposition substrate, wherein the mask includes: a substrate including a plurality of cell regions and edge regions dividing the plurality of cell regions; a mask diaphragm disposed on the plurality of cell regions of the substrate; a first line and a second line disposed on the edge regions of the substrate, wherein the first line and the second line extend between adjacent cell regions in the plurality of cell regions; a first pad connected to the first line and configured to provide a first voltage value to the first line from an outer edge of the substrate; and a second pad connected to the second line and configured to provide a second voltage value to the second line from the outer edge of the substrate.

[0012] In one embodiment, the first line and the second line are configured such that the first line and the second line are parallel to each other between the adjacent cell regions.

[0013] In an embodiment, when the substrate is viewed on a plane, each of the first line and the second line extends in a straight line.

[0014] In one embodiment, when the substrate is viewed on a plane, each of the first line and the second line extends according to an irregular shape.

[0015] In one embodiment, the first line and the second line generate an electrostatic force based on the voltage of the first value applied to the first line and the voltage of the second value applied to the second line to clamp the deposited substrate.

[0016] Depending on the deposition mask and the deposition apparatus including the deposition mask, shading defects or color mixing defects can be reduced by decreasing the gap between the deposition substrate and the mask. Attached Figure Description

[0017] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0018] Figure 1 This is an exploded perspective view showing a display device according to an embodiment;

[0019] Figure 2 This is a block diagram illustrating a display device according to an embodiment;

[0020] Figure 3 This is an equivalent circuit diagram of the first sub-pixel according to an embodiment;

[0021] Figure 4 This is a layout diagram showing an example of a display panel according to an embodiment;

[0022] Figure 5 and Figure 6 It is shown Figure 4 A layout diagram of an embodiment of the display area;

[0023] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel taken by line I1-I1';

[0024] Figure 8 This is a perspective view showing a head-mounted display according to an embodiment;

[0025] Figure 9 It is shown Figure 8 An exploded perspective view of an example of a head-mounted display;

[0026] Figure 10 This is a perspective view showing a head-mounted display according to an embodiment;

[0027] Figure 11 This is a perspective view of the mask according to an embodiment;

[0028] Figure 12 This is a schematic plan view of the mask according to an embodiment;

[0029] Figure 13 This is a plan view showing the mask of the electrostatic line according to an embodiment;

[0030] Figure 14 It shows along Figure 13 A cross-sectional view of an example mask intercepted by line AB;

[0031] Figures 15 to 17 This is a cross-sectional view illustrating a method for manufacturing a mask according to an embodiment;

[0032] Figure 18This is a plan view showing a mask for an electrostatic line according to another embodiment;

[0033] Figure 19 It shows along Figure 18 Another example of a cross-sectional view of the mask intercepted by line AB;

[0034] Figure 20 This is a schematic diagram illustrating the configuration of a deposition apparatus according to an embodiment;

[0035] Figure 21 This is a block diagram of an electronic device according to an embodiment of the present disclosure; and

[0036] Figure 22 This is a schematic diagram of an electronic device according to various embodiments of the present disclosure. Detailed Implementation

[0037] Embodiments supported by this disclosure will now be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of this disclosure are illustrated. However, aspects supported by this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary aspects of this disclosure to those skilled in the art.

[0038] It will also be understood that when a layer or substrate is referred to as being "on" another layer or substrate, the layer or substrate may be directly on the other layer or substrate, or an intermediary layer may be present. Throughout the specification, the same reference numerals refer to the same components.

[0039] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the teachings of this disclosure, a first element discussed later may be referred to as a second element. Similarly, a second element may also be referred to as a first element.

[0040] Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity, the terms “about” or “approximately” as used herein include the stated value and a suitable range of deviations from the particular value as determined by one of ordinary skill in the art. For example, the terms “about” or “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0041] As used herein, the term "substantially" means approximately or actually. The term "substantially equal" means approximately equal or actually equal. The term "substantially identical" means approximately identical or actually identical. The term "substantially perpendicular" means approximately perpendicular or actually perpendicular. The term "substantially parallel" means approximately parallel or actually parallel.

[0042] Each of the features in the various embodiments of this disclosure can be combined in part or in whole with each other, and various interlocks and drives are technically possible. Each embodiment can be implemented independently of each other or can be implemented together in association.

[0043] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0044] Figure 1 This is an exploded perspective view showing a display device according to an embodiment. Figure 2 This is a block diagram illustrating a display device according to an embodiment.

[0045] Reference Figure 1 and Figure 2 The display device 10 according to the embodiment is a device for displaying moving or still images. The display device 10 according to the embodiment can be applied to portable electronic devices (such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, or ultra-mobile PCs (UMPCs). For example, the display device 10 according to the embodiment can be applied as a display unit in a television, laptop computer, monitor, billboard, or Internet of Things (IoT) terminal. Optionally, the display device 10 according to the embodiment can be applied to smartwatches, smartwatch phones, and head-mounted displays (HMDs) for realizing virtual and augmented reality.

[0046] The display device 10 according to an embodiment includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0047] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the angle at the intersection of the short side in the first direction DR1 and the long side in the second direction DR2 may be a right angle or be rounded with a predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to other polygonal shapes, circular shapes, or elliptical shapes. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but the embodiments of this disclosure are not limited thereto.

[0048] like Figure 2 As shown, the display panel 100 includes a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0049] The display area DAA includes multiple pixels (PX), multiple scan lines (SL), multiple emission control lines (EL), and multiple data lines (DL).

[0050] Multiple pixels (PX) can be arranged in a matrix on the first direction DR1 and the second direction DR2. Multiple scan lines (SL) and multiple emission control lines (EL) can extend on the first direction DR1 and be arranged on the second direction DR2. Multiple data lines (DL) can extend on the second direction DR2 and be arranged on the first direction DR1.

[0051] The multiple scan lines SL include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. The multiple emit control lines EL include multiple first emit control lines EL1 and multiple second emit control lines EL2.

[0052] Multiple pixels PX include multiple sub-pixels SP1, SP2, and SP3. The multiple sub-pixels SP1, SP2, and SP3 can include, for example... Figure 3 The multiple pixel transistors shown can be formed by semiconductor processes and disposed on a semiconductor substrate SSUB (see Figure 7 For example, multiple pixel transistors of multiple sub-pixels SP1, SP2, and SP3 can be formed by complementary metal-oxide-semiconductor (CMOS).

[0053] Each of the multiple sub-pixels SP1, SP2, and SP3 can be connected to a corresponding write scan line GWL among multiple write scan lines GWL, a corresponding control scan line GCL among multiple control scan lines GCL, a corresponding bias scan line GBL among multiple bias scan lines GBL, a corresponding first emission control line EL1 among multiple first emission control lines EL1, a corresponding second emission control line EL2 among multiple second emission control lines EL2, and a corresponding data line DL among multiple data lines DL. Each of the multiple sub-pixels SP1, SP2, and SP3 can receive the data voltage of the data line DL in response to the write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0054] The non-display area NDA includes a scan driver 610, a transmit driver 620, and a data driver 700.

[0055] The scan driver 610 includes multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB (see [reference needed]) using semiconductor processes. Figure 7 In CMOS, for example, multiple scanning transistors and multiple light-emitting transistors can be formed. Although in Figure 2 The diagram shows a scan driver 610 positioned on the left side of the display area DAA and a transmit driver 620 positioned on the right side of the display area DAA; however, embodiments of this disclosure are not limited thereto. For example, both the scan driver 610 and the transmit driver 620 may be positioned on the left or right side of the display area DAA.

[0056] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS from the timing control circuit 400, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line GBL.

[0057] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal according to the transmit timing control signal ECS and sequentially outputs the first transmit control signal to the first transmit control line EL1. The second transmit control driver 622 can generate a second transmit control signal according to the transmit timing control signal ECS and sequentially outputs the second transmit control signal to the second transmit control line EL2.

[0058] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB (see [reference needed]) using semiconductor processes. Figure 7 In, for example, multiple data transistors can be formed using CMOS.

[0059] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0060] The heat dissipation layer 200 may overlap the display panel 100 on a third-direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on the surface of the display panel 100 (e.g., on the rear surface of the display panel 100). The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer with high thermal conductivity (including, for example, silver (Ag), copper (Cu), or aluminum (Al)) or graphite.

[0061] Circuit board 300 can be electrically connected to the first pad portion of display panel 100 PDA1 (see [reference]) using conductive adhesive components such as anisotropic conductive film. Figure 4 Multiple first pads PD1 (see) Figure 4 Circuit board 300 can be a flexible printed circuit board or a flexible film made of flexible material. Although circuit board 300 is in Figure 1The circuit board 300 is shown unfolded, but it can be bent. In this case, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. This one end of the circuit board 300 can be a first pad portion of the circuit board 300 connected to the display panel 100 using a conductive adhesive component (see PDA1). Figure 4 Multiple first pads PD1 (see) Figure 4 The opposite end of the other end.

[0062] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0063] The power supply circuit 500 can generate multiple panel driving voltages based on external power voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. This will be discussed later. Figure 3 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0064] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to the surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0065] Optionally, similar to the scan driver 610, transmit driver 620, and data driver 700, each of the timing control circuit 400 and power supply circuit 500 may be located in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include multiple timing transistors, and each power supply circuit 500 may include multiple power transistors. The multiple timing transistors and multiple power transistors can be formed on a semiconductor substrate SSUB (see [link to semiconductor diagram]) using semiconductor processes. Figure 7 In, for example, multiple timing transistors and multiple power transistors can be formed by CMOS. Each of the timing control circuit 400 and the power supply circuit 500 can be disposed in the data driver 700 and the first pad portion of PDA1 (see...). Figure 4 )between.

[0066] Figure 3 This is an equivalent circuit diagram of the first sub-pixel according to an embodiment.

[0067] Reference Figure 3 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line EL1, the second emit control line EL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to a first drive voltage VSS corresponding to a low potential voltage (see...). Figure 2 The first driving voltage line VSL applied, and the second driving voltage VDD corresponding to the high potential voltage (see...) Figure 2 The second drive voltage line VDL and the third drive voltage VINT corresponding to the initialization voltage (see...) are applied. Figure 2 The third driving voltage line VIL is applied. That is, the first driving voltage line VSL can be a low-potential voltage line, the second driving voltage line VDL can be a high-potential voltage line, and the third driving voltage line VIL can be the initialization voltage line. In this case, the first driving voltage VSS can be lower than the third driving voltage VINT. The second driving voltage VDD can be higher than the third driving voltage VINT.

[0068] The first sub-pixel SP1 includes multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0069] The light-emitting element LE emits light in response to a drive current flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE can be proportional to the drive current. The light-emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE can be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the embodiments of this disclosure are not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in this case, the light-emitting element LE can be a miniature light-emitting diode.

[0070] The first transistor T1 may be a driving transistor that controls the source-drain current (also referred to herein as "drive current") flowing between the source and drain electrodes of the first transistor T1 according to the voltage applied to the gate electrode of the first transistor T1. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0071] A second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal to write scan line GWL, thereby connecting one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0072] A third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal controlling the scan line GCL to connect the first node N1 to the second node N2. For this purpose, since the gate and drain electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0073] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emitter control signal on the first emitter control line EL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0074] A fifth transistor T5 can be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0075] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by a second emitter control signal via the second emitter control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0076] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0077] A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second drive voltage line VDL.

[0078] The first node N1 is the junction between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is the junction between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is the junction between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0079] Each of the first transistors T1 to the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 can be a P-type MOSFET, but the embodiments of this disclosure are not limited thereto. Each of the first transistors T1 to the sixth transistor T6 can be an N-type MOSFET. Optionally, some of the first transistors T1 to the sixth transistor T6 can be P-type MOSFETs, and each of the remaining transistors can be an N-type MOSFET.

[0080] Despite Figure 3 The diagram shows the first sub-pixel SP1 comprising six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 3 As shown in the diagram. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 3 The number of transistors and capacitors in the first sub-pixel SP1 shown.

[0081] Furthermore, the second sub-pixel SP2 (see...) Figure 2 The equivalent circuit diagram of ) and the third sub-pixel SP3 (see Figure 2 The equivalent circuit diagram of ) can be combined with Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the descriptions of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 are not repeated in this disclosure.

[0082] Figure 4 This is a layout diagram showing an example of a display panel according to an embodiment.

[0083] Reference Figure 4 The display area DAA of the display panel 100 according to the embodiment includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to the embodiment includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0084] The scan driver 610 can be disposed on a first side of the display area DAA, and the transmit driver 620 can be disposed on a second side of the display area DAA. For example, the scan driver 610 can be disposed on one side of the display area DAA in the first direction DR1, and the transmit driver 620 can be disposed on the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 can be disposed on the left side of the display area DAA, and the transmit driver 620 can be disposed on the right side of the display area DAA. However, the embodiments of this disclosure are not limited thereto, and both the scan driver 610 and the transmit driver 620 can be disposed on either the first side or the second side of the display area DAA.

[0085] The first pad portion of PDA1 may include a connection to circuit board 300 via a conductive adhesive component (see...). Figure 1 Multiple first pads PD1 of pads or bumps. The first pad portion PDA1 can be located on the third side of the display area DAA. For example, the first pad portion PDA1 can be located on one side of the display area DAA in the second direction DR2.

[0086] The first pad portion of PDA1 can be positioned on the outside of the data driver 700 on the second direction DR2. That is, the first pad portion of PDA1 can be positioned closer to the edge of the display panel 100 than the data driver 700.

[0087] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to a fixture or probe pins during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a printed circuit board formed of a rigid material or a flexible printed circuit board formed of a flexible material.

[0088] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to multiple data lines DL (see...). Figure 3 For example, the first distribution circuit 710 can distribute the data voltage applied through a first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, and as a result, the number of multiple first pads PD1 can be reduced. The first distribution circuit 710 can be disposed on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 can be disposed on the lower side of the display area DAA.

[0089] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the plurality of pixels PX in the display area DAA. The second distribution circuit 720 can be disposed on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on the other side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 can be disposed on the upper side of the display area DAA.

[0090] Figure 5 and Figure 6 It is shown Figure 4 A layout diagram of an embodiment of the display area.

[0091] Reference Figure 5 and Figure 6 Multiple pixel PX (see Figure 4 Each of the sub-pixels includes a first emission region EA1 as the emission region of the first sub-pixel SP1, a second emission region EA2 as the emission region of the second sub-pixel SP2, and a third emission region EA3 as the emission region of the third sub-pixel SP3.

[0092] Each of the first launch area EA1, the second launch area EA2, and the third launch area EA3 can have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape in the plan view.

[0093] The maximum length of the third transmission region EA3 in the first direction DR1 can be less than the maximum length of the first transmission region EA1 in the first direction DR1 and the maximum length of the second transmission region EA2 in the first direction DR1. The maximum length of the first transmission region EA1 in the first direction DR1 and the maximum length of the second transmission region EA2 in the first direction DR1 can be substantially the same.

[0094] The maximum length of the third transmission region EA3 in the second direction DR2 can be longer than the maximum length of the first transmission region EA1 in the second direction DR2 and the maximum length of the second transmission region EA2 in the second direction DR2. The maximum length of the first transmission region EA1 in the second direction DR2 can be longer than the maximum length of the second transmission region EA2 in the second direction DR2.

[0095] like Figure 5 and Figure 6As shown, each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a hexagonal shape formed by six straight lines in the plan view, but the embodiments of this disclosure are not limited thereto. Each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape other than a hexagon in the plan view.

[0096] like Figure 5 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the second direction DR2. Furthermore, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. In some aspects, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the first direction DR1. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different.

[0097] Optionally, such as Figure 6 As shown, the first transmission region EA1 and the second transmission region EA2 can be adjacent to each other in the first direction DR1, but the second transmission region EA2 and the third transmission region EA3 can be adjacent to each other in the first diagonal direction DD1, and the first transmission region EA1 and the third transmission region EA3 can be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to the direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be the direction perpendicular to the first diagonal direction DD1.

[0098] The first emission region EA1 can emit light of a first color, the second emission region EA2 can emit light of a second color, and the third emission region EA3 can emit light of a third color. Here, the first color light can be light in the blue wavelength range, the second color light can be light in the green wavelength range, and the third color light can be light in the red wavelength range. For example, the blue wavelength range can be the wavelength range of light whose main peak wavelength is in the range of about 370 nm to about 460 nm, the green wavelength range can be the wavelength range of light whose main peak wavelength is in the range of about 480 nm to about 560 nm, and the red wavelength range can be the wavelength range of light whose main peak wavelength is in the range of about 600 nm to about 750 nm.

[0099] exist Figure 5 and Figure 6In the example, each of the plurality of pixels PX includes three emission regions EA1, EA2, and EA3, but the embodiments of this disclosure are not limited thereto. That is, each of the plurality of pixels PX may include four emission regions.

[0100] In some respects, the layout of the emission regions of multiple pixel PXs is not limited to Figure 5 and Figure 6 The layout is shown in the figure. For example, the emission regions of multiple pixels PX can be configured as a strip structure in which the emission regions are arranged in a first direction DR1, or in a diamond shape. A structure or a hexagonal structure in which emitting regions with a hexagonal shape are arranged in a plan view (e.g.) Figure 6 (as shown in the image).

[0101] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel taken by line I1-I1'.

[0102] Reference Figure 7 The display panel 100 includes a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), an encapsulation layer (TFE), an organic film (APL), a cover layer (CVL), and a polarizing plate (POL).

[0103] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films (SINS1 to SINS3) covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be a reference. Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0104] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be disposed on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. In an example where the first type of impurity is a P-type impurity, the second type of impurity can be an N-type impurity. Optionally, when the first type of impurity is an N-type impurity, the second type of impurity can be a P-type impurity.

[0105] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0106] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can be disposed on the lower insulating film (BINS).

[0107] Each of the source region SA and drain region DA can be a region doped with type I impurities. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on the third-direction DR3. The channel region CH can overlap with the gate electrode GE on the third-direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0108] Each of the multiple well regions WA also includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region with a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region with a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The distance between the source region SA and the drain region DA can be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH of each of the multiple pixel transistors PTR can be increased, thereby reducing or preventing punch-through (or breakdown) and hot carrier phenomena that may be caused by short channels.

[0109] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be made of silicon carbonitride (SiCN) or silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0110] The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0111] Multiple contact terminals (CTEs) can be disposed on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each of the multiple pixel transistors (PTRs) through holes penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or alloys thereof.

[0112] A third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the plurality of contact terminals (CTEs). The top surface of each of the plurality of contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3). The third semiconductor insulating film (SINS3) can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0113] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate, such as a polyimide substrate. In this case, the thin-film transistor can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, while the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0114] The backplane (EBP) of the light-emitting element includes multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS9. In some aspects, the backplane (EBP) of the light-emitting element includes multiple insulating films INS2 to INS8 disposed between the first conductive layers ML1 to the eighth conductive layers ML8.

[0115] The first conductive layers ML1 to the eighth conductive layers ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving Figure 3 The circuitry for the first sub-pixel SP1 is shown. For example, the first transistor T1 (see...) Figure 3 ) to the sixth transistor T6 (see Figure 3 The first transistor T1 to the sixth transistor T6 and the first capacitor CP1 (see [reference]) are formed in the semiconductor backplane SBP (e.g., not in a portion different from the semiconductor backplane SBP), and are formed in the semiconductor backplane SBP. Figure 3 ) and the second capacitor CP2 (see Figure 3 The connection is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. In some aspects, this corresponds to the fourth transistor T4 (see...). Figure 3 The drain region of the drain electrode of the fifth transistor T5 (see...) Figure 3The connection between the source region of the source electrode of the light-emitting element LE and the first electrode AND is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0116] A first insulating film INS1 may be disposed on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first insulating film INS1 and connect to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be disposed on the first insulating film INS1 and may connect to the first via VA1.

[0117] A second insulating film INS2 can be disposed on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 can penetrate the second insulating film INS2 and connect to the exposed first conductive layer ML1. Each of the second conductive layers ML2 can be disposed on the second insulating film INS2 and can connect to the second via VA2.

[0118] A third insulating film INS3 may be disposed on the second insulating film INS2 and the second conductive layer ML2. Each of the third vias VA3 may penetrate the third insulating film INS3 and be connected to the exposed second conductive layer ML2. Each of the third conductive layers ML3 may be disposed on the third insulating film INS3 and may be connected to the third via VA3.

[0119] A fourth insulating film INS4 can be disposed on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth vias VA4 can penetrate the fourth insulating film INS4 and connect to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 can be disposed on the fourth insulating film INS4 and can connect to the fourth via VA4.

[0120] A fifth insulating film INS5 can be disposed on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 can penetrate the fifth insulating film INS5 and connect to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 can be disposed on the fifth insulating film INS5 and can connect to the fifth via VA5.

[0121] A sixth insulating film INS6 can be disposed on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 can penetrate the sixth insulating film INS6 and connect to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 can be disposed on the sixth insulating film INS6 and can connect to the sixth via VA6.

[0122] A seventh insulating film INS7 can be disposed on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 can penetrate the seventh insulating film INS7 and connect to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 can be disposed on the seventh insulating film INS7 and can connect to the seventh via VA7.

[0123] An eighth insulating film INS8 can be disposed on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 can penetrate the eighth insulating film INS8 and connect to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 can be disposed on the eighth insulating film INS8 and can connect to the eighth via VA8.

[0124] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or alloys thereof. The first insulating films INS1 to INS8 can be formed of substantially the same material. The first insulating films INS1 to INS8 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0125] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be approximately... The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately The thickness of each of the following vias can be approximately: VA1 (first via), VA2 (second via), VA3 (third via), VA4 (fourth via), VA5 (fifth via), and VA6 (sixth via).

[0126] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately... The thickness of each of the seventh via VA7 and the eighth via VA8 can be approximately

[0127] The ninth insulating film INS9 can be disposed on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0128] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 and connect to the exposed eighth conductive layer ML8. The ninth vias VA9 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys thereof. The thickness of the ninth via VA9 can be approximately...

[0129] The display element layer EML can be disposed on the light-emitting element backplane EBP. The display element layer EML may include light-emitting elements LE and pixel-defining films PDL. Each light-emitting element LE includes a reflective electrode layer RL, a tenth insulating film INS10 and an eleventh insulating film INS11, a tenth via VA10, a first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0130] A reflective electrode layer RL can be disposed on the ninth insulating film INS9. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, as... Figure 7 As shown, the reflective electrode layer RL may include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0131] Each of the first reflective electrodes RL1 can be disposed on the ninth insulating film INS9 and can be connected to the ninth via VA9. The first reflective electrodes RL1 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys or nitrides thereof. For example, the first reflective electrode RL1 may include titanium nitride (TiN).

[0132] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrodes RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or alloys thereof. For example, the second reflective electrode RL2 may include aluminum (Al).

[0133] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys or nitrides thereof. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0134] Each of the fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or alloys thereof. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0135] Since the second reflective electrode RL2 is essentially the electrode that reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately... And the thickness of the second reflective electrode RL2 can be approximately

[0136] The tenth insulating film INS10 can be disposed on the ninth insulating film INS9. The tenth insulating film INS10 can be disposed between horizontally adjacent reflective electrode layers RL. The tenth insulating film INS10 can be made of silicon oxide (SiO2). x Inorganic membranes of this type can be formed, but the embodiments disclosed herein are not limited thereto.

[0137] The eleventh insulating film INS11 can be disposed on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 can be made of silicon oxide (SiO2). x The inorganic film is formed, but the embodiments disclosed herein are not limited thereto. The tenth insulating film INS10 and the eleventh insulating film INS11 may be optical auxiliary layers through which light reflected by the reflective electrode layer RL passes in the light emitted from the light-emitting element LE.

[0138] To match the resonant distance of the light emitted by the light-emitting element LE from at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the tenth insulating film INS10 or the eleventh insulating film INS11 may not be disposed below the first electrode AND. For example, the first electrode AND of the first sub-pixel SP1 may be disposed directly on the reflective electrode layer RL. The eleventh insulating film INS11 may be disposed below the first electrode AND of the second sub-pixel SP2. The tenth insulating film INS10 and the eleventh insulating film INS11 may be disposed below the first electrode AND of the third sub-pixel SP3.

[0139] In summary, the distance between the first electrode AND and the reflective electrode layer RL can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the dominant wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the tenth insulating film INS10 and the eleventh insulating film INS11 can be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. This disclosure is not limited to the above examples.

[0140] In some aspects, although a tenth insulating film INS10 and an eleventh insulating film INS11 are shown in this disclosure, a twelfth insulating film may be additionally disposed below the first electrode AND of the first sub-pixel SP1. In this case, the eleventh insulating film INS11 and the twelfth insulating film may be disposed below the first electrode AND of the second sub-pixel SP2, and the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be disposed below the first electrode AND of the third sub-pixel SP3.

[0141] Each of the tenth vias VA10 can penetrate the tenth insulating film INS10 and / or the eleventh insulating film INS11 in the second sub-pixel SP2 and the third sub-pixel SP3, and can be connected to the exposed reflective electrode layer RL. The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys thereof. The thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0142] The first electrode AND of each of the light-emitting elements LE can be disposed on the eleventh insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the first reflective electrodes RL1 to the fourth reflective electrodes RL4, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys or nitrides thereof. For example, the first electrode AND of each of the light-emitting elements LE can be titanium nitride (TiN).

[0143] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can be used to delineate a first emission region EA1, a second emission region EA2, and a third emission region EA3.

[0144] The first emission region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0145] The pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be disposed on the edge of the first electrode AND of each of the light-emitting elements (LEs). The second pixel-defining film (PDL2) may be disposed on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be disposed on the second pixel-defining film (PDL2). The first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may be made of silicon oxide (SiO2). x The inorganic film is formed, but the embodiments disclosed herein are not limited thereto. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 may each have approximately The thickness.

[0146] When the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 form a single pixel defining film, the height of this single pixel defining film increases, making the first encapsulating inorganic film TFE1 potentially cut due to step coverage. Step coverage refers to the ratio of the degree of film coating on the inclined portion to the degree of film coating on the flat portion. The lower the step coverage, the more likely the film is to be cut at the inclined portion.

[0147] Therefore, according to one or more embodiments of this disclosure, in order to reduce or prevent the possibility of the first encapsulated inorganic film TFE1 being cut due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure with a stepped portion. For example, the width of the first pixel defining film PDL1 may be greater than the width of the second pixel defining film PDL2 and the width of the third pixel defining film PDL3, and the width of the second pixel defining film PDL2 may be greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1 refers to the horizontal length of the first pixel defining film PDL1 defined in the first direction DR1 and the second direction DR2.

[0148] The light-emitting stack IL can include multiple intermediate layers. The light-emitting stack IL includes a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3 that emit different lights. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 are discontinuous between adjacent sub-pixels.

[0149] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The first stacked layer IL1 is disposed in the first emission region EA1 of the first sub-pixel SP1 on the first electrode AND and the pixel defining film PDL.

[0150] The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The second stacked layer IL2 is disposed in the second emission region EA2 of the second sub-pixel SP2 on the first electrode AND and the pixel defining film PDL.

[0151] The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of the second color, and a third electron transport layer are sequentially stacked. The third stacked layer IL3 is disposed on the first electrode AND and the pixel defining film PDL in the third emission region EA3 of the third sub-pixel SP3.

[0152] The second electrode CAT can be disposed on the third stacked layer IL3 and the pixel-defining film PDL. The second electrode CAT can be formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. In the example where the second electrode CAT is formed of a semi-transmissive conductive material, the light emission efficiency can be improved in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 due to the microcavity effect.

[0153] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1 and TFE2 to reduce or prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0154] The first encapsulating inorganic film TFE1 can be disposed on the second electrode CAT. The first encapsulating inorganic film TFE1 can be formed in which silicon nitride (SiN) is selected. x ) membrane, silicon oxynitride (SiO) x N y ) film and silicon dioxide (SiO) xA multilayer of two or more inorganic films stacked alternately. The first encapsulating inorganic film TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0155] The second encapsulating inorganic film TFE2 can be disposed on the first encapsulating inorganic film TFE1. The second encapsulating inorganic film TFE2 can be made of titanium oxide (TiO2). x ) or aluminum oxide (AlO x The second encapsulation inorganic film TFE2 can be formed by atomic layer deposition (ALD). The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0156] Organic film APL can be a layer used to increase the interfacial adhesion between the encapsulation layer TFE and the cover layer CVL. Organic film APL can be an organic film containing materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0157] The CVL (capping layer) can be deposited on the organic membrane APL. The CVL can be a glass substrate or a polymer resin substrate.

[0158] A polarizing plate (POL) can be disposed on the surface of a CVL (containerless glass layer). The polarizing plate (POL) can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizing plate (POL) can include a linear polarizing plate and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but embodiments of this disclosure are not limited thereto.

[0159] Figure 8 This is a perspective view showing a head-mounted display according to an embodiment. Figure 9 It is shown Figure 8 An exploded perspective view of an example of a head-mounted display.

[0160] Reference Figure 8 and Figure 9 According to an embodiment, the head-mounted display 1000 includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0161] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. Because each of the first display device 10_1 and the second display device 10_2 is combined with... Figure 1 and Figure 2The display devices 10 described are substantially the same, so the description of the first display device 10_1 and the second display device 10_2 will be omitted.

[0162] The first optical component 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0163] The intermediate frame 1400 can be disposed between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0164] The control circuit board 1600 can be positioned between the intermediate frame 1400 and the display device housing 1100.

[0165] The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data (DATA). Figure 2 The digital video data DATA is transmitted to the first display device 10_1 and the second display device 10_2 via a connector.

[0166] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Optionally, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0167] The display device housing 1100 is used to house a first display device 10_1, a second display device 10_2, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. The housing cover 1200 is configured to cover an opening surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 8 and Figure 9 The first eyepiece 1210 and the second eyepiece 1220 are shown to be separately configured, but the embodiments of this disclosure are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0168] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can observe the image of the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can observe the image of the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0169] A headband 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned over the user's left and right eyes, respectively. In an example where the display device housing 1100 is implemented as lightweight and compact, the head-mounted display 1000 can be provided as follows: Figure 10 The eyeglasses frame shown is not the headband 1300.

[0170] In some aspects, the head-mounted display 1000 may also include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0171] Figure 10 This is a perspective view showing a head-mounted display according to an embodiment.

[0172] Reference Figure 10 The head-mounted display 1000_1 according to an embodiment may be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to an embodiment may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, an optical path changing component 1070, and a display device housing 1200_1.

[0173] The display device housing 1200_1 may include a display device 10_3, an optical component 1060, and a light path changing component 1070. The image displayed on the display device 10_3 can be magnified by the optical component 1060, and the image can be provided to the user's right eye via the right eye lens 1020 after the light path of the image is changed by the light path changing component 1070. As a result, the user can observe an augmented reality image, which combines a virtual image displayed on the display device 10_3 with a real image seen through the right eye lens 1020, through their right eye.

[0174] Figure 10 The illustration shows the display device housing 1200_1 located at the right end of the support frame 1030, but the embodiments of this disclosure are not limited thereto. For example, the display device housing 1200_1 may be located at the left end of the support frame 1030, and in this case, the image displayed on the display device 10_3 can be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be located at both the left and right ends of the support frame 1030, and in this case, the user can view the image displayed on the display device 10_3 through both the left and right eyes.

[0175] Figure 11 This is a perspective view of the mask according to an embodiment. Figure 12 This is a schematic plan view of the mask according to an embodiment. Figure 11 This shows a perspective view of the state in which a unit mask UM is separated from multiple unit masks. According to Figure 11 and Figure 12 The mask shown in the embodiment can be used in the reference Figure 7 The process described involves at least a portion of the deposition of a light-emitting stack IL. For example, the light-emitting stack IL can be configured to emit light of a different color in each of the sub-pixels SP1, SP2, and SP3.

[0176] Reference Figure 11 and Figure 12 According to an embodiment, the mask MK can be a shadow mask in which a mask diaphragm MM is disposed on a silicon substrate 1700. The mask MK according to an embodiment can be referred to as a "silicon mask".

[0177] According to an embodiment, the mask MK may include a silicon substrate 1700, and a mask diaphragm MM may be disposed on the silicon substrate 1700. The mask diaphragm MM may be disposed in cell regions 1710 arranged in a matrix, and each cell region 1710 may be surrounded by a mask lip region 1721. The mask lip region 1721 may accommodate a portion of the silicon substrate 1700 disposed in the mask lip region 1721, and may be used to support the mask diaphragm MM.

[0178] The mask diaphragm MM can be a portion of the unit mask UM set in each of multiple cell regions 1710.

[0179] The silicon substrate 1700 may include a plurality of cell regions 1710 and a mask frame region 1720 in addition to the plurality of cell regions 1710. The mask frame region 1720 may include a mask edge region 1721 surrounding each cell region 1710 and an outer frame region 1722 disposed at the outermost edge of the silicon substrate 1700. A mask frame MF may be disposed in the mask frame region 1720, and the mask frame MF may include a mask edge surrounding the cell regions 1710.

[0180] The mask edge region 1721 can be a region divided into multiple cell regions 1710. For example, the multiple cell regions 1710 can be arranged in a matrix, and the mask edge provided in the mask edge region 1721 can be configured to surround the outer edge of the mask diaphragm MM provided in each cell region 1710.

[0181] Cell openings (COPs) and unit masks (UMs) for masking at least a portion of the cell openings (COPs) can be disposed in each of the plurality of cell regions 1710 of the silicon substrate 1700.

[0182] Multiple cell openings (COPs) can penetrate the mask frame MF along the thickness direction of the mask MK (e.g., third-direction DR3). Multiple cell openings (COPs) can be formed by etching a portion of the silicon substrate 1700 from the rear direction.

[0183] Each unit mask UM may include a mask diaphragm MM, and the mask diaphragm MM may include a mask opening OP.

[0184] The mask opening OP of the mask diaphragm MM can be referred to as a "hole" or "mask hole". The mask opening OP can penetrate the unit mask UM along the thickness direction of the mask MK (e.g., third direction DR3).

[0185] One unit mask UM can be used in a display panel 100 (see Figure 1 In the deposition process of ), the term "unit mask UM" may be replaced by a term such as mask unit UM.

[0186] Figure 13 This is a plan view showing the mask of the electrostatic line according to an embodiment. Figure 14 It shows along Figure 13 A cross-sectional view of an example mask intercepted by line AB. For example, in Figure 13 and Figure 14 At least a portion of the mask shown in each of them can be similar to Figure 12 The mask shown.

[0187] Reference Figure 13 and Figure 14 According to the embodiment, the mask MK (see Figure 11 The device includes a substrate 1700, which includes a plurality of cell regions 1710 and a mask edge region 1721 that divides the plurality of cell regions 1710. For example, the mask edge region 1721 may divide the plurality of cell regions 1710 into multiple groups of cell regions 1710. Here, the substrate 1700 may be a silicon substrate 1700.

[0188] The mask diaphragm MM can be disposed in multiple cell regions 1710, and cell openings COPs of the mask diaphragm MM can be formed to expose the lower surface of the substrate 1700.

[0189] The cell opening COP can be formed by etching a portion of the substrate 1700. The remaining area of ​​the substrate 1700 after the process of forming the cell opening COP can become the mask frame area 1720 (see...). Figure 12 The mask frame region 1720 can be divided into a mask edge region 1721 surrounding each cell region 1710 and an outer frame region 1722 disposed on the outermost edge of the silicon substrate 1700. Here, the mask edge 1701 surrounding the cell region 1710 is disposed in the mask edge region 1721, and the electrostatic line 1810 is disposed on the mask edge 1701.

[0190] The mask diaphragm MM may include an inorganic membrane 1910 containing multiple openings OP. The inorganic membrane 1910 may contain materials selected from silicon (Si) and silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ), amorphous silicon (a-Si) and aluminum oxide (AlO) x At least one of the following materials.

[0191] The electrostatic line 1810 may be an electrostatic chuck or part of an electrostatic chuck. For example, the electrostatic line 1810 may be disposed as an electrostatic chuck (or part of an electrostatic chuck) on the mask edge region 1721 of the substrate 1700. The electrostatic line 1810 may include at least one line for generating electrostatic forces. The electrostatic line 1810 may clamp (e.g., electrostatically attract or hold) the deposited substrate 2020 (see [link to deposition process]) during the deposition process. Figure 20 ) or release the clamped depositional substrate 2020 (see Figure 20In the example where a specific voltage is applied to the electrostatic wire 1810, the electrostatic wire 1810 clamps the deposition substrate 2020. If no specific voltage is applied to the electrostatic wire 1810, the electrostatic wire 1810 can release the deposition substrate 2020.

[0192] According to an embodiment, the electrostatic wire 1810 can be bipolar or unipolar. In an example where the electrostatic wire 1810 is bipolar, it may include two wires (i.e., a first wire 1811 and a second wire 1812). In an example where the electrostatic wire 1810 is unipolar, it may include a single wire.

[0193] In the following description, the focus will be primarily on the fact that the electrostatic wire 1810 is bipolar, but the embodiments of this disclosure are not limited thereto.

[0194] According to an embodiment, the electrostatic wire 1810 may include a first wire 1811 and a second wire 1812. Figure 13 In the diagram, the first line 1811 is shown as a solid line, and the second line 1812 is shown as a dashed line. As shown, the first line 1811 and the second line 1812 extend in the first direction DR1 between adjacent cell regions 1710 (e.g., cell regions 1710 adjacent to each other in the second direction DR2). For example, the first line 1811 and the second line 1812 may traverse the region located between adjacent cell regions 1710. For example, each of the first line 1811 and the second line 1812 is disposed on the substrate 1700 and extends in the first direction DR1.

[0195] According to an embodiment, the first line 1811 and the second line 1812 are configured such that the first line 1811 and the second line 1812 are parallel to each other between adjacent cell regions 1710. The first line 1811 and the second line 1812 may also be configured such that the first line 1811 and the second line 1812 are spaced apart between adjacent cell regions 1710.

[0196] According to an embodiment, the mask MK may further include a pad portion 1820 that provides voltage from the outer edge of the substrate 1700 to the electrostatic line 1810. The pad portion 1820 includes a first pad 1821 and a second pad 1822, the first pad 1821 being configured to provide a positive voltage from the outer edge of the substrate 1700 to the first line 1811, and the second pad 1822 being configured to provide a negative voltage from the outer edge of the substrate 1700 to the second line 1812. In the example, the deposition apparatus described herein may apply or provide a positive voltage to the first line 1811 via the first pad 1821, and the deposition apparatus may apply or provide a negative voltage to the second line 1812 via the second pad 1822. For example, the first pad 1821 and the second pad 1822 may be disposed in either region of the outer frame region 1722.

[0197] The first pad 1821 is configured to receive a positive voltage from the outside and supply the received positive voltage to the first line 1811. The second pad 1822 is configured to receive a negative voltage from the outside and supply the received negative voltage to the second line 1812.

[0198] In this disclosure, a positive voltage can mean a voltage with a relatively high potential compared to a negative voltage. In this disclosure, a negative voltage can mean a voltage with a relatively low potential compared to a positive voltage.

[0199] The positive voltage disclosed herein may be referred to by terms such as "first voltage", "high potential voltage" and "voltage of first value".

[0200] The negative voltage disclosed herein may be referred to by terms such as "second voltage", "low potential voltage" and "voltage of second value".

[0201] Figures 15 to 17 This is a cross-sectional view illustrating a method for manufacturing a mask according to an embodiment. For example, Figures 15 to 17 It can be based on Figure 14 The following is an example of the sequence of the mask manufacturing process in the embodiment shown. Referring below, [the text continues with further details]. Figures 15 to 17 The following describes a method for manufacturing a mask according to an embodiment.

[0202] In the description of the methods and processes herein, operations may be performed in a different order than those shown and / or described, or in a different order or at different times. Certain operations may also be omitted from the flowchart, one or more operations may be repeated, or additional operations may be added. Descriptions of elements as "can be set up" and "can be formed" include methods, processes, and techniques for setting up, forming, positioning, and modifying elements, etc., based on the exemplary aspects described herein.

[0203] Reference Figure 15 The substrate 1700 can be prepared. The substrate 1700 can be a silicon substrate 1700. The substrate 1700 can be referred to as a "host substrate" or a "film substrate", but the embodiments of this disclosure are not limited thereto.

[0204] In an example of fabricating substrate 1700, the method may include forming electrostatic lines 1810 on substrate 1700. Electrostatic lines 1810 include a first line 1811 and a second line 1812, and are formed corresponding to mask edge region 1721. Electrostatic lines 1810 may be formed from any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0205] Reference Figure 16 After forming electrostatic lines 1810 on the substrate 1700, the method may include forming a mask diaphragm MM by using an inorganic membrane 1910. The inorganic membrane 1910 may comprise a single layer or multiple layers.

[0206] According to an embodiment, the inorganic film 1910 may comprise a monolayer and may contain materials selected from silicon (Si) and silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ), amorphous silicon (a-Si) and aluminum oxide (AlO) x At least one of the following materials.

[0207] According to an embodiment, the inorganic membrane 1910 may include a first inorganic membrane and a second inorganic membrane as a multilayer. In this case, the first inorganic membrane may contain silicon oxide (SiO2). x Furthermore, the second inorganic film may contain silicon nitride (SiN). x However, the material of each of the first and second inorganic films is not limited thereto. For example, the material of each of the first and second inorganic films may comprise silicon (Si), silicon nitride (SiN), etc. x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ), amorphous silicon (a-Si) and aluminum oxide (AlO) x At least one of the following materials.

[0208] After depositing the inorganic film 1910 on the substrate 1700, the method may include performing a patterning process of the inorganic film 1910 in association with the formation of a plurality of openings OP. The patterning process of the inorganic film 1910 may include forming a photoresist pattern on the inorganic film 1910 and etching a portion of the inorganic film 1910 using the photoresist pattern as a mask. The etching process of the inorganic film 1910 may include a wet etching process or a dry etching process.

[0209] Reference Figure 17 After forming a mask diaphragm MM using an inorganic membrane 1910, the method may include forming a cell opening COP. The method may include forming the cell opening COP by etching a portion of the substrate 1700 in a rearward direction.

[0210] The area of ​​substrate 1700 retained during the process of forming the cell opening COP becomes the mask frame region 1720 (see...). Figure 12 The mask frame region 1720 can be divided into a mask edge region 1721 surrounding each cell region 1710 and an outer frame region 1722 disposed at the outermost edge of the silicon substrate 1700. Here, the mask edge 1701 surrounding the cell region 1710 is disposed in the mask edge region 1721, and the electrostatic line 1810 is disposed on the mask edge 1701.

[0211] Figure 18 This is a plan view showing a mask for an electrostatic line according to another embodiment.

[0212] Figure 18 Implementation examples and Figure 13 The difference in this embodiment is that the electrostatic wire 1810 has an irregular shape. In the following, reference is made to... Figure 18 The description will be related to Figure 13 The differences are as follows. For the sake of brevity, repeated descriptions of the same components have been omitted. References will be used... Figure 13 The description is used to replace the description with Figure 18 Related undescribed features.

[0213] Reference Figure 18 According to the embodiment, the mask MK (see Figure 11 It includes an electrostatic wire 1810 containing a first wire 1811 and a second wire 1812.

[0214] According to an embodiment, the first line 1811 and the second line 1812 are configured such that the first line 1811 and the second line 1812 are parallel to each other between adjacent cell regions 1710. The first line 1811 and the second line 1812 may also be configured such that the first line 1811 and the second line 1812 are spaced apart between adjacent cell regions 1710.

[0215] According to an embodiment, when the substrate 1700 is viewed in a plane, each of the first line 1811 and the second line 1812 extends in an irregular shape (e.g., a wavy line). The irregular shape of each of the first line 1811 and the second line 1812 increases the electrostatic line 1810 relative to the deposition substrate 2020 (see embodiment). Figure 20 The corresponding area (e.g., relative to the second direction DR2). For example, with according to Figure 13 In the embodiment, the electrostatic line 1810, compared to the corresponding area of ​​the deposition substrate 2020, according to Figure 18 In this embodiment, the electrostatic line 1810 has a larger corresponding area relative to the deposition substrate 2020 (e.g., relative to the second direction DR2).

[0216] exist Figure 18In one embodiment, by increasing the corresponding area of ​​the electrostatic wires 1810 relative to the deposition substrate 2020, the electrostatic wires 1810 of the mask MK can more effectively clamp (e.g., electrostatically attract or fix) the deposition substrate 2020 and reduce the gap between the deposition substrate 2020 and the mask MK. In the example of reduced gap between the deposition substrate 2020 and the mask MK, shadowing defects can be reduced during the deposition process.

[0217] Figure 19 It shows along Figure 18 Another example of a cross-sectional view of a mask cut by line AB.

[0218] Figure 19 Implementation examples and Figure 14 The difference in this embodiment is that an insulating film 1920 is formed below the electrostatic line 1810. In the following, refer to... Figure 19 The description will be related to Figure 14 The differences are as follows. For the sake of brevity, repeated descriptions of the same components have been omitted. References will be used... Figure 14 The description is used to replace the description with Figure 19 Related undescribed features.

[0219] Reference Figure 19 Mask MK (see Figure 11 It includes an electrostatic wire 1810 containing a first wire 1811 and a second wire 1812.

[0220] According to an embodiment, the first line 1811 and the second line 1812 are configured such that the first line 1811 and the second line 1812 are parallel to each other between adjacent cell regions 1710. The first line 1811 and the second line 1812 may also be configured such that the first line 1811 and the second line 1812 are spaced apart between adjacent cell regions 1710.

[0221] According to an embodiment, the insulating film 1920 may be disposed below the first line 1811 and the second line 1812. For example, the mask MK may also include the insulating film 1920 disposed between the substrate 1700 and each of the first line 1811 and the second line 1812.

[0222] According to an embodiment, the insulating film 1920 comprises an inorganic film. For example, the insulating film 1920 may contain materials selected from silicon (Si) and silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ), amorphous silicon (a-Si) and aluminum oxide (AlO) x Inorganic membrane of at least one of the following materials:

[0223] The insulating film 1920 can prevent the flow of static electricity from the electrostatic wire 1810 to a portion of the deposition equipment (e.g., during the deposition process) Figure 20 The leakage current of the chamber 2010. The insulating film 1920 may include materials with high heat resistance and chemical stability. For example, the insulating film 1920 may include yttrium oxide and aluminum oxide.

[0224] Figure 20 This is a schematic diagram illustrating the configuration of a deposition apparatus according to an embodiment.

[0225] Reference Figure 20 The deposition apparatus according to an embodiment includes a chamber 2010, a deposition source DS disposed inside the chamber 2010, and a mask MK disposed inside the chamber 2010 between a deposition substrate 2020 and the deposition source DS (see [reference]). Figure 11 ) and a mask support 2040 disposed between the deposition source DS and the mask MK and configured to support at least a portion of the mask MK.

[0226] According to an embodiment, the mask MK includes a substrate 1700 (see...). Figure 12 ) and mask diaphragm MM, substrate 1700 includes multiple unit regions 1710 (see Figure 12 ) and mask frame region 1720 (see multiple unit regions 1710) excluding the multiple unit regions 1710. Figure 12 Furthermore, the mask diaphragm MM is set in each cell region 1710.

[0227] Figure 20 The deposition substrate 2020 shown can be a reference. Figures 1 to 10 The described display panel 100. Therefore, using reference... Figures 1 to 10 The description of the display panel 100 is used instead of the description of the deposition substrate 2020.

[0228] Figure 20 The mask MK shown can be a reference. Figures 13 to 19 The mask MK is described.

[0229] According to an embodiment, the mask MK includes an electrostatic line 1810 comprising a first line 1811 and a second line 1812. The electrostatic line 1810 can clamp or unclamp the deposition substrate 2020 during the deposition process. In an example of applying a specific voltage to the electrostatic line 1810, such as... Figure 20 As indicated by arrow 2101, electrostatic wire 1810 can clamp the deposition substrate 2020. In an example where no specific voltage is applied to electrostatic wire 1810, electrostatic wire 1810 can release the deposition substrate 2020.

[0230] The mask support 2040 can be used to support and fix the mask MK below it. For example, the mask support 2040 may include an electrostatic chuck. According to an embodiment, the mask support 2040 may include a first support region 2041 supporting the mask edge region 1721 and a second support region 2042 supporting the outer frame region 1722. However, the mask support 2040 may not support the mask edge region 1721, and for example, the first support region 2041 may be omitted.

[0231] Figure 20 The reference numeral 2030 shown is a fixing member 2030 for fixing the deposition substrate 2020, and the fixing member 2030 may include, for example, an electrostatic chuck.

[0232] The display device according to one embodiment of the present disclosure can be applied to various electronic devices. An electronic device according to one embodiment of the present disclosure includes the aforementioned display device, and may further include modules or devices with additional functions in addition to the display device.

[0233] Figure 21 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0234] Reference Figure 21 An electronic device 1 according to an embodiment of the present disclosure may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0235] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0236] The memory 13 can store data necessary for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0237] The power module 14 may include a power supply module, such as a power adapter or battery, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 1.

[0238] At least one of the components of an electronic device 1 according to an embodiment of the present disclosure may be included in a display device 10 according to an embodiment of the present disclosure (see Figure 1In addition, some modules that are functionally included in a module may be included in the display device 10, while other modules may be provided separately from the display device 10. For example, the display device 10 may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided as other devices within the electronic device 1 besides the display device 10.

[0239] Figure 22 This is a schematic diagram of an electronic device according to various embodiments of the present disclosure.

[0240] Reference Figure 22 Various electronic devices that can be used with the display device 10 according to embodiments of the present disclosure may include not only image display electronic devices (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e), but also wearable electronic devices that include display modules (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) and vehicle electronic devices 10_3a that include display modules (such as CIDs (central information displays) and interior mirror displays arranged on the dashboard, central dashboard, and dashboard of a car).

[0241] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the exemplary embodiments without substantially departing from the principles of this disclosure. Therefore, the exemplary embodiments disclosed herein are intended for a general and descriptive purpose and not for limiting purposes.

Claims

1. A deposition mask, characterized in that, The deposition mask includes: The base includes multiple unit regions and edge regions that divide the multiple unit regions; A mask diaphragm is disposed on the plurality of unit regions of the substrate; A first line and a second line are disposed on the edge region of the substrate, wherein the first line and the second line extend between adjacent unit regions in the plurality of unit regions; A first pad, connected to the first line, is configured to provide a first value of voltage to the first line from the outer edge of the substrate; and The second pad is connected to the second line and is configured to provide a second voltage value to the second line from the outer edge of the substrate.

2. The deposition mask according to claim 1, Its features are, The first line and the second line are configured such that the first line and the second line are parallel to each other between the adjacent cell regions.

3. The deposition mask according to claim 2, Its features are, When the substrate is viewed on a plane, each of the first and second lines extends in a straight line.

4. The deposition mask according to claim 2, Its features are, When the substrate is viewed on a plane, each of the first and second lines extends according to an irregular shape.

5. The deposition mask according to claim 1, Its features are, Based on the voltage of the first value applied to the first line and the voltage of the second value applied to the second line, the first line and the second line generate electrostatic forces to clamp the deposited substrate.

6. A deposition apparatus, characterized in that, The deposition apparatus includes: Sediment source; and A mask is disposed between the deposition source and the deposition substrate. The mask includes: The base includes multiple unit regions and edge regions that divide the multiple unit regions; A mask diaphragm is disposed on the plurality of unit regions of the substrate; A first line and a second line are disposed on the edge region of the substrate, wherein the first line and the second line extend between adjacent unit regions in the plurality of unit regions; A first pad, connected to the first line, is configured to provide a first value of voltage to the first line from the outer edge of the substrate; and The second pad is connected to the second line and is configured to provide a second voltage value to the second line from the outer edge of the substrate.

7. The deposition apparatus according to claim 6, Its features are, The first line and the second line are configured such that the first line and the second line are parallel to each other between the adjacent cell regions.

8. The deposition apparatus according to claim 7, Its features are, When the substrate is viewed on a plane, each of the first and second lines extends in a straight line.

9. The deposition apparatus according to claim 7, Its features are, When the substrate is viewed on a plane, each of the first and second lines extends according to an irregular shape.

10. The deposition apparatus according to claim 7, Its features are, Based on the voltage of the first value applied to the first line and the voltage of the second value applied to the second line, the first line and the second line generate electrostatic forces to clamp the deposited substrate.

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