Memory device and method of manufacturing the same
By employing a first gate electrode layer and a second gate electrode layer in the memory device, combined with the vertical extension of the word line contacts, the challenges of high-integration manufacturing are solved, the process is simplified and the cost is reduced, gate-to-drain leakage current is reduced, and voltage transmission efficiency is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SK HYNIX INC
- Filing Date
- 2025-05-29
- Publication Date
- 2026-05-22
AI Technical Summary
In existing technologies, the increased integration of memory devices makes manufacturing more difficult, resulting in complex processes and high costs.
The design of burying the first and second gate electrode layers in the substrate, combined with the vertical extension of the word line contacts, simplifies the manufacturing process of memory devices and reduces manufacturing costs.
By simplifying the process and reducing costs, high integration of memory devices has been achieved, gate-drain leakage current has been reduced, and voltage transmission efficiency has been improved.
Smart Images
Figure CN122073801A_ABST
Abstract
Description
Cross-reference to related applications
[0001] This application claims priority to Korean Patent Application No. 10-2024-0168413, filed on November 22, 2024, the entire contents of which are incorporated herein by reference. Technical Field
[0002] Embodiments of this disclosure relate to a storage device and a method of manufacturing the same. Background Technology
[0003] Memory devices have attracted attention as important components in the electronics industry due to their characteristics such as miniaturization, versatility, and / or low manufacturing cost. With the rapid development of the electronics industry, the integration level of memory devices is increasing. To achieve high integration, the linewidth of the wiring included in memory devices is gradually decreasing, and the size of memory cells is becoming smaller. Because of this, the difficulty in forming memory cells is increasing. Summary of the Invention
[0004] The various embodiments of this disclosure are intended to provide a memory device that can simplify the process and reduce costs, and a method for manufacturing the memory device.
[0005] In one embodiment of this disclosure, a memory device may include: a substrate including a cell region having memory cells and an extended region outside the cell region; a first gate electrode layer buried in the substrate and extending from the cell region to the extended region in a predetermined direction, the upper surface of the first gate electrode layer in the cell region being at the same level as the upper surface of the first gate electrode layer in the extended region; a second gate electrode layer disposed on the first gate electrode layer and extending from the cell region to the extended region in a predetermined direction; and a word line contact located in the extended region and extending into the second gate electrode layer in a vertical direction perpendicular to the predetermined direction.
[0006] In one embodiment of this disclosure, a memory device may include: a substrate including a cell region having memory cells and an extended region outside the cell region; a first gate electrode layer buried in the substrate and extending from the cell region to the extended region in a defined direction; a second gate electrode layer disposed on the first gate electrode layer and extending from the cell region to the extended region in a defined direction, the thickness of the second gate electrode layer in the extended region being substantially the same as the thickness of the second gate electrode layer in the cell region; and a word line contact located in the extended region and extending into the second gate electrode layer in a vertical direction perpendicular to the defined direction.
[0007] In one embodiment of this disclosure, a method for manufacturing a memory device may include: forming a first gate electrode layer in a substrate, the substrate including a cell region having memory cells and an extended region outside the cell region; forming a second gate electrode layer on the first gate electrode layer; forming a through-hole in the extended region that passes through the second gate electrode layer in a vertical direction; and forming word line contacts to fill the through-hole.
[0008] According to embodiments of this disclosure, the manufacturing process of storage devices can be simplified and manufacturing costs can be reduced. Attached Figure Description
[0009] Figure 1 This is a view showing the planar structure of a storage device according to an embodiment of the present disclosure.
[0010] Figure 2 This is a view showing the cross-sectional structure of a storage device according to an embodiment of the present disclosure.
[0011] Figure 3 yes Figure 2 Enlarged views of parts 10 and 11.
[0012] Figure 4 It is shown that... Figure 3 Views of different alternative embodiments.
[0013] Figures 5 to 10 This is a view illustrating a method for manufacturing a storage device according to an embodiment of the present disclosure.
[0014] Figure 11 and Figure 12 This is a view showing a cross-sectional structure of a memory device that differs from the memory device described in the embodiments of this disclosure. Detailed Implementation
[0015] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples for illustrating the concepts disclosed in this specification. Examples or embodiments based on these concepts can be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.
[0016] In all the accompanying drawings, crosshairs illustrate corresponding or similar areas between the drawings, rather than indicating the material associated with that area.
[0017] When one element is labeled "connected" or "coupled" to another element, these elements can be directly connected or coupled, or connected or coupled through an intermediate element between the elements. When two elements are labeled "directly connected" or "directly coupled," one element is directly connected or directly coupled to the other element, and there is no intermediate element between the two elements.
[0018] When a component is identified as “on another component,” “above another component,” “below another component,” or “under another component,” these components may be in direct contact with each other, or intermediate components may be placed between these components.
[0019] Terms such as “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “under,” “below,” “above,” “on,” “side,” “upper,” “top,” “lower,” “front,” “back,” “left,” “right,” “column,” “row,” and “horizontal,” as well as other terms that suggest relative spatial relationships or orientations, are used for the purpose of description or reference to the accompanying drawings and are not intended to be limiting. Within the scope of this disclosure, other spatial relationships or orientations may exist that are not shown in the drawings or described in the specification.
[0020] Terms such as "first" and "second" are used to distinguish between elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one embodiment, a first element may be named a second element, while in another embodiment, a second element may be named a first element.
[0021] In the specification, when an element included in an embodiment is described in the singular, the element can be interpreted as including a plurality of elements that perform the same or similar functions.
[0022] In the accompanying drawings, three directions parallel to the upper surface of the substrate are defined as the first direction FD, the second direction SD, and the third direction TD, respectively, and a direction projecting perpendicularly from the upper surface of the substrate is defined as the fourth direction VD. The first direction FD and the second direction SD may be substantially perpendicular to each other. The fourth direction VD is perpendicular to the first direction FD, the second direction SD, and the third direction TD. In the following description, the term "perpendicular" or "perpendicular direction" will be used to have substantially the same meaning as the fourth direction VD. In the accompanying drawings, the direction indicated by the arrow and the direction opposite to it represent the same direction.
[0023] Figure 1 This is a plan view showing the structure of a storage device 100 according to an embodiment of the present disclosure.
[0024] refer to Figure 1The storage device 100 may include a cell region CA and an extension region EA. The cell region CA is a region where storage cells are disposed. Within the cell region CA, the storage device 100 includes an active region 110, a bit line BL, and a word line WL. The word line WL intersects the active region 110. The word line WL extends in a first direction FD. The word lines WL are arranged parallel to each other in a second direction SD. In one embodiment, each active region 110 may intersect with two corresponding word lines WL.
[0025] Bit line BL intersects with active region 110. Bit line BL extends in the second direction SD. Bit lines BL are arranged parallel to each other in the first direction FD. Bit line BL intersects with word line WL. Bit line BL may be orthogonal to word line WL. In one embodiment, a corresponding bit line BL may intersect with at least one active region 110.
[0026] An extended region EA is located outside the cell region CA in the first direction FD. The extended region EA may be a region provided with contacts for connecting each memory cell in the cell region CA to peripheral circuitry. The memory device 100 may also include a peripheral region outside the extended region EA, which is provided with peripheral circuitry. The memory cells in the cell region CA and the peripheral circuitry in the peripheral region can be connected to each other via contacts provided in the extended region EA. For example, contacts provided in the extended region EA can contact word lines WL in the extended region EA. Contacts can be connected to sub-word line drivers located in the peripheral region. That is, word lines WL can be connected to sub-word line drivers via contacts.
[0027] An extended region EA is located outside the cell region CA on the second direction SD. The memory cells in cell region CA and the peripheral circuitry in the peripheral region can be connected to each other via contacts in the extended region EA located outside cell region CA on the second direction SD. For example, the contacts in the extended region EA can contact the bit line BL in the extended region EA. The contacts can be connected to a sense amplifier located in the peripheral region. That is, the bit line BL can be connected to the sense amplifier via the contacts.
[0028] Figure 2 This is a view showing the cross-sectional structure of a storage device according to an embodiment of the present disclosure. Figure 2 In the middle, the left side shows along Figure 1 The right side shows a cross-sectional view of the storage device 100 taken along line I-I′, while the left side shows a view along... Figure 1 The cross-sectional view of the storage device 100 taken from line Ⅱ-Ⅱ′ in the figure.
[0029] refer to Figure 2The memory device 100 includes a substrate 200, an isolation layer 210, a gate structure 220, a bit line contact 230, a bit line BL, an isolation insulating layer 233, a contact plug 231, a first insulating layer 240, a landing pad 241, a support layer 260, a capacitor 250, a word line contact 270, and a second insulating layer 280.
[0030] Substrate 200 may include a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. Substrate 200 may include a III-V group semiconductor substrate, such as a compound semiconductor substrate like GaAs. Substrate 200 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof.
[0031] The substrate 200 includes at least one isolation layer 210. The isolation layer 210 can be formed using trench isolation techniques such as shallow trench isolation (STI). The isolation layer 210 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or combinations thereof.
[0032] In the cell region CA, the gate structure 220 can be buried in the active region 110 of the substrate 200. The gate structure 220 includes a word line WL, a gate capping layer 222, and a gate insulating layer 223. The upper surface of the word line WL is located at a level lower than the upper surface of the isolation layer 210. The word line WL can be a buried gate or a buried word line. The word line WL can include a first gate electrode layer 221a and a second gate electrode layer 221b. The second gate electrode layer 221b is disposed on the first gate electrode layer 221a. The gate capping layer 222 is disposed on the second gate electrode layer 221b of the word line WL. The gate insulating layer 223 surrounds the side surface of the word line WL and the side surface of the gate capping layer 222.
[0033] Each of the first gate electrode layer 221a and the second gate electrode layer 221b may include a conductive material, such as a metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof. The gate capping layer 222 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. The gate insulating layer 223 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof.
[0034] In the cell region CA, bit line contacts 230, contact plugs 231, and isolation insulating layers 233 are disposed on the active region 110 of the substrate 200.
[0035] Bit line BL is disposed on bit line contact 230. Bit line BL may be arranged in a direction perpendicular to word line WL. Bit line BL may not be in contact with contact plug 231. For example, at least one insulating layer or spacer may be additionally disposed between bit line BL and contact plug 231.
[0036] Contact plug 231 is stacked on the active region 110 of substrate 200 in the vertical direction VD. The lower surface of contact plug 231 contacts the active region 110. The upper surface of contact plug 231 contacts the landing pad 241.
[0037] In the cell region CA, a first insulating layer 240 and a landing pad 241 are disposed on an insulating layer 233 and a contact plug 231. The landing pad 241 is stacked on the contact plug 231 in the vertical direction VD.
[0038] Each of the bit line contact 230, bit line BL, contact plug 231, and landing pad 241 may include a conductive material, such as a metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof. Each of the insulating layer 233 and the first insulating layer 240 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.
[0039] In cell region CA, capacitor 250 is disposed on first insulating layer 240 and landing pad 241. Capacitor 250 includes lower electrode 251, dielectric layer 252 and upper electrode 253.
[0040] The lower electrode 251 can correspond one-to-one with the landing pad 241. The lower electrode 251 is stacked with the landing pad 241 in the vertical direction VD. The lower electrode 251 may include a first lower electrode 251a and a second lower electrode 251b. The lowermost surface of the first lower electrode 251a contacts the upper surface of the landing pad 241. The second lower electrode 251b contacts the first lower electrode 251a. The second lower electrode 251b fills the space formed between the inner surfaces of the first lower electrode 251a. In one embodiment, because the second lower electrode 251b fills the space formed between the inner surfaces of the first lower electrode 251a, tilting of the first lower electrode 251a can be prevented. Figure 2 In the diagram, the lower electrode 251 is shown in a columnar shape, but is not limited to this. The lower electrode 251 may also have a cylindrical shape.
[0041] A support layer 260 is disposed on a side surface of the lower electrode 251. Each support layer 260 may contact a portion of the side surface of the lower electrode 251. In one embodiment, the support layer 260 may prevent the lower electrode 251 from tilting. The support layers 260 may be configured to be spaced apart from each other in the vertical direction VD.
[0042] The dielectric layer 252 is disposed along the contour of the surfaces of the lower electrode 251 and the support layer 260. The dielectric layer 252 may be configured to cover the surfaces of the lower electrode 251, the support layer 260, and the upper surface of the first insulating layer 240. In one embodiment, the lowermost surface of the dielectric layer 252 may form substantially the same plane as the lowermost surface of the lower electrode 251. Alternatively, an etch stop layer may be additionally disposed between the dielectric layer 252 and the first insulating layer 240. In this case, the lowermost surface of the dielectric layer 252 may be located at a level higher than the lowermost surface of the lower electrode 251.
[0043] An upper electrode 253 is disposed on the surface of the dielectric layer 252. The upper electrode 253 is configured to fill the space formed between the outer surfaces of the dielectric layer 252. The upper surface of the upper electrode 253 may be located at a horizontal level higher than the upper surface of the lower electrode 251 in the vertical direction VD. A second insulating layer 280 is disposed on the upper electrode 253.
[0044] Each of the first lower electrode 251a, the second lower electrode 251b, and the upper electrode 253 may include a conductive material, such as a metal, metal oxide, metal nitride, metal silicide, polycrystalline silicon, conductive carbon, or a combination thereof. In one embodiment, the first lower electrode 251a may be a metal nitride, and the second lower electrode 251b may be polycrystalline silicon. The support layer 260 may include a nitride such as silicon nitride or silicon carbonitride. The dielectric layer 252 may include a high-k dielectric, silicon oxide, silicon nitride, or a combination thereof.
[0045] In the extended region EA, at least one isolation layer 210 is buried in the substrate 200. A gate insulating layer 223 is disposed on the isolation layer 210. A first gate electrode layer 221a, a second gate electrode layer 221b, a gate capping layer 222, and an isolation insulating layer 233 are sequentially disposed on the gate insulating layer 223.
[0046] The gate insulating layer 223, the first gate electrode layer 221a, the second gate electrode layer 221b, the gate capping layer 222, and the isolation insulating layer 233 may extend from the cell region CA to the extended region EA in the first direction FD. In one embodiment, each of the first gate electrode layer 221a and the second gate electrode layer 221b may have a flat upper surface in the extended region EA.
[0047] In the extended region EA, a word line contact 270 is disposed on an insulating layer 233, and the word line contact 270 includes a contact portion 270a and an extension portion 270b. The contact portion 270a protrudes toward the substrate 200 in the vertical direction VD. The extension portion 270b is continuous with the contact portion 270a and extends in the insulating layer 233 along a first direction FD. The contact portion 270a extends into the first gate electrode layer 221a by penetrating the insulating layer 233, the gate capping layer 222, and the second gate electrode layer 221b in the vertical direction VD. In some embodiments, the extension portion 270b may further extend in the first direction FD to the outside of the extended region EA. In one embodiment, the extension portion 270b may be connected to a sub-word line driver outside the extended region EA. The word line contact 270 may include a conductive material, such as a metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof. A second insulating layer 280 is disposed on the word line contact 270.
[0048] Figure 3 yes Figure 2 Enlarged views of parts 10 and 11.
[0049] refer to Figure 3 The first gate electrode layer 221a and the second gate electrode layer 221b are buried in the substrate 200. The first gate electrode layer 221a and the second gate electrode layer 221b extend from the cell region CA to the extended region EA in the first direction FD.
[0050] In one embodiment, the first gate electrode layer 221a may include titanium nitride, tungsten, titanium, tantalum, aluminum, molybdenum, silicon, silicon germanium, polycrystalline silicon, or a combination thereof.
[0051] In one embodiment, the upper surface of the first gate electrode layer 221a in the cell region CA and the upper surface of the first gate electrode layer 221a in the extended region EA may be located at substantially the same level. In this specification, "substantially the same" means including differences due to process variations.
[0052] The thickness d2 of the second gate electrode layer 221b in the cell region CA can be substantially the same as the thickness of the second gate electrode layer 221b in the extended region EA. In one embodiment, the thickness d2 of the second gate electrode layer 221b can be greater than or equal to 10 angstroms and less than or equal to 250 angstroms.
[0053] The second gate electrode layer 221b may include a material different from the material forming the first gate electrode layer 221a. In one embodiment, the second gate electrode layer 221b may include titanium nitride, tungsten, titanium, tantalum, aluminum, molybdenum, silicon, silicon-germanium, polycrystalline silicon, or combinations thereof. In one embodiment, the second gate electrode layer 221b may include a material having a lower work function than the material forming the first gate electrode layer 221a. When the second gate electrode layer 221b includes a material having a lower work function than the material forming the first gate electrode layer 221a, gate-induced drain leakage (GIDL) can be prevented.
[0054] In one embodiment, the upper surface of the second gate electrode layer 221b in the cell region CA may be located at substantially the same level as the upper surface of the second gate electrode layer 221b in the extended region EA. In one embodiment, the thickness d2 of the second gate electrode layer 221b may be constant in both the cell region CA and the extended region EA.
[0055] In the cell region CA, the maximum thickness d1 of the first gate electrode layer 221a can be greater than the thickness d2 of the second gate electrode layer 221b.
[0056] In the cell region CA, the gate insulating layer 223 surrounds the side and bottom surfaces of the first gate electrode layer 221a and the side surface of the second gate electrode layer 221b. In one embodiment, the thickness of the gate insulating layer 223 may be greater than or equal to 20 angstroms and less than or equal to 45 angstroms.
[0057] Typically, the amount of gate-induced drain leakage current can be varied depending on the thickness of the second gate electrode layer 221b. For example, when the thickness of the second gate electrode layer 221b is large, the amount of gate-induced drain leakage current can be small. When the thickness of the gate insulating layer 223 is less than or equal to 45 angstroms, the effect of the thickness of the second gate electrode layer 221b on the amount of gate-induced drain leakage current can be reduced.
[0058] The lower surface of the contact portion 270a of the word line contact 270 in the extended region EA contacts the first gate electrode layer 221a. The side surface of the contact portion 270a of the word line contact 270 contacts the first gate electrode layer 221a and the second gate electrode layer 221b. In one embodiment, the word line contact 270 can transfer the voltage for turning on the transistors included in the memory cell from the sub-word line driver to the word line WL.
[0059] Figure 4 It is shown that... Figure 3 Views of different alternative embodiments.
[0060] In the following embodiments, the preceding will be omitted. Figure 3 The components in the embodiments are substantially the same or similar to the components described.
[0061] refer to Figure 4 The gate structure 220 includes a word line WL, a gate cover layer 222, and a gate insulating layer 223. The word line WL includes a first gate electrode layer 421a and a second gate electrode layer 421b disposed on the first gate electrode layer 421a.
[0062] In the extended region EA, the contact portion 470a of the word line contact 270 extends vertically in the direction VD through the gate capping layer 222 into the second gate electrode layer 421b. The side and lower surfaces of the contact portion 470a are in contact with the second gate electrode layer 421b. The lower surface of the contact portion 470a is located at a level higher than the upper surface of the first gate electrode layer 421a.
[0063] In one embodiment, the second gate electrode layer 421b may include a material with a lower work function than the material forming the first gate electrode layer 421a. In one embodiment, the second gate electrode layer 421b may include a material with a lower resistance than the material forming the first gate electrode layer 421a. When the second gate electrode layer 421b includes a material with a lower resistance than the first gate electrode layer 421a, the contact portion 470a of the word line contact 270 can transmit the voltage for turning on the transistors included in the memory cell to the word line WL through the second gate electrode layer 421b.
[0064] Figures 5 to 10 This is a view illustrating a method for manufacturing a storage device according to an embodiment of the present disclosure.
[0065] refer to Figure 5 An isolation layer 210 defining the active region is formed in the substrate 200 within the cell region CA. A gate trench 500 intersecting the active region in the first direction FD is formed in the substrate 200. In the extended region EA, a portion of the upper region of the substrate 200 may be removed, such that the upper surface of the substrate 200 is recessed downward in the vertical direction VD. The isolation layer 210 is formed to fill the recessed space of the substrate 200. The recessed space of the substrate 200 and the isolation layer 210 filling the recessed space can be formed in various sizes.
[0066] A gate insulating layer 223 is formed on the side and bottom surfaces of the gate trench 500 in the cell region CA and on the substrate 200 and isolation layer 210 in the extended region EA. The gate insulating layer 223 is formed along the steps of the underlying layer. In one embodiment, the gate insulating layer 223 may conformally cover the side and bottom surfaces of the gate trench 500 in the cell region CA, the top and partial side surfaces of the substrate 200 in the extended region EA, and the top surface of the isolation layer 210. In one embodiment, the thickness of the gate insulating layer 223 may be greater than or equal to 20 angstroms and less than or equal to 45 angstroms. In the cell region CA, the gate insulating layer 223 formed in areas other than the area where the gate trench 500 is formed may be removed.
[0067] In the cell region CA and the extended region EA, a gate electrode material 510 is formed on the gate insulating layer 223 and the substrate 200. In one embodiment, the gate electrode material 510 may be formed to a level higher than the upper surface of the substrate 200. The gate electrode material 510 may include the same as referenced above. Figures 2 to 4 The first gate electrode layer 221a described is made of the same material. The gate electrode material 510 may include titanium nitride, tungsten, titanium, tantalum, aluminum, molybdenum, silicon, silicon germanium, polycrystalline silicon, or combinations thereof.
[0068] refer to Figure 6 A first gate electrode layer 221a is formed by removing a portion of the gate electrode material 510 from the cell region CA and the extended region EA. The process for forming the first gate electrode layer 221a may include an etch-back process. The upper surface of the first gate electrode layer 221a in the cell region CA may be formed into a plane that is substantially the same as the upper surface of the first gate electrode layer 221a in the extended region EA.
[0069] refer to Figure 7 In the cell region CA and the extended region EA, a second gate electrode layer 221b is formed on the first gate electrode layer 221a. The process for forming the second gate electrode layer 221b may include an etch-back process. The upper surface of the second gate electrode layer 221b in the cell region CA may be formed into a plane substantially the same as the upper surface of the second gate electrode layer 221b in the extended region EA. In one embodiment, the thickness of the second gate electrode layer 221b in the cell region CA may be substantially the same as the thickness of the second gate electrode layer 221b in the extended region EA. In one embodiment, the thickness of the second gate electrode layer 221b may be greater than or equal to 10 angstroms and less than or equal to 250 angstroms.
[0070] refer to Figure 8In the cell region CA and the extended region EA, a gate capping layer 222 is formed on the second gate electrode layer 221b. In the cell region CA, bit line contacts 230, bit lines BL, contact plugs 231, and an isolation insulating layer 233 are formed on the gate capping layer 222. After forming the isolation insulating layer 233, the contact plugs 231 can be formed to penetrate the isolation insulating layer 233 and contact the active region of the substrate 200. In the extended region EA, the isolation insulating layer 233 is formed on the gate capping layer 222. In one embodiment, the upper surface of the isolation insulating layer 233 in the cell region CA can be formed as a plane substantially the same as the upper surface of the isolation insulating layer 233 in the extended region EA.
[0071] refer to Figure 9 In the extended region EA, a via 900 is formed that extends in the vertical direction VD through the isolation insulating layer 233, the gate cover layer 222 and the second gate electrode layer 221b into the first gate electrode layer 221a.
[0072] The lower surface of the via 900 contacts the first gate electrode layer 221a. The lower surface of the via 900 is located at a level lower than the upper surface of the first gate electrode layer 221a. The side surface of the via 900 contacts the first gate electrode layer 221a and the second gate electrode layer 221b.
[0073] The process of forming the via 900 may include an etching process. In one embodiment, the etching process may include a directional etching process. In one embodiment, a portion of the isolation insulating layer 233, the gate capping layer 222, and the second gate electrode layer 221b may be removed by a directional etching process.
[0074] refer to Figure 10 In the cell region CA, a first insulating layer 240 is formed on the isolation insulating layer 233 and the contact plug 231. After the first insulating layer 240 is formed, a landing pad 241 is formed that penetrates the first insulating layer 240 in the vertical direction VD.
[0075] A lower electrode 251 and a support layer 260 are formed on a landing pad 241. The lower electrode 251 is formed to overlap the landing pad 241 in the vertical direction VD. The lower surface of the lower electrode 251 is formed to contact the upper surface of the landing pad 241. The process of forming the lower electrode 251 may include forming a plurality of insulating layers on the first insulating layer 240 and the landing pad 241, forming holes penetrating the plurality of insulating layers, and then depositing electrode material to fill the holes. In one embodiment, the process of forming the support layer 260 may include etching portions of the plurality of insulating layers by an etch process after depositing the electrode material.
[0076] A dielectric layer 252 is formed along the contour of the surfaces of the first insulating layer 240, the lower electrode 251, and the support layer 260. An upper electrode 253 is formed on the dielectric layer 252. A second insulating layer 280 is formed on the upper electrode 253.
[0077] In the extended region EA, word line contacts 270 are formed in the via 900 and on the insulating layer 233. In one embodiment, the word line contacts 270 can be formed using the same process as that used to form the landing pads 241. The contact portion 270a of the word line contacts 270 is formed to fill the interior of the via 900. A second insulating layer 280 is formed on the word line contacts 270.
[0078] Figure 11 and Figure 12 This is a view showing a cross-sectional structure of a memory device that differs from some embodiments of the memory device according to this disclosure.
[0079] refer to Figure 11 and Figure 12 In a portion of the extended region EA, more first gate electrode layers 1101a may be deposited than in other regions of the extended region EA. For example, in the extended region EA, the upper surface of the first gate electrode layer 1101a may include a step. A portion of the upper surface of the first gate electrode layer 1101a in the extended region EA may be located at a higher level than the upper surface of the first gate electrode layer 1101a in the cell region CA. The maximum thickness d1′ of the first gate electrode layer 1101a in the cell region CA may be smaller than the above reference. Figure 3 The maximum thickness d1 of the first gate electrode layer 221a in the described cell region CA.
[0080] In the extended region EA, a portion of the upper surface of the second gate electrode layer 1101b, which protrudes from the first gate electrode layer 1101a, can be removed. When this portion of the second gate electrode layer 1101b is removed, the upper surface of the first gate electrode layer 1101a can be exposed. The upper surface of the second gate electrode layer 1101b in the cell region CA can be formed into a plane substantially the same as the upper surface of the second gate electrode layer 1101b in the extended region EA. The thickness d2′ of the second gate electrode layer 1101b in the cell region CA can be greater than the thickness of this portion of the second gate electrode layer 1101b in the extended region EA. The thickness d2′ of the second gate electrode layer 1101b in the cell region CA can be greater than the thickness of the portion of the second gate electrode layer 1101b in the extended region EA. Figure 3 The thickness d2 of the second gate electrode layer 221b is described.
[0081] The portion of the second gate electrode layer 1101b located on the raised upper surface of the first gate electrode layer 1101a may not be removed. Alternatively, the upper surface of the first gate electrode layer 1101a in the region where this portion of the second gate electrode layer 1101b is removed may be at the same level as the upper surface of the first gate electrode layer 1101a in the cell region CA.
[0082] The sum of the maximum thickness d1′ of the first gate electrode layer 1101a in cell region CA and the thickness d2′ of the second gate electrode layer 1101b in cell region CA can be compared with the above reference. Figure 3 The sum of the maximum thickness d1 of the first gate electrode layer 221a and the thickness d2 of the second gate electrode layer 221b in the described cell region CA is the same.
[0083] The contact portion 1170a of the word line contact 1170 extends in the vertical direction VD through the gate cover layer 1102 and into the first gate electrode layer 1101a. The word line contact 1170 extends into the first gate electrode layer 1101a in the region where the upper surface of the first gate electrode layer 1101a is exposed.
[0084] As described above, the greater the thickness of the second gate electrode layer 1101b, the more the gate-drain leakage current can be reduced. Therefore, when forming a memory cell, such as Figure 11 and Figure 12 As shown, while the thickness of the word line WL in the cell region CA remains constant, the thickness of the first gate electrode layer 1101a can be reduced, while the thickness of the second gate electrode layer 1101b can be increased.
[0085] However, as the thickness of the second gate electrode layer 1101b increases, it becomes difficult to form word line contacts through the second gate electrode layer 1101b. Therefore, an additional process is required to partially open the second gate electrode layer 1101b in the extended region EA.
[0086] Furthermore, when the thickness of the first gate electrode layer 1101a decreases, there is a risk that the first gate electrode layer 1101a may be cut off in the extended region EA. Therefore, an additional process is required to locally increase the thickness of the first gate electrode layer 1101a in the extended region EA. (Refer to...) Figure 2The upper surface of the first gate electrode layer 221a in the cell region CA can be located at substantially the same level as the upper surface of the first gate electrode layer 221a in the extended region EA. In one embodiment, the thickness d2 of the second gate electrode layer 221b can be greater than or equal to 10 angstroms and less than or equal to 250 angstroms. In the cell region CA, the maximum thickness d1 of the first gate electrode layer 221a can be greater than the thickness d2 of the second gate electrode layer 221b. In one embodiment, the thickness of the gate insulating layer 223 can be greater than or equal to 20 angstroms and less than or equal to 45 angstroms. The contact portion 270a of the word line contact 270 extends into the first gate electrode layer 221a by penetrating the insulating layer 233, the gate cover layer 222, and the second gate electrode layer 221b in the vertical direction VD.
[0087] According to embodiments of this disclosure, when the thickness of the gate insulating layer 223 is formed to be thinner, the influence of the thickness of the second gate electrode layer 221b on the amount of gate-induced drain leakage current can be reduced. That is, it is not necessary to significantly increase the thickness of the second gate electrode layer 221b to prevent gate-induced drain leakage. Because it is not necessary to increase the thickness of the second gate electrode layer 221b, the process of partially opening the second gate electrode layer 221b when forming the word line contact 270 can be omitted. When the thickness of the second gate electrode layer 221b is thinner, it is easier to penetrate the second gate electrode layer 221b; therefore, when forming the word line contact 270, a separate process of opening the second gate electrode layer 221b is not required. Therefore, the process can be simplified.
[0088] Furthermore, since it is not necessary to increase the thickness of the second gate electrode layer 221b, it is not necessary to reduce the thickness of the first gate electrode layer 221a. Because it is not necessary to reduce the thickness of the first gate electrode layer 221a, defects caused by the cutting off of the first gate electrode layer 221a in the extended region EA can be prevented. Furthermore, since it is not necessary to reduce the volume of the first gate electrode layer 221a disposed in the cell region CA and the extended region EA, power loss caused by the resistance of the word line WL itself when supplying voltage to the memory cell through the word line WL can be reduced.
[0089] While some detailed embodiments of this disclosure have been disclosed, those skilled in the art will understand that various modifications, additions, and substitutions related to these embodiments are possible without departing from the scope and technical concept of this disclosure. Therefore, the scope of this disclosure should not be limited to the foregoing embodiments. All changes within the scope and meaning of equivalents of the claims are included within its scope. Furthermore, these embodiments can be combined to form other embodiments.
Claims
1. A storage device, comprising: The substrate includes a cell region where memory cells are disposed and an extended region outside the cell region; A first gate electrode layer is buried in the substrate and extends from the cell region to the extended region in a defined direction. The upper surface of the first gate electrode layer in the cell region is at the same level as the upper surface of the first gate electrode layer in the extended region. A second gate electrode layer is disposed on the first gate electrode layer and extends from the cell region to the extended region in the predetermined direction; as well as A word line contact is located in the extended region and extends into the second gate electrode layer in a vertical direction perpendicular to the set direction.
2. The storage device according to claim 1, wherein, The thickness of the second gate electrode layer is greater than or equal to 10 and less than or equal to 250 angstroms.
3. The storage device according to claim 1, wherein, The side surface of the word line contact is in contact with the second gate electrode layer.
4. The storage device according to claim 1, wherein, The lower surface of the word line contact is located at a level higher than the upper surface of the first gate electrode layer.
5. The storage device according to claim 1, wherein, The word line contact extends through the second gate electrode layer and further into the first gate electrode layer in the vertical direction.
6. The storage device according to claim 1, wherein, The upper surface of the second gate electrode layer in the cell region is located at the same level as the upper surface of the second gate electrode layer in the extended region.
7. The storage device according to claim 1, wherein, The thickness of the second gate electrode layer in the extended region is the same as the thickness of the second gate electrode layer in the cell region.
8. The storage device according to claim 1, further comprising: A gate insulating layer surrounding the lower and side surfaces of the first gate electrode layer and the side surface of the second gate electrode layer. The thickness of the gate insulating layer is greater than or equal to 20 angstroms and less than or equal to 45 angstroms.
9. The storage device according to claim 1, wherein, The second gate electrode layer comprises a material having a lower work function than the material of the first gate electrode layer.
10. The storage device according to claim 1, wherein, The second gate electrode layer comprises titanium nitride, tungsten, titanium, tantalum, aluminum, molybdenum, silicon, silicon germanium, polycrystalline silicon, or a combination thereof.
11. The storage device according to claim 1, wherein, The first gate electrode layer and the second gate electrode layer constitute a word line.
12. A storage device comprising: The substrate includes a cell region where memory cells are disposed and an extended region outside the cell region; A first gate electrode layer is buried in the substrate and extends from the cell region to the extended region in a defined direction; A second gate electrode layer is disposed on the first gate electrode layer and extends from the cell region to the extended region in the predetermined direction. The thickness of the second gate electrode layer in the extended region is the same as the thickness of the second gate electrode layer in the cell region. as well as A word line contact is located in the extended region and extends into the second gate electrode layer in a vertical direction perpendicular to the set direction.
13. The storage device according to claim 12, wherein, The thickness of the second gate electrode layer is greater than or equal to 10 angstroms and less than or equal to 250 angstroms.
14. The storage device according to claim 12, wherein, The lower surface of the word line contact is located at a level higher than the upper surface of the first gate electrode layer.
15. The storage device according to claim 12, wherein, The word line contact extends through the second gate electrode layer and further into the first gate electrode layer in the vertical direction.
16. The storage device according to claim 12, further comprising: A gate insulating layer surrounding the lower and side surfaces of the first gate electrode layer and the side surface of the second gate electrode layer. The thickness of the gate insulating layer is greater than or equal to 20 angstroms and less than or equal to 45 angstroms.
17. The storage device according to claim 12, wherein, The upper surface of the second gate electrode layer in the cell region is located at the same level as the upper surface of the second gate electrode layer in the extended region.
18. The storage device according to claim 12, wherein, The thickness of the first gate electrode layer in the extended region is greater than the thickness of the first gate electrode layer in the cell region.
19. A method of manufacturing a storage device, the method comprising: A first gate electrode layer is formed in a substrate, the substrate including a cell region where memory cells are disposed and an extended region outside the cell region; A second gate electrode layer is formed on the first gate electrode layer; A through-hole penetrating the second gate electrode layer in the vertical direction is formed in the extended region; and Form word line contacts to fill the through holes.
20. The method according to claim 19, wherein, The thickness of the second gate electrode layer is greater than or equal to 10 angstroms and less than or equal to 250 angstroms.