A display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a display area and a non-display area, a plurality of data lines, a plurality of connection wires and a plurality of signal wires, the connection wires are electrically connected with the data lines and the signal wires respectively; the data lines and the connection wires are located in the display area, and the signal wires are located in the non-display area; the display area comprises a first display area, the first display area comprises a first light emitting element setting area, a first pixel circuit setting area and a first pixel driving circuit setting area; along the thickness direction of the display panel, the first light emitting element setting area overlaps with the first pixel circuit setting area, and overlaps with the first pixel driving circuit setting area; part of the first pixel circuit is electrically connected with the first light emitting element through a signal transmission wire, and at least part of the signal transmission wire is arranged in the same layer as the connection wire. While improving the narrow frame effect of the display panel, the difficulty of arranging the signal transmission wire is reduced, and the preparation process of the signal transmission wire is simplified.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In electronic devices, including display panels, the pursuit of a high screen-to-body ratio for a superior visual experience has become a current trend in display technology development. In existing technologies, the pixel drive control circuit, which provides driving control signals to the sub-pixels within the display area, is generally located in the bezel area of ​​the display panel. This arrangement results in the pixel drive control circuit occupying a large area of ​​the bezel, which is not conducive to achieving a narrow bezel for the display panel. Summary of the Invention

[0003] In view of this, the present invention provides a display panel and a display device to reduce the size of the bezel area of ​​the display panel and achieve a narrow bezel in the display panel.

[0004] In a first aspect, embodiments of the present invention provide a display panel, including a display area and a non-display area;

[0005] The display panel also includes multiple data lines, multiple connection traces, and multiple signal traces. The connection traces are electrically connected to the data lines and the signal traces, respectively. The data lines and the connection traces are located in the display area, and the signal traces are located in the non-display area.

[0006] The display area includes a first display area, which includes a first light-emitting element setting area, a first pixel circuit setting area, and a first pixel driving circuit setting area. The first light-emitting element setting area is provided with a plurality of first light-emitting elements, the first pixel circuit setting area is provided with a plurality of first pixel circuits, and the first pixel driving circuit setting area is provided with a first pixel driving circuit. The first pixel circuits are electrically connected to the first pixel driving circuit and the first light-emitting elements, respectively. Along the thickness direction of the display panel, the first light-emitting element setting area overlaps with the first pixel circuit setting area and also overlaps with the first pixel driving circuit setting area.

[0007] A portion of the first pixel circuit is electrically connected to the first light-emitting element via signal transmission traces, and at least a portion of the signal transmission traces are disposed on the same layer as the connection traces.

[0008] Secondly, embodiments of the present invention provide a display device, including the display panel described in the first aspect of the present invention.

[0009] The technical solution provided in this application reduces the area occupied by signal wiring in the non-display area by placing the connection traces within the display area, thereby reducing the size of the bottom bezel of the display panel. Simultaneously, the overlapping of the first light-emitting element setting area and the first pixel driving circuit setting area, i.e., placing the first pixel driving circuit in the display area, reduces the number of pixel driving circuits in the non-display areas on the left and right sides of the display panel, thus reducing the size of the left and right bezels and improving the narrow bezel effect. Furthermore, by electrically connecting a portion of the first pixel circuit to the first light-emitting element via signal transmission traces, with at least a portion of the signal transmission traces on the same layer as the connection traces, it ensures that the first light-emitting element can normally receive the driving signals transmitted by the first pixel circuit, while also reducing the difficulty of laying out the signal transmission traces and simplifying the fabrication process. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0011] Figure 2 for Figure 1 A magnified structural diagram at point A;

[0012] Figure 3 for Figure 2 A magnified structural diagram at point B;

[0013] Figure 4 for Figure 1 A schematic diagram of the cross-sectional structure along the C-C' direction;

[0014] Figure 5 for Figure 1 A magnified structural diagram at point D;

[0015] Figure 6 for Figure 5 A schematic diagram of the cross-sectional structure along the E-E' direction;

[0016] Figure 7 This is a partially enlarged structural diagram of a display panel provided in an embodiment of the present invention;

[0017] Figure 8 A partially enlarged structural diagram of another display panel provided in an embodiment of the present invention;

[0018] Figure 9 A partially enlarged structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0019] Figure 10 A partially enlarged structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0020] Figure 11A partially enlarged structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0021] Figure 12 A partial cross-sectional structural diagram of a display panel provided in an embodiment of the present invention;

[0022] Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0023] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0024] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 for Figure 1 Enlarged structural diagram at point A Figure 3 for Figure 2 Enlarged structural diagram at point B Figure 4 for Figure 1 A schematic diagram of the cross-sectional structure along the C-C' direction, for reference. Figures 1-4 In this embodiment of the invention, the display panel includes: a display area AA and a non-display area NA; the display panel also includes multiple data lines 1, multiple connection lines 2, and multiple signal lines 3, the connection lines 2 being electrically connected to the data lines 1 and the signal lines 3 respectively; the data lines 1 and connection lines 2 are located in the display area AA, and the signal lines 3 are located in the non-display area NA; the display area AA includes a first display area AA1, the first display area AA1 including a first light-emitting element setting area 4, a first pixel circuit setting area 5, and a first pixel driving circuit setting area 6, the first light-emitting element setting area 4 being provided with multiple first... The light-emitting element 7, the first pixel circuit setting area 5 is provided with a plurality of first pixel circuits 8, the first pixel driving circuit setting area 6 is provided with a first pixel driving circuit 9, and the first pixel circuits 8 are electrically connected to the first pixel driving circuit 9 and the first light-emitting element 7 respectively; along the thickness direction Z of the display panel, the first light-emitting element setting area 4 overlaps with the first pixel circuit setting area 5 and overlaps with the first pixel driving circuit setting area 6; some of the first pixel circuits 8 are electrically connected to the first light-emitting element 7 through signal transmission lines 10, and at least some of the signal transmission lines 10 are set on the same layer as the connecting lines 2.

[0025] refer to Figures 1-4The display panel has multiple data lines 1 and multiple connection lines 2 in the display area AA, and multiple signal lines 3 in the non-display area NA. Data lines 1 provide data signals to the light-emitting elements in the display area AA. Data lines 1 are arranged along a first direction X and extend along a second direction Y in the display area AA. The first direction X can be the row direction shown in the figure, and the second direction Y can be the column direction shown in the figure. Signal lines 3 are fan-out lines used to connect each data line 1 to a driver module (not shown in the figure).

[0026] Among them, connection trace 2 is implemented using FIAA (Fanout in AA, fanout trace located in the display area) technology. FIAA technology introduces a multi-layer connection trace design to create wiring space for the fanout trace. For example... Figure 1 As shown, by using FIAA technology, some data lines 1 are connected to signal wiring 3 through connection wiring 2 in the display area AA, so that the signal wiring 3 occupies a smaller area in the non-display area NA. Figure 1 The signal wiring 3 shown is located in the non-display area NA below the display panel. The actual arrangement is not limited to this; this arrangement can reduce the size of the bottom bezel of the display panel. The number of metal traces (data line 1, connection trace 2, and signal wiring 3, etc.) shown in this embodiment is merely an example and does not represent the actual situation.

[0027] Furthermore, the display area AA further includes a first display area AA1, which can be further divided into a first light-emitting element setting area 4, a first pixel circuit setting area 5, and a first pixel driving circuit setting area 6. The first light-emitting element setting area 4 is used to set multiple first light-emitting elements 7, which can be organic light-emitting diodes (OLEDs), Mini LEDs, Micro LEDs, or quantum dot light-emitting diodes (QLEDs), etc. The first light-emitting elements 7 may include a red light-emitting element R, a green light-emitting element G, and a blue light-emitting element B. Figure 3 The example shown illustrates a diamond pixel arrangement for the red light-emitting element R, green light-emitting element G, and blue light-emitting element B, but the actual arrangement is not limited to this. In other embodiments not shown, the red light-emitting element R, green light-emitting element G, and blue light-emitting element B may also be arranged in a standard RGB arrangement, a delta pixel arrangement, a pearl pixel arrangement, or a 2-in-1 pixel arrangement, etc., but are not limited to these. In this application, the diamond pixel arrangement is used for illustration.

[0028] The first pixel circuit setting area 5 is used to set multiple first pixel circuits 8. The first pixel circuit 8 can be a 2T1C circuit, a 7T1C circuit, or a 7T2C circuit, etc. "2T1C circuit" refers to a pixel circuit that includes two thin-film transistors (T) and one capacitor (C). Other "7T1C circuit", "7T2C circuit", etc., follow the same logic. The first pixel driving circuit setting area 6 is used to set a first pixel driving circuit 9. The first pixel driving circuit 9 may also include thin-film transistors and capacitors. The number of thin-film transistors and capacitors in the first pixel driving circuit 9 can be set by those skilled in the art according to actual needs. This embodiment of the invention does not elaborate on this nor limit it.

[0029] In this design, the first pixel circuit 8 is electrically connected to the first light-emitting element 7 to provide a driving signal to the first light-emitting element 7, thereby driving the first light-emitting element 7 to emit light. It is understood that, generally, the first pixel circuit 8 and the first light-emitting element 7 correspond one-to-one, with each first light-emitting element 7 driven by its corresponding first pixel circuit 8. For example, the first pixel circuit 8 may be electrically connected to the anode of the first light-emitting element 7 to transmit the driving signal to the first light-emitting element 7. The circular first light-emitting element 7 shown in the figure may represent the anode of the first light-emitting element 7.

[0030] The first pixel driving circuit 9 is electrically connected to the first pixel circuit 8 to provide a driving control signal to the first pixel circuit 8. Under the control of the driving control signal, the first pixel circuit 8 generates a driving signal and transmits the driving signal to the first light-emitting element 7. The first pixel driving circuit 9 can be electrically connected to the first pixel circuit 8 through a driving control signal line (not shown in the figure), and the driving control signal is transmitted to the first pixel circuit 8 through the driving control signal line.

[0031] Compared to placing the pixel driving circuit in the non-display areas NA on the left and right sides of the display panel, in this embodiment, by placing the first pixel driving circuit 9 in the first display area AA1, the number of pixel driving circuits placed in the non-display areas NA on the left and right sides of the display panel can be reduced, thereby reducing the size of the left and right bezels of the display panel.

[0032] The first light-emitting element setting area 4 and the first pixel circuit setting area 5 overlap along the thickness direction Z of the display panel, and the first light-emitting element setting area 4 and the first pixel driving circuit setting area 6 overlap along the thickness direction Z of the display panel. It can also be understood that at least a portion of the first pixel circuit 8 has its orthographic projection on the film layer where the first light-emitting element 7 is located within the first light-emitting element setting area 4; similarly, at least a portion of the first pixel driving circuit 9 has its orthographic projection on the film layer where the first light-emitting element 7 is located within the first light-emitting element setting area 4.

[0033] In this embodiment, the first pixel circuit 8 and the first pixel driving circuit 9 can be located on the same film layer, thereby reducing the number of film layers in the display panel and reducing the thickness of the display panel. When the first pixel circuit 8 and the first pixel driving circuit 9 are located on the same film layer, the projections of the first pixel circuit setting area 5 and the first pixel driving circuit setting area 6 along the thickness direction Z of the display panel do not overlap. In other embodiments, the first pixel circuit 8 and the first pixel driving circuit 9 can also be located on different film layers.

[0034] It is understandable that in related technologies, the display area AA of the display panel does not have a pixel driving circuit, and the area of ​​the pixel circuit setting area is relatively large. In this case, the pixel circuit setting area and the light-emitting element setting area can be arranged to coincide along the thickness direction Z of the display panel. Each light-emitting element is driven by a pixel circuit that partially overlaps with it, and the two can be electrically connected directly through vias between the film layers. However, in this application, as... Figures 1-4 As shown, because the first pixel driving circuit 9 occupies part of the space originally belonging to the first pixel circuit 8, the overall size of the first pixel circuit setting area 5 is compressed to some extent. The presence of the first pixel driving circuit 9 occupies part of the area below the first light-emitting element 7 (the direction from the film layer where the first light-emitting element 7 is located to the film layer where the first pixel circuit 8 is located can be defined as the direction from top to bottom). The distance between this part of the first light-emitting element 7 and the first pixel circuit 8 used to drive this part of the first light-emitting element 7 increases, making it more difficult to directly connect the two through vias. For the above reasons, the display panel provided in this application also includes a signal transmission trace 10, which is used to realize the electrical connection between part of the first light-emitting element 7 and part of the first pixel circuit 8. Part of the first pixel circuit 8 transmits the driving signal to the corresponding first light-emitting element 7 through the signal transmission trace 10, so as to ensure that the part of the first light-emitting element 7 that overlaps with the first pixel driving circuit 9 and does not overlap with the first pixel circuit 8 normally receives the driving signal. To clearly show the arrangement of the signal transmission trace 10, Figure 3 The first pixel driving circuit 9 is not shown in the diagram. Figure 3 The rectangular black dots represent the switching holes at different film layers when the signal transmission line 10 is electrically connected to the first pixel circuit 8, and the circular black dots represent the switching holes at different film layers when the signal transmission line 10 is electrically connected to the first light-emitting element 7.

[0035] One point that needs to be made is that, Figure 4 Only a portion of the first light-emitting element 7 that overlaps with the projection of the first pixel driving circuit setting area 6 is shown as an example; the first light-emitting element 7 that overlaps with the projection of the first pixel circuit setting area 5 is not shown.

[0036] In addition, such as Figure 4As shown, at least a portion of the signal transmission traces 10 and the connection traces 2 are disposed on the same layer. Thus, at least a portion of the signal transmission traces 10 and the connection traces 2 can be fabricated using the same metal layer and the same etching process, without adding any additional fabrication steps or increasing the thickness of the display panel. Furthermore, the connection traces 2 are generally disposed on a different layer from the electronic components (thin-film transistors and / or capacitors, etc.) in the first pixel driving circuit 9 or the first pixel circuit 8. That is, the signal transmission traces 10 disposed on the same layer as the connection traces 2 and the electronic components in the first pixel driving circuit 9 are located on different film layers. The signal transmission traces 10 do not occupy the positions of the original electronic components or traces in the first pixel driving circuit 9, which helps to reduce the fabrication difficulty of the signal transmission traces 10. Figure 4 The first pixel driving circuit 9 or the first pixel circuit 8 shown are their respective electronic component structures.

[0037] Since the overall size of the first pixel circuit setting area 5 is compressed, but the number of first pixel circuits 8 contained therein remains unchanged, it is necessary to adaptively reduce the projected size of each first pixel circuit 8 in the thickness direction Z of the display panel, that is, to reduce the area occupied by the first pixel circuit 8 in the first display area AA1. This embodiment of the invention does not limit the specific method of reducing the size of the first pixel circuit 8; those skilled in the art can design it according to actual needs. For example, the number of electronic components in the first pixel circuit 8 can be reduced, the size of the electronic components can be reduced, the distance between the electronic components can be reduced, or the driving method of the first light-emitting element 7 can be changed, but it is not limited to these.

[0038] Optionally, embodiments of the present invention do not limit the specific form of the signal transmission line 10. Figure 3 The example shown is a straight line for the signal transmission line 10, but it is not limited to this and can also be a curve or a broken line, etc. Those skilled in the art can set it according to actual needs.

[0039] In this application, the display panel includes a display area and a non-display area. The display panel also includes multiple data lines, multiple connection traces, and multiple signal traces, with the connection traces electrically connected to the data lines and signal traces respectively. The data lines and connection traces are located in the display area, while the signal traces are located in the non-display area. This reduces the area occupied by the signal traces in the non-display area, thereby reducing the size of the bottom bezel of the display panel. Furthermore, the display area includes a first display area, which includes a first light-emitting element setting area, a first pixel circuit setting area, and a first pixel driving circuit setting area. The first light-emitting element setting area has multiple first light-emitting elements, the first pixel circuit setting area has multiple first pixel circuits, and the first pixel driving circuit setting area has a first pixel driving circuit. The first pixel circuits are electrically connected to both the first pixel driving circuit and the first light-emitting elements. Along the thickness direction of the display panel, the first light-emitting element setting area overlaps with the first pixel circuit setting area and also overlaps with the first pixel driving circuit setting area. By placing the first pixel driving circuit within the first display area, the number of pixel driving circuits located in the left and right non-display areas of the display panel can be reduced, thereby reducing the size of the left and right bezels of the display panel. In addition, this application also provides that a portion of the first pixel circuit is electrically connected to the first light-emitting element via signal transmission traces, with at least a portion of the signal transmission traces and connection traces disposed on the same layer. By adopting the above scheme, it is possible to ensure that the first light-emitting element can normally receive the driving signals transmitted by the first pixel circuit, while also reducing the difficulty of laying out the signal transmission traces and simplifying the fabrication process of the signal transmission traces.

[0040] Optional, you can continue to refer to Figure 1 and Figure 2 In a possible embodiment, the first display area AA1 may include two first pixel circuit setting areas 5; the first pixel driving circuit setting area 6 is located between the two first pixel circuit setting areas 5.

[0041] Specifically, in this application, two first pixel circuit setting areas 5 can be provided within the first display area AA1, and the two first pixel circuit setting areas 5 are located on both sides of the first pixel driving circuit setting area 6 along the first direction X. In this way, the first pixel driving circuit 9 can be electrically connected to the first pixel circuits 8 on both sides simultaneously, thereby driving the first pixel circuits 8 on both sides simultaneously. When the first pixel driving circuit 9 transmits driving control signals to the first pixel circuits 8 on both sides simultaneously, the voltage drop of the driving control signals during transmission on the driving control signal lines is the same or similar, and both are small, which is beneficial to improving the overall brightness uniformity of the first light-emitting element 7.

[0042] Of course, in other embodiments not shown, only one first pixel circuit setting area 5 may be provided in the first display area AA1, and the first pixel driving circuit setting area 6 may be located on one side of the first pixel circuit setting area 5. In this configuration, the first pixel circuit 8 may be located on one side of the first display area AA1 along the first direction X, and the first pixel driving circuit 9 may be located on the other side of the first display area AA1 along the first direction X, which helps to reduce the difficulty of setting the first pixel circuit 8 and the first pixel driving circuit 9. In the embodiments of this application, the first display area AA1 including two first pixel circuit setting areas 5 is used as an example for description.

[0043] Optional, Figure 5 for Figure 1 Enlarged structural diagram at point D Figure 6 for Figure 5 A schematic diagram of the cross-sectional structure along the E-E' direction, which can be referenced. Figure 1 , Figure 5 and Figure 6 In a possible embodiment, the display area AA may further include a second display area AA2. The second display area AA2 includes a second light-emitting element setting area 11 and a second pixel circuit setting area 12. The second light-emitting element setting area 11 is provided with a plurality of second light-emitting elements 13, and the second pixel circuit setting area 12 is provided with a plurality of second pixel circuits 14. The second pixel circuits 14 are electrically connected to the first pixel driving circuit 9 and the second light-emitting elements 13 respectively. Along the thickness direction Z of the display panel, the second light-emitting element setting area 11 and the second pixel circuit setting area 12 overlap. The second display area AA2 is located on the side of the first pixel circuit setting area 5 away from the first pixel driving circuit setting area 6.

[0044] Specifically, such as Figure 1 , Figure 2 and Figure 6 As shown, a second display area AA2 is also provided within the display area AA. The second display area AA2 can be further divided into a second light-emitting element setting area 11 and a second pixel circuit setting area 12. The second light-emitting element setting area 11 is used to set multiple second light-emitting elements 13, which can be organic light-emitting diodes (OLED), Mini LED, Micro LED, or quantum dot light-emitting diodes (QLED), etc. The second pixel circuit setting area 12 is used to set multiple second pixel circuits 14, which can be 2T1C circuits, 7T1C circuits, or 7T2C circuits, etc. "2T1C circuit" refers to a pixel circuit that includes two thin-film transistors (T) and one capacitor (C), and so on for "7T1C circuit", "7T2C circuit", etc.

[0045] The second pixel circuit 14 is electrically connected to the second light-emitting element 13 to provide a driving signal to the second light-emitting element 13, thereby driving the second light-emitting element 13 to emit light. It is understood that, generally, the second pixel circuit 14 and the second light-emitting element 13 correspond one-to-one, with each second light-emitting element 13 driven by its corresponding second pixel circuit 14. For example, the second pixel circuit 14 may be electrically connected to the anode of the second light-emitting element 13 to transmit the driving signal to the second light-emitting element 13.

[0046] Continue to refer to Figure 1 , Figure 5 and Figure 6 Unlike the first display area AA1, the second display area AA2 does not require a pixel driving circuit, therefore the size of the second pixel circuit 14 within the second pixel circuit setting area 12 does not need to be compressed. The second light-emitting element setting area 11 and the second pixel circuit setting area 12 can overlap along the thickness direction Z of the display panel. Each second light-emitting element 13 can be driven by the second pixel circuit 14 that partially overlaps with it, and the two can be electrically connected directly through the via b between the film layers. At the same time, the second pixel circuit 14 is still electrically connected to the first pixel driving circuit 9 (electrical connection not shown in the figure) and receives the driving control signal output by the first pixel driving circuit 9.

[0047] The second pixel circuit setting area 12 can be located on the side of the first pixel circuit setting area 5 that is away from the first pixel driving circuit 9. That is, relative to the first pixel circuit 8, the second pixel circuit 14 is closer to the bezel area of ​​the display panel. For example, when the number of first pixel circuit setting areas 5 is 2, the number of second pixel circuits 14 can also be 2. In this case, along the first direction X, the second pixel circuit setting area 12, the first pixel circuit setting area 5, the first pixel driving circuit setting area 6, the first pixel circuit setting area 5, and the second pixel circuit setting area 12 are arranged sequentially.

[0048] In this embodiment, only the design of the first pixel circuit 8 in the first display area AA1 can be improved, while the second pixel circuit 14 in the second display area AA2 can still be designed using the existing scheme, thereby simplifying the overall manufacturing process of the display panel.

[0049] Optional, can be referenced Figure 4 and Figure 6The first pixel circuit 8 includes at least two first electronic components 15, each of which includes at least one first transistor T1 and at least one first storage capacitor C1; the second pixel circuit 14 includes at least two second electronic components 16, each of which includes at least one second transistor T2 and at least one second storage capacitor C2; the channel width-to-length ratio of at least one first transistor T1 is less than that of the channel width-to-length ratio of the second transistor T2, the area of ​​at least one first storage capacitor C1 is less than that of the second storage capacitor C2, and / or, along the first direction X, the distance between two adjacent first electronic components 15 is less than the distance between two adjacent second electronic components 16; the first direction X is the same as the arrangement direction of the plurality of data lines 1.

[0050] The first pixel circuit 8 can be composed of at least two first electronic components 15, each of which is at least one first transistor T1 and at least one first storage capacitor C1. The first transistor T1 is the thin-film transistor mentioned above. Correspondingly, the second pixel circuit 14 can be composed of at least two second electronic components 16, each of which is at least one second transistor T2 and at least one second storage capacitor C2.

[0051] refer to Figure 1 Since the first driving pixel circuit setting area is located in the central region along the first direction X in the first display area AA1, the overall size of the first pixel circuit setting area 5 along the first direction X is compressed. Therefore, in this embodiment, the area of ​​the first pixel circuit setting area 5 can be compressed by reducing the size of the first electronic component 15 in the first pixel circuit 8 along the first direction X, and / or by reducing the distance between two adjacent first electronic components 15 along the first direction X.

[0052] Specifically, generally, the channel of a transistor has a width along the first direction X and a length along the second direction Y. Therefore, to reduce the size of the first electronic component 15 along the first direction X, the channel width-to-length ratio of the first transistor T1 can be appropriately reduced. Additionally, the product of the dimensions of the storage capacitor along the first direction X and / or the second direction Y is the area of ​​the storage capacitor. Therefore, to reduce the size of the first electronic component 15 along the first direction X, the area of ​​the first storage capacitor C1 can also be appropriately reduced. It is understood that the size of the second pixel circuit setting area 12 does not need to be compressed, and the size of the second electronic component 16 does not need to be reduced. Therefore, the channel width-to-length ratio of the second transistor T2 will be slightly larger than that of the first transistor T1, and the area of ​​the second storage capacitor C2 will be slightly larger than the area of ​​the first storage capacitor C1.

[0053] Correspondingly, the distance between two adjacent second electronic components 16 along the first direction X does not need to be reduced. If the distance between adjacent first electronic components 15 along the first direction X is appropriately reduced, the distance between two adjacent second electronic components 16 along the first direction X will be slightly greater than the distance between two adjacent first electronic components 15 along the first direction X.

[0054] Compared to compressing the first pixel circuit setting area 5 by reducing the number of first electronic components 15 in the first pixel circuit 8 (e.g., changing from a 7T1C circuit to a 2T1C circuit), the solution in this example does not cause a brightness difference between the first light-emitting element 7 and the second light-emitting element 13, resulting in better display uniformity. Compared to compressing the first pixel circuit setting area 5 by changing the driving method of the first light-emitting element 7 (e.g., changing from one first pixel circuit 8 driving one first light-emitting element 7 to one first pixel circuit 8 driving at least two first light-emitting elements 7), the solution in this example does not reduce the PPI, and there are no additional drive control lines added to the circuit, thus reducing manufacturing complexity.

[0055] Optional, Figure 7 This is a partially enlarged structural diagram of a display panel provided in an embodiment of the present invention, which can be referred to in conjunction with reference to [reference needed]. Figure 3 and Figure 7 In a possible embodiment, the first pixel circuit setting area 5 includes multiple first sub-pixel circuit setting areas 17 and multiple second sub-pixel circuit setting areas 18. The first sub-pixel circuit setting area 17 is provided with a first sub-pixel circuit 24, and the second sub-pixel circuit setting area 18 is provided with a second sub-pixel circuit 19. The first light-emitting element 7 area includes a first sub-light-emitting element setting area 20 and a second sub-light-emitting element setting area 21. The first sub-light-emitting element setting area 20 is provided with a first sub-light-emitting element 22, and the second sub-light-emitting element setting area 21 is provided with a second sub-light-emitting element 23. The first sub-pixel circuit 24 is directly electrically connected to the first sub-light-emitting element 22, or the first sub-pixel circuit 24 is electrically connected to the first sub-light-emitting element 22 through a first signal transmission line 101. The second sub-pixel circuit 19 is electrically connected to the second sub-light-emitting element 23 through a second signal transmission line 102, and the length of the second signal transmission line 102 is greater than the length of the first signal transmission line 101.

[0056] Specifically, such as Figure 3 and Figure 7As shown, in this embodiment, the first pixel circuit setting area 5 can be further divided into multiple first sub-pixel circuit setting areas 17 and multiple second sub-pixel circuit setting areas 18. The first sub-pixel circuit setting areas 17 are used to set first sub-pixel circuits 24, and the second sub-pixel circuit setting areas 18 are used to set second sub-pixel circuits 19. Correspondingly, the first light-emitting element setting area 4 can be divided into a first sub-light-emitting element setting area 20 and a second sub-light-emitting element setting area 21. The first sub-light-emitting element setting area 20 is used to set multiple first sub-light-emitting elements 22, and the second sub-light-emitting element setting area 21 is used to set multiple second sub-light-emitting elements 23. The first sub-pixel circuit 24 drives and controls the first sub-light-emitting elements 22 to emit light, and the second sub-pixel circuit 19 drives and controls the second sub-light-emitting elements 23 to emit light.

[0057] Along the thickness direction Z of the display panel, the first sub-light-emitting element setting area 20 may overlap with the first pixel driving circuit setting area 6, and the second sub-light-emitting element setting area 21 may overlap with the first pixel driving circuit setting area 6. (Reference) Figure 3 and Figure 7 Understandably, in this configuration, the first sub-light-emitting element 22 is relatively close to the first sub-pixel circuit 24 that transmits the driving signal to it. Therefore, the first sub-light-emitting element 22 can be directly electrically connected to the first sub-pixel (e.g., ...). Figure 7 As shown), it can also be electrically connected to the first sub-pixel circuit 24 via signal transmission line 10 (as shown). Figure 3 As shown in the figure, the direct electrical connection mentioned here refers to the electrical connection between the two through the via b between the membrane layers.

[0058] Furthermore, as mentioned in the above embodiments, since the second sub-light-emitting element 23 and the second sub-pixel circuit 19 that transmits the driving signal to it are far apart, direct electrical connection between the two is technically challenging. Therefore, the second sub-light-emitting element 23 can be electrically connected to the second sub-pixel circuit 19 through the signal transmission trace 10.

[0059] The signal transmission trace 10 used to connect the first sub-pixel circuit 24 and the first sub-light-emitting element 22 is defined as the first signal transmission trace 101, and the signal transmission trace 10 used to connect the second sub-pixel circuit 19 and the second sub-light-emitting element 23 is defined as the second signal transmission trace 102. Given that the distance between the first sub-pixel circuit 24 and the first sub-light-emitting element 22 along the first direction X is greater than the distance between the second sub-pixel circuit 19 and the second sub-light-emitting element 23 along the first direction X, the length of the first signal transmission trace 101 along the first direction X is less than the length of the second signal transmission trace 102 along the first direction X.

[0060] Optional, you can continue to refer to Figure 3In a possible embodiment, the first sub-pixel circuit setting area 17 is located on the side of any second sub-pixel circuit setting area 18 away from the first pixel driving circuit 9.

[0061] Specifically, in Figure 3 In the illustrated embodiment, the first sub-pixel circuit setting area 17 is entirely located on the side of the second sub-pixel circuit setting area 18 that is away from the first pixel driving circuit setting area 6. That is, the first sub-pixel circuit setting area 17 is entirely located in the outer region of the first pixel circuit setting area 5. As a result, the distance between the second sub-pixel circuit setting area 18 and the second sub-light-emitting element setting area 21 is closer, the length of the second signal transmission trace 102 along the first direction X is shorter, and the voltage drop when transmitting the driving signal is smaller.

[0062] in, Figure 3 The example shows an electrical connection between the first sub-pixel circuit 24 and the first sub-light-emitting element 22 via a first signal transmission trace 101. However, the actual configuration is not limited to this; they can also be directly electrically connected. When they are directly electrically connected, the first signal transmission trace 101 is not required.

[0063] Optional, you can continue to refer to Figure 7 In another possible embodiment, there exists a first sub-pixel circuit setting area 17 located between two adjacent second sub-pixel circuit setting areas 18, and there exists a second sub-pixel circuit setting area 18 located between two adjacent first sub-pixel circuit setting areas 17.

[0064] Specifically, Figure 7 In the illustrated embodiment, a portion of the first sub-pixel circuit setting area 17 and a portion of the second sub-pixel circuit setting area 18 may be interspersed along the first direction X. Along the first direction X, one or more first sub-pixel circuit setting areas 17 are arranged between two adjacent second sub-pixel circuit setting areas 18; correspondingly, along the first direction X, one or more second sub-pixel circuit setting areas 18 are arranged between two adjacent first sub-pixel circuit setting areas 17. Figure 7 In this configuration, the first sub-pixel circuit 24 and the first sub-light-emitting element 22 can be directly electrically connected, and the signal transmission trace 10 only includes the second signal transmission trace 102. Thus, since the second sub-pixel circuit areas 18 are spaced a certain distance apart, the density of the second signal transmission trace 102 can be reduced to some extent. This reduces the difficulty of laying out the second signal transmission trace 102 while preventing interference between the driving signals transmitted between adjacent second signal transmission traces 102.

[0065] For example, please refer to... Figure 7Along the first direction X, the first sub-pixel circuit setting area 17 and the second sub-pixel circuit setting area 18 are alternately and cyclically set; the first direction X is the same as the arrangement direction of the multiple data lines 1.

[0066] Specifically, such as Figure 7 As shown, the first sub-pixel circuit setting area 17 and the second sub-pixel circuit setting area 18 can be arranged alternately along the first direction X. A second sub-pixel circuit setting area 18 is positioned between any two adjacent first sub-pixel circuit setting areas 17, and a first sub-pixel circuit setting area 17 is positioned between any two adjacent second sub-pixel circuit setting areas 18. With this configuration, the overall arrangement of the second signal transmission trace 102 is relatively uniform.

[0067] Of course, the actual arrangement of the first sub-pixel circuit setting area 17 and the second sub-pixel circuit setting area 18 is not limited to this, and those skilled in the art can adjust it according to actual needs. When the arrangement of the first sub-pixel circuit setting area 17 and the second sub-pixel circuit setting area 18 is changed, the setting of the first signal transmission line 101 and the second signal transmission line 102 can also be adjusted accordingly.

[0068] Additionally, refer to Figure 7 In the diamond pixel arrangement, red light-emitting elements R, green light-emitting elements G, blue light-emitting elements B, and green light-emitting elements G are arranged alternately and cyclically along the first direction X. One red light-emitting element R (or blue light-emitting element B) and one green light-emitting element G constitute the first sub-pixel. In this arrangement, for sub-pixels in the same row, the green light-emitting element G is always located at the upper position along the second direction Y. Therefore, in this embodiment, for sub-pixels in the same row, the orthographic projection of the second signal transmission line 102 electrically connected to the green light-emitting element G on the plane of the display panel can be located on the side of the current row sub-pixel (or the current row second sub-pixel circuit 19) closer to the previous row sub-pixel (or the previous row (or the previous row second sub-pixel circuit 19); the orthographic projection of the second signal transmission line 102 electrically connected to the red light-emitting element R or the blue light-emitting element B on the plane of the display panel is located on the side of the current row sub-pixel (or the current row second sub-pixel circuit 19) closer to the next row sub-pixel (or the next row second sub-pixel circuit 19), so as to facilitate the arrangement of the second signal transmission line 102.

[0069] For other types of light-emitting elements, the arrangement of the second signal transmission line 102 can also be adjusted accordingly. Examples of each type will not be given in this embodiment.

[0070] Those skilled in the art will recognize that the first pixel driving circuit 9, used to provide driving control signals to the first pixel circuit 8, includes various types, such as a scanning driving circuit for transmitting scanning control signals and / or a light emission control driving circuit for transmitting light emission control signals. The scanning driving circuit is electrically connected to the first pixel circuit 8 via scan lines, and the light emission control driving circuit is electrically connected to the first pixel circuit 8 via light emission control signal lines. The scan lines and light emission control signal lines are the driving control signal lines. This embodiment of the invention does not limit the specific configuration type of the first pixel driving circuit 9; those skilled in the art can configure it according to actual needs.

[0071] Optional, Figure 8 This is a partially enlarged structural diagram of another display panel provided in an embodiment of the present invention, which can be referred to. Figure 8 Multiple first pixel circuits 8 can be arranged in an array; the first pixel driving circuit 9 includes a scanning driving circuit 25; the display panel also includes a light emission control driving circuit 26 located in the non-display area NA, the light emission control driving circuit 26 includes multiple cascaded light emission control units 27; the light emission control units 27 are electrically connected to the adjacent n rows of first pixel circuits 8, and the light emission control units 27 overlap with the adjacent n rows of first pixel circuits 8 along the first direction X; the first direction X is the same as the arrangement direction of the multiple data lines 1; where n≥2 and n is an integer.

[0072] like Figure 8 As shown, multiple first pixel circuits 8 can be arranged in an array along the first direction X and the second direction Y. In this embodiment, the first pixel driving circuit 9 can be a scan driving circuit 25, which provides scan control signals to the arrayed first pixel circuits 8. The light emission control driving circuit 26 is disposed in the non-display area NA, specifically in the non-display area NA to the left and / or right of the display area AA.

[0073] The scan driving circuit 25 can be composed of multiple cascaded scan driving units 28. Each scan driving unit 28 can be electrically connected to a row of first pixel circuits 8 via a scan line 29 extending along the first direction X, and transmits scan control signals to the row of first pixel circuits 8. That is, the scan driving unit 28 can drive and control a row of first pixel circuits 8 in a one-to-one manner to ensure the normal operation of the first pixel circuits 8. When the number of first pixel circuit setting areas 5 is 2, the scan driving unit 28 simultaneously transmits scan control signals to the first pixel circuits 8 on both sides.

[0074] The light-emitting control driving circuit 26 consists of multiple cascaded light-emitting control units 27. Each light-emitting control unit 27 can be electrically connected to n rows of first pixel circuits 8 via a light-emitting control signal line 30 extending along the first direction X, for simultaneously driving and controlling n rows of first pixel circuits 8. That is, the light-emitting control units 27 are in a one-to-many driving mode, with each light-emitting control unit 27 driving at least two rows of first pixel circuits 8. Those skilled in the art will understand that, generally, the enable phase of the light-emitting control signal is relatively long, and the one-to-many driving mode of the light-emitting control units 27 will not significantly affect the display effect of the display panel. At the same time, the one-to-many driving mode of the light-emitting control units 27 helps to reduce the difficulty of laying out the signal lines between the light-emitting control units 27 and the first pixel circuits 8. The figure exemplarily shows each light-emitting control unit 27 electrically connected to two rows of first pixel circuits 8, but the actual setup is not limited to this.

[0075] Continue to refer to Figure 8 In this embodiment, the projection of the light-emitting control unit 27 along the first direction X and the projection of the n rows of first pixel circuits 8 electrically connected to it along the first direction X may overlap. In this configuration, the length of the light-emitting control unit 27 along the second direction Y is similar to or the same as the length of the n rows of first pixel circuits 8 along the second direction Y.

[0076] in, Figure 8 An exemplary embodiment shows that light-emitting control driving circuits 26 are provided in the non-display areas NA on both the left and right sides of the display panel. In this configuration, the light-emitting control units 27 at the same level in the non-display areas NA on both sides are electrically connected to the same n-row first pixel circuits 8. The light-emitting control units 27 can drive the n-row first pixel circuits 8 in a bilateral driving manner. The adjacent n-row first pixel circuits 8 simultaneously receive the light-emitting control signals transmitted by the light-emitting control units 27 in the non-display areas NA on both sides, thereby reducing the load on the light-emitting control signal line 30. Of course, in other embodiments not shown, the light-emitting control driving circuit 26 may be provided only in the non-display area NA on one side, and the light-emitting control unit 27 may drive the n-row first pixel circuits 8 in a unilateral driving manner. This embodiment of the present invention will not describe it in detail.

[0077] Optional, Figure 9 This is a partially enlarged structural schematic diagram of another display panel provided in an embodiment of the present invention, with reference to... Figure 9In other possible embodiments, a plurality of first pixel circuits 8 are arrayed, and the display panel includes a plurality of first pixel circuit groups 31, which are arranged along a second direction Y. Each first pixel circuit group 31 includes 2*n rows of first pixel circuits arranged adjacent to each other along the second direction Y. The second direction Y is the same as the extension direction of the data line 1, n≥2 and n is an integer. The first pixel driving circuit 9 includes a scanning driving circuit 25. The non-display area NA includes a first non-display area NA1 and a second non-display area NA2 located on opposite sides of the display area AA. The display panel also includes a first light emission control driving circuit 261 located in the first non-display area NA1 and a second light emission control driving circuit 262 located in the second non-display area NA2. The system includes a multi-level first light-emitting control unit 271 and a second light-emitting control driving circuit 262, which includes a multi-level second light-emitting control unit 272. The i-th level first light-emitting control unit 271 is electrically connected to the first n rows of first pixel circuits in the i-th group of first pixel circuits 31, and the i-th level second light-emitting control unit 272 is electrically connected to the last n rows of first pixel circuits in the i-th group of first pixel circuits 31. The light-emitting control signal output terminal 32 of the i-th level first light-emitting control unit 271 is electrically connected to the enable signal receiving terminal 33 of the i-th level second light-emitting control unit 272. Along the first direction X, both the i-th level first light-emitting control unit 271 and the i-th level second light-emitting control unit 272 overlap with the i-th group of first pixel circuits 31. The first direction X is the same as the arrangement direction of the multiple data lines 1.

[0078] Specifically, such as Figure 9 As shown, the arrangement of the first pixel circuit 8 is similar to... Figure 8 The embodiment shown is the same; the first pixel driving circuit 9 can still be the scanning driving circuit 25, and the light emission control driving circuit 26 can still be located in the non-display areas NA on both sides of the display area AA. The difference lies in that, in this embodiment, the light emission control driving circuit 26 can be divided into a first light emission control driving circuit 261 and a second light emission control driving circuit 262. The first light emission control driving circuit 261 is located in the first non-display area NA1 on one side of the display panel, and the second light emission control driving circuit 262 is located in the second non-display area NA2 on the other side of the display panel. The first light emission control driving circuit 261 is composed of multiple levels of first light emission control units 271 arranged along the second direction Y, and the second light emission control driving circuit 262 is composed of multiple levels of second light emission control units 272 arranged along the second direction Y.

[0079] In addition, in this embodiment, the plurality of first pixel circuits 8 are further divided into multiple groups of first pixel circuit groups 31. Each group of first pixel circuit groups 31 has 2*n rows of first pixel circuits 8 adjacent to each other along the second direction Y. The multiple groups of first pixel circuit groups 31 are arranged along the second direction Y. Among them, the 2*n rows of first pixel circuits 8 in each group of first pixel circuit groups 31 are driven by a first light-emitting control unit 271 and a second light-emitting control unit 272 arranged at the same level.

[0080] Specifically, the first n rows of first pixel circuits 8 in the i-th group of first pixel circuits 31 receive the light-emitting control signal output by the i-th level first light-emitting control unit 271, and the last n rows of first pixel circuits 8 receive the light-emitting control signal output by the i-th level second light-emitting control unit 272. i ≥ 1 and i is an integer. Taking n = 2 as an example, the first two rows of first pixel circuits 8 in the first group of first pixel circuits 31 receive the light-emitting control signal output by the first level first light-emitting control unit 271, and the last two rows of first pixel circuits 8 receive the light-emitting control signal output by the first level second light-emitting control unit 272. The connection method of other first pixel circuit groups 31 and other light-emitting control driving circuits 26 is similar.

[0081] In addition, such as Figure 9 As shown, the first light-emitting control unit 271 and the second light-emitting control unit 272 of the first to i levels can be cascaded alternately. Simply put, the light-emitting control signal output terminal 32 of the first light-emitting control unit 271 is electrically connected to the enable signal receiving terminal 33 of the second light-emitting control unit 272 of the first level. The light-emitting control signal output by the first light-emitting control unit 271 is used not only to drive the first n rows of first pixel circuits 8 in the first pixel circuit group 31, but also as the enable signal for the second light-emitting control unit 272 of the first level. After receiving the enable signal, the second light-emitting control unit 272 of the first level sends the light-emitting control signal to the last n rows of first pixel circuits 8 in the first pixel circuit group 31. Similarly, the light emission control signal output by the first-level second light emission control unit 272 is not only used to drive the last n rows of first pixel circuits 8 in the first group of first pixel circuits 31, but also used as the enable signal for the second-level first light emission control unit 271. After receiving the enable signal, the second-level first light emission control unit 271 sends the light emission control signal to the first n rows of first pixel circuits 8 in the second group of first pixel circuits 31, and so on.

[0082] In this configuration, each level of the light-emitting control unit 27 can drive the corresponding n-row first pixel circuit 8 using a single-sided driving method. Compared to... Figure 8In the illustrated embodiment, each level of light-emitting control unit 27 overlaps with n rows of first pixel circuits 8 along the first direction X. In this embodiment, under the single-sided driving mode, each level of first light-emitting control unit 271 and the same level of second light-emitting control unit 272 can overlap with 2*n rows of first pixel circuits 8 along the first direction X, thereby further increasing the length of the first light-emitting control unit 271 and the second light-emitting control unit 272 along the second direction Y, and shortening the length of the first light-emitting control unit 271 and the second light-emitting control unit 272 along the first direction X, further improving the narrow bezel effect.

[0083] Optional, Figure 10 This is a partially enlarged structural schematic diagram of another display panel provided in an embodiment of the present invention, with reference to... Figure 10 As shown, in other possible embodiments, the plurality of first pixel circuits 8 are still arranged in an array; the first pixel driving circuit 9 includes a light emission control driving circuit 26, the light emission control driving circuit 26 includes a multi-level cascaded light emission control unit 27; the light emission control unit 27 is electrically connected to the adjacent n rows of first pixel circuits 8, and along the first direction X, the light emission control unit 27 overlaps with the adjacent n rows of first pixel circuits 8; the first direction X is the same as the arrangement direction of the plurality of data lines 1; where n≥2 and n is an integer.

[0084] Specifically, such as Figure 10 As shown, the first pixel circuit 8 is still arranged in an array. However, unlike the previous embodiment, in this embodiment, the first pixel driving circuit 9 can be configured as a light-emitting control driving circuit 26. The scanning driving circuit 25 can be located in the bezel area of ​​the display panel.

[0085] The light-emitting control driving circuit 26 may still include cascaded multi-level light-emitting control units 27, and the light-emitting control units 27 may still be in a one-to-many driving mode. Each level of light-emitting control unit 27 may be configured to overlap with n rows of first pixel circuits 8 electrically connected to it along a first direction X, and each level of light-emitting control unit 27 may be electrically connected to n adjacent rows of first pixel circuits 8 along a second direction Y. When the number of first pixel circuit setting areas 5 is 2, the light-emitting control unit 27 simultaneously transmits light-emitting control signals to the n rows of first pixel circuits 8 on both sides.

[0086] Figure 9 and Figure 10In the illustrated embodiment, either the scan driving circuit 25 or the light emission control driving circuit 26 is located in the display area AA, and the other is located in the non-display area NA. This effectively reduces the bezel size and avoids the problem of too many first pixel driving circuits 9 in the display area AA affecting the normal driving of the first pixel circuit 8 to the first light-emitting element 7. In other embodiments not shown, both the scan driving circuit 25 and the light emission control driving circuit 26 can be located in the display area AA, further reducing the bezel size.

[0087] Optional, you can continue to refer to Figure 8 In a possible embodiment, a plurality of first pixel circuits 8 are arranged in an array; the display panel may also include a plurality of initialization signal lines 34, the initialization signal lines 34 being connected to the first pixel circuits 8 in the same column; the initialization signal lines 34 extend along a second direction Y, and the plurality of initialization signal lines 34 are arranged along a first direction X; the first direction X is the same as the arrangement direction of the plurality of data lines 1, and the second direction Y is the same as the extension direction of the data lines 1.

[0088] Specifically, such as Figure 8 As shown, the first pixel circuits 8 are still arranged in an array, and the display panel also has multiple initialization signal lines 34. The initialization signal lines 34 are arranged in the same way as the data lines 1, extending along the second direction Y and arranged in the first direction X. Each initialization signal line 34 is electrically connected to the first pixel circuits 8 in the same column to transmit an initialization signal to the first pixel circuits 8 in the same column. Figure 8 The diagram only shows the arrangement of the initialization signal lines 34, and does not show their electrical connection with the first pixel circuit 8. Those skilled in the art will understand that each initialization signal line 34 should actually be electrically connected to the same column of the first pixel circuit 8.

[0089] The advantage of this setup is that the initialization signal line 34 is mainly located in the display area AA, and will not occupy the non-display area NA on the left and right sides of the display panel, thus further reducing the size of the left and right bezels of the display panel.

[0090] Optional, you can continue to refer to Figure 8 The display panel may also include an initialization signal bus 35 located in the non-display area NA, the initialization signal bus 35 extending along the first direction X; multiple initialization signal lines 34 are electrically connected to the initialization signal bus 35.

[0091] like Figure 8As shown, an initialization signal bus 35 extending along the first direction X is also provided in the non-display area NA. The initialization signal bus 35 is electrically connected to multiple initialization signal lines 34. The initialization signal bus 35 is used to connect the drive module (not shown in the figure) and the multiple initialization signal lines 34. The initialization signal bus 35 extends along the first direction X and can be located in the upper and / or lower non-display area NA of the display panel, without occupying the area of ​​the left and right non-display areas NA of the display panel.

[0092] Optional, can be referenced Figure 1 and Figure 8 In a possible embodiment, the initialization signal line 34 is set on the same layer as the data line 1; or, the connection trace 2 includes a first connection portion 201 and a second connection portion 202, the first connection portion 201 and the second connection portion 202 are connected, and the first connection portion 201 extends along a first direction X, and the second connection portion 202 extends along a second direction Y; the initialization signal line 34 is set on the same layer as the second connection portion 202.

[0093] Among them, such as Figure 8 As shown, the initialization signal line 34 can be set to be on the same layer as the traces extending in the same direction, thereby reducing the difficulty of laying out the initialization signal line 34. As mentioned in the above embodiment, the initialization signal line 34 extends in the same direction as the data line 1. Therefore, in one possible embodiment, the initialization signal line 34 and the data line 1 can be located on the same film layer and fabricated in the same process.

[0094] Among them, such as Figure 1 As shown, the connection trace 2 can be composed of a first connection portion 201 and a second connection portion 202 that are electrically connected, wherein the first connection portion 201 extends along a first direction X (i.e., the row direction), and the second connection portion 202 extends along a second direction Y (i.e., the column direction). In a possible embodiment, the initialization signal line 34 may also be located in the same film layer as the second connection portion 202 and fabricated in the same process.

[0095] Additionally, you can refer to Figure 4 In this embodiment, the display panel may include a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 sequentially stacked along the light emission direction of the display panel, with each metal layer being insulated from the others. The first transistor T1 in the first pixel circuit 8 includes a gate, a source, and a drain. The gate may be fabricated using the first metal layer M1, and the source and drain may be fabricated using the second metal layer M2. (Data line) Figure 4The data line (not shown) is used to output a data signal to the source (or drain). The data line can also be fabricated using the second metal layer M2. The third metal layer M3 can be used to fabricate a light-shielding metal layer, connection trace 2, power transmission line, and connection bridge between the anode of the first light-emitting element 7 and the source (or drain) of the first transistor T1. The fourth metal layer M4 can be used to fabricate the connection trace 2. Therefore, in this embodiment, the initialization signal line (… Figure 4 (Not shown) can be prepared using a second metal layer M2, a third metal layer M3, or a third metal layer M4.

[0096] Of course, in other embodiments not shown, the initialization signal line 34 can also be fabricated using other metal layers. This application will not describe them in detail, and those skilled in the art can set them according to actual needs.

[0097] Optional, Figure 11 This is a partially enlarged structural schematic diagram of another display panel provided in an embodiment of the present invention, with reference to... Figure 1 and Figure 11 In a possible embodiment, the display panel may further include a virtual connection trace 36 located in the second display area AA2. The virtual connection trace 36 is on the same layer as the connection trace 2 and is insulated from it. The virtual connection trace 36 is electrically connected to the fixed potential signal structure.

[0098] Specifically, the display panel may further include virtual connection traces 36, which are disposed in the second display area AA2 and on the same layer as the connection traces 2. Since no signal transmission traces 10 are disposed in the second display area AA2, the virtual connection traces 36 can improve the balance of resistance differences during signal transmission 10 transmission, ensuring the stability of signal transmission on the display surface. In addition, the virtual connection traces 36 and the signal transmission traces 10 can be disposed on the same film layer, for example, both can be located in the fourth metal layer M4, to improve the uniformity of the trace layout in the fourth metal layer M4, thereby avoiding different light reflectivity in different areas of the display panel due to uneven placement of the signal transmission traces 10, and improving display uniformity.

[0099] Specifically, the virtual connection trace 36 is insulated from the connection trace 2 to prevent the virtual connection trace 36 from interfering with the signals transmitted in the connection trace 2. Furthermore, to prevent the virtual connection trace 36 from sensing other signals and affecting the normal transmission of display signals when it is floating, the virtual connection trace 36 can be electrically adjusted. For example, the virtual connection trace 36 can be electrically connected to a fixed-potential signal structure. In this way, on the one hand, the virtual connection trace 36 transmits a fixed-potential signal, and its potential is not affected by other signals, thus preventing interference; on the other hand, when the virtual connection trace 36 is electrically connected to the fixed-potential signal structure, the resistance loss of the signal in the metal trace providing the fixed-potential signal during transmission can also be reduced, improving the signal transmission effect in the display panel.

[0100] It should be noted that the embodiments of the present invention do not specifically limit the setting position of the fixed potential signal structure. For example, the fixed potential signal structure includes at least one of a positive power supply signal line (not shown in the figure), a negative power supply signal line (not shown in the figure), and an initialization signal line 34.

[0101] The virtual connection trace 36 can be electrically connected to at least one of the positive power signal line, the negative power signal line, and the initialization signal line 34.

[0102] In an optional embodiment, the virtual connection trace 36 can be electrically connected to the negative power signal line. The negative power signal line typically connects from the non-display area NA of the display panel bezel, resulting in high impedance and a large loading of the negative power signal. Connecting the virtual connection trace 36 to it is equivalent to connecting a resistor in parallel with the negative power signal line, effectively reducing the impedance of the negative power signal line, thereby reducing the voltage drop of the negative power signal line and facilitating stable transmission of the negative power signal.

[0103] Optional, can be referenced Figure 1 , Figure 3 , Figure 4 and Figure 7 The connecting trace 2 includes a first connecting portion 201 and a second connecting portion 202. The first connecting portion 201 and the second connecting portion 202 are connected, and the first connecting portion 201 extends along a first direction X, and the second connecting portion 202 extends along a second direction Y. The first direction X is the same as the arrangement direction of the multiple data lines 1, and the second direction Y is the same as the extension direction of the data lines 1. The signal transmission trace 10 is arranged on the same layer as the first connecting portion 201.

[0104] The configuration of the connecting trace 2 has been mentioned in the above embodiments. One end of the first connecting portion 201 is electrically connected to the data line 1, and the other end of the first connecting portion 201 is electrically connected to the second connecting portion 202. The end of the second connecting portion 202 furthest from the first connecting portion 201 is electrically connected to the signal wiring 3. The extension direction of the second connecting portion 202 is the same as the extension direction of the data line 1, and the extension direction of the first connecting portion 201 is the same as the extension direction of the signal transmission trace 10.

[0105] The first connecting portion 201 and the second connecting portion 202 can be arranged in the same layer or in different layers. When they are arranged in the same layer, the first connecting portion 201 and the second connecting portion 202 can both be arranged in the fourth metal layer M4. When they are arranged in different layers, the first connecting portion 201 can be located in the fourth metal layer M4 and the second connecting portion 202 can be located in the third metal layer M3.

[0106] Since the number of metal traces in the fourth metal layer M4 is relatively small, this embodiment can use the fourth metal layer M4 to prepare signal transmission lines, reducing the difficulty of laying signal transmission lines while avoiding mutual interference between adjacent signal transmission traces 10.

[0107] It should be noted that the above Figure 3 In the illustrated embodiment, the signal transmission trace 10 extends entirely along the first direction X, therefore the signal transmission trace 10 can be entirely located in the same film layer. In other embodiments, such as Figure 7 As shown, the signal transmission trace 10 can be composed of a first portion 101 connected along the first direction X and a second portion 102 extending along the second direction Y. In this configuration, the first portion 101 and the first connecting portion 201 can be on the same layer, and the second portion 102 and the second connecting portion 202 can be on the same layer. For example, the first portion 101 and the first connecting portion 201 can both be located in the fourth metal layer M4, and the second portion 102 and the second connecting portion 202 can both be located in the third metal layer M3, so that the same metal film layer only includes metal traces with the same extension direction.

[0108] Optional, Figure 12 This is a partial cross-sectional structural diagram of a display panel provided in an embodiment of the present invention, with reference to... Figure 12 In a possible embodiment, the display panel may further include an encapsulation structure 37 located on the side of the first light-emitting element 7 away from the first pixel circuit 8, the encapsulation structure 37 including an organic encapsulation layer 38; the display panel may also include a barrier structure 39 located in the non-display area NA, the barrier structure 39 surrounding the display area AA, and the barrier structure 39 including a ring of barrier substructures 40; the barrier substructures 40 are used to prevent the organic material in the organic encapsulation layer 38 from extending to the edge of the display panel, and the barrier substructures 40 are used to define the setting boundary of the metal traces in the display area AA.

[0109] Specifically, such as Figure 12 As shown, the display panel also includes an encapsulation structure 37 and a barrier structure 39. The encapsulation structure 37 is located on the side of the first light-emitting element 7 away from the first pixel circuit 8. The barrier structure 39 is disposed in the non-display area NA at the edge of the display panel and surrounds the display area AA. The encapsulation structure 37 may include, but is not limited to, an organic encapsulation layer 38, and may also include stacked organic encapsulation layers 38 and inorganic encapsulation layers 41, etc. The function of the encapsulation structure 37 is to block water, oxygen, and external contaminant particles to prevent water, oxygen, or external contaminant particles from entering the interior of the display panel and affecting the normal operation of the pixel circuit or light-emitting element and the display effect. The organic encapsulation layer 38 can also relieve the stress of adjacent film layers when the display panel is bent, and at the same time play a planarization role.

[0110] The materials forming the organic encapsulation layer 38 may include, but are not limited to, epoxy resins, acrylic resins, acrylic acid, or methacrylic acid; the organic encapsulation layer 38 may be prepared by inkjet printing, and is also not limited to this method. The materials forming the inorganic encapsulation layer 41 may include, but are not limited to, silicon nitride or silicon oxide; the inorganic encapsulation layer 41 may be prepared by atomic layer deposition, chemical vapor deposition, or other methods, and is also not limited to this method.

[0111] In this embodiment, as Figure 12 As shown, the barrier structure 39 is composed of barrier substructures 40 arranged around the display area AA. The barrier substructures 40 prevent the outflow of organic material during inkjet printing to prepare the organic encapsulation layer 38, thus avoiding the epitaxy of organic material. Simultaneously, the barrier substructures 40 also serve as the cutoff boundary for various metal traces d in the display area AA. These metal traces d may include electrode traces in the first light-emitting element 7, metal film layer wiring in the first pixel circuit 8, and metal film layer wiring in the pixel driving circuit, etc. The metal traces d within the display area AA extend from the display area AA to the side of the barrier substructure 40 closest to the display area AA. Of course, the barrier substructure 40 can also serve as the cutoff boundary for various metal traces d in the non-display area NA. The metal traces d in the non-display area NA extend from the side of the non-display area NA closest to the display area AA to the side of the barrier substructure 40 closest to the non-display area NA.

[0112] In this embodiment, a ring of barrier substructure 40 serves to block both the organic encapsulation layer 38 and the metal trace d, which not only ensures the reliability of the display panel but also further reduces the area of ​​the non-display area NA, improving the narrow bezel effect.

[0113] In this embodiment of the invention, the specific shape, material, or other parameters of the retaining wall substructure 40 are not limited, and those skilled in the art can set them according to actual needs. Optionally, the display panel provided in this application may also include any structure known to those skilled in the art, such as a buffer layer, a planarization layer, an optical adhesive layer, etc., which will not be described in detail here.

[0114] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 13 This is a schematic diagram of a display device provided in an embodiment of the present invention. Figure 13 As shown, the display device includes the display panel 100 provided in any embodiment of the present invention. Therefore, the display device provided in the embodiments of the present invention has the corresponding beneficial effects of the display panel provided in the embodiments of the present invention, which will not be elaborated here. For example, the display device may be an electronic device such as a mobile phone, computer, smart wearable device (e.g., smartwatch), and in-vehicle display device, and the embodiments of the present invention do not limit it to this.

[0115] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, Includes display area and non-display area; The display panel also includes multiple data lines, multiple connection traces, and multiple signal traces. The connection traces are electrically connected to the data lines and the signal traces, respectively. The data lines and the connection traces are located in the display area, and the signal traces are located in the non-display area. The display area includes a first display area, which includes a first light-emitting element setting area, a first pixel circuit setting area, and a first pixel driving circuit setting area. The first light-emitting element setting area is provided with a plurality of first light-emitting elements, the first pixel circuit setting area is provided with a plurality of first pixel circuits, and the first pixel driving circuit setting area is provided with a first pixel driving circuit. The first pixel circuits are electrically connected to the first pixel driving circuit and the first light-emitting elements, respectively. Along the thickness direction of the display panel, the first light-emitting element setting area overlaps with the first pixel circuit setting area and also overlaps with the first pixel driving circuit setting area. A portion of the first pixel circuit is electrically connected to the first light-emitting element via signal transmission traces, and at least a portion of the signal transmission traces are disposed on the same layer as the connection traces; The display area further includes a second display area, which includes a second light-emitting element setting area and a second pixel circuit setting area. The second light-emitting element setting area is provided with a plurality of second light-emitting elements, and the second pixel circuit setting area is provided with a plurality of second pixel circuits. The second pixel circuits are electrically connected to the first pixel driving circuit and the second light-emitting elements, respectively. Along the thickness direction of the display panel, the second light-emitting element setting area and the second pixel circuit setting area overlap. The second display area is located on the side of the first pixel circuit setting area that is away from the first pixel driving circuit setting area; The first pixel circuit includes at least two first electronic components, and the at least two first electronic components include at least one first transistor and at least one first storage capacitor; The second pixel circuit includes at least two second electronic components, each of which includes at least one second transistor and at least one second storage capacitor; At least one of the first transistors has a channel width-to-length ratio smaller than that of the second transistor, at least one of the first storage capacitors has an area smaller than that of the second storage capacitor, and / or, along a first direction, the distance between two adjacent first electronic components is smaller than the distance between two adjacent second electronic components; the first direction is the same as the arrangement direction of the plurality of data lines.

2. The display panel according to claim 1, characterized in that, The first display area includes two first pixel circuit setting areas; The first pixel driving circuit setting area is located between the two first pixel circuit setting areas.

3. The display panel according to claim 1, characterized in that, The first pixel circuit setting area includes multiple first sub-pixel circuit setting areas and multiple second sub-pixel circuit setting areas. The first sub-pixel circuit setting areas are provided with first sub-pixel circuits, and the second sub-pixel circuit setting areas are provided with second sub-pixel circuits. The first light-emitting element setting area includes a first sub-light-emitting element setting area and a second sub-light-emitting element setting area, wherein the first sub-light-emitting element setting area is provided with a first sub-light-emitting element, and the second sub-light-emitting element setting area is provided with a second sub-light-emitting element; The first sub-pixel circuit is directly electrically connected to the first sub-light-emitting element, or the first sub-pixel circuit is electrically connected to the first sub-light-emitting element through a first signal transmission line. The second sub-pixel circuit is electrically connected to the second sub-light-emitting element through a second signal transmission line, and the length of the second signal transmission line is greater than the length of the first signal transmission line.

4. The display panel according to claim 3, characterized in that, The first sub-pixel circuit setting area is located on the side of any second sub-pixel circuit setting area away from the first pixel driving circuit.

5. The display panel according to claim 3, characterized in that, There exists a first sub-pixel circuit setting area located between two adjacent second sub-pixel circuit setting areas, and there exists a second sub-pixel circuit setting area located between two adjacent first sub-pixel circuit setting areas.

6. The display panel according to claim 5, characterized in that, Along the first direction, the first sub-pixel circuit setting area and the second sub-pixel circuit setting area are alternately and cyclically set; the first direction is the same as the arrangement direction of the plurality of data lines.

7. The display panel according to claim 1, characterized in that, Multiple first pixel circuit arrays are arranged; The first pixel driving circuit includes a scanning driving circuit; The display panel also includes a light-emitting control driving circuit located in the non-display area, and the light-emitting control driving circuit includes multiple cascaded light-emitting control units. The light-emitting control unit is electrically connected to the adjacent n rows of the first pixel circuit, and the light-emitting control unit overlaps with the adjacent n rows of the first pixel circuit along the first direction; the first direction is the same as the arrangement direction of the multiple data lines; wherein, n≥2 and n is an integer.

8. The display panel according to claim 1, characterized in that, Multiple first pixel circuit arrays are arranged, and the display panel includes multiple groups of first pixel circuits. The multiple groups of first pixel circuits are arranged along a second direction. Each group of first pixel circuits includes 2*n rows of first pixel circuits arranged adjacent to each other along the second direction. The second direction is the same as the extension direction of the data line, n≥2 and n is an integer. The first pixel driving circuit includes a scanning driving circuit; The non-display area includes a first non-display area and a second non-display area located on opposite sides of the display area; the display panel also includes a first light-emitting control driving circuit located in the first non-display area and a second light-emitting control driving circuit located in the second non-display area, the first light-emitting control driving circuit including a multi-level first light-emitting control unit, and the second light-emitting control driving circuit including a multi-level second light-emitting control unit. The first light-emitting control unit of the i-th stage is electrically connected to the first n rows of the first pixel circuits in the i-th group of the first pixel circuits, and the second light-emitting control unit of the i-th stage is electrically connected to the last n rows of the first pixel circuits in the i-th group of the first pixel circuits. The light-emitting control signal output terminal of the first light-emitting control unit of the i-th stage is electrically connected to the enable signal receiving terminal of the second light-emitting control unit of the i-th stage. Along the first direction, both the first light-emitting control unit of the i-th stage and the second light-emitting control unit of the i-th stage overlap with the first pixel circuits in the i-th group. The first direction is the same as the arrangement direction of the multiple data lines.

9. The display panel according to claim 1, characterized in that, Multiple first pixel circuit arrays are arranged; The first pixel driving circuit includes a light emission control driving circuit, which includes multiple cascaded light emission control units. The light-emitting control unit is electrically connected to the adjacent n rows of the first pixel circuit, and the light-emitting control unit overlaps with the adjacent n rows of the first pixel circuit along the first direction; the first direction is the same as the arrangement direction of the multiple data lines; wherein, n≥2 and n is an integer.

10. The display panel according to claim 1, characterized in that, Multiple first pixel circuit arrays are arranged; The display panel also includes multiple initialization signal lines, which are connected to the first pixel circuit column in the same column; the initialization signal lines extend along a second direction, and the multiple initialization signal lines are arranged along a first direction; the first direction is the same as the arrangement direction of the multiple data lines, and the second direction is the same as the extension direction of the data lines.

11. The display panel according to claim 10, characterized in that, The display panel also includes an initialization signal bus located in the non-display area, the initialization signal bus extending along the first direction; All of the initialization signal lines are electrically connected to the initialization signal bus.

12. The display panel according to claim 10, characterized in that, The initialization signal line is configured on the same layer as the data line; Alternatively, the connection trace includes a first connection portion and a second connection portion, the first connection portion and the second connection portion are connected, and the first connection portion extends along the first direction and the second connection portion extends along the second direction; the initialization signal line is disposed on the same layer as the second connection portion.

13. The display panel according to claim 1, characterized in that, The display panel also includes a virtual connection trace located in the second display area, the virtual connection trace being on the same layer as the connection trace and insulated from it; The virtual connection trace is electrically connected to the fixed potential signal structure.

14. The display panel according to claim 13, characterized in that, The fixed potential signal structure includes at least one of a positive power supply signal line, a negative power supply signal line, and an initialization signal line.

15. The display panel according to claim 1, characterized in that, The connection trace includes a first connection portion and a second connection portion, the first connection portion and the second connection portion are connected, and the first connection portion extends along a first direction, and the second connection portion extends along a second direction; the first direction is the same as the arrangement direction of the plurality of data lines, and the second direction is the same as the extension direction of the data lines; The signal transmission trace is located on the same layer as the first connection section.

16. The display panel according to claim 1, characterized in that, The display panel further includes an encapsulation structure located on the side of the first light-emitting element away from the first pixel circuit, the encapsulation structure including an organic encapsulation layer; The display panel also includes a barrier structure located in the non-display area, the barrier structure surrounding the display area, and the barrier structure including a ring of barrier substructures; The barrier substructure is used to prevent the organic material in the organic encapsulation layer from extending to the edge of the display panel, and the barrier substructure is used to define the setting boundary of the metal traces in the display area.

17. A display device, characterized in that, Includes the display panel as described in any one of claims 1-16.

Images