Flip-flop with transistors having different threshold voltages, semiconductor device with the same, and method for their manufacture

Abstract

Semiconductor device (100B) comprising: a cell region (102B) containing active regions extending in a first direction and comprising transistor components formed therein; wherein the transistors of the cell region (102B) are arranged to function as a D flip-flop (234, 434), DFF, comprising a primary latch (236, 336), a secondary latch (238, 338), and a clock buffer (246, 346); the primary latch (236, 336) comprising a first sleepy inverter (250, 350) and a first non-sleepy inverter (248, 348), NS inverter; the secondary latch (238, 338) comprising a second sleepy inverter (250, 350) and a second NS inverter (248, 348) includes; and the clock buffer (246, 346) includes the third and fourth NS inverters (248, 348); a first group of some, but not all, of the transistor elements has elements configured with a standard threshold voltage, these being referred to as Vt_std elements;a second group of some, but not all, of the transistor elements that have a low threshold voltage configured lower than the standard threshold voltage, these being referred to as Vt_low elements; and those of the transistors that comprise the third NS inverter (248, 348) and / or the fourth NS inverter (248, 348) are Vt_low elements of the second group, wherein: a third group of some, but not all, of the transistor elements that have a high threshold voltage configured higher than the standard threshold voltage, these being referred to as Vt_high elements; and those of the transistors that comprise the first sleepy inverter (250, 350) of the primary latch (236, 336) and the second sleepy inverter (250, 350) of the secondary latch (238, 338) are Vt_high elements of the third group.

Description

BACKGROUND

[0001] The integrated circuit (IC) industry produces a wide variety of analog and digital semiconductor devices to solve problems in various fields. Developments in semiconductor process technology nodes have led to ever smaller component sizes and tighter pitches, resulting in ever higher transistor densities. ICs are becoming ever smaller.

[0002] Flip-flops (latches) are used as data storage elements. In some cases, a flip-flop stores a single bit of data (binary digit). In some cases, a flip-flop (latch) is used to store a state and represents a basic storage element of sequential logic in electronics, such as shift registers.

[0003] One type of flip-flop is a delay (D) flip-flop (FF). A D FF is a digital electronic circuit that delays the change in state of its output signal (Q) until the next rising or falling edge of a clock input signal. The D FF is a modified set-reset flip-flop with an additional inverter to prevent the S and R inputs from having the same logic level.

[0004] One type of DFF is a scan-insertion DFF (SDFQ), used, for example, to implement design for testing (DFT). An SDFQ is a D flip-flop that includes a multiplexer to controllably select between a D input during normal operation and a scan input in scan / test mode. Scan flip-flops, such as SDFQs, are used for device testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The figures of the accompanying drawings illustrate one or more embodiments by way of example and not by way of limitation. Elements with the same reference numbers represent like elements throughout. The drawings are not to scale unless otherwise indicated. Fig. 1A-1B are block diagrams of semiconductor devices according to some embodiments. Fig. 2A-2B are schematic diagrams of a semiconductor device according to some embodiments. Fig. 2C is an installation plan according to some embodiments. Fig. 2D-2E are cross sections according to some embodiments. Fig. 2F is a table according to some embodiments. Fig. 3A(1), Fig. 3B(1), Fig. 3D(1), Fig. 3E(1), Fig. 3F(1), Fig. 3G, Fig. 3H(1), Fig. 3I(1), Fig. 3 years, Fig.3K and Fig. 3L(1) are block diagrams according to some embodiments. Fig. 3A(2), Fig. 3B(2), Fig. 3D(2), Fig. 3E(2), Fig. 3F(2), Fig. 3H(2), Fig. 31(2) and Fig. 3L(2) are installation plans according to some embodiments. Fig. 4A, Fig. 4C, Fig. 4D(1) and Fig. 4E-4F are block diagrams according to some embodiments. Fig. 4B is a table according to some embodiments. Fig. 4D(2) is a schematic diagram according to some embodiments. Fig. 4D(3) is an installation plan according to some embodiments. Fig. 6A is a flowchart of a method of manufacturing a semiconductor device according to some embodiments. Fig. 6B is a method of manufacturing a semiconductor device according to some embodiments. Fig. 7 is a block diagram of an electronic design automation (EDA) system according to some embodiments. Fig. 8 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith, in accordance with some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure discloses many different embodiments or examples of implementing different features of the described subject matter. Examples of components, materials, values, steps, acts, arrangements, or the like are described to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, acts, materials, arrangements, or the like are also contemplated. The formation of a first feature over or on top of a second feature in the following description includes, for example, embodiments in which the first and second features are formed in direct contact, and also includes embodiments in which additional features are formed between the first and second features such that the first and second features are in indirect contact.Furthermore, the present disclosure repeats reference numbers and / or letters throughout the various examples. This repetition is for the purpose of simplicity and clarity and does not, in and of itself, dictate a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "beneath," "under," "deeper," "above," "upper," and the like are used herein for ease of description to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. It is intended that the spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device is also oriented differently (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein are to be interpreted accordingly. In some embodiments, the term standard cell structure refers to a standardized building block included in a library of various standard cell structures.In some embodiments, various standard cell structures are selected from a library and used as components in an installation plan representing a circuit.

[0008] In some embodiments, a semiconductor device comprises a cell region including active regions extending in a first direction and having transistor components formed therein. The transistors of the cell region are arranged to act as a D-type flip-flop comprising a primary latch, a secondary latch, and a clock buffer. The primary and secondary latches each include two types of inverters: a sleepy inverter and a non-sleepy (NS) inverter. The terms "sleepy" and "non-sleepy" are explained below. The primary latch includes a first sleepy inverter and a first non-sleepy (NS) inverter. The secondary latch includes a second sleepy inverter and a second NS inverter. The clock buffer includes third and fourth NS inverters.A first group of some, but not all, transistors has elements configured with a standard threshold voltage (Vt_std elements with threshold voltage Vt_std). A second group of some, but not all, transistors has elements configured with a low threshold voltage lower than the standard threshold voltage (Vt_low elements with threshold voltage Vt_low). Those of the transistors comprising the first LV inverter and / or the second LV inverter are Vt_low elements of the second group. In some embodiments, the transistors of the cell region are further arranged to function as a scan-insertion D flip-flop (SDFQ) comprising the D flip-flop itself and a multiplexer; and those of the transistors comprising the multiplexer are Vt_low elements of the second group.

[0009] A counterpart to the SDFQ according to another approach uses only transistors that have a substantially equal threshold voltage, i.e., Vt_std. To avoid hold slack violations, the other approach either (1) adds additional transistors, which adversely increases the area requirement of the SDFQ according to the other approach, or (2) eliminates the counterpart to a fourth NS inverter of the clock buffer, which adversely contributes to data racing issues. In contrast, to avoid hold slack violations, SDQF embodiments of the present disclosure do not add additional transistors, as is the case with the SDFQ according to the other approach, but are instead configured with transistors with a mix of threshold voltages.In some SDFQ embodiments, some, but not all, of the transistors are configured with Vt_low and some, but not all, of the transistors are configured with Vt_std, which helps avoid adversely increasing the area requirements of the SDFQ embodiments. Also in contrast, to avoid hold slack violations, SDFQ embodiments of the present disclosure do not eliminate the fourth NS inverter of the clock buffer, as is done with the SDFQ according to the other approach. Instead, SDFQ embodiments of the present disclosure retain the fourth NS inverter of the clock buffer and configure some, but not all, of the transistors with Vt_low and some, but not all, of the transistors with Vt_std, which helps the SDFQ embodiments avoid adversely favoring data racing issues.

[0010] Relevant terminology includes the following: When data input to a sequential logic circuit, such as an SDFQ, changes state, propagation delay refers to a finite amount of time required by the logic gates to perform operations on the changed input data. One condition for a valid operation is that the interval between clock pulses is long enough so that all logic gates have time to respond to the changes in the input data, and their corresponding outputs adjust to stable logic values ​​before the next clock pulse occurs. Generally, if this condition is met, the circuit is stable and reliable.

[0011] The setup time is the minimum time a signal must be stable before the rising clock edge. If the setup time is too short, there is a risk that a logical state of the signal will be misinterpreted. In particular, if the setup time is too short, there is a risk that the signal will not settle into a first range of voltages that clearly represents a logical zero or a third range of voltages that clearly represents a logical one, but instead will remain in a second intermediate range of voltages that clearly represents neither a logical zero nor a logical one. This results in the possibility of misinterpretation of the logical state of the signal that is input to a register, i.e., latched. Setup slack is the time difference between the time the signal becomes valid and the setup time.In other words, if the setup slack is positive, then the signal becomes valid sooner than required by the setup time. A setup slack violation is a type of violation in which the setup slack is negative, so the signal becomes valid after the time required by the setup time. In general, although a large positive setup slack prevents misinterpretation of the signal state, it is nevertheless undesirable because a significant portion of the large positive setup slack represents a delay that could be avoided. Accordingly, the target for the setup slack is generally a positive number close to zero.

[0012] Hold time is the shortest time a signal must remain stable after the rising clock edge. If the hold time is not met, there is a risk that a misinterpretation of the signal's logic state will be entered into a register, i.e., latched. Hold slack is the time difference between the moment the signal becomes valid and the hold time. In other words, if the hold slack is positive, then the signal remains valid longer than required by the hold time. A hold slack violation is a type of slack violation where the hold slack is negative, so the signal remains valid for too short a time, i.e., the signal remains valid for a shorter time than required by the hold time. In general, although a large positive hold slack prevents misinterpretation, it is nevertheless undesirable because a significant portion of the large positive hold slack represents delay that could be avoided.Accordingly, the target for the hold slack is generally a positive number close to zero.

[0013] Fig. 1A-1B are block diagrams of respective semiconductor devices 100A-100B according to some embodiments.

[0014] Semiconductor device 100A includes a cell region 102A. Cell region 102A includes a region 104 and a region 106, each containing transistors. The transistors in region 104 have substantially the same first threshold voltage. The transistors in region 106 have substantially the same second threshold voltage, which is greater than the first threshold voltage. Since the first threshold voltage is less than the second threshold voltage, the transistors in region 104 are described as having a low threshold voltage (Vt_low), while the transistors in region 106 are described as having a standard threshold voltage (Vt_std). Example semiconductor process techniques for fabricating transistors with different threshold voltages are explained below. In general, the values ​​for Vt_low and Vt_std are determined by the design rules and scaling of the corresponding semiconductor process technology node.

[0015] Semiconductor device 100B is similar to semiconductor device 100A except that cell region 102B of semiconductor device 100B additionally includes a region 108 compared to cell region 102A of semiconductor device 102A. The transistors in region 108 have substantially the same third threshold voltage, which is greater than the second threshold voltage of region 106. Since the second threshold voltage is less than the third threshold voltage, the transistors in region 108 are described as having a high threshold voltage (Vt_high). Example semiconductor process techniques for fabricating transistors with different threshold voltages are explained below. In general, the values ​​for Vt_low, Vt_std, and Vt_high are determined by the design rules and scaling of the corresponding semiconductor process technology node.

[0016] Fig.2A is a schematic diagram according to some embodiments.

[0017] In particular, Fig. 2A is a schematic diagram of a scan insertion D FF (SDFQ) 230. Among the transistors of the SDFQ 230, there is a mix of threshold voltages, i.e., a majority of the transistors in the SDFQ 230 have a standard threshold voltage (see below), although a minority of the transistors have a low threshold voltage (see below). The mix of transistors with different threshold voltages in the SDFQ 230 has advantages, e.g., with respect to avoiding a hold slack violation (see below). SDFQ 230 is an example of a cell area 102A in Fig. 1A. Before discussing the mix of different threshold voltages, the schematic arrangement of the transistors is explained.

[0018] The SDFQ 230 is a transmission gate-based design (see below). The SDFQ 230 is an edge-triggered device that is triggered by a rising edge (positive edge) of a clock signal. Variations of the SDFQ 230 are triggered by a falling edge (negative edge) of the clock signal. Other variations of the SDFQ 230 are dual-edge triggered, meaning they are triggered by both the rising edge (positive edge) and the falling edge (negative edge) of the clock signal.

[0019] SDFQ 230 includes a multiplexer 232, a D-type flip-flop 234, a sample buffer 244, and a clock buffer 246. SDFQ 230 includes field-effect transistors (FETs), and specifically, positive-channel metal-oxide-semiconductor (PMOS) FETs (PFETs) and negative-channel metal-oxide-semiconductor (NMOS) FETs (NFETs). Some of the FETs of SDFQ 230 are arranged to operate together as sleepy inverters (see below). Some of the FETs of SDFQ 230 are arranged to operate together as non-sleepy inverters (NS inverters) (see below).

[0020] In Fig.2A, scan buffer 244 receives a scan / test enable (SE) signal that selects between normal, i.e., non-scan / test, operation relative to the data signal D or scan / test operation relative to a scan input (SI) signal. Scan buffer 244 includes a non-sleepy (NS) inverter 248(4), comprising PFET P41 and NFET N41 connected in series. An NS inverter, e.g., 248(4), is a counterpart to a sleepy inverter, e.g., 250(1) (see below). Hereinafter, an FET whose reference numeral is alphanumerically preceded by the capital letter P, e.g., P41, is a PFET, and an FET whose reference numeral is alphanumerically preceded by the capital letter N, e.g., N41, is an NFET.

[0021] In the low-voltage inverter 248(4), transistor P41 is connected between a node with a first reference voltage, e.g., VDD, and a node nd41. Transistor N41 is connected between node nd41 and a node with a second reference voltage, e.g., VSS. The gate terminals of the two transistors P41 and N41 are connected together and configured to receive signal SE. Node nd41 has a signal seb, which is the inversion of signal SE.

[0022] In Fig.2A, clock buffer 246 includes a pair of low-voltage inverters 248(5) and 248(6). Low-voltage inverter 248(5) includes series-connected transistors P31 and N31. Transistor P31 is connected between a node with a voltage VDD and a node nd31. Transistor N31 is connected between node nd31 and a node with a voltage VSS. The gate terminals of the two transistors P31 and N31 are connected together and configured to receive a clock signal CP. Node nd31 represents an output node of low-voltage inverter 248(5) and has a clock signal clkb, which represents the inversion of the clock signal CP.

[0023] In clock buffer 246, low-voltage inverter 248(6) includes series-connected transistors P32 and N32. Transistor P32 is connected between a node with a voltage VDD and a node nd32. Transistor N32 is connected between node nd32 and a node with a voltage VSS. The gate terminals of the two transistors P32 and N32 are connected to each other and to node nd31 and are thus configured to receive clock signal clkb. Node nd32 represents an output node of low-voltage inverter 248(6) and has a clock signal clkbb, which represents the inversion of clock signal clkb.

[0024] In Fig.2A comprises 232 multiplexers comprising transistors P11-P15 and N11-N15. Transistor P11 is connected between a node with voltage VDD and a node nd11. The gate of transistor P11 receives signal SI. Transistor P12 is connected between node nd11 and a node nd13. The gate of transistor P12 receives signal seb. Transistor P13 is connected between a node with voltage VDD and a node nd12. The gate of transistor P13 receives input signal D. Transistor P14 is connected between node nd12 and node nd13. The gate of transistor P14 receives signal SE. Transistor P15 is connected between node nd13 and a node nd14, the latter having a signal ml_ax. The gate of transistor P15 receives signal clkbb. Transistor N11 is connected between node nd14 and node nd15. The gate terminal of transistor N11 receives signal clkb.Transistor N12 is connected between node nd15 and node nd16. The gate of transistor N12 receives signal SE. Transistor N13 is connected between node nd16 and a node with voltage VSS. The gate of transistor N13 receives signal SI. Transistor N14 is connected between node nd15 and node nd17. The gate of transistor N14 receives signal SEB. Transistor N15 is connected between node nd17 and a node with voltage VSS. The gate of transistor N15 receives input signal D.

[0025] In multiplexer 232, transistors P13, P14, N14, and N15 define a group of data transistors GRPDAT (data group GRPDAT) of multiplexer 232. Data group GRPDAT is used to select the data input signal D. Transistors P11, P12, N12, and N13 define a group of sampling transistors GRPSC (sampling group GRPSC) of multiplexer 232. Sampling group GRPSC is used to select the sampling input signal SI. Transistors P15 and N11 define a group of delay transistors GRPDEL (delay group GRPDEL) of multiplexer 232. Delay group GRPDEL is used to delay the propagation of the selected input, either SI or D, through multiplexer 232.

[0026] In Fig. 2A, a D flip-flop 234 includes a primary latch 236, an internal buffer 241, a secondary latch 238, and an output buffer 242.

[0027] The primary latch 236 includes an LV inverter 248(1) and a sleepy inverter 250(1). LV inverter 248(1) includes transistors P21 and N21. Transistor P21 is connected between a node with a voltage VDD and a node nd21. Transistor N21 is located between node nd21 and a node with a voltage VSS. The gate terminals of transistors P21 and N21 are connected to each other and to node nd14 and are thus configured to receive signal ml_ax. Thus, signal ml_ax represents the input signal of D-flip-flop 234. Node nd21 represents an output node of the LV inverter 248(1) and has a signal ml_b that represents the inversion of signal ml_ax.

[0028] In primary latch 236, sleepy inverter 250(1) includes transistors P22-P23 and N22-N23. Transistor P22 is connected between a node with a voltage VDD and a node nd22. Transistor P23 is connected between node nd22 and node nd14. The gate of transistor P23 receives signal clkb. Transistor N22 is connected between node nd14 and a node nd23. The gate of transistor N22 receives signal clkbb. In some embodiments, the gate of transistor N22 receives signal CP instead of signal clkbb. Transistor N23 is connected between node nd23 and a node with voltage VSS. Sleepy inverter 250(1) can be placed into a sleep mode due to transistors P23 and N22. In contrast, the LV inverter 248(1) lacks transistors corresponding to transistors P23 and N22, so that inverter 248(1) of the primary latch 236 has no sleep mode.Accordingly, LV inverter 248(1) is described as a non-sleepy inverter (LV inverter). The gate terminals of transistors P22 and N23 are connected to each other and to node nd21. Accordingly, sleepy inverter 250(1) feeds an inverted version of the ml_b signal (from node nd21) back to node nd14.

[0029] In Fig. 2A, the internal buffer 241 includes a transmission gate 240, the latter comprising transistors P24 and N24. The description of SDFQ 230 as a transmission-gate-based design is justified by the inclusion of transmission gate 240 in SDFQ 230. Transistors P24 and N24 are connected in parallel between node nd21 and a node nd24. The gate terminal of transistor P24 receives signal clkb. The gate terminal of transistor N24 receives signal clkbb. Nodes nd21 and nd24 represent input and output nodes of transmission gate 240, respectively. Node nd24 has a signal sl_a.

[0030] In D-type flip-flop 234, secondary latch 238 includes an LV inverter 248(2) and a sleepy inverter 250(2). LV inverter 248(2) includes transistors P25 and N25. Transistor P25 is connected between a node with a voltage VDD and a node nd25. Transistor N25 is connected between node nd25 and a node with a voltage VSS. The gate terminals of transistors P25 and N25 are connected to each other and to node nd24 and are thus configured to receive signal sl_a. Node nd25 represents an output node of LV inverter 248(2) and has a signal sl_bx, which represents the inversion of signal sl_a.

[0031] In secondary latch 238, sleepy inverter 250(2) includes transistors P26-P27 and N26-N27. Transistor P26 is connected between a node with voltage VDD and node nd26. Transistor P27 is connected between node nd26 and node nd24. The gate of transistor P27 receives signal clkbb. Transistor N26 is connected between node nd24 and node nd27. Transistor N27 is connected between node nd27 and a node with voltage VSS. The gate of transistor N26 receives signal clkb. Sleepy inverter 250(2) can be put into sleep mode due to transistors P27 and N26. The gates of transistors P26 and N27 are connected to each other and to node nd25. Accordingly, sleepy inverter 250(2) returns an inverted version of the signal sl_bx (from node nd25) to node nd24.

[0032] In D-flip-flop 234, output buffer 242 includes an LV inverter 248(3), the latter comprising transistors P28 and N28. Transistor P28 is connected between a node with a voltage VDD and a node nd28. Transistor N28 is connected between node nd28 and a node with a voltage VSS. The gate terminals of transistors P28 and N28 are connected to each other and to node nd25 and are thus configured to receive signal sl_bx. Node nd28 represents an output node of the LV inverter 248(3) and thus of the D-flip-flop 234. In addition, node nd28 also represents the output node of SDFQ 230. Node nd28 has a signal Q, which represents the inversion of signal bl_bx.

[0033] Fig.2A assumes that SDFQ 230 is triggered on the rising edge (positive edge) of the clock signal CP. Variations that cause SDFQ 230 to trigger on the falling edge (negative edge) of a clock signal include, for example, the following. Instead of receiving the clock signal CP, the gate terminals of both transistors P31 and N31 are configured to receive a clock signal CPN, where CPN is an inverted version of the clock signal CP. Instead of receiving the signal clkbb, the gate terminal of transistor P15 receives signal clkb. Instead of receiving the signal clkb, the gate terminal of transistor N11 receives signal clkbb. Instead of receiving the signal clkb, the gate terminal of transistor P23 receives signal clkbb. In some embodiments, the gate terminal of transistor P23 receives signal CPN instead of signal clkbb. Instead of receiving the signal clkbb, the gate terminal of transistor N22 receives signal clkb.Instead of receiving the clkb signal, the gate terminal of transistor P24 receives the clkbb signal. Instead of receiving the clkbb signal, the gate terminal of transistor N24 receives the clkb signal. Instead of receiving the clkbb signal, the gate terminal of transistor P27 receives the clkb signal. Instead of receiving the clkb signal, the gate terminal of transistor N26 receives the clkbb signal.

[0034] In Fig. 2A, D flip-flop 234 is a transmission-gate-based design because its internal buffer 241 includes transmission gate 240. In some embodiments, D flip-flop 234 is a stack-gate-based design (not shown). In particular, a stack-gate-based version of D flip-flop 234, while the internal buffer 241 in Fig.2A includes a transmission gate 240, a version of an internal buffer 241 that is stack-gate based. In some embodiments, the stack-gate based version of the internal buffer 241 includes a sleepy inverter (not shown) instead of the transmission gate 240, where a sleepy inverter is an example of a stack-gate based device. Like transmission gate 240, the output of the alternative sleepy inverter is connected to node nd24. Unlike transmission gate 240, the input of the alternative sleepy inverter in the stack-gate based device is not connected to node nd21, but instead is connected to node nd14.

[0035] In Fig. 2A, the FETs of clock buffer 246 have Vt_low. The FETs of sample buffer 244, multiplexer 232, and D-flip-flop 234 have Vt_std. In relation to the total number of transistors in Fig.2A, 12.50% of the transistors have Vt_low and 87.5% of the transistors have Vt_std. To illustrate which transistors have Vt_low and which transistors have Vt_std, use Fig. 2 and similarly each of the Fig. 3A(1), Fig. 3B(1), Fig. 3C, Fig. 3D(1), Fig. 3E(1), Fig. 3F(1), Fig. 3G, Fig. 3H(1), Fig. 3I(1), Fig. 3 years, Fig. 3K, Fig. 3L(1), Fig. 4C, Fig. 4D(1), Fig. 4E, Fig. 4F, Fig. 5A(1), Fig. 5B(1), Fig. 5C(1), Fig. 5D(1) and Fig. 5E-5F different mold filling processes.

[0036] A counterpart to the SDFQ 230 according to another approach uses only transistors that have a substantially equal threshold voltage, i.e., Vt_std. To avoid hold slack violations, the other approach (1) adds additional transistors, which adversely increases the area requirement of the SDFQ according to the other approach, or (2) eliminates the counterpart to the LV inverter 248(3), which adversely promotes data racing problems. In contrast, SDQF embodiments of the present disclosure, such as SDFQ 230, to avoid hold slack violations, do not add additional transistors as does the SDFQ according to the other approach, but are instead configured with transistors with a mix of threshold voltages.In some SDFQ embodiments, for example, SDFQ 230, some, but not all, of the transistors are configured with Vt_low and some, but not all, of the transistors are configured with Vt_std, which helps avoid adversely increasing the area requirements of the SDFQ embodiments. Also in contrast, to avoid hold slack violations, SDFQ embodiments of the present disclosure, for example, SDFQ 230, do not eliminate NS inverters 248(3), as does the SDFQ according to the other approach. Instead, SDFQ embodiments retain NS inverters 248(3) and configure some, for example, a minority, of the transistors with Vt_low and some, for example, a majority, of the transistors with Vt_std, which helps the SDFQ embodiments avoid adversely favoring data racing issues.

[0037] Regarding the threshold voltages of the transistors, different processes are used during the fabrication of a semiconductor device to produce regions whose transistors have different threshold voltages. In some embodiments, during the fabrication of such a semiconductor device, a first doping process is performed in a first region of a substrate in which components of transistors with a low threshold voltage (Vt_low) are formed. The first doping process results in the first region having a first dopant concentration. Then, a second doping process is performed on a second region of the substrate in which components of transistors with a standard threshold voltage (Vt_std) are formed. The second doping process results in the second region having a second dopant concentration that differs from the first dopant concentration.In some embodiments, the second dopant concentration is greater than the first dopant concentration. In some embodiments, the second doping process is performed before the first doping process. The first and second dopant concentrations result in the transistors of the first and second regions having different threshold voltages, ie, they each have a low threshold voltage and a standard threshold voltage. Value ranges for the dopant concentrations are determined by the design rules and scaling of the corresponding semiconductor process technology node.

[0038] In some embodiments, a third doping process is performed on a third region of the substrate in which components of transistors with a high threshold voltage (Vt_high) are formed. The third doping process results in the third region having a third dopant concentration that is different from the first and second dopant concentrations. In some embodiments, the third dopant concentration is greater than the second dopant concentration. In some embodiments, the first, second, and third doping processes are performed in a different order than the first before the second and the second before the third. The first, second, and third dopant concentrations result in the transistors of the first, second, and third regions having different threshold voltages, i.e., they have a low threshold voltage, a standard threshold voltage, and a high threshold voltage, respectively.

[0039] In some embodiments, during the fabrication of a semiconductor device having transistors with different threshold voltages, a first type of gate is deposited over channel regions in a first region of a substrate in which Vt_low transistors are formed. Then, a second type of gate is deposited over channel regions in a second region of the substrate in which Vt_std transistors are formed. In some embodiments, the second type of gate is deposited before the first type of gate. The first and second types of gates accordingly have different first and second working functions due to different materials and / or different thicknesses and / or a different number of layers or the like, for example.Due to the different first and second work functions corresponding to the first and second gate types, the transistors in the first and second regions have different threshold voltages, i.e., they have a low threshold voltage and a standard threshold voltage, respectively. Value ranges for the work function parameters of the different gate types are determined by the design rules and scaling of the corresponding semiconductor process technology node.

[0040] In some embodiments, a third type of gate is deposited over channel region transistors in a third region of the substrate in which Vt_high transistors are formed. Compared to the work functions of the first and second types of gates, the third type of gate has a different work function due to, for example, different materials and / or different thicknesses and / or a different number of layers and the like. Due to the different first, second, and third work functions corresponding to the first, second, and third types of gates, the transistors in the first, second, and third regions have correspondingly different threshold voltages, i.e., they have a low threshold voltage, a standard threshold voltage, and a high threshold voltage, respectively.In some embodiments, the first, second, and third types of gates are deposited in a different order than first before second and second before third.

[0041] Regarding the distribution of transistors with different threshold voltages, in some embodiments with first and second regions, the first region comprises multiple regions in which the second region is interspersed as a whole. In some embodiments, the second region comprises multiple regions in which the first region is interspersed as a whole. In some embodiments, the first and second regions each have corresponding multiple regions, and the multiple regions of the first region are interspersed among the multiple regions of the second region. In some embodiments with a third region in addition to the first and second regions, the third region comprises multiple regions in which: the first region as a whole or one or more regions thereof is / are interspersed; and / or the second region as a whole or one or more regions thereof is / are interspersed.

[0042] Fig.2B is a schematic diagram according to some embodiments.

[0043] Fig. 2B is a simplified version of Fig. 2A. Fig. 2B provides a key for the interpretation of the installation plans in Fig. 3A(2), Fig. 3B(2), Fig. 3D(2), Fig. 3E(2), Fig. 3F(2), Fig. 3H(2), Fig. 31(2) and Fig. 3 years, Fig. 3K, Fig. 3L(2), which are explained below.

[0044] In Fig. 2B, the transistors SDFQ 230 are enclosed by fields A, B, C, D & E, F1, F2, G, H, I and J, respectively. To show their positions in an installation plan, fields A, B, C, D & E, F1, F2, G, H, I and J are shown in each of the Fig. 3A(2) are arranged one above the other accordingly.

[0045] In Fig. 2B, fields A, B, C, D & E, F1, F2, G, H, I and J correspond to the components of SDFQ 230 in Fig. 2A, as shown in Table 1. Table 1 Components in Fig. 2A fields LV inverter 248(5) of clock buffer 246 A LV inverter 248(6) of clock buffer 246 B LV inverter 248(4) of the sampling buffer 244 C Transistors P11-P14 and N12-N15 of the sampling group GRPSC and data group GRPDAT of the multiplexer 232 D & E Transistors of the delay group GRPDEL of the multiplexer 232 F1 Sleepy inverter 250(1) of primary latch 236 F2 LV inverter 248(1) of primary latch 236 G Transfer gate 240 of the internal buffer 241 and sleepy inverter 250(2) of the secondary latch 238 HA LV inverter 248(2) of the secondary latch 238 I LV inverter 248(3) of output buffer 242 J

[0046] Fig. 2C is an installation plan of the output buffer 242 of SDFQ 230 in Fig. 2A according to some embodiments.

[0047] The installation plan in Fig. 2C is part of a larger installation plan, as indicated by the break line 278. Examples of the larger diagrams include the installation plans in Fig. 3A(2), Fig. 3B(2), Fig. 3D(2), Fig. 3E(2), Fig. 3F(2), Fig. 3H(2), Fig. 31(2) and Fig. 3 years, Fig. 3K, Fig. 3L(2), which are explained below, or the like.

[0048] In general, an installation plan represents a semiconductor device. The shapes in the installation plan represent corresponding components in the semiconductor device. The installation plan itself is a top view. The shapes in the installation plan are two-dimensional, for example, relative to the X-axis and the Y-axis, while the semiconductor device is represented three-dimensionally. Typically, the semiconductor device is organized with respect to the Z-axis as a layer stack in which corresponding structures are located, i.e., to which corresponding structures belong. Accordingly, each shape in the installation plan represents, in particular, a component in a corresponding layer of the corresponding semiconductor device. Typically, the installation plan represents the relative depth, i.e.,Positions along the Z-axis of shapes, and thus layers, are created by superimposing a second shape on a first shape such that the second shape at least partially overlaps the first shape. For some similarly sized contact structures stacked along the Z-axis in an installation plan, for example, VD and VIA_1st contact structures (see below), the stacking order along the Z-axis is relative to the stacking order in . Fig. 2C compared to corresponding contact structures in a corresponding semiconductor device ( Fig. 2D-2E) in reverse. This was done in the installation plan, for example Fig. 2C, to simplify the illustration. To simplify the discussion, ie as a discussion aid, some elements in the installation plan (e.g. Fig.2C and the other installation plans disclosed herein) are referred to as if they were counterpart structures in a corresponding semiconductor device rather than structures / shapes as such.

[0049] Installation plans vary in the extent of the details depicted. In some cases, selected layers of an installation plan are combined / abstracted into a single layer, e.g., for simplicity. Alternatively and / or additionally, in some cases, not all layers of the corresponding semiconductor device are depicted, e.g., for simplicity of illustration, selected layers of the installation plan are omitted. Fig. 2C and the other installation plans disclosed herein are examples of installation plans where selected layers have been omitted, for example, interconnect and metallization layers have been omitted over the M_2nd layer in Fig.2B omitted.

[0050] The positions of transistors P28 and N28 of the output buffer 242 are shown in Fig. 2C. Output buffer 242 includes an active area (AR) 256P configured using PMOS technology and an AR 256N configured using NMOS technology. The AR 256P and AR 256N each have a long axis extending in a first direction, such as the X-axis direction. The AR 256P and AR 256N each have a short axis extending in a second direction perpendicular to the first axis, such as the Y-axis direction. The AR 256P and AR 256N include doped first regions that represent source / drain (S / D) regions 224 of the ARs. S / D regions 224 represent first transistor components. Second regions of ARs 256P and 256N, which lie between corresponding S / D regions 224, are channel regions 226, which represent second transistor components.

[0051] In Fig. 2C and in other installation plans disclosed herein, a distance or size relative to the Y-axis is alternatively referred to as a height. The AR 256P and AR 256N each have a height. Relative to the Y-axis, the AR 256P and AR 256N are separated by a gap. The height and gap sizes are determined by the corresponding design rules of the corresponding semiconductor process technology node.

[0052] In some embodiments, transistors P28 and N28, corresponding to AR256P and AR256N, are fin-type FETs (fin-FETs). In some embodiments, transistors P28 and N28 are gate-all-around FETs (GAAFETs), using, for example, nanowires, nanosheets, or the like. In some embodiments, transistors P28 and N28 are complementary FETs (CFETs). In some embodiments, transistors P28 and N28 represent a transistor architecture other than fin-FET, GAAFET, or CFET.

[0053] Selected ones of the gate lines 262(1)-262(3) included in corresponding transistors represent third transistor components. Long axes of the gate lines 262(1)-262(3) extend parallel to the Y-axis. Of the gate lines 262(1), 262(2), and 262(3), the gate line 260(2) overlies a corresponding one of the channel regions 226. Metal-to-S / D (MD) contact structures 264 overlies a corresponding one of the S / D regions 224. MD contact structures 264 represent a first type of fourth transistor components. In some embodiments, MG contact structures 226 represent a second type of fourth transistor components. Metal-to-gate (MG) contact structures 262 overlies a corresponding one of the gate lines 260.In some embodiments, a given S / D region is formed by doping a portion of an AR that lies between corresponding instances of gate lines or that extends to a corresponding instance of an IDG (not shown; see below) with an appropriate conductive type dopant.

[0054] Via-to-MD contact structures (VD contact structures) 268 represent connections between corresponding MD contact structures 264 and conductive segments on a first metallization level (M_1st conductive segments) 272. Via-to-gate contact structures (VG contact structures) 270 represent connections between gate lines 262(1)-262(2) and M_1st conductive segments 272, and more particularly between MG contact structures 266 and M_1st conductive segment 272. M_1st conductive segments 272 are disposed over corresponding gate lines 262(1)-262(3) and MD contact structures 264. A first one of the M_1st conductive segments 272 is dedicated to VDD and thus represents a VDD power rail. A second one of the M_1st conductive segments 272 is intended for VSS and thus represents a VSS power rail.Via structures in a first layer interconnects (VIA_1st structures) 274 represent connections between corresponding M_1st conductive segments 272 and conductive segments on a second metallization level (M_2nd conductive segments) 276. M_2nd conductive segments 276 overlie corresponding M_1st conductive segments 272.

[0055] In some embodiments, depending on the numbering convention of the corresponding process node through which such a semiconductor device is fabricated, the first (1st) metallization layer M_1st is either metallization layer zero, Mo, or metallization layer one, M1, and accordingly, the first layer of interconnect V_1st is either VIA0 or VIA1. In some embodiments, M0 is the first metallization layer above a transistor layer. In some embodiments, the transistor layer comprises transistor components, e.g., ARs with S / D regions and channel regions therein, MD contact structures, VD contact structures, via-to-gate (VG contact structures), gate structures, MG contact structures, or the like. In some embodiments, AR 256P is doped with a first conductive-type dopant and AR 230N is doped with a second conductive-type dopant.In some embodiments configured according to complementary metal oxide semiconductor (CMOS) technology, AR 256P is doped with a first conductive-type dopant, such as a P-type dopant, such that the transistors corresponding to AR 256P are PFETs; AR 256N is doped with a second conductive-type dopant, such as an N-type dopant, such that the transistors corresponding to AR 256N are NFETs; and AR 256P is formed in a corresponding N-well 255 (. Fig. 2D-2E).

[0056] In some embodiments, an instance of gate line 340 has been replaced with an insulating dummy gate (IDG) (not shown). An insulating dummy gate, such as that created from an insulating dummy gate structure (not shown), is a dielectric structure comprising one or more dielectric materials and functioning as an electrical insulating structure. Accordingly, an insulating dummy gate is not a structure that is electrically conductive and thus does not function, for example, as a gate electrode of an active transistor. In some embodiments, an insulating dummy gate is referred to as a dielectric gate structure. In some embodiments, an insulating dummy gate is an example of a structure included in a CPODE layout scheme. In some embodiments, CPODE is an acronym for Continuous Poly on Diffusion Edge.In some embodiments, CPODE is an acronym for "Continuous Poly on Oxide Definition Edge." In some embodiments, an isolation dummy gate is based on a gate structure as a precursor. In some embodiments, an isolation dummy gate is formed by first forming a gate structure, e.g., a dummy gate structure, sacrificing / removing (e.g., etching) the gate structure to form a trench, (optionally) removing a portion of a substrate that was previously located beneath the gate structure to deepen the trench, and then filling the trench with one or more dielectric materials such that the physical dimensions of the resulting electrical isolation structure, i.e., the isolation dummy gate, correspond to the dimensions of the precursor that was sacrificed, namely, the gate structure or the combination of the gate structure and the portion of the substrate.

[0057] Fig.2D-2E are respective cross-sectional views of a cell region included in a semiconductor device, according to some embodiments.

[0058] Fig. 2D-2E are particularly cross-sectional views of a cell region 202 of a semiconductor device, which may be based on cell region 102A or 102B of the corresponding Fig. 2A-2B. Fig. 2D-2E are based on the context of complementary metal oxide semiconductor (CMOS) technology, where cell region 202 contains N-well 255. Fig. 2D-2E correspond to section lines 2D-2D' and 2E-2E' in Fig. 2C. To simplify the display, go Fig.2D-2E further assume a fin-FET architecture where each AR is represented by two fins, i.e., AR 256P is represented by X instances of P-type fins 257P and AR 256N is represented by X instances of N-type fins 257N, where X=2. In other embodiments, X is a positive integer other than 3. In some embodiments, AR 256P has a different number of fins 257P compared to the number of fins 257N of AR 256N.

[0059] Each of the Fig. 2D-2E includes: a P-type substrate 254; an N-well 255 in substrate 254; P-type fins 257P partially within N-well 255 with respect to the Z-axis; N-type fins 257P partially within substrate 254 with respect to the Z-axis; a first gate insulator 258 against fins 257P in N-well 255; and a second gate insulator 260 at fins 257P and 257N, first gate insulator 258, N-well 255, and P-substrate 254.

[0060] In Fig.2D, a cell region 202 further comprises: MD contact structures 265 on the second gate insulator 260; VD contact structures 269 in a VD / VG interlayer and on corresponding MD contact structures 265; M_1st conductive segments 273 in the M_1st layer and above the VD / VG interlayer, the VDD power rail instance of the M_1st conductive segment 273 and the VSS power rail instance of the M_1st conductive segment above corresponding instances of the VD contact structure 269; VIA_1st structures 275 in a first interlayer and above the VDD power rail instance of the M_1st conductive segment 273 and the VSS power rail instance of the M_1st conductive segment 273, respectively; and M_2nd conductive segments above VIA_1st structures 275, respectively.

[0061] In Fig.2E, cell region 202 further includes: gate line 263(2) to second gate insulator 260; MG contact structure 266 to gate line to gate line 263(2); VG contact structure 271 in the VD / VG interconnect layer and to MG contact structure 266; M_1st conductive segments 273 in the M_1st layer and above the VD / VG interconnect layer, a central (with respect to the Y-axis) instance of M_1st conductive segment 273 above VG contact structure 271.

[0062] In some embodiments, the P-type substrate comprises silicon, silicon germanium (SiGe), gallium arsenic, or other suitable semiconductor materials. The fins are formed in or over the P-type substrate using one or more masks corresponding to one or more active areas in the installation plans described herein. The second gate insulating layer is deposited over the P-type substrate, among others. Example materials that the second gate insulating layer includes, but are not limited to, a high-k dielectric layer, an interface layer, and / or combinations thereof. In some embodiments, the second gate dielectric material is deposited over the P-type substrate by atomic layer deposition (ALD) or other suitable techniques. Example materials that include the gate lines include, among others,, but not limited to polysilicon, metal, Al, AlTi, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN and / or other suitable conductive materials.

[0063] Fig. 2F is a Table 2 according to some embodiments.

[0064] In Fig. 2F Table 2 summarizes the mix of threshold voltage transistors in SDFQ 230 in Fig. 2A and in the SDFQs in Fig. 3A(1), Fig. 3B(1), Fig. 3C, Fig. 3D(1), Fig. 3E(1), Fig. 3F(1), Fig. 3G, Fig. 3H(1), Fig. 3I(1), Fig. 3 years, Fig. 3K, Fig. 3L(1), Fig. 4C, Fig. 4D(1), Fig. 4E and Fig. 4F (see below) together.

[0065] For example, row 1 in Table 2 summarizes the mix of different threshold voltage transistors in SDFQ 230 from Fig.2A together. In the SDFQ 230, the FETs of the LV inverters 248(5) and 248(6) of the clock buffer 246 have Vt_low. The FETs of the sample buffer 244, multiplexer 232, the LV inverter 248(1) and the sleepy inverter 250(1) of the primary latch 236, the internal buffer 241, the LV inverter 248(2) and the sleepy inverter 250(2) of the secondary latch 238, and the output buffer 242 have Vt_std. In contrast, a minority of the FETs have the low threshold voltage (Vt_low), i.e.

[0066] Fig. 3A(1) is a block diagram of an SDFQ 330A(1) according to some embodiments.

[0067] SDFQ 330A(1) is also a block diagram that corresponds to the schematic diagram in Fig. 2A. That is, SDFQ 330A(1) in Fig. 3A(1) is the block diagram equivalent of the SDFQ 230 in Fig. 2A. SDFQ 330A(1) is an example of a cell range 102A in Fig. 1A. Thus, row 1 in Table 2 summarizes the mix of different threshold voltage transistors in SDFQ 330A(1) of Fig.3A(1) and in SDFQ 230 in Fig. 2A together. The counterpart to SDFQ 230 in Fig. 2A of the other approach is also a counterpart to SDFQ 330A(1) in Fig. 3A(1). Accordingly, SDFQ 330A(1) is an improvement over the counterpart of the other approach at least for the reasons that SDFQ 230A is an improvement over the counterpart of the other approach. Relative to the total number of transistors in Fig. 2A 12.50% of the FETs have Vt_low and 87.50% of the FETs have Vt_std.

[0068] Fig. 3A(2) is an installation plan 330A(2) according to some embodiments.

[0069] Installation plan 330A(2) is in particular a representation of the block diagram SDFQ 330A(1) in Fig. 3A(1).

[0070] In the installation plan 330A(2), fields A, B, C, D & E, F1, F2, G, H, I and J correspond to the components of SDFQ 330A(1) in Fig. 3A(1), as shown in the mapping of Table 3 below. Table 3 Components in Fig. 3A(1) box LV inverter 348(5) of clock buffer 346 A LV inverter 348(6) of clock buffer 346 B LV inverter 348(4) of the sampling buffer 344 C Transistors P11-P14 and N12-N15 of the sampling group GRPSC and data group GRPDAT of the multiplexer 332 D & E Transistors of the delay group GRPDEL of the multiplexer 332 F1 Sleepy inverter 350(1) of primary latch 336 F2 LV inverter 348(1) of primary latch 336 G Transfer gate 340 of the internal buffer 341 and sleepy inverter 350(2) of the secondary latch 338 HA LV inverter 348(2) of the secondary latch 338 I LV inverter 348(3) of the output buffer 342 J

[0071] It should be noted that the assignment in Table 3 is not only valid for the installation plan in Fig. 3A(2), but also to the installation plans of 3B(2), 3D(2), 3E(2), 3F(2), 3H(2), 3I(2) and 3L(2).

[0072] In Fig. In 3A(2), the transistors in arrays B and A have Vt_low. The transistors in arrays C, D & E, J, F1, F2, G, H, and I have Vt_std.

[0073] Fig. 3B(1) is a block diagram of an SDFQ 330B(1) according to some embodiments.

[0074] SDFQ 330B(1) is SDFQ 330A(1) in Fig. 3A(1) except that the mix of different threshold transistors in SDFQ 330B(1) is different than in SDFQ 330(1).

[0075] Fig. 3B(1) is also a block diagram corresponding to the schematic diagram in Fig. 2A, except that Fig.3B(1) has a different distribution of threshold voltage transistors than Fig. 2A. SDFQ 330B(1) is an example of a cell range 102A in Fig. 1A.

[0076] In SDFQ 330B(1) in Fig. 3B(1) has a minority of the FETs, i.e., the FETs of the LV inverters 348(5) and 348(6) of the clock buffer 346 and the FETs of the multiplexer 332, Vt_low. In contrast, a majority of the FETs, i.e., the FETs of the sample buffer 344, LV inverter 348(1) and sleepy inverter 350(1) of the primary latch 336, internal buffer 341, LV inverter 348(2) and sleepy inverter 350(2) of the secondary latch 338 and output buffer 342, Vt_std. In relation to the total number of transistors in Fig. 3B(1) 43.75% of the FETs have Vt_low and 56.25% of the FETs have Vt_std. Row 2 in Table 2 summarizes the mix of the different threshold voltage transistors in SDFQ 330B(1) of Fig. 3B(1) together.

[0077] The counterpart to SDFQ 330A(1) in Fig.3A is also a counterpart to SDFQ 330B(1) in Fig. 3B(1). Accordingly, SDFQ 330B(1) is an improvement over the counterpart of the other approach at least for the reasons that SDFQ 330A(1) is an improvement over the counterpart of the other approach.

[0078] Fig. 3B(2) is an installation plan 330B(2) according to some embodiments.

[0079] Installation plan 330B(2) is in particular a representation of the block diagram SDFQ 330B(1) in Fig. 3B(1).

[0080] In Fig. 3B(2), the transistors in fields B, D & E, A, F1 and F2 have Vt_low. The transistors in fields G, H, I, J and C have Vt_std. Again, in the above figure of Table 3, correspondences between fields A, B, C, D & E, F1, F2, G, H, I and J in the installation plan in Fig. 3B(2) and the components of SDFQ 330B(1) in Fig. 3B(1) shown.

[0081] Fig.3C is a block diagram of an SDFQ 330C according to some embodiments.

[0082] SDFQ 330C is SDFQ 330A(1) in Fig. 3A(1), except that the mix of different threshold voltage transistors in SDFQ 330C is different than in SDFQ 330A(1).

[0083] Fig. 3C is also a block diagram corresponding to the schematic diagram in Fig. 2A, except that Fig. 3C has a different distribution of threshold voltage transistors than Fig. 2A.

[0084] In SDFQ 330C in Fig. 3C, in addition to some, but not all, of the FETs being configured with Vt_low and some, but not all, of the FETs being configured with Vt_std, some, but not all, of the FETs being configured with Vt_high. SDFQ 330C is an example of a cell range 102B in Fig.1B. Specifically, the FETs of low-voltage inverters 348(5) and 348(6) of clock buffer 346 have Vt_low. The FETs of sample buffer 344, multiplexer 332, low-voltage inverter 348(1) of primary latch 336, internal buffer 341, low-voltage inverter 348(2) of secondary latch 338, and output buffer 342 have Vt_std. The FETs of sleepy inverter 350(1) of primary latch 336 and sleepy inverter 350(2) of secondary latch 338 have Vt_high.

[0085] Regarding the proportions relative to the total number of transistors, 12.50% of the FETs have Vt_low, 62.50% of the FETs have Vt_std, and 25.00% of the FETs have Vt_high. Row 3 in Table 2 summarizes the mix of the different threshold voltage transistors in the SDFQ 330C of Fig. 3C together.

[0086] The counterpart to SDFQ 330A(1) of the other approach in Fig. 3A is also a counterpart to SDFQ 330C in Fig.3C. Accordingly, SDFQ 330C is an improvement over the counterpart of the other approach at least to the extent that SDFQ 330A(1) is an improvement over the counterpart of the other approach.

[0087] Fig. 3D(1) is a block diagram of an SDFQ 330D(1) according to some embodiments.

[0088] SDFQ 330D(1) is SDFQ 330A(1) in Fig. 3A(1), except that the mix of different threshold voltage transistors in SDFQ 330D(1) is different than in SDFQ 330A(1). Fig. 3D(1) is also a block diagram corresponding to the schematic diagram in Fig. 2A, except that Fig. 3D(1) has a different distribution of threshold voltage transistors than Fig. 2A.

[0089] In SDFQ 330D(1) in Fig.3D(1), in addition to some, but not all, of the FETs being configured with Vt_low and some, but not all, of the FETs being configured with Vt_std, some, but not all, of the FETs being configured with Vt_high. SDFQ 330D(1) is an example of a cell range 102B in Fig. 1B. Specifically, the FETs of low-voltage inverters 348(5) and 348(6) of clock buffer 346 and the FETs of multiplexer 332 have Vt_low. The FETs of sample buffer 332, low-voltage inverter 348(1) of primary latch 336, internal buffer 341, low-voltage inverter 348(2) of secondary latch 338, and output buffer 342 have Vt_std. The FETs of sleepy inverter 350(1) of primary latch 336 and sleepy inverter 350(2) of secondary latch 338 have Vt_high. Regarding the proportions relative to the total number of transistors, 43.75% of the FETs have Vt_low, 31.25% of the FETs have Vt_std, and 25.00% have Vt_high. Row 4 in Table 2 summarizes the mix of threshold voltage transistors in SDFQ 330D(1) of Fig. 3D(1) together.

[0090] The counterpart to SDFQ 330A(1) of the other approach in Fig. 3A is also a counterpart to SDFQ 330D(1) in Fig. 3D(1). Accordingly, SDFQ 330D(1) is an improvement over the counterpart of the other approach at least to the extent that SDFQ 330A(1) is an improvement over the counterpart of the other approach.

[0091] Fig. 3D(2) is an installation plan 330D(2) according to some embodiments.

[0092] Installation plan 330D(2) is in particular a representation of the block diagram SDFQ 330D(1) in Fig. 3D(1).

[0093] In Fig. 3D(2) the transistors in fields B, D & E, A and F1 have Vt_low. The transistors in fields I, J and C have Vt_std. The transistors in fields F2, H and G have Vt_high. Again, in the above figure of Table 3, correspondences between fields A, B, C, D & E, F1, F2, G, H, I and J in the installation plan in Fig.3D(2) and the components of SDFQ 330D(1) in Fig. 3D(1) shown.

[0094] Fig. 3E(1) is a block diagram of an SDFQ 330E(1) according to some embodiments.

[0095] SDFQ 330E(1) is SDFQ 330A(1) in Fig. 3A(1), except that the mix of different threshold voltage transistors in SDFQ 330E(1) is different than in SDFQ 330A(1). Fig. 3E(1) is also a block diagram corresponding to the schematic diagram in Fig. 2A, except that Fig. 3E(i) has a different distribution of threshold voltage transistors than Fig. 2A. SDFQ 330E(1) is an example of a cell range 102A in Fig. 1A.

[0096] In SDFQ 330E(1) in Fig.3E(1), the FETs of low-voltage inverter 348(5) of clock buffer 346 and the FETs of output buffer 342 have Vt_low. The FETs of sample buffer 344, low-voltage inverter 348(6) of clock buffer 346, multiplexer 332, low-voltage inverter 348(1) and sleepy inverter 350(1) of primary latch 336, internal buffer 341, and low-voltage inverter 348(2) and sleepy inverter 350(2) of secondary latch 338 have Vt_std. As a percentage of the total number of transistors, 12.50% of the FETs have Vt_low and 87.5% of the FETs have Vt_std. Row 5 in Table 2 summarizes the mix of different threshold voltage transistors in SDFQ 330E(i) of Fig. 3E(1) together.

[0097] The counterpart to SDFQ 330A(1) of the other approach in Fig. 3A is also a counterpart to SDFQ 330E(1) in Fig. 3E(1). Accordingly, SDFQ 330E(1) is an improvement over the counterpart of the other approach at least to the extent that SDFQ 330A(1) is an improvement over the counterpart of the other approach.

[0098] Fig. 3E(2) is an installation plan 330E(2) according to some embodiments.

[0099] Installation plan 330E(2) is in particular a representation of the block diagram SDFQ 330E(1) in Fig. 3E(1).

[0100] In Fig. 3E(2) the transistors in fields J and A have Vt_low. The transistors in fields C, D & E, A, F1, F2, H, and I have Vt_std. Again, in the above figure of Table 3, correspondences between fields A, B, C, D & E, F1, F2, G, H, I and J in the installation plan in Fig. 3E(2) and the components of SDFQ 330E(1) in Fig. 3E(1) shown.

[0101] Fig. 3F(1) is a block diagram of an SDFQ 330F(1) according to some embodiments.

[0102] SDFQ 330F(1) is SDFQ 330A(1) in Fig. 3A(1), except that the mix of different threshold voltage transistors in SDFQ 330F(1) is different than in SDFQ 330A(1). Fig. 3F(1) is also a block diagram corresponding to the schematic diagram in Fig. 2A, except that Fig. 3F(1) has a different distribution of threshold voltage transistors than Fig. 2A. SDFQ 330F(1) is an example of a cell range 102A in Fig. 1A.

[0103] In SDFQ 330F(1) in Fig. 3F(1), the FETs of low-voltage inverter 348(5) of clock buffer 346, and the FETs of multiplexer 332 and output buffer 342 have Vt_low. The FETs of sample buffer 344, low-voltage inverter 348(6) of clock buffer 332, low-voltage inverter 348(1) and sleepy inverter 350(1) of primary latch 336, internal buffer 341, and low-voltage inverter 348(2) and sleepy inverter 350(2) of secondary latch 338 have Vt_std. As a percentage of the total number of transistors, 43.75% of the FETs have Vt_low and 56.25% of the FETs have Vt_std. Row 6 in Table 2 summarizes the mix of different threshold voltage transistors in SDFQ 330F(1) of Fig. 3F(1) together.

[0104] The counterpart to SDFQ 330A(1) of the other approach in Fig. 3A is also a counterpart to SDFQ 330F(1) in Fig. 3F(1). Accordingly, SDFQ 330F(1) is an improvement over the counterpart of the other approach at least to the extent that SDFQ 330A(1) is an improvement over the counterpart of the other approach.

[0105] Fig. 3F(2) is an installation plan 330F(2) according to some embodiments.

[0106] Installation plan 330F(2) is in particular a representation of the block diagram SDFQ 330F(1) in Fig. 3F(1).

[0107] In Fig. 3F(2) the transistors in A, D & E, J and F1 have Vt_low. The transistors in F2, H, G, I, C and B have Vt_std. Again, in the above figure of Table 3, correspondences between fields A, B, C, D & E, F1, F2, G, H, I and J in the installation plan in Fig. 3F(2) and the components of SDFQ 330F(1) in Fig. 3F(1) shown.

[0108] Fig. 3G is a block diagram of an SDFQ 330G according to some embodiments.

[0109] SDFQ 330G is SDFQ 330A(1) in Fig. 3A(1), except that the mix of different threshold voltage transistors in SDFQ 330G is different than in SDFQ 330A(1).

[0110] Fig. 3G is also a block diagram that corresponds to the schematic diagram in Fig. 2A, except that Fig. 3G has a different distribution of threshold voltage transistors than Fig. 2A.

[0111] In SDFQ 330G in Fig. 3G, in addition to some, but not all, of the FETs being configured with Vt_low and some, but not all, of the FETs being configured with Vt_std, some, but not all, of the FETs being configured with Vt_high. SDFQ 330G is an example of a cell range 102B in Fig. 1B. Specifically, the FETs of LV inverter 348(5) of clock buffer 346 and the FETs of output buffer 342 have Vt_low. The FETs of sample buffer 344, LV inverter 348(6) of clock buffer 346, multiplexer 332, LV inverter of primary latch 336, internal buffer 341, and LV inverter of secondary latch 338 have Vt_std. The FETs of sleepy inverter 350(1) of primary latch 336 and sleepy inverter 350(2) of secondary latch 338 have Vt_high. Regarding the proportions relative to the total number of transistors, 12.50% of the FETs have Vt_low, 62.5% of the FETs have Vt_std, and 25.00% have Vt_high. Row 7 in Table 2 summarizes the mix of the different threshold voltage transistors in SDFQ 330G of Fig. 3G together.

[0112] The counterpart to SDFQ 330A(1) of the other approach in Fig. 3A is also a counterpart to SDFQ 330G in Fig. 3G. Accordingly, SDFQ 330G is an improvement over the counterpart of the other approach at least to the extent that SDFQ 330A(1) is an improvement over the counterpart of the other approach.

[0113] Fig. 3H(1) is a block diagram of an SDFQ 330H(1) according to some embodiments.

[0114] SDFQ 330H(1) is SDFQ 330A(1) in Fig. 3A(1), except that the mix of different threshold voltage transistors in SDFQ 330H(1) is different than in SDFQ 330A(1). Fig. 3H(1) is also a block diagram corresponding to the schematic diagram in Fig. 2A, except that Fig. 3H(1) has a different distribution of threshold voltage transistors than Fig. 2A.

[0115] In SDFQ 330H(1) in Fig. 3H(1) are, in addition to some, but not all, of the FETs being configured with Vt_low and some, but not all, of the FETs being configured with Vt_std, some, but not all, of the FETs being configured with Vt_high. SDFQ 330H(1) is an example of a cell range 102B in Fig. 1B. Specifically, the FETs of LV inverter 348(5) of clock buffer 346 and the FETs of multiplexer 332 and output buffer 342 have Vt_low. The FETs of sample buffer 344, LV inverter 348(6) of clock buffer 346, LV inverter 348(1) of primary latch 336, internal buffer 341, and LV inverter 348(2) of secondary latch 338 have Vt_std. The FETs of sleepy inverter 350(1) of primary latch 336 and sleepy inverter 350(2) of secondary latch 338 have Vt_high. Regarding the proportions relative to the total number of transistors, 43.75% of the FETs have Vt_low, 31.25% of the FETs have Vt_std, and 25.00% have Vt_high. Row 8 in Table 2 summarizes the mix of the different threshold voltage transistors in SDFQ 330H(1) of Fig. 3H(1) together.

[0116] The counterpart to SDFQ 330A(1) of the other approach in Fig. 3A is also a counterpart to SDFQ 330H(1) in Fig. 3H(1). Accordingly, SDFQ 330H(1) is an improvement over the counterpart of the other approach at least to the extent that SDFQ 330A(1) is an improvement over the counterpart of the other approach.

[0117] Fig. 3H(2) is an installation plan 330H(2) according to some embodiments.

[0118] Installation plan 330H(2) is in particular a representation of the block diagram SDFQ 330H(1) in Fig. 3H(1).

[0119] In Fig. 3H(2), the transistors in A, D & E, J and F1 have Vt_low. The transistors in fields G, I, C and B have Vt_std. The transistors in fields F2 and H have Vt_high. Again, in the above figure of Table 3, correspondences between fields A, B, C, D & E, F1, F2, H(1), H, I and J in the installation plan in Fig. 3H(2) and the components of SDFQ 330H(1) in Fig. 3H(1) shown.

[0120] Fig. 3I(1) is a block diagram of an SDFQ 330I(1) according to some embodiments.

[0121] SDFQ 330I(1) is SDFQ 330A(1) in Fig. 3A(1), except that the mix of different threshold voltage transistors in SDFQ 33I(1) is different than in SDFQ 330A(1).

[0122] Fig. 3I(1) is also a block diagram corresponding to the schematic diagram in Fig. 2A, except that Fig. 3I(1) has a different distribution of threshold voltage transistors than Fig. 2A. SDFQ 330I(1) is an example of a cell range 102A in Fig. 1A.

[0123] In SDFQ 330I(1) in Fig. In 3I(1), the FETs of low-voltage inverter 348(6) of clock buffer 346 and the FETs of output buffer 342 have Vt_low. The FETs of sample buffer 344, low-voltage inverter 348(5) of clock buffer 346, multiplexer 332, low-voltage inverter 348(1) and sleepy inverter 350(1) of primary latch 336, internal buffer 341, and low-voltage inverter 348(2) and sleepy inverter 350(2) of secondary latch 338 have Vt_std. As a percentage of the total number of transistors, 12.5% ​​of the FETs have Vt_low and 87.5% of the FETs have Vt_std. Line 9 in Table 2 summarizes the mix of different threshold voltage transistors in SDFQ 330I(1) of Fig. 3I(1) together.

[0124] The counterpart to SDFQ 330A(1) of the other approach in Fig. 3A is also a counterpart to SDFQ 330I(1) in Fig. 3I(1). Accordingly, SDFQ 330I(1) is an improvement over the counterpart of the other approach at least to the extent that SDFQ 330A(1) is an improvement over the counterpart of the other approach.

[0125] Fig. 3I(2) is an installation plan 330I(2) according to some embodiments.

[0126] Installation plan 330I(2) is in particular a representation of the block diagram SDFQ 330I(1) in Fig. 3I(1).

[0127] In Fig. 3I(2) the transistors in fields J and B have Vt_low. The transistors in fields C, D & E, A, F1, F2, G, H and I have Vt_std. Again, in the above figure of Table 3, correspondences between fields A, B, C, D & E, F1, F2, G, H, I and J in the installation plan in Fig. 3I(2) and the components of SDFQ 330I(1) in Fig. 3I(1) shown.

[0128] Fig. 3J is a block diagram of an SDFQ 330J according to some embodiments.

[0129] SDFQ 330J is SDFQ 330A(1) in Fig. 3A(1), except that the mix of different threshold voltage transistors in SDFQ 33J is different than in SDFQ 330A(1). Fig. 3J is also a block diagram corresponding to the schematic diagram in Fig. 2A, except that Fig. 3J has a different distribution of threshold voltage transistors than Fig. 2A. SDFQ 330J is an example of a cell range 102A in Fig. 1A.

[0130] In SDFQ 330J in Fig. 3J, the FETs of low-voltage inverter 348(6) of clock buffer 346 and the FETs of multiplexer 332 and output buffer 342 have Vt_low. The FETs of sample buffer 344, low-voltage inverter 348(5) of clock buffer 332, low-voltage inverter 348(1) and sleepy inverter 350(1) of primary latch 336, internal buffer 341, and low-voltage inverter 348(2) and sleepy inverter 350(2) of secondary latch 338 have Vt_std. As a percentage of the total number of transistors, 43.75% of the FETs have Vt_low and 56.25% of the FETs have Vt_std. Row 10 in Table 2 summarizes the mix of different threshold voltage transistors in SDFQ 330J of Fig. 3 years together.

[0131] The counterpart to SDFQ 330A(1) of the other approach in Fig. 3A is also a counterpart to SDFQ 330J in Fig. 3J. Accordingly, SDFQ 330J is an improvement over the counterpart of the other approach at least to the extent that SDFQ 330A(1) is an improvement over the counterpart of the other approach.

[0132] Fig. 3K is a block diagram of an SDFQ 330K according to some embodiments.

[0133] SDFQ 330K is SDFQ 330A(1) in Fig. 3A(1), except that the mix of different threshold voltage transistors in SDFQ 330K is different than in SDFQ 330A(1). Fig. 3K is also a block diagram similar to the schematic diagram in Fig. 2A, except that Fig. 3K has a different distribution of threshold voltage transistors than Fig. 2A.

[0134] In SDFQ 330K in Fig. 3K are, in addition to some, but not all, of the FETs being configured with Vt_low and some, but not all, of the FETs being configured with Vt_std, some, but not all, of the FETs being configured with Vt_high. SDFQ 330K is an example of a cell range 102B in Fig. 1B. Specifically, the FETs of LV inverter 348(6) of clock buffer 346 and the FETs of output buffer 342 have Vt_low. The FETs of sample buffer 344, multiplexer 332, LV inverter 348(6) of clock buffer 346, LV inverter 348(1) of primary latch 336, internal buffer 341, and LV inverter 348(2) of secondary latch 338 have Vt_std. The FETs of sleepy inverter 350(1) of primary latch 336 and sleepy inverter 350(2) of secondary latch 338 have Vt_high. Regarding the proportions relative to the total number of transistors, 12.50% of the FETs have Vt_low, 62.5% of the FETs have Vt_std, and 25.00% have Vt_high. Row 11 in Table 2 summarizes the mix of the different threshold voltage transistors in the SDFQ 330K of Fig. 3K together.

[0135] The counterpart to SDFQ 330A(1) of the other approach in Fig. 3A is also a counterpart to SDFQ 330K in Fig. 3K. Accordingly, SDFQ 330K is an improvement over the counterpart of the other approach at least to the extent that SDFQ 330A(1) is an improvement over the counterpart of the other approach.

[0136] Fig. 3L(1) is a block diagram of an SDFQ 330L(1) according to some embodiments.

[0137] SDFQ 330L(1) is SDFQ 330A(1) in Fig. 3A(1), except that the mix of different threshold voltage transistors in SDFQ 330L(1) is different than in SDFQ 330A(1). Fig. 3L(1) is also a block diagram corresponding to the schematic diagram in Fig. 2A, except that Fig. 3L(1) has a different distribution of threshold voltage transistors than Fig. 2A.

[0138] In SDFQ 330L(1) in Fig. 3L(1) are, in addition to some, but not all, of the FETs being configured with Vt_low and some, but not all, of the FETs being configured with Vt_std, some, but not all, of the FETs being configured with Vt_high. SDFQ 330L(1) is an example of a cell range 102B in Fig. 1B. Specifically, the FETs of LV inverter 348(6) of clock buffer 346 and the FETs of multiplexer 332 and output buffer 342 have Vt_low. The FETs of sample buffer 344, LV inverter 348(5) of clock buffer 346, LV inverter 348(1) of primary latch 336, internal buffer 341, and LV inverter 348(2) of secondary latch 338 have Vt_std. The FETs of sleepy inverter 350(1) of primary latch 336 and sleepy inverter 350(2) of secondary latch 338 have Vt_high. Regarding the proportions relative to the total number of transistors, 43.75% of the FETs have Vt_low, 31.25% of the FETs have Vt_std, and 25.00% have Vt_high. Row 12 in Table 2 summarizes the mix of the different threshold voltage transistors in SDFQ 330L(1) from Fig. 3L(1) together.

[0139] The counterpart to SDFQ 330A(1) of the other approach in Fig. 3A is also a counterpart to SDFQ 330L(1) in Fig. 3L(1). Accordingly, SDFQ 330L(1) is an improvement over the counterpart of the other approach at least to the extent that SDFQ 330A(1) is an improvement over the counterpart of the other approach.

[0140] Fig. 3L(2) is an installation plan 330L(2) according to some embodiments.

[0141] Installation plan 330L(2) is in particular a representation of the block diagram SDFQ 330L(1) in Fig. 3L(1).

[0142] In Fig. 3L(2), the transistors in B, D & E, J and F1 have Vt_low. The transistors in fields G, I, C and A have Vt_std. The transistors in fields F2 and H have Vt_high. Again, in the above figure of Table 3, correspondences between fields A, B, C, D & E, F1, F2, L(1), H, I and J in the installation plan in Fig. 3L(2) and the components of SDFQ 330L(1) in Fig. 3L(1) shown.

[0143] In general, each of the SDFQs in Fig. 2A-2B, Fig. 3A(1)-(2), 3B(1)-(2), 3C, 3D(1)-(2), 3E(1)-(2), 3F(1)-(2), 3G, 3H(1)-(2), 3I(1)-(2), 3J, 3K, and 3L(1)-(2): Transistors with a mix of threshold voltages are used; and a single-bit SDFQ is used. The use of transistors with a mix of threshold voltages also applies to multibit SDFQs ( Fig. 4A-4C, Fig. 4D(1)-4D(3) and Fig. 4E-4F).

[0144] Fig. 4A is a block diagram of a multi-bit flip-flop device 431A according to some embodiments.

[0145] In some embodiments of multi-bit flip-flop devices 431A, for example Fig. 4C, Fig. 4D(1)-4D(3), some, but not all, of the transistors are configured with Vt_low, and some, but not all, of the transistors are configured with Vt_std, as explained below. In such embodiments, a multi-bit flip-flop device 431A is an example of a cell area 102A in Fig. 1A. In some embodiments of multi-bit flip-flop devices 431A, for example Fig. 4E-4F, some, but not all, of the transistors are configured with Vt_low, some, but not all, of the transistors are configured with Vt_std, and some, but not all, of the transistors are configured with Vt_high, as explained below. In such embodiments, a multi-bit flip-flop device 431A is an example of a cell area 102B in Fig. 1B.

[0146] In Fig. 4A, the semiconductor device 400 includes a flip-flop FF1 and a flip-flop FF2. Each of the flip-flops FF1 and FF2 is an SDFQ. Each of the flip-flops FF1 and FF2 is an example of SDFQs 230 in Fig. 2A and 330A(1) in Fig. 3A, with two exceptions. The first exception is that flip-flops FF1 and FF2 share sample buffer 444 and clock buffer 446, rather than flip-flops FF1 and FF2 having their own instance of sample buffer 44 and their own instance of clock buffer 446. The second exception is that the mix of different threshold transistors in each of flip-flops FF1 and FF2 is different than the mix of different threshold transistors in SDFQs 230 in Fig. 2A and 330A(1) in Fig. 3A.

[0147] Each of the flip-flops FF1 and FF2 includes a data terminal DT and a scan input terminal SIT. Data input signals D1 and D2 are received by flip-flops FF1 and FF2, respectively, at the data terminal DT. A scan input signal SI is received by flip-flop FF1 at the scan input terminal SIT. Flip-flops FF1 and FF2 are connected in series. The output bit value Q1 of flip-flop FF1 is received by FF2 at the scan input terminal SIT. Each of the flip-flops FF1 and FF2 also includes terminals for receiving scan enable signals SE and seb and terminals for receiving clock signals clkb and clkbb.

[0148] The operation of flip-flops FF1 and FF2 is coordinated by the clock signal CP. In normal operation, i.e., non-scan / test operation, the scan enable signal SE is in a deactivated state, so that signals at scan input terminals SIT are not selected, but rather data signals D1 and D2 are selected by flip-flops FF1 and FF2, respectively. During one oscillation of the clock signal CP (assuming proper operation of flip-flops FF1 and FF2): the bit value of the data input signal D1 at the data terminal DT of flip-flop FF1 is transferred from the data terminal DT of flip-flop FF1 to the output terminal Q of flip-flop FF1 as output bit value Q1; and the bit value of the data input signal D2 at the data terminal DT of flip-flop FF2 is transferred from the data terminal DT of flip-flop FF2 to the output terminal Q of flip-flop FF2 as output bit value Q2.

[0149] During scan / test operation, the scan enable signal SE is in an activated state so that: data signals D1 and D2 are ignored by flip-flops FF1 and FF2, respectively; scan input signal SI is selected by flip-flop FF1; and the output bit value Q1 of flip-flop FF2 is selected. During a first oscillation of the clock signal CP (assuming proper operation of flip-flop FF1), the bit value of the scan input signal SI at the scan input terminal SIT of flip-flop FF1 is transferred from the scan input terminal SIT of flip-flop FF1 to the output terminal Q of flip-flop FF1 as output bit value Q1. During a second oscillation of the clock signal CP (assuming proper operation of flip-flop FF2), the output bit value Q1 of flip-flop FF1 is transferred to the output terminal Q of flip-flop FF2.At the end of the second clock cycle (assuming proper operation of flip-flops FF1 and FF2), the output bit value Q2 of flip-flop FF2 corresponds to the sampling input signal SI.

[0150] Fig. 4B is a Table 4 according to some embodiments.

[0151] In Fig. 4B, Table 4 summarizes the mix of threshold voltage transistors in the multibit SDFQs in Fig. 4C, Fig. 4D(1), Fig. 4E and Fig. 4F together (see below).

[0152] Fig. 4C is a schematic diagram of a multi-bit SDFQ 431c according to some embodiments.

[0153] In Fig. 4C includes multibit SDFQ (MB SDFQ) 431C, sample buffer 444 (which itself includes NS inverter 448(4)), clock buffer 446, and flip-flops FF1 and FF2. FF1 includes multiplexer 432(1) and D-type flip-flop 434(1). FF2 includes multiplexer 432(2) and D-type flip-flop 434(2). Output Q1 of FF1 is connected to the gate terminals of transistors P11 and N12. 13 the scanning group GRPSC of multiplexer 432(2) of FF2. MB SDFQ 431C is an example of a cell area 102A in Fig. 1A. Each of D flip-flops 434(1) and 434(2) includes: primary latch 436, which itself contains LV inverter 448(1) and sleepy inverter 450(1); internal buffer 441, which itself contains transmission gate 440; secondary latch 438, which itself contains LV inverter 448(2) and sleepy inverter 450(2); and output buffer 442, which itself contains LV inverter 450(3).

[0154] In MB SDFQ 431C in Fig. 4C, the FETs of LV inverters 448(5) and 448(6) of the clock buffer 446 and the FETs of the output buffer 442 of the D-flip-flops 434(1)-434(2) have Vt_low. The other FETs in MB SDFQ 431C have Vt_std. In terms of the proportions relative to the total number of transistors, ≈14.29% of the FETs have Vt_low and ≈85.71% of the FETs have Vt_std. Row 1 in Table 4 summarizes the mix of the various threshold voltage transistors in MB SDFQ 431C of Fig. 4C together.

[0155] Fig. 4D(1) is a schematic diagram of an MB SDFQ 431D(1) according to some embodiments.

[0156] MB SDFQ 431D(1) is MB SDFQ 431C in Fig. 4C, except that the mix of different threshold voltage transistors in MB SDFQ 431D(1) is different than in MB SDFQ 431C. MB SDFQ 431D(1) is an example of a cell area 102A in Fig. 1A.

[0157] In MB SDFQ 431D(1) in Fig. 4D(1), the FETs of the LV inverters 448(5) and 448(6) of clock buffer 446, the FETs of the multiplexers 432(1)-432(2), and the FETs of the output buffer 442 of the D-flip-flops 434(1)-434(2) have Vt_low. The other FETs in MB SDFQ 431D(1) have Vt_std. Regarding the proportions relative to the total number of transistors, 50% of the FETs have Vt_low and 50% of the FETs have Vt_std. Row 2 in Table 4 summarizes the mix of the various threshold voltage transistors in MB SDFQ 431D(1) of Fig. 4D(1) together.

[0158] Fig. 4D(2) is a schematic diagram according to some embodiments.

[0159] Fig. 4D(2) a simplified version of Fig. 4D(1). Fig. 4D(2) shows a legend for the interpretation of the installation plans in Fig. 4D(3), which are explained below.

[0160] In Fig. 4D(2), the transistors MB SDFQ 431D(1) are enclosed by fields A, B, C, D & E, F1, F2, G, H, I and J. To show their positions in an installation plan, fields A, B, C, D & E, F1, F2, G, H, I and J are in Fig. 4D(3) superimposed accordingly.

[0161] Fig. 4D(3) is an installation plan 431D(3) according to some embodiments.

[0162] Installation plan 431D(3) is in particular a representation of the schematic diagram of MB SDFQ 431D(1) in Fig. 4D(1).In Fig. In 4D(3), the transistors in arrays D & E, F1, J, A, and B have Vt_low. The transistors in arrays C, F2, I, G, and H have Vt_high.

[0163] Fig. 4E is a schematic diagram of an MB SDFQ 431E according to some embodiments.

[0164] MB SDFQ 431E is MB SDFQ 431C in Fig. 4C, except that the mix of different threshold voltage transistors in MB SDFQ 431E is different than in MB SDFQ 431C. MB SDFQ 431E is an example of a cell area 102B in Fig. 1B.

[0165] In MB SDFQ 431E in Fig. 4E, the FETs of low-voltage inverters 448(5) and 448(6) of clock buffer 446 and the FETs of output buffer 442 of D flip-flops 434(1)-434(2) have Vt_low. The FETs of sleepy inverters 450(1) of primary latches 436 of each D flip-flop 434(1)-434(2) and the FETs of sleepy inverters 450(2) of secondary latches 438 of each D flip-flop 434(1)-434(2) have Vt_high. The other FETs in MB SDFQ 431E have Vt_std. Regarding the proportions relative to the total number of transistors, ≈14.29% of the FETs have Vt_low, ≈57.14% of the FETs have Vt_std, and ≈28.57% of the FETs have Vt_high. Row 3 in Table 4 summarizes the mix of the different threshold voltage transistors in MB SDFQ 431E of Fig. 4E together.

[0166] Fig. 4F is a schematic diagram of an MB SDFQ 431F according to some embodiments.

[0167] MB SDFQ 431F is MB SDFQ 431C in Fig. 4C, except that the mix of different threshold voltage transistors in MB SDFQ 431F is different than in MB SDFQ 431C. MB SDFQ 431F is an example of a cell area 102B in Fig. 1B.

[0168] In MB SDFQ 431F in Fig. 4F, the FETs of the low-voltage inverters 448(5) and 448(6) of clock buffer 446, the FETs of the multiplexers 432(1)-432(2), and the FETs of the output buffer 442 of the D-flip-flops 434(1)-434(2) have Vt_low. The FETs of the sleepy inverters 448(1) of the primary latches 436 of each D-flip-flop 434(1)-434(2) and the FETs of the sleepy inverters 448(2) of the secondary latches 438 of each D-flip-flop 434(1)-434(2) have Vt_high. The other FETs in MB SDFQ 431F have Vt_std. Regarding the proportions relative to the total number of transistors, ≈50.00% of the FETs have Vt_low, ≈21.43% of the FETs have Vt_std, and ≈28.57% of the FETs have Vt_high. Row 4 in Table 4 summarizes the mix of the different threshold voltage transistors in MB SDFQ 431F of Fig. 4F together.

[0169] The use of transistors with a mix of threshold voltages was discussed in the context of flip-flop devices. The use of transistors with a mix of threshold voltages also applies to combinational logic ( Fig. 5A(1)-5A(2), Fig. 5B(1)-5B(2), Fig. 5C(1)-5C(2), Fig. 5D(1)-5D(2) and Fig. 5E-5F.

[0170] Fig. 5A(1) and Fig. 5B(1) are corresponding schematic diagrams of inverters according to some embodiments.

[0171] In Fig. 5A(1) PFET P51 has Vt_low while NFET N52 has Vt_std. In Fig. 5B(1) PFET P51 has Vt_std while NFET N52 has Vt_low.

[0172] Fig. 5A(2) and Fig. 5B(2) are corresponding installation plans according to some embodiments.

[0173] In particular, the installation plan in Fig. 5A(2) is a representation of the inverter in Fig. 5A(1). The installation plan in Fig. 5B(2) is a representation of the inverter in Fig. 5B(1).

[0174] Fig. 5C(1), Fig. 5D(1), Fig. 5E and Fig. 5F are corresponding schematic installation plans of NAND gates according to some embodiments.

[0175] In Fig. 5C(1), PFET P61 and NFET N61 have Vt_low, while PFET P62 and NFET N62 have Vt_std. In Fig. 5D(1) PFET P62 and NFET N62 have Vt_low, while PFET P61 and NFET N61 have Vt_std.

[0176] In Fig. 5E, PFETs P61 and P62 have Vt_low, while NFETs N61 and N62 have Vt_std. In Fig. 5F PFETs P61 and P62 have Vt_std, while NFETs N61 and N62 have Vt_low.

[0177] Fig. 5C(2) and Fig. 5D(2) are corresponding installation plans according to some embodiments.

[0178] In particular, the installation plan in Fig. 5C(2) is a representation of the inverter in Fig. 5C(1). The installation plan in Fig. 5D(2) is a representation of the inverter in Fig. 5D(1).

[0179] Fig. 6A is a flowchart 600A of a method of manufacturing a semiconductor device according to some embodiments.

[0180] The method of flowchart 600A is, for example, implemented using EDA system 700 ( Fig. 7, see below) and an IC manufacturing system 800 ( Fig. 8, see below) according to some embodiments. Examples of a semiconductor device that can be manufactured according to the method of flowchart 600A include the semiconductor devices of Fig. 1A-1B, semiconductor devices implementing the schematic diagrams disclosed herein, semiconductor devices implementing the block diagrams disclosed herein, semiconductor devices based on the installation plans disclosed herein, or the like.

[0181] In Fig. 6A, the method of flowchart 600A includes blocks 602-604. In block 602, an installation plan is generated, including, among other things, one or more of the installation plans disclosed herein or the like. Block 602 is implemented, for example, using EDA system 700 ( Fig. 7, see below) according to some embodiments. From block 602, the flow continues to block 604.

[0182] In block 604, based on the installation plan, (A) one or more photolithographic exposures are made, (B) one or more semiconductor masks are fabricated, and / or (C) one or more components in a layer of a semiconductor device are fabricated. See the following discussion of the IC manufacturing system 800 in Fig. 8 below.

[0183] Fig. 6B is a method 600B of manufacturing a semiconductor device according to some embodiments.

[0184] The method of flowchart 600A is, for example, implemented using IC manufacturing system 800 ( Fig. 8, see below) according to some embodiments. Examples of a semiconductor device that can be manufactured according to the method of flowchart 600B include the semiconductor devices of Fig. 1A or Fig. 1B, semiconductor devices embodying the schematic diagrams disclosed herein, semiconductor devices based on the installation plans disclosed herein, or the like.

[0185] Method 600B includes blocks 610-618. In block 610, a substrate is formed. From block 610, the process proceeds to block 612.

[0186] In block 612, active regions (ARs) are formed in the substrate, including doping corresponding regions of the substrate. Examples of the active regions include ARs 256P and 256N in Fig. 2C or the like. From block 612, flow continues to block 614.

[0187] In block 614, source / drain regions (S / D regions) representing first transistor components (TCs) are formed in the ARs, including doping corresponding first regions of the active regions, wherein second regions of the ARs located between corresponding S / D regions represent channel regions that are second TCs. Examples of S / D regions include S / D regions 224 in Fig. 2C, 225 in Fig. 2D or the like. Examples of channel areas include channel areas 226 in Fig. 2C, 227 in Fig. 2E or the like. From block 614, flow continues to block 616.

[0188] In block 616, gate lines representing third TCs are formed over corresponding ones of the channel regions. Examples of the gate lines include gate line 262(2) in Fig. 2C, 263(2) in Fig. 2E or the like. From block 616, flow continues to block 618.

[0189] In block 618, metal-to-S / D contact structures (MD contact structures) representing third TCs are formed over corresponding S / D regions. Examples of MD contact structures include MD contact structures 264 in Fig. 2C, 265 in Fig. 2D or something like that.

[0190] In relation to Fig. 6B, in some embodiments, forming active regions of block 612, forming the S / D regions and corresponding channel regions of block 614, forming gate lines of block 616, and forming MD contact structures of block 618 results in: a first set of first to fourth transistor components connected as respective transistors defining a primary latch (e.g., 236, 336, or the like); a second set of the first to fourth transistor components connected as respective transistors defining a secondary latch (e.g., 238, 338, or the like); and a third set of the first to fourth transistor components connected as respective transistors defining a clock buffer (e.g., 246, 346, or the like), or the like. In such embodiments: the primary latch, the secondary latch, and the clock buffer comprise a D-type flip-flop (DFF) (e.g.,234, 334 or the like); the primary latch comprises a first sleepy inverter (e.g., 248(1), 348(2) or the like) and a first non-sleepy inverter (NS inverter) (e.g., 250(1), 350(1) or the like); the secondary latch comprises a second sleepy inverter (e.g., 248(2), 348(2) or the like) and a second NS inverter (e.g., 250(2), 350(2) or the like); and the clock buffer comprises first NS (248(5), 348(4) or the like) and second NS inverters (248(6), 348(6) or the like). Also in such embodiments: a first group of some, but not all, of the transistors has elements configured with a standard threshold voltage (Vt_std elements), and a second group of some, but not all, of the transistors has elements configured with a low threshold voltage lower than the standard threshold voltage (Vt_low elements), e.g. . Fig. 2A, Fig. 3A, Fig. 3B(1); Fig. 3C, Fig. 3D(1), Fig. 3E(1), Fig. 3F(1), Fig. 3G, Fig. 3H(1), Fig. 3I(1), Fig. 3 years, Fig. 3K, Fig. 3L(1) or the like; and those of the transistors that form the first LV inverter (e.g. 248(5) or 248(5) in Fig. 3A-3H, Fig. 4B-4E or the like) and / or the second LV inverters (e.g. 249(6) or 348(6) in Fig. 3A-3D, Fig. 3I-3L and Fig. 4B-4E or the like) are elements of the second set.

[0191] In relation to Fig. 6B, the formation of active regions of block 612, the formation of S / D regions and corresponding channel regions of block 614, the formation of gate lines of block 616, and the formation of MD contact structures of block 618 results in some embodiments in that: those of the transistors comprising the first NS inverter (e.g., 248(5), 348(5) or the like) and the second NS inverters (e.g., 248(6), 348(6) or the like) of the clock buffer (e.g., 246, 346 or the like) are Vt_low elements of the second group, e.g., as in Fig. 2A, Fig. 3A(1), Fig. 3B(1), Fig. 3C, Fig. 3D(1) or similar.

[0192] In relation to Fig. 6B, the formation of active regions of block 612, the formation of S / D regions and corresponding channel regions of block 614, the formation of gate lines of block 616, and the formation of MD contact structures of block 618, in some embodiments, results in: a fourth set of the first to fourth transistor components being connected as respective transistors defining an output buffer (e.g., 242, 342, or the like) included in the D-flip-flop (234, 334, or the like). In such embodiments, those of the transistors comprising the output buffer (242, 342, or the like) are Vt_low elements of the second group, such as in Fig. 3E(1), Fig. 3F(1), Fig. 3G, Fig. 3H(2), Fig. 3I(1), Fig. 3 years, Fig. 3K, Fig. 3L(1) or similar.

[0193] In relation to Fig. 6B, forming active regions of block 612, forming S / D regions and corresponding channel regions of block 614, forming gate lines of block 616, and forming MD contact structures of block 618 results in some embodiments in that: a third group of some, but not all, of the transistors having elements configured with a high threshold voltage (Vt_high) that is higher than the standard threshold voltage (Vt_high elements). In such embodiments, those of the transistors comprising the first sleepy inverter (e.g., 248(1), 348(1) or the like) of the primary latch (e.g., 236, 336 or the like) and the second sleepy inverter (248(2), 348(2) or the like) of the secondary latch (238, 338 or the like) are Vt_high elements of the third group, for example, as in Fig. 3C, Fig. 3D(1), Fig. 3G, Fig. 3H(1) or the like.

[0194] In relation to Fig. 6B, the formation of active regions of block 612, the formation of S / D regions and corresponding channel regions of block 614, the formation of gate lines of block 616, and the formation of MD contact structures of block 618, in some embodiments, results in: a fourth set of the first to fourth transistor components being connected as respective transistors defining an output buffer (e.g., 242, 342, or the like) included in the DFF (e.g., 234, 334, or the like). In such embodiments, those of the transistors comprising the output buffer (242, 342, or the like) are Vt_low elements of the second group, such as in Fig. 3E(1), Fig. 3F(1), Fig. 3G, Fig. 3H(1), Fig. 3I(1), Fig. 3 years, Fig. 3K, Fig. 3L(1) or similar.

[0195] In relation to Fig. 6B, the formation of active regions of block 612, the formation of S / D regions and corresponding channel regions of block 614, the formation of gate lines of block 616, and the formation of MD contact structures of block 618, in some embodiments, results in: a fourth set of the first to fourth transistor components being connected as respective transistors defining a multiplexer (232, 332, or the like). In such embodiments, the D-flop (234, 334, or the like) comprises a scan-insertion DFF (SDFQ); and those of the transistors comprising the multiplexer (232, 332, or the like) are Vt_low elements of the second group, such as in Fig. 3B(1), Fig. 3D(1), Fig. 3F(1), Fig. 3H(1), Fig. 3 years, Fig. 3L(1) or similar.

[0196] Fig. 7 is a block diagram of an electronic design automation (EDA) system 700 according to some embodiments.

[0197] In some embodiments, EDA system 700 includes an APR system. In some embodiments, EDA system 700 is a general-purpose computing device including a hardware processor 802 and a non-transitory, computer-readable storage medium 704. Storage medium 704 is, among other things, encoded with, i.e., stores, computer program code 706, i.e., a set of executable instructions. Execution of instructions 706 by hardware processor 702 represents (at least in part) an EDA tool that may perform a portion or all of, for example, the methods in Fig. 6A, Fig. 6B and Fig. 7 according to one or more embodiments (hereinafter referred to as the processes and / or methods). Storage medium 704 stores, among other things, the installation plan of the cell area 202 in Fig. 2B. Installation plans 402B-402F in Fig. 4B-4F, installation plans 502B-502C in Fig. 5A-5B and other such installation plans are within the scope of the present disclosure.

[0198] Processor 702 is electrically coupled to computer-readable storage medium 704 via a bus 708. Processor 702 is further electrically coupled to an I / O interface 710 via bus 708. A network interface 712 is also electrically connected to processor 702 via bus 708. Network interface 712 is connected to a network 714 such that processor 702 and computer-readable medium 704 are capable of connecting to external elements via network 714. Processor 702 is configured to execute computer program code 706 encoded in computer-readable storage medium 704 to cause system 700 to be usable for performing some or all of the recited processes and / or methods.In one or more embodiments, processor 702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or any suitable processing unit.

[0199] In one or more embodiments, computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). Computer-readable storage medium 704 includes, for example, semiconductor or solid-state memory, magnetic tape, a removable computer diskette, random access memory (RAM), read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium 704 includes a compact disk read-only memory (CD-ROM), a compact disk read / write memory (CD-R / W), and / or a digital video disc (DVD).

[0200] In one or more embodiments, storage medium 704 stores computer program code 706 configured to cause system 700 (where such execution represents (at least in part) the EDA tool) to be usable for performing some or all of the recited processes and / or methods. In one or more embodiments, storage medium 704 further stores information enabling some or all of the recited processes and / or methods to be performed. In one or more embodiments, storage medium 704 stores a library 707 of standard cells, including those standard cells disclosed herein or the like, one or more circuit diagrams 709, such as those disclosed herein or the like, and / or one or more installation plans 711, such as those disclosed herein or the like.

[0201] EDA system 700 includes I / O interface 710. I / O interface 710 is coupled to external circuitry. In one or more embodiments, I / O interface 710 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or arrow keys for communicating information and commands to processor 702.

[0202] EDA system 700 further includes network interface 712 coupled to processor 702. Network interface 712 enables system 700 to communicate with network 714 to which one or more other computer systems are connected. Network interface 712 includes wireless network interfaces, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces, such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the aforementioned processes and / or methods are implemented in two or more systems 700.

[0203] System 700 is configured to receive information through I / O interface 710. The information received through I / O interface 710 includes one or more instructions, data, design rules, libraries of standard cells, and / or other parameters for processing by processor 702. The information is transferred to processor 702 via bus 708. EDA system 700 is configured to receive information related to a UI through I / O interface 710. The information is stored in computer-readable medium 704 as user interface (UI) 742.

[0204] In some embodiments, some or all of the recited processes and / or methods are implemented as a stand-alone software application for execution by a processor. In some embodiments, some or all of the recited processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the recited processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of the recited processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the recited processes and / or methods are implemented as a software application used by the EDA system 700.In some embodiments, a design containing standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool.

[0205] In some embodiments, the processes are implemented as functions of a program stored in a non-transitory, computer-readable recording medium. Examples of a non-transitory, computer-readable recording medium include, but are not limited to, external / removable and / or internal / built-in storage devices, for example, one or more of an optical disk such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as ROM, RAM, a memory card, and the like.

[0206] Fig. 8 is a block diagram of an integrated circuit (IC) manufacturing system 800 and an IC manufacturing flow associated therewith, in accordance with some embodiments.

[0207] After Block 602 in Fig. 6A implements IC manufacturing system 800 based on design block 604, wherein (A) one or more semiconductor masks and / or (B) at least one component in a layer of an incomplete semiconductor integrated circuit is manufactured using manufacturing system 800. In some embodiments, blocks 606-614 are implemented by IC manufacturing system 800 to perform block 604.

[0208] In Fig. 8, IC manufacturing system 800 includes entities such as a design house 820, a mask house 830, and an IC fabricator / fabricator ("fab") 840 that interact with each other in the design, development, and manufacturing cycles and / or services related to the fabrication of an IC device 860. The entities in system 800 are connected via a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a plurality of different networks, such as an intranet and the Internet. The communications network includes wired and / or wireless communications channels. Each entity interacts with one or more of the other entities and provides and / or receives services to one or more of the other entities. In some embodiments, two or more of the design house 820, mask house 830, and IC fab 840 are owned by a single, larger company.In some embodiments, two or more of design house 820, mask house 830, and IC fab 840 coexist in a common facility and use common resources.

[0209] Design house (or design team) 820 creates an IC design layout 822. IC design layout 822 contains various geometric patterns designed for an IC device 860. The geometric patterns correspond to patterns of the metal, oxide, or semiconductor layers that form the various components of the IC device 860 to be manufactured. The various layers combine to form various IC features. A portion of the IC design layout 822 includes, for example, various IC features, such as an active area, gate electrode, source and drain, metal lines or vias of an interlayer interconnect, and openings for connection pads to be formed in a semiconductor substrate (such as a silicon wafer), and various material layers disposed on the semiconductor substrate. Design house 820 implements a suitable design method for forming the IC design layout 822.The design process includes one or more logic designs, physical designs, or placement and routing. IC design layout 822 is presented in one or more data files containing geometric pattern information. IC design layout 822 is expressed, for example, in a GDSII file format or DFII file format.

[0210] Mask house 830 includes data preparation 832 and mask fabrication 834. Mask house 830 uses IC design layout 822 to create one or more masks to be used to fabricate the various layers of IC device 860 in accordance with IC design layout 822. Mask house 830 performs mask data preparation 832, translating IC design layout 822 into a representative data file (“RDF”). Mask data preparation 832 provides the RDF to mask fabrication 834. Mask fabrication 834 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The design layout is manipulated by mask data preparation 832 so that it conforms to certain properties of the mask writer and / or requirements of the IC fab 840. In Fig.8, mask data preparation 832, mask fabrication 834, and mask 845 are illustrated as separate elements. In some embodiments, mask data preparation 832 and mask fabrication 834 are collectively referred to as mask data preparation.

[0211] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC), which utilizes lithography enhancement techniques to compensate for image defects, such as those that may result from diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout 822. In some embodiments, mask data preparation 832 further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist functions, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is further utilized, which treats OPC as an inverse imaging problem.

[0212] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that checks the IC design layout that has undergone processes in the OPC against a set of mask generation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 834 that undo some of the modifications performed by the OPC to satisfy mask generation rules.

[0213] In some embodiments, mask data preparation 832 includes lithography process checking (LPC), which simulates processing implemented by IC fab 840 to fabricate IC device 860. LPC simulates this processing based on IC design layout 822 to fabricate a simulated fabricated device, such as IC device 860. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to fabricate the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of field ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and the like, or combinations thereof.In some embodiments, after a simulated fabricated device is fabricated by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and / or MRC are repeated to further refine IC design layout 822.

[0214] The above description of mask data preparation 832 has been simplified for clarity. In some embodiments, data preparation 832 includes additional features, such as a logic operation (LOP) for modifying the IC design layout according to manufacturing rules. Furthermore, the processes applied to IC design layout 822 during data preparation 832 can be performed in a variety of different orders.

[0215] After mask data preparation 832 and during mask fabrication 834, a mask 845 or a group of masks is fabricated based on the modified IC design layout. In some embodiments, an electron beam (e-beam) or a multiple electron beam mechanism is used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout. These masks are formed using various technologies. In some embodiments, the mask is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image-sensitive material layer (e.g., photoresist) deposited on a wafer is blocked by the opaque region and transmitted through the transparent region.In one example, a binary mask of the mask comprises a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) deposited in the opaque areas of the mask. In another example, the mask is formed using a phase-shifting technology. In the phase-shifting mask (PSM), various features in the structure formed on the mask are configured to obtain an appropriate phase difference to improve resolution and image quality. In various examples, the phase-shifting mask is an attenuated PSM or alternating PSM. The mask(s) produced by mask fabrication 834 is / are used in a variety of processes. Such one or more masks is / areare used, for example, in an ion implantation process to form various doped regions in the semiconductor wafer, in an etching process to form various etched regions in the semiconductor wafer and / or in other suitable processes.

[0216] IC fab 840 is an IC manufacturing company that has one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC fab 840 is a semiconductor foundry. For example, there may be one manufacturing facility for the front-end manufacturing of a variety of IC products (front-end-of-line (FEOL) manufacturing), while a second manufacturing facility may provide back-end manufacturing for interconnecting and packaging the IC products (back-end-of-line (BEOL) manufacturing), and a third manufacturing facility may provide other services for the foundry business.

[0217] IC fab 840 uses the mask (or masks) manufactured by mask house 830 to fabricate IC device 860 using fabrication tools 842. Thus, IC fab 840 at least indirectly uses IC design layout 822 to fabricate IC device 860. In some embodiments, semiconductor wafer 853 is fabricated by IC fab 840 using the mask (or masks) to form IC device 860. Semiconductor wafer 853 comprises a silicon substrate or other suitable substrate with material layers formed thereon. The semiconductor wafer further comprises one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed in subsequent fabrication steps).

[0218] In some embodiments, a semiconductor device comprises: a cell region including active regions extending in a first direction and having transistor components formed therein; the transistors of the cell region are arranged to function as a D-type flip-flop (DFF) including a primary latch, a secondary latch, and a clock buffer; the primary latch includes a first sleepy inverter and a first non-sleepy inverter (NS inverter); the secondary latch includes a second sleepy inverter and a second NS inverter; and the clock buffer includes third and fourth NS inverters; a first group of some, but not all, of the transistors have elements configured with a standard threshold voltage (Vt_std elements);a second group of some, but not all, of the transistors has elements configured for a low threshold voltage lower than the standard threshold voltage (Vt_low elements); and those of the transistors comprising the first LV inverter and / or the second LV inverter are Vt_low elements of the second group.;

[0219] In some embodiments, those of the transistors comprising the first LV inverter and the second LV inverter of the clock buffer are Vt_low elements of the second group. In some embodiments, the DFF further comprises an output buffer; and those of the transistors comprising the output buffer are Vt_low elements of the second group.

[0220] In some embodiments, a third group of some, but not all, of the transistors has elements configured with a high threshold voltage higher than the standard threshold voltage (Vt_high elements); and those of the transistors comprising the first sleepy inverter of the primary latch and the second sleepy inverter of the secondary latch are Vt_high elements of the third group. In some embodiments, the DFF further comprises an output buffer; and those of the transistors comprising the output buffer are Vt_low elements of the second group. In some embodiments, those of the transistors comprising the first NS inverter and the second NS inverter of the clock buffer are Vt_low elements of the second group. In some embodiments, the transistors of the cell area are further arranged to function as a scan-insertion type DFF (SDFQ), which includes the DFF itself and a multiplexer.Transistors comprising the multiplexer are Vt_low elements of the second group.

[0221] In some embodiments, the transistors of the cell region are further arranged to function as a scan-insertion-type DFF (SDFQ) comprising the DFF itself and a multiplexer. Transistors comprising the multiplexer are Vt_low elements of the second group. In some embodiments, those of the transistors comprising the first NS inverter of the primary latch and the second NS inverter of the secondary latch are Vt_std elements of the first group. In some embodiments, the transistors of the cell region are further arranged to function as a scan-insertion-type DFF (SDFQ) comprising the DFF, a multiplexer, and a sample buffer. Those transistors comprising the sample buffer are Vt_std elements of the second group.

[0222] In some embodiments, a third group of some, but not all, of the transistors has elements configured with a high threshold voltage higher than the standard threshold voltage (Vt_high elements); the DFF further comprises an output buffer; the transistors of the cell area are further arranged to function as a scan insertion type DFF (SDFQ) including the DFF and a multiplexer; at least one of a configuration (A) or a configuration (B) or a configuration (C) is true; for configuration (A), those of the transistors comprising the output buffer are Vt_low elements of the second group; for configuration (B), those of the transistors comprising the multiplexer are Vt_low elements of the second group;and for configuration (C), those of the transistors comprising the first sleepy inverter of the primary latch and the second sleepy inverter of the secondary latch are Vt_high elements of the third group.;

[0223] In some embodiments, a semiconductor device comprises: a cell region including active regions extending in a first direction and having transistor components formed thereon; the transistors of the cell region are arranged to function as a scan insertion type D flip-flop (SDFQ) comprising a multiplexer and a D flip-flop (DFF), the DFF including a primary latch and a secondary latch; the primary latch includes a first sleepy inverter and a first non-sleepy inverter (NS inverter); the secondary latch includes a second sleepy inverter and a second NS inverter; and a first group of some, but not all, of the transistors has elements configured with a standard threshold voltage (Vt_std elements);a second group of some, but not all, of the transistors with elements configured with a low threshold voltage lower than the standard threshold voltage (Vt_low elements); and those of the transistors comprising the multiplexer are Vt_low elements of the second group.;

[0224] In some embodiments, a third group of some, but not all, of the transistors has elements configured with a high threshold voltage higher than the standard threshold voltage (Vt_high elements); and those of the transistors comprising the first sleepy inverter of the primary latch and the second sleepy inverter of the secondary latch are Vt_high elements of the third group. In some embodiments, the DFF further comprises an output buffer; and those of the transistors comprising the output buffer are Vt_low elements of the second group. In some embodiments, the transistors of the cell region are further arranged to function as a scan-insertion-type DFF (SDFQ) comprising the DFF itself and a multiplexer. Transistors comprising the multiplexer are Vt_low elements of the second group.In some embodiments, the DFF further comprises a clock buffer, the clock buffer includes first and second LV inverters; and those of the transistors comprising the first LV inverter and / or the second LV inverter are Vt_low elements of the second group.

[0225] In some embodiments, a method (of forming a semiconductor device) comprises: forming active regions comprising doped regions of a substrate; forming source / drain (S / D) regions comprising doped first regions of the active regions, wherein the S / D regions represent first transistor components, wherein second regions of the active regions located between corresponding S / D regions are channel regions representing second transistor components; forming gate lines over corresponding ones of the channel regions, wherein the gate lines represent third transistor components;and forming metal-to-S / D (MD) contact structures over corresponding ones of the S / D regions, wherein the MD contact structures represent fourth transistor components. Forming active regions, forming S / D regions, forming MD contact structures, and forming gate lines results in: a first set of the first to fourth transistor components connected as corresponding transistors defining a primary latch; a second set of the first to fourth transistor components connected as corresponding transistors defining a secondary latch; and a third set of the first to fourth transistor components connected as corresponding transistors defining a clock buffer; wherein the primary latch, the secondary latch, and the clock buffer comprise a D-type flip-flop (DFF); the primary latch comprises a first sleepy inverter and a first non-sleepy (NS) inverter;the secondary latch comprises a second sleepy inverter and a second LV inverter; and the clock buffer comprises first and second LV inverters; a first group of some, but not all, of the transistors having elements configured with a standard threshold voltage (Vt_std elements); a second group of some, but not all, of the transistors having elements configured with a low threshold voltage lower than the standard threshold voltage (Vt_low elements); and those of the transistors comprising the first LV inverter or the second LV inverter are Vt_low elements of the second group.

[0226] In some embodiments, forming active regions, forming S / D regions, forming gate lines, and forming MD contact structures further results in: those of the transistors comprising the first NS inverter and the second NS inverter of the clock buffer being Vt_low elements of the second group. In some embodiments, forming active regions, forming S / D regions, forming gate lines, and forming MD contact structures further results in: a fourth set of the first to fourth transistor components connected as corresponding transistors defining an output buffer included in the DFF; and those of the transistors comprising the output buffer being Vt_low elements of the second group.

[0227] In some embodiments, forming active regions, forming S / D regions, forming gate lines, and forming MD contact structures further results in: a third group of some, but not all, of the transistors having elements configured with a high threshold voltage higher than the standard threshold voltage (Vt_high elements); and those of the transistors comprising the first sleepy inverter of the primary latch and the second sleepy inverter of the secondary latch being Vt_high elements of the third group.In some embodiments, forming active regions, forming S / D regions, forming gate lines, and forming MD contact structures further results in: a fourth set of the first to fourth transistor components, connected as corresponding transistors, defining an output buffer included in the DFF; and those of the transistors comprising the output buffer being Vt_low elements of the second group. In some embodiments, those of the transistors comprising the first NS inverter and the second NS inverter of the clock buffer are Vt_low elements of the second group.In some embodiments, forming active regions, forming S / D regions, forming gate lines, and forming MD contact structures further results in: a fourth set of the first to fourth transistor components connected as respective transistors defining a multiplexer; wherein the DFF and the multiplexer comprise a scan insertion type DFF (SDFQ); and those of the transistors comprising the multiplexer are Vt_low elements of the second group.

[0228] In some embodiments, forming active regions, forming S / D regions, forming gate lines, and forming MD contact structures further results in: a fourth set of the first to fourth transistor components connected as corresponding transistors defining a multiplexer; wherein the DFF and the multiplexer comprise a scan insertion type DFF (SDFQ); and those of the transistors comprising the multiplexer are Vt_low elements of the second group. In some embodiments, those of the transistors comprising the first NS inverter of the primary latch and the second NS inverter of the secondary latch are Vt_std elements of the first group.

[0229] In some embodiments, a semiconductor device comprises: a cell region including active regions extending in a first direction and having transistor components formed therein; the transistors of the cell region are arranged to function as a D-type flip-flop (DFF) including a primary latch, a secondary latch, a clock buffer, and an output buffer; the primary latch includes a first sleepy inverter and a first non-sleepy inverter (NS inverter); the secondary latch includes a second sleepy inverter and a second NS inverter; the clock buffer includes third and fourth NS inverters; and the output buffer includes a fifth NS inverter; a first group of some, but not all, of the transistors have elements configured with a standard threshold voltage (Vt_std elements);a second group of some, but not all, of the transistors has elements configured for a low threshold voltage lower than the standard threshold voltage (Vt_low elements); and those of the transistors that comprise at least two of the first LV inverter or the second LV inverter or the output buffer are Vt_low elements of the second group.;

[0230] It will be readily apparent to one skilled in the art that one or more of the disclosed embodiments will achieve one or more of the advantages set forth above. After reading the above specifications, one skilled in the art will be able to effect various modifications, substitutions of equivalents, and various other embodiments as broadly disclosed herein. Therefore, it is intended that the protection granted herein be limited only by the definition contained in the appended claims and equivalents thereof.

Claims

[1] A semiconductor device comprising: a cell region including active regions extending in a first direction and having transistor components formed therein; wherein the transistors of the cell region are arranged to function as a D-type flip-flop (DFF) comprising a primary latch, a secondary latch, and a clock buffer; the primary latch comprises a first sleepy inverter and a first non-sleepy inverter (NS inverter); the secondary latch comprises a second sleepy inverter and a second LV inverter; and the clock buffer includes third and fourth LV inverters; a first group of some, but not all, of the transistors has elements configured with a standard threshold voltage (Vt_std elements); a second group of some, but not all, of the transistors has elements configured with a low threshold voltage that is lower than the standard threshold voltage (Vt_low elements); and those of the transistors comprising the first LV inverter and / or the second LV inverter are Vt_low elements of the second group. [2] A semiconductor device according to claim 1, wherein: those of the transistors comprising the first LV inverter and the second LV inverter of the clock buffer are Vt_low elements of the second group. [3] A semiconductor device according to claim 1 or 2, wherein: the DFF further comprises an output buffer; and those of the transistors comprising the output buffer are Vt_low elements of the second group. [4] A semiconductor device according to claim 1, wherein: a third group of some, but not all, of the transistors has elements configured with a high threshold voltage higher than the standard threshold voltage (Vt_high elements); and those of the transistors comprising the first sleepy inverter of the primary latch and the second sleepy inverter of the secondary latch, Vt_high are elements of the third group. [5] A semiconductor device according to claim 4, wherein: the DFF further comprises an output buffer; and those of the transistors comprising the output buffer are Vt_low elements of the second group. [6] A semiconductor device according to any one of the preceding claims, wherein: the transistors of the cell region are further arranged to function as a scan insertion type DFF (SDFQ) including the DFF and a multiplexer; and those of the transistors comprising the multiplexer are Vt_low elements of the second group. [7] A semiconductor device according to any one of the preceding claims, wherein: those transistors comprising the first LV inverter of the primary latch and the second LV inverter of the secondary latch, Vt_std are elements of the first group. [8] A semiconductor device according to claim 1, wherein: the transistors of the cell area are further arranged to function as a scan insertion type DFF (SDFQ) including the DFF, a multiplexer, and a scan buffer; and those of the transistors comprising the sampling buffer Vt_std are elements of the first group. [9] A semiconductor device according to claim 1, wherein: a third group of some, but not all, of the transistors has elements configured with a high threshold voltage higher than the standard threshold voltage (Vt_high elements); the DFF further comprises an output buffer; and the transistors of the cell region are further arranged to function as a scan insertion type DFF (SDFQ) including the DFF and a multiplexer; at least one of a configuration (A) or a configuration (B) or a configuration (C) is true; for configuration (A), those of the transistors comprising the output buffer Vt_low are elements of the second group; for configuration (B), those transistors comprising the multiplexer are Vt_low elements of the second group; and for configuration (C), those of the transistors comprising the first sleepy inverter of the primary latch and the second sleepy inverter of the secondary latch are Vt_high elements of the third group. [10] A semiconductor device comprising: a cell region including active regions extending in a first direction and having transistor components formed therein; wherein the transistors of the cell region are arranged to function as a scan insertion D flip-flop (SDFQ) including a multiplexer and a D flip-flop (DFF), the DFF comprising a primary latch and a secondary latch; the primary latch comprises a first sleepy inverter and a first non-sleepy inverter (NS inverter); the secondary latch comprises a second sleepy inverter and a second LV inverter; and a first group of some, but not all, of the transistors has elements configured with a standard threshold voltage (Vt_std elements); a second group of some, but not all, of the transistors has elements configured with a low threshold voltage that is lower than the standard threshold voltage (Vt_low elements); and those of the transistors comprising the multiplexer are Vt_low elements of the second group. [11] A semiconductor device according to claim 10, wherein: a third group of some, but not all, of the transistors has elements configured with a high threshold voltage higher than the standard threshold voltage (Vt_high elements); and those of the transistors comprising the first sleepy inverter of the primary latch and the second sleepy inverter of the secondary latch, Vt_high are elements of the third group. [12] A semiconductor device according to claim 11, wherein: the DFF further comprises an output buffer; and those of the transistors comprising the output buffer are Vt_low elements of the second group. [13] A semiconductor device according to claim 11, wherein: the transistors of the cell region are further arranged to function as a scan insertion type DFF (SDFQ) including the DFF and a multiplexer; and those of the transistors comprising the multiplexer are Vt_low elements of the second group. [14] A semiconductor device according to any one of claims 10 to 13, wherein: the DFF further comprises a clock buffer, the clock buffer including first and second LV inverters; and those of the transistors comprising the first LV inverter and / or the second LV inverter are Vt_low elements of the second group. [15] A method of forming a semiconductor device, the method comprising: Forming active regions comprising doping regions of a substrate; Forming source / drain (S / D) regions comprising doping first regions of the active regions, the S / D regions representing first transistor components, second regions of the active regions located between corresponding S / D regions being channel regions representing second transistor components; Forming gate lines over corresponding ones of the channel regions, the gate lines representing third transistor components; and Forming metal-to-S / D contact structures (MD contact structures) over corresponding ones of the S / D regions, the MD contact structures representing fourth transistor components; and where forming active regions, forming S / D regions, forming MD contact structures and forming gate lines results in: a first set of the first to fourth transistor components connected as respective transistors defining a primary latch; a second set of the first to fourth transistor components connected as respective transistors defining a secondary latch; and a third set of the first to fourth transistor components connected as respective transistors defining a clock buffer; wherein the primary latch, the secondary latch, and the clock buffer comprise a D-type flip-flop (DFF); the primary latch comprises a first sleepy inverter and a first non-sleepy inverter (NS inverter); the secondary latch comprises a second sleepy inverter and a second LV inverter; and the clock buffer comprises first and second LV inverters; a first group of some, but not all, of the transistors has elements configured with a standard threshold voltage (Vt_std elements); a second group of some, but not all, of the transistors has elements configured with a low threshold voltage that is lower than the standard threshold voltage (Vt_low elements); and those of the transistors comprising the first LV inverter and / or the second LV inverter are Vt_low elements of the second group. [16] The method of claim 15, wherein forming active regions, forming S / D regions, forming gate lines, and forming MD contact structures further results in: those of the transistors comprising the first LV inverter and the second LV inverter of the clock buffer are Vt_low elements of the second group. [17] A method according to claim 15 or 16, wherein: the formation of active regions, the formation of S / D regions, the formation of gate lines and the formation of MD contact structures further result in: a fourth set of the first to fourth transistor components connected as corresponding components defining an output buffer included in the DFF; and those of the transistors comprising the output buffer are Vt_low elements of the second group. [18] The method of claim 15, wherein: the formation of active regions, the formation of S / D regions, the formation of gate lines and the formation of MD contact structures further result in: a third group of some, but not all, of the transistors has elements configured with a high threshold voltage higher than the standard threshold voltage (Vt_high elements); and those of the transistors comprising the first sleepy inverter of the primary latch and the second sleepy inverter of the secondary latch, Vt_high are elements of the third group. [19] The method of claim 18, wherein: the formation of active regions, the formation of S / D regions, the formation of gate lines and the formation of MD contact structures further result in: a fourth set of the first to fourth transistor components connected as corresponding components defining an output buffer included in the DFF; and those of the transistors comprising the output buffer are Vt_low elements of the second group. [20] The method of claim 18, wherein: the formation of active regions, the formation of S / D regions, the formation of gate lines and the formation of MD contact structures further result in: a fourth set of the first to fourth transistor components connected as respective transistors defining a multiplexer; wherein the DFF and the multiplexer comprise a scan insertion type DFF (SDFQ); and those of the transistors comprising the multiplexer are Vt_low elements of the second group.