Semiconductor device
By dividing the semiconductor device cell into two cell regions and adjusting the contact hole and gate structure, the current path is extended and the on-resistance is increased, thus solving the problem of insufficient short-circuit current capability of silicon carbide devices and achieving a balance between device reliability and performance.
Patent Information
- Application Number
- CN202423075489.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-12
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2034-12-12
AI Technical Summary
Silicon carbide semiconductor devices are not as capable of handling short-circuit current as silicon-based devices, which affects their reliability and lifespan.
The semiconductor device cell is divided into two cell regions. The contact hole exposes a part of the embedded region in the source region, so that the source metal is connected to the embedded region, extending the current path length. By optimizing the ratio of the embedded region length to the cell length and the ratio of the contact hole width to the contact region width, the gate structure is adjusted to increase the on-resistance and improve the short-circuit current capability.
This improves the short-circuit current capability of semiconductor devices while maintaining good on-current capability, thereby enhancing device reliability and performance.
Smart Images
Figure CN223639611U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of semiconductor devices, and relates to a semiconductor device. BACKGROUND
[0002] Compared with the traditional silicon material, the third-generation semiconductor material silicon carbide (SiC) exhibits more excellent performance. It has a wider band gap, higher electron mobility, better thermal conductivity and higher critical breakdown field. These characteristics make silicon carbide devices surpass silicon-based devices in high temperature, low loss, high voltage resistance, radiation resistance and temperature stability, indicating their potential for wide application in multiple industries.
[0003] However, the high critical breakdown field of silicon carbide also brings some challenges. Under the same blocking voltage and rated current conditions, silicon carbide devices can achieve smaller chip size and higher current density. This high current density makes the heat more concentrated, resulting in that the silicon carbide device is not as good as the silicon-based device in short-circuit current bearing capacity, which can adversely affect its reliability and service life.
[0004] Therefore, how to provide a semiconductor device to improve the short-circuit current capacity of the semiconductor device and improve the reliability of the device has become an important technical problem to be solved by those skilled in the art.
[0005] It should be noted that the above introduction to the technical background is only to facilitate the clear and complete description of the technical scheme of the present application, and to facilitate the understanding of those skilled in the art. The above technical scheme cannot be considered as known to those skilled in the art merely because it is described in the background section of the present application. SUMMARY
[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a semiconductor device to solve the problem that the short-circuit current of the semiconductor device in the prior art needs to be improved.
[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides a semiconductor device, comprising a plurality of cells, the cells are divided into two cell regions along a first direction, each of the cell regions comprises:
[0008] a drift region;
[0009] a source doped region located in the drift region, the source doped region comprises a well region, a source region and a plurality of contact regions, wherein the source region and the contact regions are located in the well region, a plurality of the contact regions are arranged in a second direction, the second direction is perpendicular to the first direction, the source region comprises at least one embedded region, the embedded region extends into between adjacent two of the contact regions from the first direction to separate any two adjacent contact regions.
[0010] a contact hole above the drift region, the contact hole exposing at least a portion of the source doped region;
[0011] a source metal above the drift region, the source metal also filling into the contact hole to connect with the source doped region;
[0012] in the cell, the contact hole exposing the source doped region is configured to expose a portion of the embedded region in at least one of the cell regions.
[0013] Optionally, in the first direction, a ratio of a width of the contact hole exposing the portion of the embedded region to a width of the contact region ranges from 0.7 to 0.8.
[0014] Optionally, in the second direction, a ratio of a length of the embedded region to a length of the cell region ranges from 0.23 to 0.29.
[0015] Optionally, in the first direction, the source region in two of the cell regions is connected, and each of the contact regions in two of the cell regions is separated.
[0016] Optionally, in the first direction, the source region in two of the cell regions is separated, and each of the contact regions in two of the cell regions is separated.
[0017] Optionally, the cell further comprises a JFET region and a gate, wherein, in the first direction, the JFET region spans across the drift region in two of the cell regions, and the JFET region is located between the well regions in two of the cell regions; the gate spans above the drift region in two of the cell regions, and the gate covers at least a portion of the JFET region.
[0018] Optionally, the semiconductor device comprises at least one whole-gate cell, and the gate in the whole-gate cell completely covers the JFET region.
[0019] Optionally, the semiconductor device further comprises at least one split-gate cell, and the gate in the split-gate cell comprises a first sub-gate and a second sub-gate, the first sub-gate and the second sub-gate are separately arranged in the first direction, and the first sub-gate and the second sub-gate both cover a portion of the JFET region.
[0020] Optionally, in the split-gate cell, a ratio of an area of the JFET region covered by the gate to an area of the JFET region ranges from 0.1 to 0.4.
[0021] Optionally, in the semiconductor device, the number of the whole gate cells is equal to the number of the split gate cells.
[0022] As described above, the semiconductor device of the present application has the following technical effects: In the first aspect, by dividing the cells of the semiconductor device into two cell regions, the contact hole of at least one cell region exposes the local part of the embedded region in the source region, so that the source metal filled into the contact hole is connected with the local part of the embedded region, the path length of the current flowing through the source region is extended, the on-resistance is increased, and the improvement of the short-circuit current capability of the device is realized. Moreover, by optimizing the ratio of the length of the embedded region to the length of the cell, and optimizing the ratio of the width of the contact hole exposing the local part of the embedded region to the width of the contact region, the on-current capability and the short-circuit current capability of the device are balanced while improving the short-circuit current capability of the device. In the second aspect, by adjusting the gate structure of at least one cell (for example, the split gate cell) in the semiconductor device, the gate structure does not completely cover the JFET region, the on-resistance is increased from the perspective of increasing the source resistance, and the contact position of the source metal and the source doped region is adjusted by adjusting the exposed position of the contact hole to improve the short-circuit current capability of the device. Moreover, under the premise of adjusting the gate structure in part of the cells, the ratio range of the length of the embedded region to the length of the cell and the ratio range of the area of the JFET region covered by the gate to the area of the JFET region are further optimized, and the balance between the short-circuit current capability and the on-current capability of the device is realized to ensure the working performance of the device. BRIEF DESCRIPTION OF DRAWINGS
[0023] Figure 1 A partial cross-sectional view of a semiconductor device provided as a comparative example is shown;
[0024] Figure 2 A structure schematic view of a cell in a semiconductor device provided by Embodiment One of the present application is shown;
[0025] Figure 3 A first cross-sectional schematic view along the I-I' part of the cell is shown; Figure 2
[0026] A second cross-sectional schematic view along the I-I' part of the cell is shown; Figure 4
[0027] Figure 5 A second structure schematic view of the cell when the source metal is not formed in the cell provided by Embodiment One of the present application is shown; Figure 2
[0028] Figure 6 A second structure schematic view of the cell when the source metal is not formed in the cell provided by Embodiment One of the present application is shown;
[0029] Figure 7 Fig. 3 shows a third structure schematic diagram of a cell without forming source metal according to the first embodiment of the present application;
[0030] Figure 8 Fig. 4 shows a fourth structure schematic diagram of a cell without forming source metal according to the first embodiment of the present application;
[0031] Figure 9 Fig. 5 shows a curve diagram of on-resistance of a semiconductor device according to the first embodiment of the present application versus embedded region length L1 / cell length L2;
[0032] Figure 10 Fig. 6 shows a curve diagram of short-circuit current time / on-resistance of a semiconductor device according to the first embodiment of the present application versus embedded region length L1 / cell length L2;
[0033] Figure 11 Fig. 7 shows a cross-sectional schematic diagram along the II-II' part of Fig. 1; Figure 2
[0034] Fig. 8 shows a third cross-sectional schematic diagram along the I-I' part of Fig. 1; Figure 12 Figure 2 Fig. 9 shows a structure schematic diagram of a semiconductor device according to the second embodiment of the present application.
[0035] Figure 13 BRIEF DESCRIPTION OF DRAWINGS
[0036] 10 - substrate, 20 - drift region, 21 - JFET region, 30 - source doped region, 31 - well region, 32 - source region, 321 - embedded region, 322 - body region, 33 - contact region, 40 - contact hole, 50 - source metal, 60 - gate, 61 - first sub-gate, 62 - second sub-gate, 70 - gate dielectric layer, 80 - interlayer dielectric layer, 90 - drain metal, A - cell region, A1 - first cell region, A2 - second cell region, C - cell, C1 - whole-gate cell, C2 - split-gate cell. DETAILED DESCRIPTION
[0037] The above embodiments of the present application are described with reference to the specific examples. However, those skilled in the art will readily appreciate that various modifications and changes can be made to the embodiments without departing from the scope of the present application, which is set forth not by the foregoing description but by the annexed claims.
[0038] Please refer to
[0039] Please refer to Figures 1 to 13 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0040] Comparative Example
[0041] Please see Figure 1 , Figure 1 This diagram shows a partial top view of a semiconductor device provided in the comparative example. The cells in the semiconductor device are arranged in a stripe pattern, and each cell includes a source region 32, a contact region 33, a gate 60, and a source contact hole. Figure 1 The location of the source contact hole, not marked, can be referenced. Figure 1 (Understanding the position of the source metal 50) and the source metal 50, wherein a portion of the source region 32 is embedded in the contact region 33, and the source contact holes are arranged in a "I" shape parallel to the gate 60, fully exposing the contact region 33 and the portion of the source region 32 embedded in the contact region 33. The source metal 50 fills the source contact holes and connects with the exposed source region 32 and contact region 33. When the semiconductor device is in the on state, the current flows directly out from the source metal 50 after passing through a very short area where the source region 32 is located. Figure 1 (The dashed arrow in the middle shows a schematic diagram of the current flow path.) Although it exhibits good conductivity, under short-circuit conditions, the short-circuit current duration is relatively short and the short-circuit current capacity is relatively weak.
[0042] Example 1
[0043] This embodiment provides a semiconductor device; please refer to [link / reference]. Figure 2 , Figure 2 A cross-sectional schematic diagram of a cell in a semiconductor device is shown. The semiconductor device includes at least one cell C. Along a first direction X, the cell C is divided into two cell regions A. Each cell region A includes a drift region 20, a source doped region 30, a contact hole, and a source metal 50. The first direction X corresponds to the width direction of the cell C. It should be noted that, for the convenience of a detailed description of the structure of the cell C below, the two cell regions A in the same cell C will be referred to as the first cell region A1 and the second cell region A2, respectively.
[0044] Specifically, the source doped region 30 is located within the drift region 20. The source doped region 30 includes a well region 31, a source region 32, and multiple contact regions 33. The source region 32 and the contact regions 33 are both located within the well region 31. Please refer to the relevant documentation. Figure 3 , Figure 3 It shows alongFigure 2 A first cross-sectional schematic diagram of the I-I' portion shows multiple contact areas 33 arranged in the second direction Y. The source region 32 includes at least one embedding region 321. The embedding region 321 extends from the first direction X between two adjacent contact areas 33, spacing any two adjacent contact areas 33. The second direction Y is perpendicular to the first direction X (the second direction Y corresponds to the length direction of the cell C).
[0045] The contact hole 40 is located above the drift region 20. Please refer to the following: Figure 4 , Figure 4 This diagram illustrates the first structural design when the cell does not form a source metal (which can be considered as...). Figure 3 The structure before the formation of the source metal 50). The contact hole 40 ( Figure 4 The outline of the contact hole 40 (shown by the dashed box) exposes at least a portion of the source doped region 30. The source metal 50 is located above the drift region 20. The source metal 50 also fills the contact hole 40 to connect with the source doped region 30. Please refer to [reference needed]. Figure 5 and Figure 6 ,in, Figure 5 It shows along Figure 2 A schematic diagram of the second cross-section at the I-I' section. Figure 6 A schematic diagram of a second structure is shown when the cell does not form a source metal (which can be considered as...). Figure 5 (Structure of the source metal 50 before its formation).
[0046] In the cell C, the contact hole 40 is configured to expose the source doped region 20 in such a state that at least one contact hole 40 in the cell region A exposes a portion of the embedding region 321 (here, the contact hole 30 exposes a portion of the embedding region 321 in the cell region A where the contact hole 30 is located). Simultaneously, the contact hole 30 also exposes a portion of each contact region 33 in the same cell region A. It should be noted that the partial or complete exposure of the contact hole 30 mentioned herein refers to a portion or complete exposure of the upper surface (the side away from the substrate) of the corresponding structure, not a portion or complete exposure in a three-dimensional state.
[0047] It should be noted that "multiple" in this document refers to two or more, for example, "multiple contact areas 33" refers to at least two contact areas 33. "Partial" in this document refers only to a part of the corresponding structure, for example, "exposing a part of the embedded area 321" means "only a part of the embedded area 321 is exposed".
[0048] In the embodiments of this application, comparison Figure 1 and Figure 2, by configuring the contact hole 40 to expose the source doped region 30 in a state that the contact hole 40 exposes part of the embedded region 321 in at least one of the cell regions A, so that after the source metal 50 is filled into the contact hole 40, the current in the corresponding cell region A needs to pass through a longer path of the source region 32 before it can flow out from the source metal 50 (i.e. the path length of the current flowing through the source region 32 is extended), so that the overall on-resistance of the device is increased, thereby reducing the saturation current of the semiconductor device and improving the short-circuit current capability of the device. At the same time, since the contact area between the source metal 50 and the source region 32 and each of the contact regions 33 is reduced, the contact resistance of the source metal 50 is increased, which also improves the on-resistance of the device to some extent. Therefore, in the embodiment of the present application, the short-circuit current capability of the device is improved by sacrificing part of the on-resistance, thereby improving the reliability of the device.
[0049] In an embodiment, as shown in Figure 3 and Figure 4 , in one of the two cell regions A (for example, the first cell region A1), the contact hole 40 exposes part of the embedded region 321, so that the source metal 50 is connected to part of the embedded region 321. And in the other of the two cell regions A (for example, the second cell region A2), the contact hole 40 also exposes part of the embedded region 321, so that the source metal 50 is also connected to part of the embedded region 321.
[0050] In another embodiment, as shown in Figure 5 and Figure 6 , in one of the two cell regions A (for example, the first cell region A1), the contact hole 40 exposes part of the embedded region 321, so that the source metal 50 is connected to part of the embedded region 321. And in the other of the two cell regions A (for example, the second cell region A2), the contact hole 40 exposes the entire embedded region 321, so that the source metal 50 is connected to the entire embedded region 321.
[0051] In addition, it is easy to understand that, since the number of the contact regions 33 in each of the cell regions A is multiple, and the embedded regions 321 extend into the adjacent two contact regions 33, it means that the number of the embedded regions 321 in the source region 32 is at least one. Then, correspondingly, in the same cell C, at least one of the two contact holes 40 exposes the partial of at least one of the embedded regions 321 in the cell region A where the contact hole 40 is located, so that at least one of the two source metals 50 is connected with the partial of one of the embedded regions 321 in the same cell region A. Or, at least one of the two contact holes 40 exposes the partial of multiple embedded regions 321 in the same cell region A, so that at least one of the two source metals 50 is connected with the partial of multiple or all of the embedded regions 321 in the same cell region A.
[0052] In yet another embodiment, please refer to Figure 7 Fig. and Figure 8 wherein, Figure 7 and Figure 8 respectively show the third and fourth structural schematic diagrams of the cell without forming the source metal. In the case of including more than two (for example, 3) contact regions 33 in each of the cell regions A, the source region 32 of the cell region A correspondingly includes more than one (for example, 2) embedded regions 321. One of the contact holes 40 in the two cell regions A exposes the partial of several embedded regions 321 of the cell region A where the contact hole 40 is located, and exposes the whole of the remaining embedded regions 321, so that the source metal 50 in the same cell region A is connected with the partial of several embedded regions 321 and the whole of the remaining embedded regions 321. At this time, the area of the source doped region 30 exposed by the contact hole 40 is close to the side edge (for example, E1 or E2) of the other cell region A in a tooth shape. And / or, the other of the contact holes 40 in the two cell regions A exposes the partial of several embedded regions 321 of the cell region A where the contact hole 40 is located, and exposes the whole of the remaining embedded regions 321, so that the source metal 50 in the cell region A where the contact hole 40 is located is connected with the partial of several embedded regions 321 and the whole of the remaining embedded regions 321.
[0053] For example, in the case that the contact hole 40 of the first cell region A1 exposes the partial of several embedded regions 321 in the first cell region A1, and exposes the whole of the remaining embedded regions 321 in the first cell region A1, the exposure state of the contact hole 40 of the second cell region A2 can be the following three situations: the contact hole 40 exposes the partial of any one of the embedded regions 321 in the second cell region A2 (please refer to Figure 4the structure exposed by the contact hole 40 in the second cell region A2), the contact hole 40 exposes the entirety of any one of the embedded regions 321 in the second cell region A2 (please refer to Figure 6 the structure exposed by the contact hole 40 in the second cell region A2), and the contact hole 30 exposes the entirety of the remaining embedded regions 321 in the second cell region A2 (please refer to Figure 7 and Figure 8 the structure exposed by the contact hole 40 in the second cell region A2). In the third case, the region of the source doped region 30 exposed by the contact hole 40 in the first cell region A1 close to one side edge of the second cell region A2 can be axially symmetric (as shown in Figure 7 ) or inversely symmetric (as shown in Figure 8 ) to the region of the source doped region 30 exposed by the contact hole 40 in the second cell region A2 close to one side edge of the first cell region A1. Figure 7 and Figure 8 , the uniformity of the current path length of the cell C in the first direction X can be achieved, and the working stability of the device can be improved. Through flexible design of the positions of the contact holes 40 of the two cell regions A, the semiconductor device can be applied to various application scenarios.
[0054] In optional embodiments, as shown in Figure 4 and Figure 6 , in the first direction X, the width of the contact hole 40 exposing the partial embedded region 321 is W1 (which is actually the width of the surface of the source doped region 30 exposed by the contact hole 40), the width of the contact region 33 is W2, and the range of W1 / W2 is 0.7-0.8 (including the end point value), which can be 0.75. The contact hole 40 is used to define the contact position and contact area of the source metal 50 and the source doped region 30. In production, the mask used to etch the contact hole 40 can be adjusted to easily adjust the contact position and contact area of the source metal 50, without additional process difficulty.
[0055] In optional embodiments, as shown in Figure 4 and Figure 6 , in the second direction Y, the ratio of the length L1 of the embedded region 321 to the length L2 of the cell C is in the range of 0.23-0.29 (including the end point value), which can be 0.24, 0.26, or 0.28.
[0056] In the embodiments of the present application, please refer to Figure 9 , Figure 9 shows a curve of the on-resistance of the semiconductor device varying with the length L1 of the embedded region and the length L2 of the cell. From the curve, it can be seen that the on-resistance of the semiconductor device is relatively stable when the length L1 of the embedded region is in the range of 0.23-0.29 times the length L2 of the cell.Figure 9 As can be seen from the above, the on-resistance of the semiconductor device increases with the decrease of the ratio of the embedded region length L1 to the cell length L2, which indicates that the on-resistance of the device can be precisely controlled by adjusting the ratio of the embedded region length L1 to the cell length L2 to adjust the short-circuit current capability of the device. Of course, this also indicates that the short-circuit current capability of the device is achieved by sacrificing part of the on-current capability of the device. In order to balance the short-circuit current capability of the device and the on-current capability of the device, please refer to Figure 10 , Figure 10 The ratio of the short-circuit current time (SC) to the on-resistance (Rs) of the device is shown as a function of the embedded region length L1 to the cell length L2, and the greater the ratio of the short-circuit current time to the on-resistance, the better the balance between the short-circuit current capability and the on-current capability of the semiconductor device, and the better the comprehensive performance. As can be seen from Figure 10 , the ratio of SC / Rs increases first and then decreases with the increase of the ratio of the embedded region length L1 to the cell length L2. Therefore, based on Figure 10 , the ratio of the embedded region length L1 to the cell length L2 in the embodiment is preferably 0.23-0.26, and in particular, when the ratio of the embedded region length L1 to the cell length L2 is 0.25, the best balance is achieved, and at this time, only a small on-current capability is sacrificed to effectively improve the short-circuit current capability of the device.
[0057] In alternative embodiments, please refer to Figure 2 and Figure 11 , wherein, Figure 11 is shown as Figure 2 is a cross-sectional schematic view of the II-II' part in FIG. 1. The cell C further comprises a JFET region 21 and a gate 60. In the first direction X, the JFET region 21 straddles the drift region 20 of two of the cell regions A. And the JFET region 21 is located between the well regions 31 of two of the cell regions A. The gate 60 straddles the drift region 20 of two of the cell regions A. And the gate 60 covers at least part of the JFET region 21. In the embodiment, the gate 60 covers the entire JFET region 21.
[0058] In alternative embodiments, as shown in Figures 2 to 11 , the source region 32 further comprises a body region 322, the body regions 322 in two of the cell regions A are opposite, and the body region 322 in the same cell region A is adjacent to each of the embedded regions 321 and each of the contact regions 33. The gate 60 covers part of the body region 322.
[0059] In alternative embodiments, as shown in Figure 2As shown, the cell C further includes a gate dielectric layer 70 and an interlayer dielectric layer 80. The gate dielectric layer 70 is located between the drift region 20 and the gate 60. The interlayer dielectric layer 80 is located above the drift region 20 and covers the gate 60. The contact hole 40 is formed by etching the interlayer dielectric layer 80 (i.e., the contact hole 40 penetrates the interlayer dielectric layer 80).
[0060] In optional embodiments, such as Figure 2 As shown, the cell C further includes a substrate 10 and a drain metal 90. The drift region 20 is located above the substrate 10, and the drain metal 90 is located below the substrate 10 to realize a vertical semiconductor device. Optionally, the substrate 10 is made of silicon carbide (i.e., the semiconductor device can be a planar silicon carbide device). The gate 60 is made of polysilicon.
[0061] In one embodiment, such as Figure 11 As shown, in the first direction X, the source regions 32 of the two cell regions A are separated, and each contact region 33 of the two cell regions A is separated respectively. At this time, the cell C in the semiconductor device has an elongated structure, such as... Figure 3 and Figure 8 As shown. Furthermore, the well regions 31 of the two cell regions A are also separated. At this time, the plurality of contact regions 33 in each cell region A are spaced apart along the length direction of the cell C.
[0062] In another embodiment, please refer to Figure 12 , Figure 12 It shows along Figure 2 A schematic diagram of the third cross-section at point I-I'. In the first direction X, the source regions 32 of the two cell regions A are connected, and the two contact regions 33 of the two cell regions A are respectively connected (at this time, the two contact regions 33 in each cell region A are also arranged in the second direction Y). In addition, the well regions 31 of the two cell regions A are also connected. At this time, the cell C of the semiconductor device has a square, circular, or polygonal structure. It should be noted that... Figure 12 The example uses a square-shaped cell C. In practical applications, cell C can have other regular or irregular shapes.
[0063] In an optional embodiment, the substrate 10, the drift region 20, and the source region 32 are all of a first conductivity type, and the contact region 33 and the well region 32 are all of a second conductivity type. For example, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
[0064] The semiconductor device of the embodiment, by dividing the cell of the semiconductor device into two cell regions, exposing the contact hole of at least one cell region to the local part of the embedded region in the source region, so that the source metal filled into the contact hole is connected with the local part of the embedded region, prolongs the path length of the current flowing through the source region, thereby increasing the on-resistance, and realizes the improvement of the short-circuit current capability of the device. And by optimizing the ratio of the length of the embedded region to the length of the cell, and optimizing the ratio of the width of the contact hole exposing the local part of the embedded region to the width of the contact region, the on-current capability and the short-circuit current capability of the device are well balanced while improving the short-circuit current capability of the device. In addition, by flexible design of the exposed position of the contact hole in the two cell regions, the connection position of the source metal and the source doped region in the two cell regions is realized, so that the semiconductor device can be applied to various application scenarios.
[0065] Embodiment two
[0066] The embodiment provides a semiconductor device (hereinafter referred to as "semiconductor device"), the difference between the embodiment and embodiment one is that: the gate in the cell C of the semiconductor device in embodiment one completely covers the JFET region (i.e. the whole gate cell C1 described later), and the semiconductor device in the embodiment also includes the cell C whose gate does not completely cover the JFET region (i.e. the split gate cell C2 described later). A kind of cross-sectional schematic diagram of cell C in the semiconductor device is shown.
[0067] Please refer to Figure 13 , as a kind of cross-sectional schematic diagram of the semiconductor device, the semiconductor device includes at least one cell C, along the first direction X, the cell C is divided into two cell regions A( Figure 12 not shown, please refer to Figure 2 ), each of the cell region A includes: drift region 20, source doped region 30, contact hole 40 and source metal 50.
[0068] Specifically, the source doped region 30 is located in the drift region 20. The source doped region 30 includes a well region 31, a source region 32, and a plurality of contact regions 33. The source region 32 and the contact regions 33 are both located in the well region 31. The plurality of contact regions 33 are arranged in the second direction Y. The source region 32 includes at least one embedded region 321. The embedded region 321 protrudes from the first direction X into between any two adjacent contact regions 33 to separate the any two adjacent contact regions 33. The second direction Y is perpendicular to the first direction X. The contact hole 40 is located above the drift region 20. The contact hole 40 exposes at least a part of the source doped region 30. The source metal 50 is located above the drift region 20. The source metal 50 also fills into the contact hole 40 to connect with the source doped region 30. In the cell C, the configuration of the contact hole 40 exposing the source doped region 30 is that: at least one of the contact holes 40 in the cell region A exposes the embedded region 321. Meanwhile, the contact hole 40 also exposes a part of each of the contact regions 33 in the same cell region A.
[0069] In optional embodiments, as shown in Figure 13 The semiconductor device at least includes one whole gate cell C1. The gate 60 in the whole gate cell C1 completely covers the JFET region 21.
[0070] In optional embodiments, as shown in Figure 13 The semiconductor device at least includes one split gate cell C2. The gate 60 in the split gate cell C2 includes a first sub-gate 61 and a second sub-gate 62. The first sub-gate 61 and the second sub-gate 62 are separately arranged in the first direction X. The first sub-gate 61 and the second sub-gate 62 both cover a part of the JFET region 21. It should be noted that although the gate 60 includes the first sub-gate 61 and the second sub-gate 62 which are separately arranged, the gate 60 can still achieve good gate control ability.
[0071] In the embodiments of the present application, under the premise of meeting the gate control ability of the gate, by adjusting the structure of at least one cell C in the semiconductor device, the gate 60 in the cell C includes a first sub-gate 61 and a second sub-gate 62 which are separately arranged. Due to the separate arrangement of the first sub-gate 61 and the second sub-gate 62, a part of the JFET region 21 located below the gate 60 is not covered by the gate 60, thereby increasing the resistance of the accumulation layer formed at the surface of the JFET region 21 close to the gate 60, increasing the on-resistance of the device from the perspective of the source resistance, and improving the short-circuit current capability of the device.
[0072] In an optional embodiment, in the split gate cell C2, the ratio of the area S2 of the JFET region 21 covered by the gate 60 to the area S1 of the JFET region 21 is in the range of 0.1-0.4 (including the end values), including 0.2 or 0.3. The area of the JFET region 21 covered by the gate 60 is the sum of the area of the JFET region 21 covered by the first sub-gate 61 and the area of the JFET region 21 covered by the second sub-gate 62. Although not shown, it is found that the on-resistance of the device increases with the decrease of the above ratio, which indicates that the short-circuit current capability of the device can be effectively adjusted by adjusting the above ratio.
[0073] Further, please refer to 4 and Figure 6 In the second direction Y, the ratio of the length L1 of the embedded region 321 to the length L2 of the cell C is in the range of 0.23-0.29 (including the end values), and can be 0.24, 0.26 or 0.28. In the present embodiment, the ratio of the embedded region length L1 to the cell length L2 is preferably 0.27-0.29. Since in the present embodiment, the short-circuit current capability of the device is improved by adjusting the source resistance and the accumulation layer resistance of the device, the area S2 of the JFET region 21 covered by the gate 60 to the area S1 of the JFET region 21 and the ratio of the embedded region length L1 to the cell length L2 are two parameters that work together. When the ratio of the embedded region length L1 to the cell length L2 is 0.27-0.29 and the ratio of the area S2 of the JFET region 21 covered by the gate 60 to the area S1 of the JFET region 21 is 0.3-0.4, the short-circuit current capability of the device can be effectively improved, so it is not necessary to sacrifice the on-current capability of the device by going beyond the above range, and the device can work well.
[0074] In an optional embodiment, in the semiconductor device, the number of the whole gate cells C1 is equal to the number of the split gate cells C2. For example, in the first direction, the whole gate cells C1 and the split gate cells C2 are arranged alternately to ensure the performance balance of the semiconductor device in each region.
[0075] The semiconductor device of the embodiment includes the whole gate cell and the split gate cell. The gate in the split gate cell includes the first sub-gate and the second sub-gate arranged separately, so that the gate structure does not completely cover the JFET region, the on-resistance is increased from the perspective of increasing the source resistance, and the short-circuit current capability of the device is further improved on the basis of adjusting the contact position of the source metal and the source doped region to improve the short-circuit current capability of the device. In addition, through the synergistic optimization of the ratio range of the length of the embedded region to the length of the cell and the ratio range of the area of the JFET region covered by the gate to the area of the JFET region, the balance between the short-circuit current capability and the on-current capability of the device can be achieved, and the working performance (such as static parameters such as on-loss) of the device is ensured.
[0076] In summary, in the first aspect, by dividing the cell of the semiconductor device into two cell regions, the contact hole of at least one cell region exposes part of the embedded region in the source region, so that the source metal filled into the contact hole is connected with the part of the embedded region, the path length of the current flowing through the source region is prolonged, and the on-resistance is increased, thereby improving the short-circuit current capability of the device. And by optimizing the ratio of the length of the embedded region to the length of the cell, and optimizing the ratio of the width of the contact hole exposing part of the embedded region to the width of the contact region, the on-current capability and the short-circuit current capability of the device are balanced while improving the short-circuit current capability of the device. In addition, through flexible design of the exposure position of the contact hole in the two cell regions, the connection position of the source metal and the source doped region in the two cell regions is flexibly designed, so that the semiconductor device can be applied to various application scenarios. In the second aspect, by adjusting the gate structure of at least one cell (for example, the split gate cell) in the semiconductor device, the gate structure does not completely cover the JFET region, the on-resistance is increased from the perspective of increasing the source resistance, and the short-circuit current capability of the device is further improved on the basis of adjusting the contact position of the source metal and the source doped region through the exposure position of the contact hole to improve the short-circuit current capability of the device. And on the premise of adjusting the gate structure in part of the cells, the length of the embedded region to the length of the cell and the ratio range of the area of the JFET region covered by the gate to the area of the JFET region are synergistically optimized, so as to balance the short-circuit current capability and the on-current capability of the device, and ensure the working performance of the device. Therefore, the present application effectively overcomes the shortcomings in the prior art and has high industrial utilization value.
[0077] The above embodiments are only illustrative of the principles of the present application and its effects, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.
Claims
1. A semiconductor device, characterized by, The semiconductor device comprises a plurality of cells, each of the cells is divided into two cell regions along a first direction, each of the cell regions comprises: a drift region; a source doped region in the drift region, the source doped region comprises a well region, a source region and a plurality of contact regions, the source region and the contact regions are in the well region, the contact regions are arranged along a second direction perpendicular to the first direction, the source region comprises at least one embedded region, the embedded region extends into between two adjacent contact regions along the first direction to separate the two adjacent contact regions; a contact hole above the drift region, the contact hole exposes at least a part of the source doped region; a source metal above the drift region, the source metal fills into the contact hole to connect with the source doped region; in the cells, the state of the contact hole exposing the source doped region is that the contact hole of at least one of the cell regions exposes the embedded region.
2. The semiconductor device of claim 1, wherein: In the first direction, the ratio of the width of the contact hole exposing the embedded region to the width of the contact region ranges from 0.7 to 0.
8.
3. The semiconductor device of claim 2, wherein, In the second direction, the ratio of the length of the embedded region to the length of the cell region ranges from 0.23 to 0.
29.
4. The semiconductor device of claim 1, wherein: In the first direction, the source regions of the two cell regions are connected, and each of the contact regions of the two cell regions is connected.
5. The semiconductor device of claim 1, wherein: In the first direction, the source regions of the two cell regions are separated, and each of the contact regions of the two cell regions is separated.
6. The semiconductor device of claim 1, wherein The cells further comprise a JFET region and a gate, in the first direction, the JFET region is across the drift regions of the two cell regions, and the JFET region is between the well regions of the two cell regions; the gate is across the drift regions of the two cell regions, and the gate covers at least a part of the JFET region.
7. The semiconductor device of claim 6, wherein The semiconductor device comprises at least one whole gate cell, and the gate of the whole gate cell completely covers the JFET region.
8. The semiconductor device of claim 7, wherein, The semiconductor device further comprises at least one split gate cell, the gate of the split gate cell comprises a first sub-gate and a second sub-gate, the first sub-gate and the second sub-gate are arranged separately along the first direction, and the first sub-gate and the second sub-gate both cover a part of the JFET region.
9. The semiconductor device of claim 8, wherein, In the split gate cell, the ratio of the area of the JFET region covered by the gate to the area of the JFET region ranges from 0.1 to 0.
4.
10. The semiconductor device of claim 8, wherein In the semiconductor device, the number of the whole gate cells is equal to the number of the split gate cells.