IGBT device and method for manufacturing an IGBT device

Abstract

Embodiments of the present application relate to an IGBT device and a preparation method of the IGBT device, wherein the IGBT device comprises a cell region, a plurality of trench gates are arranged in the cell region, the plurality of trench gates at least comprise a first trench gate and a second trench gate, a cross-sectional area of the first trench gate and a cross-sectional area of the second trench gate are different, a depth of the first trench gate and a depth of the second trench gate are the same; the first trench gate and the second trench gate are connected to a gate potential; thus, it is beneficial to adjust the feedback capacitance of the device, improve the switching characteristics of the device, avoid the current oscillation problem, and improve the stability of the device working.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to an IGBT device and a preparation method of the IGBT device. BACKGROUND

[0002] IGBT (Insulated Gate Bipolar Transistor) is a composite full-control voltage-driven power semiconductor device composed of a bipolar transistor and an insulated gate field effect transistor, which has both high input impedance of the insulated gate field effect transistor and low on-state voltage drop of the bipolar transistor. Due to the superior performance of IGBT devices in large current and high voltage, etc., IGBT devices have become a relatively ideal switching device. Trench gate IGBT devices have low on-state loss, strong anti-latch-up capability and excellent short-circuit capability, and have become the mainstream product in the market.

[0003] However, with the gradual reduction of the lateral size (Pitch Size), the switching speed of the trench gate IGBT device is getting faster and faster. The faster switching speed of the IGBT device can easily cause current oscillation problems, thereby seriously affecting the stability of the device operation. SUMMARY

[0004] Therefore, the embodiments of the present application provide an IGBT device and a preparation method of the IGBT device to solve at least one problem in the background art.

[0005] To achieve the above-mentioned purpose, the technical scheme of the present application is as follows:

[0006] In a first aspect, an IGBT device is provided in the embodiments, the IGBT device comprising a cell region, a plurality of trench gates are arranged in the cell region, wherein

[0007] The plurality of trench gates at least comprises a first trench gate and a second trench gate, the cross-sectional area of the first trench gate and the cross-sectional area of the second trench gate are different, and the depth of the first trench gate and the depth of the second trench gate are the same.

[0008] The first trench gate and the second trench gate are both connected to a gate potential.

[0009] Optionally, the ratio of the cross-sectional area of the first trench gate to the cross-sectional area of the second trench gate is in the range of 1:1.3 to 1:4.

[0010] Optionally, a plurality of repeating units are included in the cell region, each of the repeating units comprises at least one first trench gate and at least one second trench gate.

[0011] Optionally, a ratio of a number of the first trench gates to a number of the second trench gates in the cell region is in a range of 10:7 to 10:13.

[0012] Optionally, cross-sectional areas of the first trench gates and the second trench gates are different, specifically, lengths of the first trench gates and the second trench gates are same but line widths are different.

[0013] In a second aspect, a method for manufacturing an IGBT device is provided in the embodiments, and the method comprises:

[0014] A substrate is provided, and the substrate comprises a cell region;

[0015] A plurality of trenches extending from a surface of the substrate to an interior of the substrate are formed in the cell region, and the plurality of trenches at least comprise first trenches and second trenches, cross-sectional areas of the first trenches and the second trenches are different, and depths of the first trenches and the second trenches are same;

[0016] A gate material is filled in the plurality of trenches to form first trench gates in the first trenches and second trench gates in the second trenches, and the first trench gates and the second trench gates are both used for connecting to a gate potential.

[0017] Optionally, the forming of the plurality of trenches extending from the surface of the substrate to the interior of the substrate in the cell region comprises:

[0018] A first mask layer is formed on the substrate, and the first mask layer has a first opening exposing a preset forming position of the first trench and a second opening exposing a preset forming position of the second trench;

[0019] A second mask layer is formed on the first mask layer, and the second mask layer covers the second opening and exposes the first opening;

[0020] A first etching process is performed to form the first trench extending from the surface of the substrate to the interior of the substrate at a position of the first opening;

[0021] The second mask layer is removed, and a third mask layer is formed on the first mask layer, and the third mask layer covers the first opening and exposes the second opening;

[0022] A second etching process is performed to form the second trench extending from the surface of the substrate to the interior of the substrate at a position of the second opening; and an etching depth of the second etching process is same as an etching depth of the first etching process.

[0023] Optionally, the cross-sectional area of the first trench gate and the cross-sectional area of the second trench gate are different, specifically, the length of the first trench gate and the second trench gate are the same but the line width is different.

[0024] Optionally, the ratio of the cross-sectional area of the first trench and the cross-sectional area of the second trench is in the range of 1:1.3 to 1:4.

[0025] Optionally, the ratio of the number of the first trench gates to the number of the second trench gates in the cell region is in the range of 10:7 to 10:13.

[0026] The IGBT device and the preparation method of the IGBT device provided in the embodiments of the present application, wherein the IGBT device comprises a cell region, and a plurality of trench gates are arranged in the cell region, the plurality of trench gates at least comprise a first trench gate and a second trench gate, the cross-sectional area of the first trench gate and the cross-sectional area of the second trench gate are different, and the depth of the first trench gate and the depth of the second trench gate are the same; the first trench gate and the second trench gate are both connected to a gate potential; in this way, by arranging the first trench gate and the second trench gate with different cross-sectional areas in the cell region, different contact areas can be formed between the first trench gate and the collector and between the second trench gate and the collector, thereby facilitating the adjustment of the feedback capacitance of the device, improving the switching characteristics of the device, avoiding the current oscillation problem, and improving the stability of the device in operation.

[0027] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings, which are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and serve to explain the principles of the present application, and do not limit the present application in any manner. In the drawings:

[0029] Figure 1 A plan view of the IGBT device provided in the embodiments of the present application;

[0030] Figure 2 A cross-sectional view along the direction of AA' of the IGBT device provided in the embodiments of the present application; Figure 1

[0031] Figure 3 A flowchart of the preparation method of the IGBT device provided in the embodiments of the present application;

[0032] Figures 4 to 13 A cross-sectional structure schematic diagram of the preparation method of the IGBT device provided in the embodiments of the present application in the execution process. DETAILED DESCRIPTION

[0033] ​Exemplary embodiments of the present application will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present application are illustrated, it will be understood that the present application can be carried out in various ways without being limited to the particular embodiments set forth herein. Conversely, additional embodiments of the present application can from time to time be set forth, of which the person of ordinary skill in the art will avail himself / herself by virtue of the conceptual description of the application as set forth herein.

[0034] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one of ordinary skill in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily obscure the present application.

[0035] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals can represent like elements throughout the several figures.

[0036] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, when an element is referred to as being "connected to" or "coupled to" another element or layer, it can be directly connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “compose” and / or “comprising,” when used in this specification, identify the presence of the stated feature but do not exclude the presence or addition of one or more other features. When used herein, the term “and / or” includes any and all combinations of the associated listed items. The term “more” means two or more.

[0039] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0040] First, this application provides an IGBT device. Figure 1 This is a planar schematic diagram of an IGBT device; Figure 2 For along Figure 1 A cross-sectional view along the AA' direction; as shown. Figure 1 and Figure 2 As shown, the IGBT device includes a cell region 210, in which a plurality of trench gates 150 are disposed. The plurality of trench gates 150 include at least a first trench gate 151 and a second trench gate 152. The cross-sectional area of ​​the first trench gate 151 is different from that of the second trench gate 152, and the depth of the first trench gate 151 is the same as that of the second trench gate 152. Both the first trench gate 151 and the second trench gate 152 are connected to the gate potential.

[0041] It can be understood that the IGBT device generally comprises a cell region and a terminal region. The cell region mainly serves as a current passing region of the chip; and the terminal region is arranged around the overall cell region and serves as a voltage withstanding structure. For the IGBT device provided by the embodiments of the present application, the terminal region can adopt the terminal region structure in the prior art, and thus is not described in detail.

[0042] The IGBT device provided by the embodiments of the present application, specifically a trench gate type IGBT device, by arranging the first trench gate 151 and the second trench gate 152 with different cross-sectional areas in the cell region, different contact areas can be formed between the first trench gate 151 and the collector 115 and between the second trench gate 152 and the collector 115, which is beneficial to adjusting the feedback capacitance C res of the IGBT device, improving the softness of the switching characteristic of the IGBT device, avoiding current oscillation problems, and improving the stability of the IGBT device.

[0043] The cross-sectional area refers to the cross-sectional area in the direction perpendicular to the depth direction of the first trench gate 151 (or the second trench gate 152). In addition, the IGBT device comprises a substrate 110, and the cross-sectional area refers to the cross-sectional area in the direction nominally parallel to the lateral surface of the substrate, with reference to the substrate 110. The word "nominally" refers to the expected or target value of the characteristics or parameters of the components or process steps during the design stage of the product or process, as well as a certain value range higher and / or lower than the expected value; the value range can be due to slight changes in the manufacturing process or tolerance. As shown in Figure 1 and Figure 2 The direction perpendicular to the lateral surface of the substrate is defined as the third direction, i.e. the depth direction of the first trench gate 151 (or the second trench gate 152) is defined as the third direction.

[0044] The depth of the first trench gate 151 and the second trench gate 152 is the same, so that the consistency of the working performance of the first trench gate 151 and the second trench gate 152 is ensured.

[0045] A plurality of trench gates 150 are arranged in the cell region 210, and the number of the trench gates 150 can be up to hundreds of thousands. Without considering the dummy gate, each trench gate in the cell region is usually the same, arranged in an array, and repeated structure. In the embodiment of the present application, the first trench gate 151 and the second trench gate 152 with different cross-sectional areas are arranged in the cell region 210, so that the arrangement of the first trench gate 151 and the second trench gate 152 needs to be considered, that is, in the hundreds of thousands of trench gates 150, which trench gates have one cross-sectional area, and which trench gates have another cross-sectional area. As a specific implementation, the cell region 210 in the present application includes a plurality of repeated units 211, and each repeated unit 211 includes at least one first trench gate 151 and at least one second trench gate 152. In this way, the first trench gate 151 and the second trench gate 152 are not randomly arranged, but each repeated unit 211 includes the first trench gate 151 and the second trench gate 152 with different cross-sectional areas, and then each repeated unit 211 is arranged according to a certain rule (such as arranged in a matrix), so that the uniformity of carrier migration when the IGBT device is turned off can be improved.

[0046] Exemplarily, in the embodiment shown in Figure 1 and Figure 2 , each repeated unit 211 includes two first trench gates 151 and two second trench gates 152, and the two second trench gates 152 are arranged adjacent to each other, and the two first trench gates 151 are arranged on the two sides of the two second trench gates 152, respectively. If each repeated unit 211 is arranged in a matrix, and the spacing between adjacent repeated units is equal to the spacing between each trench gate in each repeated unit 211, then for the cell region, the first trench gate 151 and the second trench gate 152 are arranged according to the rule of two first trench gates 151, two second trench gates 152, two first trench gates 151, two second trench gates 152, and so on. Of course, the present application also does not exclude that the first trench gate 151 and the second trench gate 152 are arranged according to the rule of one first trench gate 151 and one second trench gate 152, or three or more first trench gates 151 and three or more second trench gates 152.

[0047] As an optional embodiment, the ratio of the cross-sectional area of the first trench gate 151 to the cross-sectional area of the second trench gate 152 is in the range of 1:1.3 to 1:4. In a pair of comparison examples, the cell region of the IGBT device includes a plurality of trench gates, and the cross-sectional area of each trench gate is equal, which is equal to the cross-sectional area of the first trench gate 151. Studies have shown that when the cross-sectional area of the first trench gate 151 to the cross-sectional area of the second trench gate 152 is less than 1:1.3, compared with the pair of comparison examples, the improvement effect of the switching characteristics of the device is limited; when the cross-sectional area of the first trench gate 151 to the cross-sectional area of the second trench gate 152 is greater than 1:4, compared with the pair of comparison examples, the feedback capacitance of the device is larger, thereby the reaction time is prolonged, and the loss is larger. When the ratio of the cross-sectional area of the first trench gate 151 to the cross-sectional area of the second trench gate 152 is in the range of 1:1.3 to 1:4, not only the feedback capacitance of the IGBT device is improved, and the switching softness of the IGBT device is improved, but also the loss is smaller.

[0048] Exemplarily, the ratio of the cross-sectional area of the first trench gate 151 to the cross-sectional area of the second trench gate 152 is 1:2.

[0049] It is easy to understand that the IGBT device includes two sides opposite to each other, the trench gate 150 extends from one side of the IGBT device to the inside of the IGBT device, specifically for example, from the upper surface of the substrate 110 to the inside of the substrate 110; the IGBT device also includes a collector 115 arranged on the other side, specifically for example, arranged in the region from the lower surface of the substrate 110 to the inside of the substrate 110. In the direction substantially parallel to the lateral surface of the substrate, the collector 115 is arranged opposite to each trench gate 150; in the third direction, the bottom of each trench gate 150 is towards the side of the collector 115 inside the substrate 110.

[0050] Although Figure 1 and Figure 2Only the case that the IGBT device includes the first trench gate 151 and the second trench gate 152 with two different cross-sectional areas is shown, but in the present embodiment, the IGBT device can include trench gates with more different cross-sectional areas, for example, a third trench gate, and the cross-sectional area of the third trench gate is different from those of the first trench gate and the second trench gate. In this way, the flexibility of adjusting the feedback capacitance of the device can be improved. In other words, the IGBT device provided by the present embodiment can include multiple trench gates, and the cross-sectional area of each trench gate is different. However, the number of types of trench gates included in the IGBT device should not be too large, because if the number of types is too large, the complexity of adjusting the feedback capacitance will increase, and the process complexity will also increase. The number of types of trench gates with different cross-sectional areas is greater than or equal to two and less than or equal to five; that is, the multiple trench gates include at least two trench gates with different cross-sectional areas and at most five trench gates with different cross-sectional areas. It can be understood that in the present embodiment, the cross-sectional area of each trench gate is changed to achieve the purpose of adjusting the feedback capacitance of the device, and although the cross-sectional area of each trench gate is different, the functional role of each trench gate is basically the same. Specifically, in addition to the different cross-sectional areas, the depth, the material filled inside, the material contacted outside, the conductive connection mode, and the connection potential of each trench gate are the same.

[0051] In a specific process, the cross-sectional area of the first trench gate 151 and the cross-sectional area of the second trench gate 152 are different, and specifically, the length of the first trench gate 151 and the length of the second trench gate 152 are the same but the line width is different. In this way, the design complexity is reduced, and the substrate surface area is saved.

[0052] It can be understood that the line width (CD) of the first trench gate 151 and the second trench gate 152, for example, is the size of the first trench gate 151 and the second trench gate 152 along the first direction, and the length of the first trench gate 151 and the second trench gate 152, for example, is the size of the first trench gate 151 and the second trench gate 152 along the second direction; wherein the first direction and the second direction are two directions that are nominally parallel to the lateral surface of the substrate, and the first direction and the second direction are perpendicular to each other.

[0053] In the case that the length of the first trench gate 151 and the length of the second trench gate 152 are the same but the line width is different, the ratio of the cross-sectional area of the first trench gate 151 to the cross-sectional area of the second trench gate 152 is in the range of 1:1.3 to 1:4, that is, the ratio of the line width of the first trench gate 151 to the line width of the second trench gate 152 is in the range of 1:1.3 to 1:4; the ratio of the cross-sectional area of the first trench gate 151 to the cross-sectional area of the second trench gate 152 is 1:2, that is, the ratio of the line width of the first trench gate 151 to the line width of the second trench gate 152 is 1:2.

[0054] Please refer to Figure 1and Figure 2 Optionally, the number of the first trench gates 151 is equal to the number of the second trench gates 152 in the cell region 210. In practical applications, the ratio of the number of the first trench gates 151 to the number of the second trench gates 152 is, for example, in the range of 10:7 to 10:13; in this way, the flexibility of adjusting the feedback capacitance of the device is improved, and the uniformity of the current distribution is avoided as much as possible.

[0055] On this basis, the embodiment of the present application further provides a preparation method of an IGBT device, Figure 3 The flowchart of the preparation method of the IGBT device provided by the embodiment of the present application, Figures 4 to 13 The cross-sectional structure diagram of the preparation method of the IGBT device provided by the embodiment of the present application in the execution process. In the following, the embodiment of the present application will be further explained and described in combination with the preparation method of the IGBT device.

[0056] First, please refer to Figure 3 The preparation method of the IGBT device provided by the embodiment of the present application comprises the following steps:

[0057] S01, providing a substrate, the substrate comprising a cell region;

[0058] S02, forming a plurality of trenches extending from the surface of the substrate to the interior in the cell region, the plurality of trenches comprising at least a first trench and a second trench, the cross-sectional area of the first trench being different from the cross-sectional area of the second trench, and the depth of the first trench being the same as the depth of the second trench;

[0059] S03, filling a gate material in the plurality of trenches to form a first trench gate in the first trench and a second trench gate in the second trench, the first trench gate and the second trench gate both being used for connecting to a gate potential.

[0060] In this way, by forming a plurality of trenches in the cell region, and the plurality of trenches comprising at least a first trench and a second trench with different cross-sectional areas, the first trench gate and the second trench gate with different cross-sectional areas are formed when filling the gate material in the subsequent process, so that different contact areas are formed between the first trench gate and the collector of the IGBT device and between the second trench gate and the collector, which is beneficial to adjusting the feedback capacitance C res of the IGBT device, improving the softness of the switching characteristics of the IGBT device, avoiding the current oscillation problem, and improving the stability of the IGBT device.

[0061] Please refer to Figure 4 Step S01 is performed to provide a substrate 110. The substrate 110 is specifically a semiconductor substrate, and the material thereof includes but is not limited to silicon. The substrate 110 comprises a cell region 210; in addition, the substrate 110 can further comprise a termination region (not shown in the figure).

[0062] Next, refer to Figures 5 to 8 . As an optional implementation, step S02 specifically comprises: forming a first mask layer 120 on the substrate 110, the first mask layer 120 having a first opening 121 exposing a preset forming position of the first trench and a second opening 122 exposing a preset forming position of the second trench. It can be understood that, in order to form the first trench and the second trench with different cross-sectional areas, the opening areas of the first opening 121 and the second opening 122 are different. Specifically, the line widths of the first opening 121 and the second opening 122 are different (please refer to Figure 5 ).

[0063] In order to provide a fine pattern, the first mask layer 120 is, for example, a hard mask layer. The first opening 121 and the second opening 122 on the first mask layer 120 are formed, for example, through a photolithography and etching process. Specifically, a first mask layer 120 that has not yet been patterned can be formed on the substrate 110 first; then, a photoresist layer (not shown in the figure) is formed on the first mask layer 120; the photoresist layer is patterned through exposure and development; and then the first mask layer 120 is etched with the patterned photoresist layer as a mask, so as to form the first opening 121 and the second opening 122 on the first mask layer 120.

[0064] Next, refer to Figure 6 . A second mask layer 130 is formed on the first mask layer 120, the second mask layer 130 covering the second opening 122 and exposing the first opening 121. The second mask layer 130 is, for example, a photoresist layer. A first etching process is performed to form a first trench 111 extending from the surface of the substrate 110 to the inside of the substrate 110 at the position of the first opening 121. The first trench 111 is a trench for forming a first trench gate 151 in a subsequent process. The part of the substrate 100 located below the second opening 122 is not etched in the first etching process due to the protection of the second mask layer 130.

[0065] It can be understood that, although Figure 6 shows the case where the second mask layer 130 covers the second opening 122 and the opening area of the second opening 122 is greater than the opening area of the first opening 121, i.e., the second mask layer 130 covers the large opening and exposes the small opening; however, the present application is not limited thereto, and in actual processes, the second mask layer 130 can also be used to cover the small opening and expose the large opening in the first etching process.

[0066] Next, refer to Figure 7The second mask layer 130 is removed, and a third mask layer 140 is formed on the first mask layer 120. The third mask layer 140 covers the first opening 121 and exposes the second opening 122. The third mask layer 140 is, for example, a photoresist layer. In this way, the first trench 111 that has been etched is protected by removing the photoresist and re-coating the photoresist. Next, a second etching process is performed to form a second trench 112 extending from the surface of the substrate 110 to the interior of the substrate 110 at the position of the second opening 122.

[0067] Next, refer to Figure 8 The third mask layer 140 is removed. At this time, a plurality of trenches extending from the surface to the interior of the substrate 110 are formed in the cell region 210, such as the first trench 111 and the second trench 112. Because the opening areas of the first opening 121 and the second opening 122 formed in the first mask layer 120 are different, the cross-sectional areas of the first trench 111 and the second trench 112 formed after etching are also different. The ratio of the cross-sectional area of the first trench 111 to the cross-sectional area of the second trench 112 is in the range of 1:1.3 to 1:4. For example, the ratio of the cross-sectional area of the first trench 111 to the cross-sectional area of the second trench 112 is 1:2.

[0068] In a specific process, the cross-sectional areas of the first trench 111 and the second trench 112 are different, and specifically, the lengths of the first trench 111 and the second trench 112 are the same but the line widths are different. In this way, the design complexity is reduced, and the surface area of the substrate is saved.

[0069] It can be understood that the cell region 210 includes a plurality of repeating units 211, and each repeating unit 211 includes at least one first trench 111 and at least one second trench 112. The ratio of the number of first trenches 111 to the number of second trenches 112 in the cell region 210 is in the range of 10:7 to 10:13.

[0070] In Figures 5 to 8 In the embodiment shown, the first trench 111 and the second trench 112 are respectively formed by the first etching process and the second etching process twice; in this way, the problem that the formation depths of the first trench 111 and the second trench 112 are different caused by directly using the first mask layer 120 for etching and simultaneously forming the first trench 111 and the second trench 112 is avoided. By controlling the etching conditions of the first etching process and the second etching process, the etching depth of the first etching process is the same as the etching depth of the second etching process.

[0071] Next, refer to Figure 9. The first mask layer 120 is removed, and the gate material is filled in the plurality of trenches to form a first trench gate 151 in the first trench 111 and a second trench gate 152 in the second trench 112, and the first trench gate 151 and the second trench gate 152 are both used to connect to a gate potential. It can be understood that, in the embodiment of the present application, the first trench gate 151 and the second trench gate 152 are both gates of an IGBT, rather than a dummy gate; and the embodiment of the present application is an improvement on the device structure of the prior art which uses a plurality of trench gates with equal cross-sectional areas.

[0072] The formation of the first trench gate 151 and the second trench gate 152 can specifically include: first forming a gate dielectric layer on the inner walls of the first trench 111 and the second trench 112; the first gate dielectric layer 1511 formed in the first trench 111 and the second gate dielectric layer 1521 formed in the second trench 112 are shown in the figure; the material of the gate dielectric layer is, for example, silicon oxide; then, the gate material is filled to form a gate layer on the gate dielectric layer; the first gate layer 1512 formed on the first gate dielectric layer 1511 and the second gate layer 1522 formed on the second gate dielectric layer 1521 are shown in the figure; the gate material is, for example, polysilicon. In actual processes, a step of etching back can also be included to remove the excess gate dielectric layer material and gate material formed on the surface of the substrate 110.

[0073] The first gate dielectric layer 1511 and the first gate layer 1512 together form the first trench gate 151; and the second gate dielectric layer 1521 and the second gate layer 1522 together form the second trench gate 152.

[0074] Next, please refer to Figure 10 The method can also include: forming a base region 113 and a drift region 114 in the substrate 110. The base region 113 can be formed by a doping process such as ion implantation. In specific applications, the base region 113 can be a P-type region, and therefore the base region 113 can also be referred to as a P-well region. The drift region 114 can be an N-type region, and therefore the drift region 114 can also be referred to as an N-drift region; the substrate 110 is, for example, an N-type substrate, so that after the base region 113 is formed by the doping process, the remaining region forms the drift region 114.

[0075] The method can also include: forming a source region 115 on both sides of the first trench gate 151 and the second trench gate 152 in the base region 113. The source region 115 is, for example, an N-type region. The source region 115 is formed, for example, by a doping process such as ion implantation.

[0076] In order to ensure the depth of ion implantation and improve the effect of ion implantation, the method can also include performing annealing after ion implantation.

[0077] Next, please refer toFigure 11 The method can further include: forming an interlayer dielectric layer 160 (i.e., an ILD layer) on the upper surface of the substrate 110; and forming a contact hole 161 that penetrates the interlayer dielectric layer 160 and extends into the base region 113. The contact hole 161 exposes part of the surface of the source region 115 and the base region 113.

[0078] Next, refer to Fig. 2. Figure 12 The method can further include: forming a contact electrode 170 in the contact hole 161. Specifically, a metal material is deposited to form a metal layer that covers the upper surface of the interlayer dielectric layer 160 and fills the contact hole 161; the metal layer can form the emitter contact electrode 170 of the IGBT device.

[0079] Next, refer to Fig. 2. Figure 13 The method can further include: forming the collector 115 in the substrate 110. Specifically, a doping process such as ion implantation is performed on the lower surface of the substrate 110 to form the collector 115 in a region extending from the lower surface of the substrate 110 into the substrate 110. The collector 115 is disposed opposite the first trench gate 151 and the second trench gate 152 in a direction nominally parallel to the lateral surface of the substrate 110; in a direction perpendicular to the lateral surface of the substrate 110, the bottoms of the first trench gate 151 and the second trench gate 152 are directed toward the side of the collector 115 located inside the substrate 110.

[0080] Each trench gate 150 penetrates the base region 113 and extends into the drift region 114; that is, the bottom of each trench gate 150 is located in the drift region 114.

[0081] Next, refer to Table 1. Table 1 shows the simulation parameters obtained by simulating the specific example 1 and the comparative example 1. In the comparative example 1, the cell region of the IGBT device includes multiple trench gates, and the cross-sectional areas of the trench gates are equal, each equal to the cross-sectional area of the first trench gate in the specific example 1; in the specific example 1, the cell region of the IGBT device includes multiple trench gates, and half of the trench gates are first trench gates and the other half are second trench gates, the ratio of the cross-sectional area of the first trench gate to the cross-sectional area of the second trench gate is 1:2, and the first trench gates and the second trench gates are arranged in the manner shown in Fig. 1. The other aspects of the specific example 1 and the comparative example 1 are the same. Figure 1 It should be noted that the distance between adjacent two trench gates in the specific example 1 is equal; similarly, the distance between adjacent two trench gates in the comparative example 1 is also equal; the number of trench gates included in the cell region in the specific example 1 is equal to the number of trench gates included in the cell region in the comparative example 1.

[0082] It should be noted that the distance between adjacent two trench gates in the specific example 1 is equal; similarly, the distance between adjacent two trench gates in the comparative example 1 is also equal; the number of trench gates included in the cell region in the specific example 1 is equal to the number of trench gates included in the cell region in the comparative example 1.

[0083] [Table 1]

[0084]

[0085]

[0086] As can be seen from Table 1, the static parameters (threshold voltage V TH , breakdown voltage BV and conduction voltage drop V cesat ) of the specific example 1 and the comparative example 1 are basically equal, that is, the specific example 1 provided with the first trench gate and the second trench gate with different cross-sectional areas basically does not change the static parameters of the device. In this case, compared with the comparative example 1, the specific example 1 has a 7.67% decrease in turn-on delay time Td_on, an 11.93% increase in rise time Tr, a 2.83% increase in turn-off delay time Td_off, a 5.13% decrease in fall time Tf, a 2.21% increase in turn-on time Ton, a 2.33% increase in turn-off time Toff, a 4.75% increase in turn-on energy Eon, a 15.64% decrease in turn-off energy Eoff, a 7.48% decrease in switching loss Ets, a 5.62% decrease in input capacitance C ies , a 13.63% increase in output capacitance C oes , a 13.74% increase in feedback capacitance C res , and a 10.82% decrease in turn-on speed di / dt_A / us. In the art, the size of di / dt is generally used to reflect the switching softness of the device, and the smaller the value is, the less likely the oscillation occurs, and the more stable the device works.

[0087] As can be seen from Table 1, compared with the comparative example 1, the specific example 1 improves the feedback capacitance C res of the IGBT device, reduces the switching softness of the IGBT device, and also improves the switching loss Ets to a certain extent.

[0088] It is easy to understand that the deviation rate in Table 1 is equal to the corresponding parameter value of the specific example 1 minus the corresponding parameter value of the comparative example 1, divided by the corresponding parameter value of the comparative example 1, and multiplied by 100%.

[0089] It should be noted that the preparation method of the IGBT device provided in the embodiments of the present application belongs to the same concept as the IGBT device embodiments; the technical features in the technical solutions recorded in each embodiment can be combined arbitrarily without conflict. However, it should be further noted that the combination of technical features of the IGBT device provided in the embodiments of the present application can already solve the technical problems to be solved by the present application; thus, the IGBT device provided in the embodiments of the present application can not be limited by the preparation method of the IGBT device provided in the embodiments of the present application, and any IGBT device prepared by a preparation method that can form the structure of the IGBT device provided in the embodiments of the present application is within the scope of protection of the present application.

[0090] It should be understood that the above examples are exemplary and are not intended to limit the scope of the claims encompassing all possible embodiments. Various modifications and changes can be made thereto without departing from the scope of the present disclosure, which is set forth in the claims. Similarly, each of the individual features of the above examples can be combined with each other to form further embodiments of the present application, which can not be explicitly described. Therefore, the above examples merely express several embodiments of the present application, and do not limit the scope of the patent protection of the present application.

Claims

1. An IGBT device, characterized by, The IGBT device comprises a cell region, and a plurality of trench gates are arranged in the cell region, wherein The plurality of trench gates at least comprise a first trench gate and a second trench gate, a cross-sectional area of the first trench gate and a cross-sectional area of the second trench gate are different, and a depth of the first trench gate and a depth of the second trench gate are the same; the cross-sectional area refers to a sectional area in a direction perpendicular to a depth direction of the first trench gate or the second trench gate; The first trench gate and the second trench gate are both connected to a gate potential; A ratio of the cross-sectional area of the first trench gate to the cross-sectional area of the second trench gate is within a range of 1:1.3 to 1:4, and / or a ratio of a number of the first trench gates to a number of the second trench gates within the cell region is within a range of 10:7 to 10:

13.

2. The IGBT device of claim 1, wherein, A plurality of repeating units are included in the cell region, and each of the repeating units comprises at least one first trench gate and at least one second trench gate.

3. The IGBT device according to claim 1, wherein The cross-sectional area of the first trench gate and the cross-sectional area of the second trench gate are different, specifically, lengths of the first trench gate and the second trench gate are the same but line widths of the first trench gate and the second trench gate are different; The line widths of the first trench gate and the second trench gate are dimensions of the first trench gate and the second trench gate in a first direction, and the lengths of the first trench gate and the second trench gate are dimensions of the first trench gate and the second trench gate in a second direction; wherein the first direction and the second direction are two directions parallel to a first plane, and the first direction and the second direction are perpendicular to each other; and the first plane is a plane perpendicular to the depth direction of the first trench gate or the second trench gate.

4. A method of manufacturing an IGBT device, characterized by, The method comprises: providing a substrate, wherein the substrate comprises a cell region; forming a plurality of trenches extending from a surface of the substrate to an interior in the cell region, wherein the plurality of trenches at least comprise a first trench and a second trench, a cross-sectional area of the first trench and a cross-sectional area of the second trench are different, and a depth of the first trench and a depth of the second trench are the same; filling a gate material in the plurality of trenches to form a first trench gate in the first trench and a second trench gate in the second trench, wherein the first trench gate and the second trench gate are both used for being connected to a gate potential; the cross-sectional area refers to a sectional area in a direction perpendicular to a depth direction of the first trench gate or the second trench gate; wherein a ratio of the cross-sectional area of the first trench to the cross-sectional area of the second trench is within a range of 1:1.3 to 1:4, and / or a ratio of a number of the first trench gates to a number of the second trench gates within the cell region is within a range of 10:7 to 10:

13.

5. The method of claim 4, wherein the step of forming the IGBT device further comprises the step of: forming a plurality of trenches extending from a surface of the substrate to an interior in the cell region comprises: forming a first mask layer on the substrate, wherein the first mask layer has a first opening exposing a preset forming position of the first trench and a second opening exposing a preset forming position of the second trench; forming a second mask layer on the first mask layer, the second mask layer covering the second opening and exposing the first opening; performing a first etching process to form a first trench extending from a surface of the substrate to an interior of the substrate at a position of the first opening; removing the second mask layer and forming a third mask layer on the first mask layer, the third mask layer covering the first opening and exposing the second opening; performing a second etching process to form a second trench extending from the surface of the substrate to the interior of the substrate at a position of the second opening; wherein an etching depth of the second etching process is the same as an etching depth of the first etching process.

6. The method of manufacturing an IGBT device according to claim 5, wherein the first trench gate and the second trench gate have the same length but different line widths; the line width of the first trench gate and the second trench gate is a dimension of the first trench gate and the second trench gate in a first direction, and the length of the first trench gate and the second trench gate is a dimension of the first trench gate and the second trench gate in a second direction; wherein the first direction and the second direction are two directions which are nominally parallel to a lateral surface of the substrate, and the first direction and the second direction are perpendicular to each other.

7. A method of manufacturing an IGBT device, characterized by, The method comprises: providing a substrate, the substrate comprising a cell region thereon; forming a plurality of trenches extending from a surface to an interior of the substrate in the cell region, the plurality of trenches comprising at least a first trench and a second trench, a cross-sectional area of the first trench and a cross-sectional area of the second trench being different, and a depth of the first trench and a depth of the second trench being the same; filling a gate material in the plurality of trenches to form a first trench gate in the first trench and a second trench gate in the second trench, the first trench gate and the second trench gate both being configured to be connected to a gate potential; the cross-sectional area refers to a sectional area in a direction perpendicular to a depth direction of the first trench gate or the second trench gate; wherein forming a plurality of trenches extending from a surface to an interior of the substrate in the cell region comprises: forming a first mask layer on the substrate, the first mask layer having a first opening exposing a preset forming position of the first trench and a second opening exposing a preset forming position of the second trench; forming a second mask layer on the first mask layer, the second mask layer covering the second opening and exposing the first opening; performing a first etching process to form a first trench extending from a surface of the substrate to an interior of the substrate at a position of the first opening; removing the second mask layer and forming a third mask layer on the first mask layer, the third mask layer covering the first opening and exposing the second opening; performing a second etching process to form a second trench extending from the surface of the substrate to the interior of the substrate at a position of the second opening; wherein an etching depth of the second etching process is the same as an etching depth of the first etching process.

8. The method of fabricating an IGBT device according to claim 7, wherein, the first trench gate and the second trench gate have the same length but different line widths; the line width of the first trench gate and the second trench gate is a dimension of the first trench gate and the second trench gate in a first direction, and the length of the first trench gate and the second trench gate is a dimension of the first trench gate and the second trench gate in a second direction; wherein the first direction and the second direction are two directions which are nominally parallel to a lateral surface of the substrate, and the first direction and the second direction are perpendicular to each other. The line width of the first trench gate and the second trench gate is a dimension of the first trench gate and the second trench gate along a first direction, and the length of the first trench gate and the second trench gate is a dimension of the first trench gate and the second trench gate along a second direction; wherein the first direction and the second direction are two directions that are nominally parallel to a lateral surface of the substrate, and the first direction and the second direction are perpendicular to each other.

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