Silicon carbide junction barrier schottky diode

Abstract

This invention discloses a silicon carbide junction barrier Schottky diode, belonging to the field of semiconductor technology. It includes a silicon carbide substrate, an N+ buffer zone, an N+ drift region, a cell region, a termination region, an isolation layer, a cathode metal, an anode metal, and a passivation layer. The N+ buffer zone is located above the silicon carbide substrate and has a first epitaxial layer. The N+ drift region is located above the N+ buffer zone and has a second and a third epitaxial layer, with the second epitaxial layer covering the first and third epitaxial layers respectively. The cell region includes a P+ junction. The termination region is located above the N+ drift region and has a P+ field-limiting ring. A P+ transition region is located between the cell region and the termination region. The isolation layer covers the termination region. The passivation layer covers the isolation layer. The cathode metal covers the bottom of the silicon carbide substrate, and the anode metal is located above the N+ drift region. This diode has a low forward voltage drop and a high reverse breakdown voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a silicon carbide junction barrier Schottky diode. Background Technology

[0002] Currently, silicon carbide Schottky diodes (SBDs) offer advantages such as low forward voltage drop and fast turn-off speed, while silicon carbide pin diodes (PIN diodes) boast high withstand voltage and low leakage current. The silicon carbide junction barrier Schottky diode (JBS) combines the structures of SBDs and pin diodes, thus possessing the advantages of both. In traditional JBS designs, changing the area ratio of the pin region to the SBD region can increase or decrease the forward current and reverse leakage current simultaneously. However, this approach often results in a high forward voltage drop and a low reverse withstand voltage, affecting operational reliability. Therefore, providing a silicon carbide junction barrier Schottky diode with low forward voltage drop and high reverse withstand voltage has become a pressing issue. Summary of the Invention

[0003] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes a silicon carbide junction barrier Schottky diode, which features low forward voltage drop and high reverse breakdown voltage.

[0004] According to an embodiment of the present invention, a silicon carbide junction barrier Schottky diode includes:

[0005] silicon carbide substrate;

[0006] An N+ buffer is located above the silicon carbide substrate, and the N+ buffer is provided with a first epitaxial layer;

[0007] The N+ drift region is located above the N+ buffer zone. The N+ drift region is provided with a second epitaxial layer and a third epitaxial layer, wherein the second epitaxial layer covers the first epitaxial layer and the third epitaxial layer covers the second epitaxial layer.

[0008] A cell region, located above the N+ buffer zone and the N+ drift region, the cell region including a P+ junction;

[0009] A terminal area is located above the N+ drift area, and a P+ field limiting loop is provided on the terminal area;

[0010] The P+ transition region is located between the cell region and the terminal region;

[0011] An isolation layer that covers the terminal area;

[0012] A passivation layer, which covers the isolation layer;

[0013] A cathode metal, which covers the silicon carbide substrate and forms an ohmic contact with the silicon carbide substrate;

[0014] The anode metal is located above the N+ drift region and forms an ohmic contact with the P+ junction. The anode metal also forms a Schottky contact with the third epitaxial layer.

[0015] The silicon carbide junction barrier Schottky diode according to embodiments of the present invention has at least the following beneficial effects: This silicon carbide junction barrier Schottky diode includes a silicon carbide substrate, an N+ buffer zone, an N+ drift region, a cell region, a termination region, an isolation layer, a passivation layer, a cathode metal, and an anode metal; the N+ buffer zone is located above the silicon carbide substrate and has a first epitaxial layer; the N+ drift region is located above the N+ buffer zone and has a second epitaxial layer and a third epitaxial layer, wherein the second epitaxial layer covers the first epitaxial layer, and the third epitaxial layer covers the second epitaxial layer. On the epitaxial layer, the cell region is located above the N+ buffer and N+ drift regions, and includes a P+ junction; the termination region is located above the N+ drift region, with a P+ field-limiting ring on the termination region; the P+ transition region is located between the cell region and the termination region; an isolation layer covers the termination region; a passivation layer covers the isolation layer; a cathode metal covers the silicon carbide substrate, forming an ohmic contact with the silicon carbide substrate; the anode metal is located above the N+ drift region, forming an ohmic contact with the P+ junction, and also forming a Schottky contact with the third epitaxial layer. This silicon carbide junction barrier Schottky diode, by setting a first, second, and third epitaxial layer, can increase the forward current and reduce the forward voltage drop of the diode. Simultaneously, the increased forward current capability can also reduce the area of ​​the JBS Schottky contact region, achieving a higher breakdown voltage than conventional JBS technology, thus resolving the contradiction between the high reverse breakdown voltage and low forward voltage drop requirements of JBS devices.

[0016] According to some embodiments of the present invention, the isolation layer is a silicon oxide isolation layer.

[0017] According to some embodiments of the present invention, the passivation layer comprises:

[0018] A nitride passivation layer covers the silicon oxide isolation layer.

[0019] A polyimide passivation layer, which covers the nitride passivation layer.

[0020] According to some embodiments of the present invention, the thickness of the third epitaxial layer is between 0.2 μm and 0.7 μm.

[0021] According to some embodiments of the present invention, the doping concentration of the third epitaxial layer is greater than that of the second epitaxial layer, and the doping concentration of the third epitaxial layer is less than that of the first epitaxial layer.

[0022] According to some embodiments of the present invention, the P+ field confinement ring, the P+ transition region, and the P+ junction are formed by multiple P-ion implantations.

[0023] According to some embodiments of the present invention, the terminal region includes an etched region for forming the etched region by etching the third epitaxial layer.

[0024] According to some embodiments of the present invention, the anode metal is composed of titanium and aluminum.

[0025] According to some embodiments of the present invention, the cathode metal is composed of titanium, silver and nickel.

[0026] According to some embodiments of the present invention, the thickness of the silicon carbide substrate is less than or equal to 150 μm.

[0027] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0028] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein:

[0029] Figure 1 This is a schematic diagram of the structure of a silicon carbide junction barrier Schottky diode according to an embodiment of the present invention;

[0030] Figure 2 This is another structural schematic diagram of a silicon carbide junction barrier Schottky diode according to an embodiment of the present invention.

[0031] Reference numerals: 101, silicon carbide substrate; 102, first epitaxial layer; 103, second epitaxial layer; 104, third epitaxial layer; 105, P+ field confinement ring; 106, P+ transition region; 107, P+ junction; 108, termination region; 109, silicon oxide isolation layer; 110, nitride passivation layer; 111, polyimide passivation layer; 112, cathode metal; 113, anode metal; 114, etched region. Detailed Implementation

[0032] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0033] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0034] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0035] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0036] In the description of this invention, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0037] Reference Figure 1 and Figure 2 ,in, Figure 2 for Figure 1The cross-sectional view at point A shows that the silicon carbide junction barrier Schottky diode of this embodiment includes a silicon carbide substrate 101, an N+ buffer zone, an N+ drift region, a cell region, a termination region 108, an isolation layer, a passivation layer, a cathode metal 112, and an anode metal 113. The N+ buffer zone is located above the silicon carbide substrate 101 and has a first epitaxial layer 102. The N+ drift region is located above the N+ buffer zone and has a second epitaxial layer 103 and a third epitaxial layer 104, wherein the second epitaxial layer 103 covers the first epitaxial layer 102, and the third epitaxial layer 104 covers the second epitaxial layer 103. The cell region is located between the N+ buffer zone and the N+ drift region. Above the N+ drift region, the cell region includes a P+ junction 107; the terminal region 108 is located above the N+ drift region, and a P+ field limiting ring 105 is provided on the terminal region 108; a P+ transition region 106 is located between the cell region and the terminal region 108; an isolation layer covers the terminal region 108; a passivation layer covers the isolation layer; a cathode metal 112 covers the silicon carbide substrate 101 below, and the cathode metal 112 forms an ohmic contact with the silicon carbide substrate 101; an anode metal 113 is located above the N+ drift region, and the anode metal 113 forms an ohmic contact with the P+ junction 107, and the anode metal 113 also forms a Schottky contact with the third epitaxial layer 104. For example, a silicon carbide junction barrier Schottky diode includes a silicon carbide substrate 101, an N+ buffer zone located above the silicon carbide substrate 101, a first epitaxial layer 102 disposed in the N+ buffer zone, and a second epitaxial layer 103 and a third epitaxial layer 104 disposed in the N+ drift region. The second epitaxial layer 103 covers the first epitaxial layer 102, and the third epitaxial layer 104 covers the second epitaxial layer 103. The third epitaxial layer 104 is made of N-type silicon carbide. An aluminum ion-implanted P+ junction 107 is located at... In the cell region, a P+ field-limiting ring 105 is located in the termination region 108. A silicon oxide isolation layer 109 covers the termination region 108, and an anode metal 113 covers the cell region, extending onto the silicon oxide isolation layer 109. A silicon nitride passivation layer covers the silicon oxide isolation layer 109 and part of the anode metal 113, and a polyimide passivation layer 111 covers the silicon nitride passivation layer and part of the anode metal 113. A cathode metal 112 covers the silicon carbide substrate 101. This silicon carbide junction barrier Schottky diode, by setting a first epitaxial layer 102, a second epitaxial layer 103, and a third epitaxial layer 104, can increase the forward current and reduce the forward voltage drop of the diode. Simultaneously, the increased forward current capability can also reduce the area of ​​the JBS Schottky contact region, achieving a higher breakdown voltage than conventional JBS technology, thus resolving the contradiction between the high reverse breakdown voltage and low forward voltage drop requirements of JBS devices.

[0038] In some embodiments, the silicon carbide substrate 101 is made of highly doped silicon carbide containing nitrogen. After the anode process is completed, the silicon carbide substrate 101 needs to be thinned so that the thickness of the silicon carbide substrate 101 is less than or equal to 150 μm. For example, the thickness of the silicon carbide substrate 101 after the thinning process is 125 μm, and the doping concentration of the silicon carbide substrate 101 is 1E. 19 cm -3 .

[0039] In some embodiments, the thickness of the third epitaxial layer 104 is between 0.2 μm and 0.7 μm. The doping concentration of the third epitaxial layer 104 is greater than that of the second epitaxial layer 103, and less than that of the first epitaxial layer 102. Specifically, the first epitaxial layer 102 is a buffer layer made of highly doped silicon carbide containing nitrogen. Both the second epitaxial layer 103 and the third epitaxial layer 104 are drift layers. Depending on the voltage withstand requirements of the drift region, the second epitaxial layer 103 can be set between 4 μm and 20 μm, and the thickness of the third epitaxial layer 104 can be between 0.2 μm and 0.7 μm. Simultaneously, the doping concentration of the third epitaxial layer 104 is set between the doping concentration of the second epitaxial layer 103 and the doping concentration of the first epitaxial layer 102. For example, the doping concentration of the first epitaxial layer 102 is 1E. 18 cm -3 The thickness of the first epitaxial layer 102 is 1 μm. The doping concentration of the second epitaxial layer 103 is 2E. 16 cm -3 The thickness of the second epitaxial layer 103 is 5.5 μm. The doping concentration of the third epitaxial layer 104 is 5E. 17 cm -3 The thickness of the third epitaxial layer 104 is 0.3 μm. The third epitaxial layer 104 provides more electrons into the anode metal 113 below the Schottky contact compared to the second epitaxial layer 103, increasing the forward current. The light doping of the second epitaxial layer 103 also provides a greater breakdown voltage for the silicon carbide junction barrier Schottky diode, effectively reducing the reverse leakage current and improving the reverse breakdown voltage.

[0040] In some embodiments, the terminal region 108 includes an etched region 114, which is formed by etching the third epitaxial layer 104. Specifically, the etched region 114 is formed by etching the third epitaxial layer 104 of the terminal region 108, the etching depth is approximately equal to the thickness of the third epitaxial layer 104, the etching morphology angle is 15° to 45°, and the etching range is the implantation region of the P+ field confinement ring 105. For example, etching the third epitaxial layer 104 in the terminal region 108 to form an etched region 114 with an etching depth of 0.35 μm allows the P+ field limiting ring 105 to be implanted onto the second epitaxial layer 103 with a lower doping concentration. This avoids the reduction in terminal breakdown voltage caused by the high concentration of N-type doping in the third epitaxial layer 104 of the terminal region 108, and can improve the breakdown voltage capability of the silicon carbide junction barrier Schottky diode.

[0041] In some embodiments, the P+ field confinement ring 105, the P+ transition region 106, and the P+ junction 107 are formed through multiple P-ion implantations. Specifically, the P+ junction 107, the P+ transition region 106, and the P+ field confinement ring 105 can be implanted simultaneously or separately. A multi-step implantation method can be used to achieve a box-shaped implantation concentration distribution. In some specific embodiments, the implanted impurity is aluminum. The aluminum doping concentration of the P+ junction 107 in the cell region is much greater than the nitrogen doping concentration of the epitaxial layers (i.e., the first epitaxial layer 102, the second epitaxial layer 103, and the third epitaxial layer 104), therefore, the implanted region exhibits the characteristics of a P-type semiconductor. The depth of the P+ junction 107 in the cell region exceeds the thickness of the third epitaxial layer 104, and the bottom of the P+ junction 107 is within the second epitaxial layer 103. The P+ field confinement ring 105 is implanted onto the second epitaxial layer 103 exposed after etching. For example, the P+ junction 107, the P+ field-limiting ring 105, and the P+ transition region 106 are formed through a four-step ion implantation and high-temperature annealing. The depth of the P+ junction 107 is 1.3 μm, and the concentration of the P+ junction 107 is 1E. 18 To 1E 20 cm -3 The ion implantation process employed a silicon oxide mask and was performed at a high temperature of 450°C. The width of the P+ junction 107 was 1.1 μm, and the void area ratio between P+ junctions 107 was 1:1. The width of the P+ transition region 106 was 20 μm. There were 13 P+ field limiting rings 105, each with a width of 3.5 μm. The initial spacing of the P+ field limiting rings 105 was 1 μm, increasing in increments of 0.1 μm. After ion implantation of the P+ field limiting rings 105, P+ transition region 106, and P+ junctions 107, they were protected with a carbon film and annealed for 25 minutes at 1800°C in an argon atmosphere. This method improves the electric field distribution at the terminal, resolves the edge effect of the P+ junction 107, and brings the diode breakdown voltage close to the ideal voltage.

[0042] In some embodiments, the anode metal 113 is composed of titanium and aluminum. Specifically, the anode uses titanium to form a Schottky contact with the third epitaxial layer 104 and an ohmic contact with the P+ junction 107. Simultaneously, aluminum is plated on the surface of the titanium, forming the anode metal 113 through the titanium and aluminum. For example, the anode metal 113 is composed of titanium and aluminum from the inside out, with the titanium plating... After rapid annealing at 450°C for 2 minutes, an ohmic contact is formed with the P+ junction 107, and a Schottky contact is formed with the third epitaxial layer 104 in the gap between the P+ junction 107. Then, 3µm of aluminum metal is plated to form the anode metal 113.

[0043] In some embodiments, the cathode metal 112 is composed of titanium, silver, and nickel. Specifically, the cathode uses nickel as the ohmic contact metal to form an ohmic contact with the silicon carbide substrate 101. Titanium, nickel, and silver are sequentially plated onto the surface of the nickel metal, and the cathode metal 112 is obtained by metallizing the cathode through titanium, silver, and nickel. For example, after thinning the silicon carbide substrate 101, nickel is plated onto the cathode. After annealing at 970℃ for 2 minutes to form ohmic contacts, then sequentially plating... Finally, cathode metal 112 is formed.

[0044] In some embodiments, the isolation layer is a silicon oxide isolation layer 109. An isolation layer is formed by covering the terminal region 108 with silicon oxide, and the silicon oxide isolation layer 109 can protect the diode.

[0045] In some embodiments, the passivation layer includes a nitride passivation layer 110 and a polyimide passivation layer 111, with the nitride passivation layer 110 covering the silicon oxide isolation layer 109. The polyimide passivation layer 111 covers the nitride passivation layer 110. Specifically, the terminal region 108 is passivated by depositing silicon nitride, thereby covering the silicon oxide isolation layer 109. Then, a second passivation is performed by depositing polyimide, thereby covering the nitride passivation layer 110. For example, silicon nitride is deposited. A silicon nitride passivation layer is then formed by photolithography. A 3-5µm polyimide layer is deposited and then photolithographically formed to form a polyimide passivation layer 111, which protects the diode.

[0046] This silicon carbide junction barrier Schottky diode, by incorporating a first, second, and third epitaxial layer, can increase the forward current and reduce the forward voltage drop. Simultaneously, the increased forward current capability also reduces the area of ​​the JBS Schottky contact region, achieving a higher breakdown voltage than conventional JBS diodes, thus resolving the contradiction between the high reverse withstand voltage and low forward voltage drop requirements of JBS devices. Comparative verification shows that, compared to conventional two-layer epitaxial 650V silicon carbide junction barrier Schottky diodes, the silicon carbide junction barrier Schottky diode of this application can reduce the forward voltage drop by 7.5% and increase the breakdown voltage by 10.5% at the same design current while maintaining the same design area and reverse leakage characteristics. Therefore, it can be determined that the silicon carbide junction barrier Schottky diode of this application has a lower forward voltage drop and a higher reverse withstand voltage, which can significantly improve operational reliability.

[0047] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments, and various changes can be made within the scope of knowledge possessed by those skilled in the art without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof can be combined with each other unless otherwise specified.

Claims

1. A silicon carbide junction barrier Schottky diode characterized by, The application relates to a silicon carbide (SiC) power device, comprising: a silicon carbide substrate with a thickness less than or equal to 150 um; an N+ buffer zone above the silicon carbide substrate, the N+ buffer zone being provided with a first epitaxial layer; an N+ drift zone above the N+ buffer zone, the N+ drift zone being provided with a second epitaxial layer and a third epitaxial layer, wherein the second epitaxial layer is covered on the first epitaxial layer, the third epitaxial layer is covered on the second epitaxial layer, the thickness of the second epitaxial layer is between 4 um and 20 um, the thickness of the third epitaxial layer is between 0.2 um and 0.7 um, the doping concentration of the third epitaxial layer is greater than the doping concentration of the second epitaxial layer, and the doping concentration of the third epitaxial layer is less than the doping concentration of the first epitaxial layer; a cell zone above the N+ buffer zone and the N+ drift zone, the cell zone comprising a P+ junction; a terminal zone above the N+ drift zone, the terminal zone being provided with a P+ field limiting ring, the terminal zone comprising an etching zone, the etching zone being formed by etching the third epitaxial layer, the etching depth of the etching zone being equal to the thickness of the third epitaxial layer, the angle of the etching profile being 15 DEG to 45 DEG, and the etching range being the injection area of the P+ field limiting ring; a P+ transition zone between the cell zone and the P+ field limiting ring and above the etching zone; an isolation layer above the terminal zone; a passivation layer above the isolation layer; a cathode metal below the silicon carbide substrate, the cathode metal forming an ohmic contact with the silicon carbide substrate; an anode metal above the N+ drift zone, the anode metal forming an ohmic contact with the P+ junction and a Schottky contact with the third epitaxial layer.

2. The silicon carbide junction barrier Schottky diode of claim 1, wherein, The isolation layer is a silicon oxide isolation layer.

3. The silicon carbide junction barrier Schottky diode of Claim 2 wherein, The passivation layer comprises: a nitride passivation layer above the silicon oxide isolation layer; a polyimide passivation layer above the nitride passivation layer.

4. The silicon carbide junction barrier Schottky diode of claim 3, wherein the first and second epitaxial layers are doped with a first conductivity type and the drift layer is doped with a second conductivity type opposite the first conductivity type. The P+ field limiting ring, the P+ transition zone and the P+ junction are formed by multiple aluminum ion implantations.

5. The silicon carbide junction barrier Schottky diode of Claim 4, wherein the metal layer is nickel. The anode metal is composed of titanium metal and aluminum metal.

6. The silicon carbide junction barrier Schottky diode of Claim 5, wherein the p-type layer is formed by implanting boron into the n-type drift layer. The cathode metal is composed of titanium metal, silver metal and nickel metal.

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