Camera device

Abstract

The imaging device of the present disclosure includes: a first switch coupling a first light receiving device and a first charge accumulation unit to each other, a second switch coupling a predetermined node and the first charge accumulation unit to each other, a third switch applying a predetermined voltage to the predetermined node, a fourth switch coupling a second light receiving device and a second charge accumulation unit to each other, a fifth switch coupling the second charge accumulation unit and the predetermined node to each other, an output unit outputting a pixel voltage, a driving unit, and a processor determining first to fourth values. The driving unit turns on the second and third switches and turns off the first, fourth, and fifth switches in a first period, turns off the third switch and turns on the fifth switch in a second period, turns on the fourth switch in a third period, and turns off the fourth switch in a fourth period. The processor determines the third value based on the pixel voltages in the second and fourth periods.

Description

Technical Field

[0001] The present disclosure relates to an image pickup apparatus that performs an image pickup operation and an image pickup method used in such an image pickup apparatus. Background Art

[0002] In an image pickup device, a wider dynamic range is desired. For example, Patent Document 1 discloses an image pickup device including a photodiode and a storage capacitor that accumulates photoelectric charges overflowing from the photodiode and expands the dynamic range.

[0003] Citation list

[0004] Patent Literature

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2005-328493. Summary of the invention

[0006] In an image pickup apparatus, it is desired that a captured image have a higher image quality, and further improvement in the image quality is desired.

[0007] It is desirable to provide an imaging device and an imaging method capable of improving the image quality of captured images.

[0008] The camera device according to the embodiment of the present disclosure includes: a first light receiving device and a second light receiving device; a first charge accumulation unit and a second charge accumulation unit; a first switch; a second switch; a third switch; a fourth switch; a fifth switch; an output unit; a driving unit; and a processor. The first switch couples the first light receiving device and the first charge accumulation unit to each other by being placed in an on state. The second switch couples a predetermined node and the first charge accumulation unit to each other by being placed in an on state. The third switch applies a predetermined voltage to a predetermined node by being placed in an on state. The fourth switch couples the second light receiving device and the second charge accumulation unit to each other by being placed in an on state. The fifth switch couples the second charge accumulation unit and the predetermined node to each other by being placed in an on state. The driving unit drives each switch. The processor determines a first value, a second value, a third value, and a fourth value based on a pixel voltage, and generates a pixel value based on these values. In a first period, the driving unit places the second switch and the third switch in an on state, and places the first switch, the fourth switch, and the fifth switch in an off state. In a second period after the first period, the driving unit places the third switch in an off state, and places the fifth switch in an on state. The driving section turns the fourth switch on in a third period after the second period, and turns the fourth switch off in a fourth period after the third period. The processor determines a third value based on the pixel voltage in the second period and the pixel voltage in the fourth period.

[0009] The imaging method according to the embodiment of the present disclosure includes: driving each switch of an imaging pixel, the imaging pixel including a first light receiving device and a second light receiving device, a first charge accumulation unit and a second charge accumulation unit, a first switch, a second switch, a third switch, a fourth switch, a fifth switch and an output unit, the first switch being placed in an on state to couple the first light receiving device and the first charge accumulation unit to each other, the second switch being placed in an on state to couple a predetermined node and the first charge accumulation unit to each other, the third switch being placed in an on state to apply a predetermined voltage to a predetermined node, the fourth switch being placed in an on state to couple the second light receiving device and the second charge accumulation unit to each other, the fifth switch being placed in an on state to couple the first light receiving device and the first charge accumulation unit to each other, The two charge accumulation parts are coupled to a predetermined node, and the output part outputs a pixel voltage corresponding to the voltage in the first charge accumulation part; a first value, a second value, a third value and a fourth value are determined based on the pixel voltage; in a first time period, the second switch and the third switch are placed in an on state, and the first switch, the fourth switch and the fifth switch are placed in an off state; in a second time period after the first time period, the third switch is placed in an off state, and the fifth switch is placed in an on state; in a third time period after the second time period, the fourth switch is placed in an on state; in a fourth time period after the third time period, the fourth switch is placed in an off state; and a third value is determined based on the pixel voltage in the second time period and the pixel voltage in the fourth time period.

[0010] In the camera device and the camera method according to the embodiment of the present disclosure, in the first time period, the second switch and the third switch are placed in the on state, and the first switch, the fourth switch and the fifth switch are placed in the off state. In the second time period after the first time period, the third switch is placed in the off state, and the fifth switch is placed in the on state. In the third time period after the second time period, the fourth switch is placed in the on state, and in the fourth time period after the third time period, the fourth switch is placed in the off state. Then, the third value is determined based on the pixel voltage in the second time period and the pixel voltage in the fourth time period. Then, the pixel value is generated based on the first value, the second value, the third value and the fourth value.

[0011] According to the camera device and the camera method of the embodiment of the present disclosure, in the first period, the second switch and the third switch are placed in the on state, and the first switch, the fourth switch and the fifth switch are placed in the off state; in the second period after the first period, the third switch is placed in the off state, and the fifth switch is placed in the on state; in the third period after the second period, the fourth switch is placed in the on state; and in the fourth period after the third period, the fourth switch is placed in the off state, and the third value is determined based on the pixel voltage in the second period and the pixel voltage in the fourth period. This makes it possible to improve the image quality of the captured image. It should be noted that the effects described here are not restrictive, but can be any effect described in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a configuration diagram showing a configuration example of an image pickup device according to an embodiment of the present disclosure.

[0013] Figure 2 It shows Figure 1 A block diagram showing an example of the configuration of a readout unit shown.

[0014] Figure 3 It shows Figure 1 A timing waveform diagram showing an example of the operation of the imaging device shown.

[0015] Figure 4A It shows Figure 1 Another timing waveform diagram of the operation example of the imaging device shown.

[0016] Figure 4B It shows Figure 1 Another timing waveform diagram of the operation example of the imaging device shown.

[0017] Figure 5A It shows Figure 1 A circuit diagram showing the operating state of an imaging pixel.

[0018] Figure 5B It shows Figure 1 A circuit diagram of another operating state of the camera device shown.

[0019] Figure 5C It shows Figure 1 A circuit diagram of another operating state of the camera device shown.

[0020] Figure 6 It shows Figure 1 An explanatory diagram of an operation example of the imaging device shown.

[0021] Figure 7 It shows Figure 1 Characteristic diagram showing an example of characteristics of an imaging device shown.

[0022] Figure 8 is a timing waveform chart showing an operation example of the image pickup device according to the comparative example.

[0023] Fig. 9A is another timing waveform chart showing an operation example of the image pickup device according to the comparative example.

[0024] Fig. 9B is another timing waveform chart showing an operation example of the image pickup device according to the comparative example.

[0025] Fig.10 is an explanatory diagram showing an operation example of the image pickup device according to the comparative example.

[0026] Fig.11 is a characteristic diagram showing a characteristic example of an image pickup device according to a comparative example.

[0027] Fig.12 : is a timing waveform chart showing an operation example of the image pickup device according to the modification.

[0028] Fig.13 : is an explanatory diagram showing an operation example of the image pickup device according to the modification. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0030] <Example>

[0031] [Construction example]

[0032] Figure 1 An example of the construction of an image pickup device (image pickup device 1) according to an embodiment is shown. The image pickup device 1 is a so-called CMOS image sensor manufactured using a process for manufacturing a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit. It should be noted that the image pickup method according to the embodiment of the present disclosure is implemented by this embodiment and will therefore be described together. The image pickup device 1 includes a pixel array 11, a scanner 12, a readout section 20, a signal processor 14, and a controller 15.

[0033] The pixel array 11 includes a plurality of imaging pixels 10 arranged in a matrix. The pixel array 11 includes a plurality of control lines TGLL, a plurality of control lines FDGL, a plurality of control lines RSTL, a plurality of control lines FCGL, a plurality of control lines TGSL, a plurality of control lines SELL, and a plurality of signal lines SGL. The control lines TGLL are arranged in the horizontal direction ( Figure 1 The control line FDGL extends in the horizontal direction, and the signal SFDG is applied to the control line FDGL via the scanner 12. The control line RSTL extends in the horizontal direction, and the signal SRST is applied to the control line RSTL via the scanner 12. The control line FCGL extends in the horizontal direction, and the signal SFCG is applied to the control line FCGL via the scanner 12. The control line TGSL extends in the horizontal direction, and the signal STGS is applied to the control line TGSL via the scanner 12. The control line SELL extends in the horizontal direction, and the signal SSEL is applied to the control line SELL via the scanner 12. The signal line SGL extends in the vertical direction ( Figure 1 Extends in the longitudinal direction) and is coupled to the read-out portion 20.

[0034] Each imaging pixel 10 includes a photodiode PD1, a transistor TGL, a photodiode PD2, a transistor TGS, a capacitor FC, transistors FCG, RST and FDG, a floating diffusion FD, and transistors AMP and SEL. In this example, transistors TGL, TGS, FCG, RST, FDG, AMP and SEL are N-type MOS transistors.

[0035] The photodiode PD1 is a photoelectric converter that generates and accumulates charges having an amount corresponding to the amount of light received. The light receiving area of ​​the photodiode PD1 capable of receiving light is larger than the light receiving area of ​​the photodiode PD2 capable of receiving light. The anode of the photodiode PD1 is grounded, and the cathode is coupled to the source of the transistor TGL.

[0036] The transistor TGL has a gate coupled to the control line TGLL, a source coupled to the cathode of the photodiode PD1 , and a drain coupled to the floating diffusion FD.

[0037] The photodiode PD2 is a photoelectric converter that generates and accumulates charges having an amount corresponding to the amount of light received. The light receiving area of ​​the photodiode PD2 capable of receiving light is smaller than the light receiving area of ​​the photodiode PD1 capable of receiving light. The anode of the photodiode PD2 is grounded, and the cathode is coupled to the source of the transistor TGS.

[0038] The gate of the transistor TGS is coupled to the control line TGSL, the source is coupled to the cathode of the photodiode PD2 , and the drain is coupled to one end of the capacitor FC and the source of the transistor FCG.

[0039] One end of the capacitor FC is coupled to the drain of the transistor TGS and the source of the transistor FCG, and the other end is supplied with the power supply voltage VDD.

[0040] The gate of the transistor FCG is coupled to the control line FCGL, the source is coupled to one end of the capacitor FC and the drain of the transistor TGS, and the drain is coupled to the source of the transistor RST and the drain of the transistor FDG.

[0041] The gate of the transistor RST is coupled to the control line RSTL, the drain is supplied with the power supply voltage VDD, and the source is coupled to the drains of the transistors FCG and FDG.

[0042] The gate of the transistor FDG is coupled to the control line FDGL, the drain is coupled to the source of the transistor RST and the drain of the transistor FCG, and the source is coupled to the floating diffusion.

[0043] The floating diffusion FD accumulates charges supplied from the photodiodes PD1 and PD2 , and is configured by using, for example, a diffusion layer formed on the surface of a semiconductor substrate. Figure 1The floating diffusion FD is shown using a capacitor symbol.

[0044] The transistor AMP has a gate coupled to the floating diffusion FD, a drain supplied with the power supply voltage VDD, and a source coupled to the drain of the transistor SEL.

[0045] The transistor SEL has a gate coupled to the control line SELL, a drain coupled to the source of the transistor AMP, and a source coupled to the signal line SGL.

[0046] By the described construction, in the imaging pixel 10, the transistor SEL is placed in an on state based on the signal SSEL applied to the control line SELL, thereby electrically coupling the imaging pixel 10 to the signal line SGL. Therefore, the transistor AMP is coupled to the current source 23 (described later) of the readout section 20, and functions as a so-called source follower. Then, the imaging pixel 10 outputs a pixel voltage VP corresponding to the voltage in the floating diffusion section FD as a signal SIG to the signal line SGL. Specifically, as described below, the imaging pixel 10 sequentially outputs seven pixel voltages VP (VP to VP7) in seven periods (conversion periods P1 to P7) within the so-called horizontal period H.

[0047] The scanner 12 sequentially drives a plurality of imaging pixels 10 in units of a single row of imaging pixels 10 based on an instruction from the controller 15, and is constructed by using, for example, a shift register. It should be noted that this is not restrictive, and, for example, an address decoder may be used instead. The scanner 12 applies a signal STGL to a plurality of control lines TGLL, a signal SFDG to a plurality of control lines FDGL, a signal SRST to a plurality of control lines RSTL, a signal SFCG to a plurality of control lines FCGL, a signal STGS to a plurality of control lines TGSL, and a signal SSEL to a plurality of control lines SELL, thereby driving a row of imaging pixels 10.

[0048] The readout section 20 performs AD (Analog-to-Digital) conversion based on the signal SIG supplied from the pixel array 11 through the signal line SGL to generate a digital value (count value CNT).

[0049] Figure 2 FIG. 2 shows a configuration example of the readout section 20. It should be noted that, in addition to the readout section 20, Figure 2 A controller 15 and a signal processor 14 are also shown.

[0050] The readout section 20 includes a readout controller 28 , a reference signal generator 29 , and a plurality of AD (Analog-to-Digital) converters ADC.

[0051] The readout controller 28 controls the readout operation in the readout section 20 based on the instruction from the controller 15. Specifically, the readout controller 28 supplies a control signal to the reference signal generator 29, thereby causing the reference signal generator 29 to generate a reference signal REF (described below). In addition, the readout controller 28 supplies a clock signal CLK and a control signal CC to a plurality of AD converters ADC, thereby controlling the A / D conversion operations in the plurality of AD converters ADC.

[0052] The reference signal generator 29 generates a reference signal REF based on an instruction from the readout controller 28. As described below, the reference signal REF has a so-called ramp waveform in which a voltage level gradually decreases over time in seven periods (conversion periods P1 to P7).

[0053] Each AD converter ADC performs AD conversion based on a signal SIG supplied from the pixel array 11 through a signal line SGL to convert a pixel voltage VP into a digital value (count value CNT). A plurality of AD converters ADC corresponding to the plurality of signal lines SGL of the pixel array 11 are provided.

[0054] Each AD converter ADC has capacitors 21 and 22, a current source 23, a comparator 24 and a counter 25. One end of the capacitor 21 is provided with a reference signal REF, and the other end is coupled to the positive input terminal of the comparator 24. One end of the capacitor 22 is coupled to the signal line SGL and the other end is coupled to the negative input terminal of the comparator 24. The current source 23 allows a current with a predetermined current value to flow from the signal line SGL to the ground. The positive input terminal of the comparator 24 is provided with a reference signal REF through the capacitor 21, and the negative input terminal is provided with a signal SIG through the capacitor 22. Subsequently, the comparator 24 compares the input voltage at the positive input terminal and the input voltage at the negative input terminal, and outputs the comparison result as a signal CMP. The counter 25 performs a counting operation based on the signal CMP, the clock signal CLK and the control signal CC. Specifically, the readout controller 28 starts to generate the clock signal CLK, so that the counter 25 starts counting the clock pulses in the clock signal CLK and increments the count value CNT. Then, the counter 25 terminates the counting operation based on the signal CMP provided from the comparator 24. Furthermore, the counter 25 resets the count value CNT based on the control signal CC.

[0055] By the configuration, in the readout section 20, each AD converter ADC performs AD conversion based on the signal SIG and outputs a count value CNT. Specifically, each AD converter ADC performs AD conversion based on seven pixel voltages VP1 to VP7 included in the signal SIG in seven conversion periods P1 to P7, and outputs seven count values ​​CNT (count values ​​CNT1 to CNT7).

[0056] The signal processor 14 performs predetermined signal processing based on the count value CNT provided from the readout section 20, and outputs the signal processing result as an image signal DATA. Specifically, the signal processor 14 generates four images PIC (images PIC1, PIC2, ​​PIC3, and PIC4) based on the seven count values ​​CNT1 to CNT7 provided from the readout section 20. Then, the signal processor 14 synthesizes the four images PIC to generate one captured image PICA. Subsequently, the signal processor 14 outputs the captured image PICA as the image signal DATA. Therefore, in the image pickup device 1, the dynamic range can be expanded as described below.

[0057] The controller 15 supplies control signals to the scanner 12 , the readout section 20 , and the signal processor 14 , and controls the operations of these circuits, thereby controlling the operations of the imaging device 1 .

[0058] Here, the photodiode PD1 corresponds to a specific example of a “first light receiving device” of the present disclosure. The photodiode PD2 corresponds to a specific example of a “second light receiving device” of the present disclosure. The floating diffusion portion FD corresponds to a specific example of a “first charge accumulation portion” of the present disclosure. The capacitor FC corresponds to a specific example of a “second charge accumulation portion” of the present disclosure. The transistor TGL corresponds to a specific example of a “first switch” of the present disclosure. The transistor FDG corresponds to a specific example of a “second switch” of the present disclosure. The transistor RST corresponds to a specific example of a “third switch” of the present disclosure. The transistor TGS corresponds to a specific example of a “fourth switch” of the present disclosure. The transistor FCG corresponds to a specific example of a “fifth switch” of the present disclosure. The transistors AMP and SEL correspond to specific examples of an “output portion” of the present disclosure. The scanner 12 corresponds to a specific example of a “driving portion” of the present disclosure. The readout portion 20 and the signal processor 14 correspond to specific examples of a “processor” of the present disclosure.

[0059] [Operation and operation]

[0060] Next, the operation and function of the image pickup apparatus 1 according to the present embodiment will be described.

[0061] (Overview of overall operation)

[0062] First, refer to Figure 1 and Figure 2The overall operation overview of the imaging device 1 is described. The scanner 12 sequentially drives a plurality of imaging pixels 10 in a single row unit. The imaging pixels 10 sequentially output seven pixel voltages VP1 to VP7 in seven conversion periods P1 to P7 in the horizontal period H. The AD converter ADC of the readout section 20 performs AD conversion based on the seven pixel voltages VP1 to VP7 and outputs corresponding seven count values ​​CNT1 to CNT7. The signal processor 14 generates four images PIC (images PIC1, PIC2, ​​PIC3, and PIC4) based on the seven count values ​​CNT1 to CNT7 provided by the readout section 20. Then, the signal processor 14 synthesizes the four images PIC to generate a captured image PICA.

[0063] (Detailed operation)

[0064] In the imaging device 1, a plurality of imaging pixels 10 outputs a pixel voltage VP as a signal SIG. Then, the AD converter ADC of the readout section 20 generates a digital value (count value CNT) based on the signal SIG. The operation of a specific target imaging pixel 10A will be described in detail below.

[0065] Figure 3 , 4A and 4B show an operation example of the imaging device 1, wherein (A) represents a waveform of a horizontal synchronization signal HSYNC, (B) represents a waveform of a signal SSEL supplied to an imaging pixel 10A, (C) represents a waveform of a signal SFDG supplied to an imaging pixel 10A, (D) represents a waveform of a signal STGL supplied to an imaging pixel 10A, (E) represents a waveform of a signal SRST supplied to an imaging pixel 10A, (F) represents a waveform of a signal SFCG supplied to an imaging pixel 10A, (G) represents a waveform of a signal STGS supplied to an imaging pixel 10A, (H) represents a waveform of a reference signal REF, (I) represents a waveform of a signal SIG output from the imaging pixel 10A, and (J) represents the operation of a counter 25 in an AD converter ADC coupled to the imaging pixel 10A. Figure 4A Shows Figure 3 The first half of the operation shown, and Figure 4B Shows Figure 3 The second half of the operation shown. Figure 3 (H) and (I), Figure 4A (H) and (I) and Figure 4B In (H) and (I), the waveforms of the various signals are plotted on the same voltage axis. Figure 3 (J), Figure 4A (J) and Figure 4B In (J), the oblique lines indicate that the counter 25 is performing a counting operation.

[0066] FIG. 5A to FIG. 5C The state of the imaging pixel 10A is shown. Figures 5A to 5C , the transistors TGL, RST, FDG, TGS, FCG, and SEL are illustrated by using switches corresponding to the operation states of the transistors.

[0067] First, in the imaging device 1, in a specific horizontal period H, the scanner 12 selects a row of imaging pixels 10 including a target imaging pixel 10A from a plurality of imaging pixels 10 in the pixel array 11 by using a signal SSEL, and electrically couples the imaging pixel 10A to a signal line SGL corresponding to the imaging pixel 10A. Then, the scanner 12 controls the operation of the imaging pixel 10A by using signals SFDG, STGL, SRST, SFCG, and STGS, and the imaging pixel 10A sequentially outputs seven pixel voltages VP1 to VP7 in seven conversion periods P1 to P7. Then, the AD converter ADC of the readout section 20 performs AD conversion based on the seven pixel voltages VP1 to VP7 and outputs seven count values ​​CNT1 to CNT7. This operation will be described in detail below.

[0068] First, at time t1, the horizontal period H starts, and then at time t2, the scanner 12 changes the voltage of the signal SSEL from a low level to a high level ( Figure 4A (B)). This causes the transistor SEL in the imaging pixel 10A to be placed in an on state, thereby electrically coupling the imaging pixel 10A to the signal line SGL.

[0069] (Operation from time t11 to time t16)

[0070] Next, at time t11, the scanner 12 changes the voltage of the signal SFDG from a low level to a high level, and changes the voltage of the signal SRST from a low level to a high level ( Figure 4A (C) and (E)). Therefore, in the imaging pixel 10A, both the transistors FDG and RST are turned on, the voltage of the floating diffusion FD is set to the power supply voltage VDD, and the floating diffusion FD is reset. In addition, at this time t11, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ( Figure 4A (H)).

[0071] Next, at time t12, the scanner 12 changes the voltage of the signal SFDG from the high level to the low level, and changes the voltage of the signal SRST from the high level to the low level ( Figure 4A (C) and (E)). This causes both transistors FDG and RST in the imaging pixel 10A to be placed in an off state.

[0072] Next, at time t13, the scanner 12 changes the voltage of the signal SFDG from a low level to a high level ( Figure 4A (C)). This causes the transistor FDG to be placed in an on state.

[0073] Therefore, if Figure 5A As shown, in the imaging pixel 10A, the transistors FDG and SEL are placed in the on state, and all other transistors are placed in the off state. The transistor FDG is in the on state, so that the floating diffusion FD and the transistor FDG constitute a combined capacitance. The combined capacitance is used as a conversion capacitor for converting the charge in the imaging pixel 10A into a voltage. As described above, in the imaging pixel 10A, the transistor FDG is in the on state, so the conversion capacitor of the imaging pixel 10A has a large capacitance value. Therefore, the conversion efficiency of the charge to voltage is low. The conversion capacitor maintains the charge in the case where the reset floating diffusion FD is reset in the period from time t11 to time t12. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP1) corresponding to the voltage in the floating diffusion FD.

[0074] Next, in the period from time t14 to time t16 (conversion period P1), the AD converter ADC performs AD conversion based on the pixel voltage VP1. Specifically, at time t14, the readout controller 28 starts to generate the clock signal CLK. At the same time, the reference signal generator 29 starts to reduce the voltage of the reference signal REF from the voltage V1 by a predetermined change degree ( Figure 4A Therefore, the counter 25 of the AD converter ADC starts the counting operation ( Figure 4A (J)).

[0075] Thereafter, at time t15, the voltage of the reference signal REF drops below the voltage of the signal SIG (pixel voltage VP1) ( Figure 4A (H) and (I)). Therefore, the comparator 24 of the AD converter ADC changes the voltage of the signal CMP. Therefore, the counter 25 stops the counting operation ( Figure 4A At this time, the count value CNT of the counter 25 is the count value CNT1. After that, the readout section 20 supplies the count value CNT1 to the signal processor 14, and thereafter resets the count value CNT of the counter 25.

[0076] Then, at time t16, at the end of the conversion period P1, the readout controller 28 stops generating the clock signal CLK, and the reference signal generator 29 stops changing the voltage of the reference signal REF ( Figure 4A (H)).

[0077] (Operation from time t21 to time t24)

[0078] Next, at time t21, the scanner 12 changes the voltage of the signal SFDG from the high level to the low level ( Figure 4A This causes the transistor FDG in the imaging pixel 10A to be turned off. In addition, at this time t21, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ( Figure 4A (H)).

[0079] Therefore, if Figure 5B As shown, in the imaging pixel 10A, the transistor SEL is placed in the on state, and all other transistors are placed in the off state. As described above, in the imaging pixel 10A, the transistor FDG is in the off state, so the conversion capacitor of the imaging pixel 10A has a smaller capacitance value. Therefore, the charge-to-voltage conversion efficiency is high. The conversion capacitor maintains the charge in the case where the reset floating diffusion FD is reset in the period from time t11 to time t12. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP2) corresponding to the voltage in the floating diffusion portion FD.

[0080] Next, in the period from time t22 to time t24 (conversion period P2), the AD converter ADC performs AD conversion based on the pixel voltage VP2. This operation is similar to the operation in the conversion period P1. The AD converter ADC performs AD conversion based on the pixel voltage VP2 to obtain the count value CNT2 ( Figure 4A After that, the readout section 20 supplies the count value CNT2 to the signal processor 14, and then resets the count value CNT of the counter 25.

[0081] (Operation from time t31 to time t35)

[0082] Next, at time t31, the scanner 12 changes the voltage of the signal STGL from the low level to the high level ( Figure 4A (D)). This causes the transistor TGL in the imaging pixel 10A to be turned on. Therefore, the charge generated in the photodiode PD1 is transferred to the floating diffusion FD. In addition, at this time t31, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ( Figure 4A (H)).

[0083] Next, at time t32, the scanner 12 changes the voltage of the signal STGL from the high level to the low level ( Figure 4A (D)). This causes the transistor TGL in the imaging pixel 10A to be placed in an off state.

[0084] Therefore, if Figure 5BAs shown, in the imaging pixel 10A, the transistor FDG is in the off state; therefore, the conversion capacitor in the imaging pixel 10A has a small capacitance value. Therefore, the charge-to-voltage conversion efficiency is high. In the period from time t31 to time t32, the conversion capacitor holds the charge transferred from the photodiode PD1. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP3) corresponding to the voltage in the floating diffusion portion FD.

[0085] Next, in the period from time t33 to time t35 (conversion period P3), the AD converter ADC performs AD conversion based on the pixel voltage VP3. This operation is similar to the operation in the conversion period P1. The AD converter ADC performs AD conversion based on the pixel voltage VP3 to obtain the count value CNT3 ( Figure 4A (J)). This count value CNT3 corresponds to the count value CNT2 obtained similarly in the case of high conversion efficiency (in the conversion period P2). After that, the readout section 20 supplies the count value CNT3 to the signal processor 14, and thereafter resets the count value CNT of the counter 25.

[0086] (Operation from time t41 to time t44)

[0087] Next, at time t41, the scanner 12 changes the voltage of the signal SFDG from a low level to a high level ( Figure 4A This causes the transistor FDG in the imaging pixel 10A to be turned on. In addition, at this time t41, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ( Figure 4A (H)).

[0088] Therefore, if Figure 5A As shown, in the imaging pixel 10A, the transistor FDG is in the on state, which makes the floating diffusion FD and the transistor FDG constitute a combined capacitance (conversion capacitance). Therefore, the conversion capacitance of the imaging pixel 10A has a large capacitance value; therefore, the conversion efficiency of the charge to voltage is low. The conversion capacitance holds the charge transferred from the photodiode PD1 in the period from time t31 to time t32. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP4) corresponding to the voltage in the floating diffusion FD.

[0089] Next, in the period from time t42 to time t44 (conversion period P4), the AD converter ADC performs AD conversion based on the pixel voltage VP4. This operation is similar to the operation in the conversion period P1. The AD converter ADC performs AD conversion based on the pixel voltage VP4 to obtain the count value CNT4 ( Figure 4A(J)). This count value CNT4 corresponds to the count value CNT1 obtained similarly in the case of low conversion efficiency (in the conversion period P1). After that, the readout section 20 supplies the count value CNT4 to the signal processor 14, and thereafter resets the count value CNT of the counter 25.

[0090] (Operation from time t51 to time t56)

[0091] Next, at time t51, the scanner 12 changes the voltage of the signal SRST from a low level to a high level ( Figure 4B (E)). This causes the transistor RST in the imaging pixel 10A to be turned on. The transistor FDG is turned on, so that the floating diffusion FD is set to the power supply voltage VDD, and the floating diffusion FD is reset. In addition, at this time t51, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ( Figure 4B (H)).

[0092] Next, at time t52, the scanner 12 changes the voltage of the signal SRST from the high level to the low level ( Figure 4B (E)). This causes the transistor RST in the imaging pixel 10A to be placed in an off state.

[0093] Next, at time t53, the scanner 12 changes the voltage of the signal SFCG from a low level to a high level ( Figure 4B This causes the transistor FCG in the imaging pixel 10A to be placed in an on state.

[0094] Therefore, if Figure 5C As shown, in the imaging pixel 10A, transistors FDG, FCG and SEL are placed in an on state, and all other transistors are placed in an off state. Both transistors FDG and FCG are in an on state, so that the floating diffusion FD, transistors FDG and FCG, and capacitor FC constitute a combined capacitance (conversion capacitance). The conversion capacitance holds the charge generated in the photodiode PD2 before time t53 and accumulated in the capacitor FC through the transistor TGS. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP5) corresponding to the voltage in the floating diffusion FD.

[0095] Next, in the period from time t54 to time t56 (conversion period P5), the AD converter ADC performs AD conversion based on the pixel voltage VP5. This operation is similar to the operation in the conversion period P1. The AD converter ADC performs AD conversion based on the pixel voltage VP5 to obtain the count value CNT5 ( Figure 4BAfter that, the readout section 20 supplies the count value CNT5 to the signal processor 14, and thereafter resets the count value CNT of the counter 25.

[0096] (Operation from time t61 to time t65)

[0097] Next, at time t61, the scanner 12 changes the voltage of the signal STGS from a low level to a high level ( Figure 4B This causes the transistor TGS in the imaging pixel 10A to be turned on. In addition, at this time t61, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ( Figure 4B (H)).

[0098] Next, at time t62, the scanner 12 changes the voltage of the signal STGS from the high level to the low level ( Figure 4B This causes the transistor TGS in the imaging pixel 10A to be placed in an off state.

[0099] Therefore, if Figure 5C As shown, in the imaging pixel 10A, the transistors FDG and FCG are both in the on state, so that the floating diffusion FD, the transistors FDG and FCG, and the capacitor FC constitute a combined capacitance (conversion capacitance). In addition to the charge generated in the photodiode PD2 before the time t53 and accumulated in the capacitor FC through the transistor TGS, the conversion capacitance also holds the charge transferred from the photodiode PD2 in the period from the time t61 to the time t62. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP6) corresponding to the voltage in the floating diffusion FD.

[0100] Next, in the period from time t63 to time t65 (conversion period P6), the AD converter ADC performs AD conversion based on the pixel voltage VP6. This operation is similar to the operation in the conversion period P1. The AD converter ADC performs AD conversion based on the pixel voltage VP6 to obtain the count value CNT6 ( Figure 4B (J)). This count value CNT6 corresponds to the count value CNT5 obtained when the floating diffusion FD, the transistors FDG and FCG, and the capacitor FC constitute a combined capacitance. Thereafter, the readout section 20 provides the count value CNT6 to the signal processor 14, and thereafter resets the count value CNT of the counter 25.

[0101] (Operation from time t71 to time t77)

[0102] Next, at time t71, the scanner 12 changes the voltage of the signal SRST from a low level to a high level ( Figure 4B(E)). This causes the transistor RST in the imaging pixel 10A to be turned on. The transistors FDG and FCG are turned on, so that the voltage of the floating diffusion FD and the voltage of the capacitor FC are set to the power supply voltage VDD, and the floating diffusion FD and the capacitor FC are reset. In addition, at this time t71, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ( Figure 4B (H)).

[0103] Next, at time t72, the scanner 12 changes the voltage of the signal SFCG from the high level to the low level ( Figure 4B This causes the transistor FCG in the imaging pixel 10A to be placed in an off state.

[0104] Next, at time t73, the scanner 12 changes the voltage of the signal SRST from the high level to the low level ( Figure 4B (E)). This causes the transistor RST in the imaging pixel 10A to be placed in an off state.

[0105] Next, at time t74, the scanner 12 changes the voltage of the signal SFCG from a low level to a high level ( Figure 4B This causes the transistor FCG in the imaging pixel 10A to be placed in an on state.

[0106] Therefore, if Figure 5C As shown, in the imaging pixel 10A, the transistors FDG and FCG are both in the on state, so that the floating diffusion FD, the transistors FDG and FCG, and the capacitor FC constitute a combined capacitance (conversion capacitance). The conversion capacitance holds the charge of the reset floating diffusion FD and the capacitor FC when they are reset in the period from time t71 to time t72. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP7) corresponding to the voltage in the floating diffusion FD.

[0107] Next, in the period from time t75 to time t77 (conversion period P7), the AD converter ADC performs AD conversion based on the pixel voltage VP7. This operation is similar to the operation in the conversion period P1. The AD converter ADC performs AD conversion based on the pixel voltage VP7 to obtain the count value CNT7 ( Figure 4B (J)). This count value CNT7 corresponds to the count value CNT5 obtained when the floating diffusion FD, the transistors FDG and FCG, and the capacitor FC constitute a combined capacitance. Thereafter, the readout section 20 supplies the count value CNT7 to the signal processor 14, and thereafter resets the count value CNT of the counter 25.

[0108] Next, at time t7, the scanner 12 changes the voltage of the signal SFDG from the high level to the low level, and changes the voltage of the signal SFCG from the high level to the low level ( Figure 4B (C) and (F)). This causes the transistors FDG and FCG in the imaging pixel 10A to be turned off. In addition, at this time t7, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V2 ( Figure 4B (H)).

[0109] Then, at time t8, the scanner 12 changes the voltage of the signal SSEL from a high level to a low level ( Figure 4B (B)). Therefore, in the imaging pixel 10A, the transistor SEL is placed in an off state, and the imaging pixel 10A is electrically separated from the signal line SGL.

[0110] Next, the operation of the signal processor 14 is described. The signal processor 14 generates four images PIC (images PIC1, PIC2, ​​PIC3, and PIC4) based on the count value CNT supplied from the readout section 20. Then, the signal processor 14 synthesizes the four images PIC to generate one captured image PICA.

[0111] Figure 6 The operation of the signal processor 14 is schematically illustrated. Figure 6 The waveforms shown in (A) to (G) are similar to Figure 3 The waveforms shown in (A) to (G).

[0112] As reference Figure 3 , 4A As described in FIG. 4B , the readout unit 20 generates a count value CNT1 based on the operation in the time period from time t11 to time t21, generates a count value CNT2 based on the operation in the time period from time t21 to time t31, generates a count value CNT3 based on the operation in the time period from time t31 to time t41, generates a count value CNT4 based on the operation in the time period from time t41 to time t51, generates a count value CNT5 based on the operation in the time period from time t51 to time t61, generates a count value CNT6 based on the operation in the time period from time t61 to time t71, and generates a count value CNT7 based on the operation in the time period from time t71 to time t7.

[0113] The signal processor 14 generates a pixel value VAL1 based on the count value CNT2 and the count value CNT3. Specifically, the signal processor 14 calculates the pixel value VAL1 by subtracting the count value CNT2 from the count value CNT3 (CNT3-CNT2). That is, the camera 1 uses the so-called Correlation double sample (CDS) principle to calculate the pixel value VAL1 by using the count value CNT2 corresponding to the P phase (pre-charge phase) data and the count value CNT3 corresponding to the D phase (data phase) data.

[0114] Similarly, the signal processor 14 generates a pixel value VAL2 based on the count value CNT1 and the count value CNT4. Specifically, the signal processor 14 calculates the pixel value VAL2 by subtracting the count value CNT1 from the count value CNT4 (CNT4-CNT1). That is, the image pickup device 1 uses the correlated double sampling principle to calculate the pixel value VAL2 by using the count value CNT1 corresponding to the P phase data and the count value CNT4 corresponding to the D phase data.

[0115] Similarly, the signal processor 14 generates the pixel value VAL3 based on the count value CNT5 and the count value CNT6. Specifically, the signal processor 14 calculates the pixel value VAL3 by subtracting the count value CNT5 from the count value CNT6 (CNT6-CNT5). That is, the camera 1 uses the correlated double sampling principle to calculate the pixel value VAL3 by using the count value CNT5 corresponding to the P phase data and the count value CNT6 corresponding to the D phase data.

[0116] Then, the signal processor 14 generates a pixel value VAL4 based on the count value CNT5 and the count value CNT7. Specifically, the signal processor 14 calculates the pixel value VAL4 by subtracting the count value CNT7 from the count value CNT5 (CNT5-CNT7). That is, the image pickup device 1 uses the so-called correlated double sampling principle to calculate the pixel value VAL4 by using the count value CNT7 after resetting the floating diffusion FD and the capacitor FC and the count value CNT5 after resetting the floating diffusion FD.

[0117] Here, the pixel value VAL1 corresponds to a specific example of the “first value” of the present disclosure. The pixel value VAL2 corresponds to a specific example of the “second value” of the present disclosure. The pixel value VAL3 corresponds to a specific example of the “third value” of the present disclosure. The pixel value VAL4 corresponds to a specific example of the “fourth value” of the present disclosure.

[0118] Then, the signal processor 14 generates an image PIC1 based on the pixel value VAL1 of all the imaging pixels 10 in the pixel array 11, generates an image PIC2 based on the pixel value VAL2 of all the imaging pixels 10 in the pixel array 11, generates an image PIC3 based on the pixel value VAL3 of all the imaging pixels 10 in the pixel array 11, and generates an image PIC4 based on the pixel value VAL4 of all the imaging pixels 10 in the pixel array 11. Then, the signal processor 14 synthesizes the images PIC1 to PIC4 to generate a captured image PICA.

[0119] Figure 7 FIG. 2 shows an example of a signal-to-noise ratio (S / N ratio) in a captured image PICA synthesized by the image pickup device 1. Figure 7 , the horizontal axis represents illuminance, and the vertical axis represents the S / N ratio.

[0120] In the case of synthesizing four images PIC1 to PIC4, the signal processor 14 increases the number of images PIC1 to PIC4 used as the illumination increases. Specifically, in the case where the illumination at the target pixel is lower than the illumination value L1, the signal processor 14 generates the pixel value at the target pixel in the captured image PICA based on the pixel value VAL1 at the target pixel in the image PIC1. In addition, in the case where the illumination at the target pixel is higher than the illumination value L1 and lower than the illumination value L2, the signal processor 14 generates the pixel value at the target pixel in the captured image PICA based on the pixel values ​​VAL1 and VAL2 at the target pixels in the two images PIC1 and PIC2. In addition, in the case where the illumination at the target pixel is higher than the illumination value L2 and lower than the illumination value L3, the signal processor 14 generates the pixel value at the target pixel in the captured image PICA based on the pixel values ​​VAL1 to VAL3 at the target pixels in the three images PIC1 to PIC3. Furthermore, in the case where the illuminance is higher than the illuminance value L3 , the signal processor 14 generates a pixel value at the target pixel in the captured image PICA based on the pixel values ​​VAL1 to VAL4 at the target pixel in the four images PIC1 to PIC4 .

[0121] like Figure 7 As shown, when the illuminance exceeds the illuminance value L2 (portion W1), the S / N ratio decreases, and when the illuminance exceeds the illuminance value L3 (portion W3), the S / N ratio further decreases. That is, in portion W1, the S / N ratio is reduced by adding the image PIC3 to the image for synthesis, and in portion W2, the S / N ratio is reduced by adding the image PIC4 to the image for synthesis.

[0122] As described above, in the image pickup device 1, the pixel value VAL3 included in the image PIC3 is determined by correlated double sampling. This makes it possible to reduce the noise included in the image PIC3 in the image pickup device 1; therefore, as described below, it is possible to suppress the noise compared to the comparative example. Figure 7 The reduction in the S / N ratio at the illuminance value L2 is shown.

[0123] (Comparative Example)

[0124] Next, the effect of the camera device 1 according to the present embodiment will be described by comparing the camera device according to the comparative example. The camera device of the comparative example includes a scanner, a readout unit, a signal processor and a controller. In the camera device of the comparative example, the camera pixel 10 sequentially outputs six pixel voltages VP1 to VP4, VP16 and VP7 in six conversion periods P1 to P6 in the horizontal period H. Each AD converter ADC of the readout unit performs AD conversion based on the six pixel voltages VP1 to VP4, VP16 and VP7, and outputs six count values ​​CNT1 to CNT4, CNT16 and CNT7. The signal processor generates three images PIC (images PIC1, PIC2 and PIC13) based on the count values ​​CNT1 to CNT4, CNT16 and CNT7 provided from the readout unit. Then, the signal processor synthesizes the three images PIC to generate a captured image PICR.

[0125] Figure 8 , 9A 9B show an operation example of a specific target imaging pixel 10A in the imaging device of the comparative example. Fig. 9A Shows Figure 8 The first half of the operation is shown, and Fig. 9B Shows Figure 8 The operation before time t51 and the operation starting from time t71 are similar to the operation of the camera 1 according to the present embodiment ( Figure 3 , 4A and 4B). Next, the operation from time t51 to time t71 will be described.

[0126] At time t51, the scanner changes the voltage of the signal SRST from a low level to a high level ( Fig. 9B (E)). This causes the transistor RST in the imaging pixel 10A to be turned on. The transistor FDG is turned on, so that the floating diffusion FD is set to the power supply voltage VDD, and the floating diffusion FD is reset. In addition, at this time t51, the reference signal generator 29 changes the voltage of the reference signal REF to the voltage V1 ( Fig. 9B (H)).

[0127] Next, at time t52, the scanner changes the voltage of the signal SRST from a high level to a low level ( Fig. 9B (E)). This causes the transistor RST in the imaging pixel 10A to be placed in an off state.

[0128] Next, at time t53, the scanner changes the voltage of the signal SFCG from a low level to a high level ( Fig. 9B This causes the transistor FCG in the imaging pixel 10A to be placed in an on state.

[0129] Next, at time t58, the scanner changes the voltage of the signal STGS from a low level to a high level ( Fig. 9B This causes the transistor TGS in the imaging pixel 10A to be placed in an on state.

[0130] Next, at time t59, the scanner changes the voltage of the signal STGS from a high level to a low level ( Figure 8 B (G)). This causes the transistor TGS in the imaging pixel 10A to be placed in an off state.

[0131] Therefore, if Figure 5C As shown, in the imaging pixel 10A, both transistors FDG and FCG are in the on state, so that the floating diffusion FD, transistors FDG and FCG, and capacitor FC constitute a combined capacitance (conversion capacitance). In addition to the charge generated in the photodiode PD2 before time t53 and accumulated in the capacitor FC through the transistor TGS, the conversion capacitance also holds the charge transferred from the photodiode PD2 in the period from time t58 to time t59. The imaging pixel 10A outputs a pixel voltage VP (pixel voltage VP16) corresponding to the voltage in the floating diffusion FD.

[0132] Next, in the period from time t63 to time t65 (conversion period P16), the AD converter ADC performs AD conversion based on the pixel voltage VP16. This operation is similar to the operation in the conversion period P1. The AD converter ADC performs AD conversion based on the pixel voltage VP16 to obtain the count value CNT16 ( Fig. 9B After that, the readout section supplies the count value CNT16 to the signal processor, and thereafter resets the count value CNT of the counter 25.

[0133] Fig.10 The operation of the signal processor of the comparative example is schematically shown. Fig.10 The waveforms shown in (A) to (G) are similar to Figure 8 The waveforms shown in (A) to (G).

[0134] As reference Figure 8 ,9A As described in FIG9B , the readout section of the comparative example generates the count value CNT16 based on the operation in the period from time t51 to time t71 , and generates the count value CNT7 based on the operation in the period from time t71 to time t7 .

[0135] The signal processor of the comparative example generates a pixel value VAL13 based on the count value CNT16 and the count value CNT7. Specifically, the signal processor calculates the pixel value VAL13 by subtracting the count value CNT7 from the count value CNT16 (CNT16-CNT7) using the double data sampling (DDS) principle.

[0136] Then, the signal processor of the comparative example generates an image PIC1 based on the pixel values ​​VAL1 in all the imaging pixels 10 in the pixel array 11, generates an image PIC2 based on the pixel values ​​VAL2 in all the imaging pixels 10 in the pixel array 11, and generates an image PIC13 based on the pixel values ​​VAL13 in all the imaging pixels 10 in the pixel array 11. Then, the signal processor of the comparative example synthesizes the images PIC1, PIC2, ​​and PIC13 to generate a captured image PICR.

[0137] Fig.11 An example of a signal-to-noise ratio (S / N ratio) in a captured image PICR synthesized by an image pickup device of a comparative example is shown.

[0138] As described in the signal processor 14 according to the present embodiment, in the case of synthesizing three images PIC, the signal processor of the comparative example increases the number of images PIC used in the images PIC1, PIC2, ​​and PIC13 as the illuminance increases. Specifically, in the case where the illuminance at the target pixel is lower than the illuminance value L11, the signal processor of the comparative example generates the pixel value at the target pixel in the captured image PICA based on the pixel value VAL1 at the target pixel in the image PIC1. In addition, in the case where the illuminance at the target pixel is higher than the illuminance value L11 and lower than the illuminance value L12, the signal processor of the comparative example generates the pixel value at the target pixel in the captured image PICA based on the pixel values ​​VAL1 and VAL2 at the target pixels in the two images PIC1 and PIC2. In addition, in the case where the illuminance at the target pixel is higher than the illuminance value L12, the signal processor of the comparative example generates the pixel value at the target pixel in the captured image PICA based on the pixel values ​​VAL1, VAL2, and VAL3 at the target pixels in the three images PIC1, PIC2, ​​and PIC13.

[0139] like Fig.11As shown in FIG. 1 , in the case where the illuminance exceeds the illuminance value L12 (portion W3), the S / N ratio decreases. That is, in portion W3, the S / N ratio decreases due to the addition of image PIC13 to the image for synthesis. That is, this image PIC13 is generated by double data sampling (DDS); therefore, it is not possible to sufficiently eliminate noise as with correlated double sampling. Therefore, in the image pickup device of the comparative example, the S / N ratio in portion W3 decreases significantly.

[0140] In contrast, in the image pickup device 1 according to the present embodiment, the image PIC3 is generated by correlated double sampling. Figure 6 In the above, the signal processor 14 generates the image PIC3 by using the count value CNT5 generated based on the operation in the period from time t51 to time t61 as the P phase data, and using the count value CNT6 generated based on the operation in the period from time t61 to time t71 as the D phase data. This makes it possible to remove, for example, the dark current component and reset the noise of the photodiode PD2 in the image pickup device 1, thereby Figure 7 As shown, it is possible to suppress a decrease in the S / N ratio when the image PIC3 is added. Therefore, in the image pickup device 1, the image quality of the captured image PICA can be improved.

[0141] [Effect]

[0142] As described above, in the present embodiment, the third image PIC3 is generated by correlated double sampling and a captured image is generated by using the third image PIC3, so that the image quality can be improved.

[0143] [First Modification]

[0144] In the above embodiment, if Figure 3 As shown, seven conversion periods P1 to P7 are provided, but this is not restrictive. Fig.12 and 13 In the imaging device 1B shown in FIG. 1 , eight transition periods P1 to P8 are provided. In the imaging device 1B, between the period from time t51 to time t61 and the period from time t61 to time t71 in the imaging device 1 according to the above-described embodiment ( Figure 3 ) adds a period including the transition period P15.

[0145] In the image pickup device 1B, the ADC converter ADC generates a count value CNT (count value CNT5) based on the pixel voltage VP (VP5) output from the image pickup pixel 10A in the conversion period P5. Then, in the image pickup device 1B, while holding the signals SSEL, SFDG, STGL, SRST, SFCG, and STGS, the ADC converter ADC subsequently generates a count value CNT (count value CNT15) based on the pixel voltage VP output from the image pickup pixel 10A in the conversion period P15.

[0146] Then, the signal processor 14 generates the pixel value VAL3 based on the count value CNT15 and the count value CNT6. Specifically, the signal processor 14 calculates the pixel value VAL3 by subtracting the count value CNT15 from the count value CNT6 (CNT6-CNT15). That is, the imaging device 1B uses the correlated double sampling principle to calculate the pixel value VAL3 by using the count value CNT15 corresponding to the P phase data and the count value CNT6 corresponding to the D phase data. In addition, as in the above-mentioned embodiment, the signal processor 14 generates the pixel value VAL4 based on the count value CNT5 and the count value CNT7.

[0147] Then, the signal processor 14 generates an image PIC1 based on the pixel values ​​VAL1 in all the imaging pixels 10 in the pixel array 11, generates an image PIC2 based on the pixel values ​​VAL2 in all the imaging pixels 10 in the pixel array 11, generates an image PIC3 based on the pixel values ​​VAL3 in all the imaging pixels 10 in the pixel array 11, and generates an image PIC4 based on the pixel values ​​VAL4 in all the imaging pixels 10 in the pixel array 11. Then, the signal processor 14 synthesizes the images PIC1 to PIC4 to generate a captured image PICA.

[0148] Although the present technology has been described above with reference to the embodiment and the modified examples, the present technology is not limited to the embodiment and the like and may be modified in various ways.

[0149] For example, the waveforms and transition timings of the signals SSEL, SFDG, STGL, SRST, SFCG, and STGS in the above-described embodiments and the like are exemplary and may be appropriately changed.

[0150] It should be noted that the effects described herein are merely exemplary and not restrictive, and other effects may be provided.

[0151] It should be noted that the present technology may have any of the following configurations.

[0152] (1) A camera device comprising:

[0153] a first light receiving device and a second light receiving device;

[0154] a first charge accumulation portion and a second charge accumulation portion;

[0155] a first switch that couples the first light receiving device and the first charge accumulation portion to each other by being placed in an on state;

[0156] a second switch that couples a predetermined node and the first charge accumulation portion to each other by being placed in an on state;

[0157] a third switch which applies a predetermined voltage to the predetermined node by being placed in an on state;

[0158] a fourth switch that couples the second light receiving device and the second charge accumulation portion to each other by being placed in an on state;

[0159] a fifth switch that couples the second charge accumulation portion and the predetermined node to each other by being placed in an on state;

[0160] an output section that outputs a pixel voltage corresponding to the voltage in the first charge accumulation section; a drive section that drives each of the switches; and

[0161] a processor that determines a first value, a second value, a third value, and a fourth value based on the pixel voltage and generates a pixel value based on the values,

[0162] In a first period, the driving unit turns the second switch and the third switch on, and turns the first switch, the fourth switch, and the fifth switch off.

[0163] In a second period after the first period, the driving unit turns the third switch off and turns the fifth switch on,

[0164] In a third period after the second period, the driving unit turns the fourth switch on.

[0165] In a fourth period after the third period, the driving unit turns the fourth switch off, and

[0166] The processor determines the third value based on the pixel voltage in the second period and the pixel voltage in the fourth period.

[0167] (2) An imaging device according to (1), wherein the processor generates a first digital value by performing AD conversion based on the pixel voltage in the second period, and generates a second digital value by performing AD conversion based on the pixel voltage in the fourth period, and determines the third value based on the first digital value and the second digital value.

[0168] (3) The imaging device according to (1) or (2), wherein:

[0169] In a fifth period after the fourth period, the driving unit turns the third switch and the fifth switch into an on state,

[0170] In a sixth period after the fifth period, the driving unit turns the third switch and the fifth switch off.

[0171] In a seventh period after the sixth period, the driving section turns the third switch off and turns the fifth switch on, and

[0172] The processor determines the fourth value based on the pixel voltage in the second period and the pixel voltage in the seventh period.

[0173] (4) The imaging device according to (1) or (2), wherein:

[0174] In a fifth period after the fourth period, the driving unit turns the third switch and the fifth switch into an on state,

[0175] In a sixth period after the fifth period, the driving unit turns the third switch and the fifth switch off.

[0176] In a seventh period after the sixth period, the driving unit turns the third switch off and turns the fifth switch on.

[0177] The second period includes a first sub-period and a second sub-period after the first sub-period,

[0178] The processor determines the third value based on the pixel voltage in the second sub-period of the second period and the pixel voltage in the fourth period, and

[0179] The processor determines the fourth value based on the pixel voltage in the first sub-period of the second period and the pixel voltage in the seventh period.

[0180] (5) The imaging device according to any one of (1) to (4), wherein:

[0181] In an eighth period, the driving unit turns the second switch and the third switch on, and turns the first switch, the fourth switch, and the fifth switch off.

[0182] In a ninth period after the eighth period, the driving unit turns the second switch on and turns the third switch off.

[0183] In a tenth time period after the ninth time period, the driving unit turns the second switch off.

[0184] In an eleventh period after the tenth period, the driving unit turns the first switch on.

[0185] In a twelfth period after the eleventh period, the driving unit turns the first switch off.

[0186] In a thirteenth period after the twelfth period and before the first period, the driving unit turns the second switch on.

[0187] The processor determines the first value based on the pixel voltage in the tenth period and the pixel voltage in the twelfth period,

[0188] The processor determines the second value based on the pixel voltage in the ninth period and the pixel voltage in the thirteenth period.

[0189] (6) The imaging device according to any one of (1) to (5), wherein:

[0190] In the case where the illumination is lower than a first illumination value, the processor generates the pixel value based on the first value,

[0191] In a case where the illuminance is higher than the first illuminance value and lower than a second illuminance value, the processor generates the pixel value based on the first value and the second value,

[0192] In a case where the illuminance is higher than the second illuminance value and lower than a third illuminance value, the processor generates the pixel value based on the first value, the second value and the third value, and

[0193] In a case where the illuminance is higher than the third illuminance value, the processor generates the pixel value based on the first value, the second value, the third value, and the fourth value.

[0194] (7) The image pickup device according to any one of (1) to (6), wherein a light receiving area of ​​the first light receiving device is larger than a light receiving area of ​​the second light receiving device.

[0195] (8) The image pickup device according to any one of (1) to (7), wherein the first charge accumulation portion includes a diffusion layer.

[0196] (9) The camera device according to any one of (1) to (8), wherein the processor comprises:

[0197] A reference signal generator that generates a reference signal whose voltage level changes,

[0198] a comparing unit for generating a comparison signal by comparing the pixel voltage with the reference signal, and

[0199] A counter generates a digital value by performing a counting operation based on the comparison signal.

[0200] (10) A method for photographing, comprising:

[0201] driving respective switches of an imaging pixel, the imaging pixel including a first light receiving device and a second light receiving device, a first charge accumulation section and a second charge accumulation section, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and an output section, the first switch coupling the first light receiving device and the first charge accumulation section to each other by being placed in an on state, the second switch coupling a predetermined node and the first charge accumulation section to each other by being placed in an on state, the third switch applying a predetermined voltage to the predetermined node by being placed in an on state, the fourth switch coupling the second light receiving device and the second charge accumulation section to each other by being placed in an on state, the fifth switch coupling the second charge accumulation section and the predetermined node to each other by being placed in an on state, and the output section outputting a pixel voltage corresponding to a voltage in the first charge accumulation section;

[0202] determining a first value, a second value, a third value, and a fourth value based on the pixel voltage, and generating a pixel value based on the values;

[0203] In a first period, the second switch and the third switch are placed in an on state, and the first switch, the fourth switch and the fifth switch are placed in an off state;

[0204] In a second time period after the first time period, the third switch is placed in an off state and the fifth switch is placed in an on state;

[0205] In a third time period after the second time period, placing the fourth switch in an on state;

[0206] In a fourth time period after the third time period, the fourth switch is placed in an off state; and

[0207] The third value is determined based on the pixel voltage in the second period and the pixel voltage in the fourth period.

[0208] This application claims the benefit of Japanese Patent Application JP2017-208118 filed with the Japan Patent Office on October 27, 2017, the entire contents of which are hereby incorporated by reference.

[0209] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and changes may be made according to design requirements and other factors without departing from the scope of the appended claims or claims equivalent thereto.

Claims

1. A camera device, comprising: Pixels, which include: a first photoelectric converter; A first transmission transistor coupled to the first photoelectric converter; a first capacitor coupled to the first pass transistor; a second transmission transistor coupled to the first capacitor; a reset transistor coupled to the second transmission transistor; a second photoelectric converter; a third transmission transistor coupled to the second photoelectric converter; a second capacitor coupled to the third transmission transistor; a fourth pass transistor coupled between the second pass transistor and the third pass transistor; and an amplifying transistor coupled to the first capacitor, wherein a light receiving area of ​​the first photoelectric converter is larger than a light receiving area of ​​the second photoelectric converter in a plan view, a signal processor, wherein the signal processor generates first image data, second image data, third image data, and fourth image data based on first pixel signals, second pixel signals, third pixel signals, and fourth pixel signals output by the pixels, and wherein the signal processor generates one image data synthesizing the first image data, the second image data, the third image data, and the fourth image data; and a driving section that drives each of the first transfer transistor, the second transfer transistor, the reset transistor, the third transfer transistor, and the fourth transfer transistor, wherein, in a first period, the driving section turns on the second transfer transistor and the reset transistor, and turns off the first transfer transistor, the third transfer transistor, and the fourth transfer transistor, In a second period after the first period, the driving section puts the reset transistor into an off state and puts the fourth transfer transistor into an on state, In a third period after the second period, the driving section turns the third transfer transistor on. In a fourth period after the third period, the driving section places the third transfer transistor in an off state, and The third pixel signal is determined based on the voltage of the pixel in the second period and the voltage of the pixel in the fourth period.

2. The imaging device according to claim 1, wherein: The second capacitor is coupled to a fixed potential.

3. The imaging device according to claim 1 or 2, wherein: The fourth transmission transistor is coupled between the second transmission transistor and the reset transistor.

4. The imaging device according to claim 1 or 2, wherein: The second capacitor is coupled between the third pass transistor and the fourth pass transistor.

5. The imaging device according to claim 1 or 2, wherein: The second pass transistor is configured to switch conversion efficiency.

6. The imaging device according to claim 1 or 2, wherein: The fourth pass transistor is configured to switch conversion efficiency.

7. The imaging device according to claim 1 or 2, wherein: The first capacitor is directly coupled to the amplifying transistor.

8. The imaging device according to claim 1 or 2, wherein: The first capacitor is a floating diffusion region.

9. The imaging device according to claim 1 or 2, wherein: The amplifying transistor outputs a pixel voltage corresponding to a voltage in the first capacitor.

10. The imaging device according to claim 1, wherein: In a fifth period after the fourth period, the driving section puts the reset transistor and the fourth transfer transistor into an on state, In a sixth period after the fifth period, the driving section places the reset transistor and the fourth transfer transistor in an off state, In a seventh period after the sixth period, the driving section places the reset transistor in an off state and places the fourth transfer transistor in an on state.

11. The imaging device according to claim 1, wherein: In a fifth period after the fourth period, the driving section puts the reset transistor and the fourth transfer transistor into an on state, In a sixth period after the fifth period, the driving section places the reset transistor and the fourth transfer transistor in an off state, In a seventh period after the sixth period, the driving section puts the reset transistor in an off state and puts the fourth transfer transistor in an on state, The second period includes a first sub-period and a second sub-period following the first sub-period.

12. The imaging device according to claim 10 or 11, wherein: In an eighth period, the driving section places the second transfer transistor and the reset transistor in an on state, and places the first transfer transistor, the third transfer transistor, and the fourth transfer transistor in an off state, In a ninth period after the eighth period, the driving section places the second transfer transistor in an on state and places the reset transistor in an off state, In a tenth period after the ninth period, the driving section puts the second transfer transistor into an off state, In an eleventh period after the tenth period, the driving section places the first transfer transistor in an on state, In a twelfth period after the eleventh period, the driving section puts the first transfer transistor into an off state, In a thirteenth period after the twelfth period and before the first period, the driving section puts the second transfer transistor into an on state.

13. The imaging device according to claim 1 or 2, wherein: A light receiving area of ​​the first photoelectric converter is larger than a light receiving area of ​​the second photoelectric converter.

14. The imaging device according to claim 1 or 2, wherein: The first capacitor includes a diffusion layer.

15. The imaging device according to claim 1 or 2, wherein: The signal processor comprises: A reference signal generator that generates a reference signal whose voltage level changes, a comparing section for generating a comparison signal by comparing the pixel voltage with the reference signal, and A counter generates a digital value by performing a counting operation based on the comparison signal.

Images