Method for preparing solar cell

Abstract

The embodiments of the present application relate to the field of solar cell technology, and more particularly to a method for preparing a solar cell, comprising: providing a substrate having a first surface; forming a doped layer and a passivation layer stacked sequentially along a direction facing away from the first surface of the substrate on the first surface of the substrate, wherein the passivation layer has a region to be laser processed; performing a laser process on the region to be laser processed on the top surface of the passivation layer to form a laser processed region, wherein the laser process converts at least a portion of the thickness of the passivation layer corresponding to the laser processed region into a first modified film layer; and forming a first gate electrode on the first surface of the substrate using a sintering process, wherein at least a portion of the first gate electrode penetrates the first modified film layer to electrically contact the doped layer. The embodiments of the present application are beneficial for improving the photoelectric conversion performance of the prepared solar cell.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and more particularly to a method for preparing a solar cell. Background Art

[0002] Solar cells have excellent photoelectric conversion capabilities. In solar cells, a metallization process is required on the surface of the silicon wafer to form multiple fine grids and a main grid, thereby collecting the current generated by the silicon wafer. Typically, the metallization process includes a sintering step to sinter the metal paste printed on the silicon wafer surface, allowing the metal paste to penetrate the passivation layer and make electrical contact with the doped conductive layer or emitter.

[0003] However, the photoelectric conversion performance of solar cells currently prepared is poor. Summary of the Invention

[0004] The embodiments of the present application provide a method for preparing a solar cell, which is at least beneficial to improving the photoelectric conversion performance of the solar cell.

[0005] An embodiment of the present application provides a method for preparing a solar cell, comprising: providing a substrate having a first surface; forming a doping layer and a passivation layer stacked in sequence along a direction away from the first surface of the substrate on the first surface of the substrate, the passivation layer having an area to be laser processed; performing a laser process on the area to be laser processed on the top surface of the passivation layer to form a laser processed area, the laser process converting at least a portion of the thickness of the passivation layer corresponding to the laser processed area into a first modified film layer; and forming a first gate line electrode on the first surface of the substrate using a sintering process, at least a portion of the first gate line electrode penetrating the first modified film layer to be in electrical contact with the doping layer.

[0006] In addition, the laser power of the laser process is 15W to 45W, the laser frequency is 100kHz to 1500kHz, the laser wavelength is 250nm to 1320nm, the laser pulse width is 1ps to 50000ps, and the laser line scanning speed is 2000mm / s to 50000mm / s.

[0007] In addition, the passivation layer has a region where a first gate line electrode is to be formed, the laser processed region at least partially overlaps with the region where the first gate line electrode is to be formed, and the sintering process includes: printing metal paste on the top surface of the passivation layer in the region where the first gate line electrode is to be formed; and heat treating the metal paste so that at least part of the metal paste penetrates the first modified film layer and electrically contacts the doping layer.

[0008] In addition, the temperature of the heat treatment is 450°C to 800°C.

[0009] In addition, the burn-through depth of the metal paste is 20 nm to 200 nm.

[0010] In addition, the area of the passivation layer other than the laser processed area is a first region, and the density of the passivation layer in the first region is greater than the density of the first modified film layer.

[0011] In addition, the area to be laser processed includes: a plurality of spaced-apart second regions, and laser processing the area to be laser processed on the top surface of the passivation layer is: laser processing the top surface of the passivation layer in the second regions.

[0012] In addition, the passivation layer has a region where a first gate line electrode is to be formed, the second region overlaps with a portion of the region where the first gate line electrode is to be formed, and the first gate line electrode includes: a first part and a second part, the first part penetrates the first modified film layer in the second region and is in electrical contact with the doping layer, and the second part is in contact with a portion of the passivation layer on the side facing the substrate.

[0013] In addition, the top surfaces of the first portion and the second portion are flush, and the ratio of the thickness of the first portion to the thickness of the second portion is 1.5-10.

[0014] In addition, multiple second regions are arranged in an array, including: multiple columns of second regions arranged at intervals along the first direction, multiple columns of second regions arranged at intervals along the second direction, the first direction is the extension direction of the first gate line electrode, and the second direction is the arrangement direction of multiple first gate line electrodes.

[0015] In addition, the second regions in one column and the second regions in an adjacent column are arranged in a staggered manner in the first direction; or, the second regions in one column and the second regions in an adjacent column are arranged in alignment along the second direction.

[0016] In addition, the laser process also converts at least a portion of the doped layer corresponding to the laser processed area into a second modified film layer, and at least a portion of the first gate line electrode penetrates the first modified film layer and is in electrical contact with the second modified film layer.

[0017] In addition, the region to be laser processed overlaps with the region to be formed with the first gate line electrode.

[0018] In addition, the doping ion type of the doping layer is the same as the doping ion type of the substrate, and the material of the doping layer is at least one of doped amorphous silicon, doped polycrystalline silicon or doped microcrystalline silicon.

[0019] In addition, the method further includes: forming a tunneling dielectric layer, wherein the tunneling dielectric layer is located between the doping layer and the first surface of the substrate.

[0020] In addition, the doping ion type of the doping layer is different from the doping ion type of the substrate, and the material of the doping layer is the same as that of the substrate.

[0021] In addition, the material of the passivation layer is at least one of silicon oxide, silicon nitride, aluminum oxide or silicon oxynitride.

[0022] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0023] In the technical solution of the method for preparing a solar cell provided in an embodiment of the present application, a laser process is performed on the area to be laser processed on the top surface of the passivation layer to form a laser processed area, and at least part of the thickness of the passivation layer in the laser processed area is converted into a first modified film layer, that is, the laser processing does not remove part of the passivation layer, but still retains the complete morphology of the passivation layer after laser processing. The area to be laser processed corresponds to the area to be formed with the first gate line electrode; a sintering process is used to form the first gate line electrode on the first surface of the substrate in the area to be formed with the first gate line electrode, and at least part of the first gate line electrode penetrates the first modified film layer and electrically contacts the doped layer. The passivation layer is modified after laser processing, making it easier to burn through the first modified film layer area during the sintering process. In this way, the temperature of the sintering process can be lower, thereby preventing the problem of damage to the doped layer, emitter or substrate due to excessively high sintering temperature. In addition, since the complete morphology of the passivation layer is retained after laser processing, the damage caused by the laser processing to the substrate and the passivation layer corresponding to the non-laser processed area can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily described by the pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0025] Figure 1 A schematic cross-sectional structure diagram corresponding to the step of providing a substrate in a method for preparing a solar cell provided in one embodiment of the present application;

[0026] Figure 2 A schematic cross-sectional structure diagram corresponding to the step of forming a tunneling layer in a method for preparing a solar cell provided in one embodiment of the present application;

[0027] Figure 3 A schematic cross-sectional structure diagram corresponding to the step of forming a doping layer in a method for preparing a solar cell provided in one embodiment of the present application;

[0028] Figure 4 A schematic cross-sectional structure diagram corresponding to the step of forming a passivation layer in a method for preparing a solar cell provided in one embodiment of the present application;

[0029] Figure 5 A schematic cross-sectional structure diagram corresponding to the step of forming a doping layer and a passivation layer in another method for preparing a solar cell provided in one embodiment of the present application;

[0030] Figure 6 A schematic top view of the structure corresponding to the step of forming a laser processing area in a method for preparing a solar cell provided in one embodiment of the present application;

[0031] Figure 7 A schematic top view of the structure corresponding to the step of forming a laser processing area in another method for preparing a solar cell provided in one embodiment of the present application;

[0032] Figure 8 for Figure 6 A schematic diagram of a cross-sectional structure in the aa' direction;

[0033] Figure 9 for Figure 6 Another cross-sectional structure diagram in the aa' direction;

[0034] Figure 10 for Figure 6 Another cross-sectional structural diagram in the aa' direction;

[0035] Figure 11 for Figure 6 Another cross-sectional structural diagram in the aa' direction;

[0036] Figure 12 A schematic top view of the structure corresponding to the step of forming a first grid line electrode in a method for preparing a solar cell provided in one embodiment of the present application;

[0037] Figure 13 for Figure 12 A schematic diagram of a cross-sectional structure in the aa' direction;

[0038] Figure 14 for Figure 12 A schematic diagram of a cross-sectional structure in the bb' direction;

[0039] Figure 15 for Figure 12 Schematic diagram of another cross-sectional structure in the bb' direction;

[0040] Figure 16 This is a structural schematic diagram corresponding to the step of forming an anti-reflection layer and a second grid line electrode in a method for preparing a solar cell provided in one embodiment of the present application. DETAILED DESCRIPTION

[0041] As known from the background art, the photoelectric conversion performance of current solar cells is poor.

[0042] Analysis has found that one of the reasons for the poor photoelectric conversion performance of current solar cells is that, during the process of forming the first gate electrode, a sintering process is usually required to sinter the metal paste printed on the top surface of the passivation layer so that the metal paste can burn through the passivation layer and make electrical contact with the doped layer. However, due to the high sintering temperature and the presence of a large number of highly corrosive components in the metal paste, at high temperatures, when the metal paste penetrates the passivation layer and makes electrical contact with the doped layer, it causes significant damage to the passivation and doped layers. This leads to greater metal recombination between the passivation and doped layers and the first gate electrode, resulting in lower photoelectric conversion efficiency of the solar cell.

[0043] An embodiment of the present application provides a method for preparing a solar cell, in which a laser process is performed on the area to be laser processed on the top surface of the passivation layer, and at least a portion of the thickness of the passivation layer is converted into a first modified film layer. That is, the laser processing does not remove part of the passivation layer, but still retains the complete morphology of the passivation layer that has been laser processed. The passivation layer after laser processing is modified, so that when the sintering process is performed to form the first gate line electrode, it is easier to burn through the first modified film layer area. In this way, the temperature of the sintering process can be lower, thereby preventing the problem of damage to the doping layer, the emitter or the substrate due to excessively high sintering temperature. In addition, since the complete morphology of the passivation layer is retained after laser processing, the damage caused by the laser processing to the substrate and the passivation layer corresponding to the non-laser processed area can be reduced.

[0044] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0045] Figure 1 This is a schematic structural diagram of a solar cell provided in one embodiment of the present application. Figure 2 for Figure 1 A partial enlarged view of the dotted box in .

[0046] refer to Figure 1 , providing a substrate 100, the substrate 100 having a first surface.

[0047] The substrate 100 is used to receive incident light and generate photogenerated carriers. In some embodiments, the substrate 100 may be a substrate 100, and the material of the substrate 100 may include at least one of single crystal silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. The substrate 100 is an N-type semiconductor substrate 100, i.e., the substrate 100 is doped with N-type dopant ions, which may be any one of phosphorus ions, arsenic ions, or antimony ions. In other embodiments, the substrate 100 may be a P-type semiconductor substrate 100, and the substrate 100 is doped with P-type dopant ions, which may be any one of boron ions, gallium ions, or indium ions.

[0048] The substrate 100 has a second surface disposed opposite the first surface. Both the first and second surfaces of the substrate 100 can be used to receive incident light or reflected light. In some embodiments, the first surface can be the back surface of the substrate 100, and the second surface can be the front surface of the substrate 100. In other embodiments, the first surface can also be the front surface of the substrate 100, and the second surface can be the back surface of the substrate 100.

[0049] In some embodiments, a texturing process may be performed on the first and second surfaces of the substrate 100 to form a pyramid velvet surface on the first and second surfaces of the substrate 100. This can enhance the absorption efficiency of incident light by the first and second surfaces of the substrate 100. In other embodiments, one of the first or second surfaces of the substrate 100 is a pyramid velvet surface, and the other of the first or second surfaces may be a non-pyramid velvet surface, such as a stacked step morphology, so that the film layer formed on the stacked step morphology has a higher density and uniformity, thereby improving the quality of the formed film layer.

[0050] In some embodiments, the solar cell is a TOPCON (Tunnel Oxide Passivated Contact) cell. In other embodiments, the solar cell may also be a PERC (Passivated Emitter and Rear Cell) cell.

[0051] refer to Figures 2 to 5 A doping layer 110 and a passivation layer 120 are formed on the first surface of the substrate 100 and are stacked in sequence along a direction away from the first surface of the substrate 100 . The passivation layer 120 has an area to be laser processed.

[0052] refer to Figures 2 to 3In some embodiments, the doping ion type of the doping layer 110 is the same as the doping ion type of the substrate 100, and the material of the doping layer 110 is at least one of doped amorphous silicon, doped polycrystalline silicon, or doped microcrystalline silicon. In other words, the doping layer 110 can serve as a doped conductive layer of a solar cell, and the doped conductive layer is used to form a field passivation layer 120, wherein the field passivation effect is: forming an electrostatic field pointing to the interior of the substrate 100 at the interface of the substrate 100, causing minority carriers to escape from the interface, thereby reducing the minority carrier concentration and making the carrier recombination rate at the interface of the substrate 100 lower, thereby making the open circuit voltage, short circuit current and fill factor of the solar cell larger, and improving the photoelectric conversion performance of the solar cell. The first gate line electrode is formed in electrical contact with the doped conductive layer, so that the first gate line electrode can collect carriers transmitted to the doped conductive layer.

[0053] In some embodiments, when the doped layer 110 is a doped conductive layer, before forming the doped layer 110, the process further includes forming a tunneling dielectric layer 130, with the tunneling dielectric layer 130 being located between the doped layer 110 and the first surface of the substrate 100. The tunneling dielectric layer 130 and the doped conductive layer can serve as a passivation contact structure. The tunneling layer is in direct contact with the first surface of the substrate 100, thereby achieving interfacial passivation on the first surface of the substrate 100, thereby achieving a chemical passivation effect, promoting recombination of photogenerated carriers, and improving the fill factor and conversion efficiency of the solar cell. In some embodiments, the material of the tunneling dielectric layer 130 can be a dielectric material, such as silicon oxide.

[0054] In some embodiments, the method of forming the tunnel dielectric layer 130 and the doped conductive layer may include:

[0055] refer to Figure 2 A tunneling dielectric layer 130 is formed on the first surface of the substrate 100 using a deposition process, such as a chemical vapor deposition process. In other embodiments, when the tunneling dielectric layer 130 is made of silicon oxide, an in-situ formation process may be used to form the tunneling dielectric layer 130. For example, a thermal oxidation process or a nitric acid passivation process may be used to form the tunneling oxide layer on the first surface of the substrate 100.

[0056] refer to Figure 3 After forming the tunnel dielectric layer 130, a deposition process is used to form an amorphous silicon layer on the surface of the tunnel dielectric layer 130 away from the substrate 100; then a crystallization process is performed on the amorphous silicon layer to convert the amorphous silicon layer into a polycrystalline silicon layer; after forming the polycrystalline silicon layer, a doping process can be performed on the polycrystalline silicon layer to form a doped conductive layer. Specifically, conductive ions, such as phosphorus ions or boron ions, can be doped into the polycrystalline silicon layer by ion implantation or source diffusion.

[0057] refer to Figure 5In other embodiments, the doping ion type of the doping layer 110 is different from the doping ion type of the substrate 100, and the material of the doping layer 110 is the same as the material of the substrate 100. The doping ion type of the doping layer 110 is different from the doping ion type of the substrate 100, so that the doping layer 110 can serve as an emitter and form a PN junction with the substrate 100. The PN junction can receive incident light irradiated onto the first surface of the substrate 100 and generate electron-hole pairs. When the substrate 100 is an N-type substrate 100, the separated electrons move into the substrate 100, and the separated holes move into the emitter. Since the first gate line electrode is in electrical contact with the doping layer 110, the electrons moving into the emitter are collected by the first gate line electrode.

[0058] In some embodiments, a method of forming an emitter may include:

[0059] An initial substrate 100 is provided, and a diffusion process is performed on a surface of the initial substrate 100 to diffuse conductive ions into a portion of the initial substrate 100 to form an emitter. The portion of the initial substrate 100 excluding the emitter forms the substrate 100. In some embodiments, when the substrate 100 is an N-type substrate 100, a boron diffusion process may be performed on the surface of the initial substrate 100. When the substrate 100 is a P-type substrate 100, a phosphorus diffusion process may be performed on the surface of the initial substrate 100.

[0060] It is worth noting that the reference Figure 4 In some embodiments, when the doping layer 110 on the first surface of the substrate 100 is a doped conductive layer, the second surface of the substrate 100 may form an emitter 101; Figure 5 In other embodiments, when the doped layer 110 on the first surface of the substrate 100 serves as an emitter, a tunneling layer 130 and a doped conductive layer 102 may be formed on the second surface of the substrate 100 .

[0061] The passivation layer 120 can effectively passivate the first surface of the substrate 100. For example, it can effectively chemically passivate the dangling bonds on the first surface of the substrate 100, reduce the defect state density on the first surface of the substrate 100, and effectively inhibit carrier recombination on the first surface of the substrate 100. In some embodiments, the passivation layer 120 can have a single-layer structure. In other embodiments, the passivation layer 120 can also have a multi-layer structure. In some embodiments, the material of the passivation layer 120 can be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0062] refer to Figure 4 as well as Figure 5In some embodiments, the method of forming the passivation layer 120 may include: forming the passivation layer 120 on the surface of the doping layer 110 away from the substrate 100 using a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

[0063] refer to Figures 6 to 10 After forming the passivation layer 120, a laser process is performed on the area to be laser processed on the top surface of the passivation layer 120 to form a laser processed area. The laser process converts at least a portion of the thickness of the passivation layer 120 corresponding to the laser processed area into the first modified film layer 10.

[0064] The laser processing area is the area where laser processing is performed, and the passivation layer 120 that has been laser processed is modified so that in the process of the subsequent sintering process, the passivation layer 120 that has been laser processed is more easily burned through. In other words, when the temperature remains unchanged, the sintering depth of the metal slurry in the passivation layer 120 that has been laser processed is deeper. Based on this, when the sintering depth remains unchanged, the sintering temperature can be lowered, thereby preventing the problem of damage to the doped layer 110, the passivation layer 120 or the substrate 100 due to the high sintering temperature. In this way, after the first gate line electrode is subsequently formed, since the damage to the passivation layer 120 and the doped layer 110 is less, the metal composite between the first gate line electrode is smaller, thereby increasing the fill factor, short-circuit current and open-circuit voltage, and improving the photoelectric conversion efficiency of the solar cell.

[0065] It is noteworthy that in the embodiment of the present application, after the laser treatment area is laser treated, the complete morphology of the passivation layer 120 is still preserved, that is, the top surface of the first modified film layer 10 is still flush with the top surface of the untreated passivation layer 120. In this way, the first modified film layer 10 can protect the doped layer 110 and the substrate 100, further preventing damage to the doped layer 110 and the substrate 100 caused by the laser treatment.

[0066] Furthermore, compared to completely etching away the laser-treated passivation layer 120, preserving the intact morphology of the passivation layer 120 can also prevent the laser treatment from damaging the passivation layer 120 and the doped layer 110 in the non-laser-treated areas. This is because if the laser-treated passivation layer 120 is completely etched away, a groove will be formed in the passivation layer 120 and even the doped layer 110. The sidewalls of the groove will expose the passivation layer 120 and a portion of the doped layer 110 in the non-laser-treated areas. As the laser process gradually etches the passivation layer 120 and the doped layer 110, the depth of the groove will become increasingly deeper. The portion of the passivation layer 120 in the non-laser-treated areas that is initially exposed will also be irradiated by the laser, causing damage. This will irreversibly affect the passivation properties of the passivation layer 120 and the doped layer 110, leading to increased metal recombination with the subsequently formed first gateline electrode, thereby reducing the photoelectric conversion performance of the solar cell. Based on this, in the embodiment of the present application, the laser processing area only modifies part of the passivation layer 120 while retaining the complete morphology of the passivation layer 120, thereby reducing the sintering temperature while protecting the complete morphology of the passivation layer 120 and the doping layer 110.

[0067] In some embodiments, the area of the passivation layer 120 other than the laser-processed area is the first area, and the density of the passivation layer 120 in the first area is greater than the density of the first modified film layer 10. The area other than the laser-processed area is the area that has not been laser-processed. In other words, the density of the passivation layer 120 is lower after laser processing, making it easier to burn through the first modified film layer 10 during the subsequent sintering process, thereby reducing the temperature of the sintering process.

[0068] In some embodiments, the parameters of the laser process can be adjusted so that the first modified film layer 10 formed by the laser treatment still retains a complete morphology. In addition, the depth of the laser reaching the passivation layer 120 can be controlled by controlling the laser process, thereby controlling the morphology of the formed first modified film layer 10. Specifically, in some embodiments, the laser power of the laser process can be 15W to 45W, for example, 15W to 20W, 20W to 25W, 25W to 30W, 30W to 35W, 35W to 40W, or 40W to 45W. The laser frequency can be 100kHz to 1500kHz, for example, 100kHz to 300kHz, 300kHz to 600kHz, 600kHz to 1000kHz, 1000kHz to 1200kHz, or 1200kHz to 1500kHz. The laser wavelength may be 250 nm to 1320 nm, for example, 250 nm to 420 nm, 420 nm to 580 nm, 580 nm to 700 nm, 700 nm to 850 nm, 850 nm to 1000 nm, or 1000 nm to 1320 nm. The laser pulse width may be 1 ps to 50,000 ps, for example, 1 ps to 1000 ps, 1000 ps to 5000 ps, 5000 ps to 10,000 ps, 10,000 ps to 18,000 ps, 18,000 ps to 30,000 ps, 30,000 ps to 45,000 ps, or 45,000 ps to 50,000 ps. The laser line scan speed may be 2,000 mm / s to 50,000 mm / s, for example, 2,000 mm / s to 4,000 mm. / s, 4000mm / s to 4500mm / s, 4500mm / s to 6000mm / s, 6000mm / s to 9000mm / s, 10000mm / s to 15000mm / s, 15000mm / s to 20000mm / s, 20000mm / s to 30000mm / s, 30000mm / s to 40000mm / s, 40000mm / s to 45000mm / s or 45000mm / s to 50000mm / s. Within this range, the first modified film layer 10 formed by laser treatment can retain a complete morphology. In addition, within this range, the energy of the laser process is not too high, preventing the laser from reaching the substrate 100 due to excessive energy of the laser process and causing damage to the substrate 100.

[0069] In some embodiments, the laser used in the laser process can be any one of infrared laser, green laser, and ultraviolet laser, and the laser used in laser processing can be any one of CO2 laser, excimer laser, titanium sapphire laser, and semiconductor laser. The embodiments of this application do not specifically limit the specific laser type.

[0070] refer to Figure 6 In some embodiments, the passivation layer 120 has a region to be formed as a first gate line electrode, and the laser-processed region overlaps with the region to be formed as the first gate line electrode. The region to be formed as the first gate line electrode is used to form the first gate line electrode, and the laser-processed region is arranged to overlap with the region to be formed as the first gate line electrode. In other words, during the subsequent sintering process to form the first gate line electrode, all portions of the passivation layer 120 to be sintered are laser-processed, i.e., all portions of the passivation layer 120 to be sintered are modified. In this way, the entire first gate line electrode to be formed is easier to sinter at different positions, thereby making it easier to perform the sintering process in the entire region to be formed as the first gate line electrode, thereby reducing the sintering temperature of the sintering process as a whole.

[0071] refer to Figure 7 In other embodiments, the laser processing area includes: a plurality of spaced-apart second regions 20, and laser processing the laser processing area on the top surface of the passivation layer 120 is performed by laser processing the top surface of the passivation layer 120 in the second regions 20. The laser process can accurately locate the target portion of the passivation layer 120, thereby allowing only the second regions 20 to be processed, while areas outside the second regions 20 are not laser processed. This allows the formed first modified film layer 10 to correspond to the arrangement of the second regions 20, that is, the first modified film layers 10 are also arranged at intervals. In this way, after the first gate line electrode is subsequently formed, the formed first gate line electrode penetrates the corresponding first modified film layer 10 and is electrically connected to the doped layer 110. That is, the first gate line electrode and the doped layer 110 are not in continuous electrical contact, but are in electrical contact with the doped layer 110 at intervals. In this way, damage to the doped layer 110 caused by the first gate line electrode penetrating the doped layer 110 can be reduced.

[0072] In some embodiments, a plurality of second regions 20 are arranged in an array, including: a plurality of columns of second regions 20 spaced apart along a first direction X, and a plurality of columns of second regions 20 spaced apart along a second direction Y, wherein the first direction X is the extension direction of the first gate line electrode, and the second direction Y is the arrangement direction of the plurality of first gate line electrodes. Arranging a column of second regions 20 along the same direction allows for a simplified screen printing stencil structure and a simplified printing process when metal paste is printed on the surface of the passivation layer 120 during the subsequent formation of the first gate line electrode. In some embodiments, a column of multiple second regions 20 spaced apart along the first direction X can correspond to the same first gate line electrode. In this way, during the formation of the first gate line electrode using a sintering process, the passivation layer 120 or even the doping layer 110 corresponding to more second regions 20 is modified, thereby reducing the difficulty of the sintering process and thereby lowering the sintering temperature.

[0073] In some embodiments, a column of second areas 20 is staggered with an adjacent column of second areas 20 in the first direction X; or, a column of second areas 20 is aligned with an adjacent column of second areas 20 in the second direction Y. Staggered arrangement means that each second area 20 in a column of second areas 20 is not opposite to each second area 20 in an adjacent column of second areas 20 in the second direction Y. Aligned arrangement means that a second area 20 in a column of second areas 20 is directly opposite to a second area 20 in an adjacent column of second areas 20 in the second direction Y. Providing a type of second area 20 domain aligned with an adjacent column of second areas 20 along the second direction Y is beneficial to simplifying the laser process. Specifically, in the laser process, it is necessary to set the parameters of the laser beam in advance to determine the effective position of the laser beam. When two adjacent columns of second areas 20 are aligned, the same laser beam parameters can be used to form multiple columns of second areas 20, thereby simplifying the process.

[0074] It is understandable that the embodiment of the present application does not specifically limit the arrangement of the second area 20. In fact, the laser process can be adjusted based on process requirements to form an arrangement of the second area 20 that meets the needs.

[0075] refer to Figure 8 , Figure 8 When the doped layer 110 serves as an emitter, a portion of the passivation layer located on the top surface of the emitter is converted into a modified film layer. In some embodiments, by controlling the laser process parameters to be smaller, the laser process only acts on a portion of the passivation layer 120, thereby only converting a portion of the passivation layer 120 into the first modified film layer 10.

[0076] refer to Figure 9 , Figure 9 This is a schematic diagram of converting a portion of the passivation layer located on the top surface of the doped conductive layer into a modified film layer when the doped layer 110 serves as the doped conductive layer.

[0077] refer to Figure 10 In other embodiments, the laser process parameters can be adjusted so that the laser process acts on the entire thickness of the passivation layer 120 in the laser-processed area, thereby converting the entire thickness of the passivation layer 120 corresponding to the laser-processed area into the first modified film layer 10. In this way, the thickness of the first modified film layer 10 is increased. In the subsequent sintering process so that the formed first gate line electrode penetrates the passivation layer 120 and contacts the doped layer 110, the entire passivation layer 120 to be sintered can be easily burned through, thereby further reducing the sintering process temperature and further minimizing damage to the passivation layer 120, the doped layer 110, and the substrate 100.

[0078] refer to Figure 11In some embodiments, the laser process also converts at least a portion of the doped layer 110 corresponding to the laser-processed area into a second modified film layer 11. Specifically, in some embodiments, the first gate electrode penetrates a portion of the doped layer 110, allowing the side surface of the first gate electrode to form electrical contact with the doped layer 110. Based on this, the laser process can convert the portion of the doped layer 110 that the first gate electrode needs to penetrate into the second modified film layer 11, making it easier to burn through the second modified film layer 11 during the sintering process.

[0079] refer to Figures 12 to 15 After the laser treatment, the process further includes forming a first gate electrode 140 on the first surface of the substrate 100 through a sintering process, wherein at least a portion of the first gate electrode 140 penetrates the first modified film layer 10 and is in electrical contact with the doped layer 110. Because the laser treatment converts a portion of the passivation layer 120 into the first modified film layer 10, which is easier to burn through, the sintering process temperature can be set to a lower level, thereby preventing damage to the doped layer 110, the emitter, or the substrate 100 caused by excessively high sintering temperatures.

[0080] refer to Figure 11 as well as Figure 13 In some embodiments, the laser process also converts at least a portion of the doped layer 110 corresponding to the laser-processed area into a second modified film layer 11, and at least a portion of the first gate electrode 140 penetrates the first modified film layer 10 and electrically contacts the second modified film layer 11. In this way, during the sintering process, all film layers that the first gate electrode 140 needs to penetrate are modified. This can further reduce the temperature required for the sintering process compared to simply converting the passivation layer 120 into the first modified film layer 10. This can further reduce damage to the passivation layer 120, the doped layer 110, and the substrate 100 caused by excessively high sintering temperatures. Furthermore, the laser-processed doped layer 110 still retains its intact morphology, allowing the second modified film layer 11 to protect the unprocessed doped layer 110 and the substrate 100.

[0081] In some embodiments, the passivation layer 120 has a region where the first gate line electrode 140 is to be formed, and the laser processed region at least partially overlaps with the region where the first gate line electrode 140 is to be formed. The sintering process includes:

[0082] A metal paste is printed on the top surface of the passivation layer 120 in the area where the first gate electrode 140 is to be formed. In some embodiments, the metal paste contains highly corrosive components such as glass. During the sintering process, these corrosive components will corrode the passivation layer 120 and portions of the doped layer 110, causing the metal paste to penetrate the passivation layer 120 and portions of the doped layer 110. Because the first modified film layer 10 is more easily burned through, a metal paste with low burn-through properties can be used during the subsequent sintering process. Metal pastes with low burn-through properties contain fewer corrosive components, preventing excessive damage to the passivation layer 120 during the sintering process due to excessive corrosive components in the metal paste, thereby maintaining the passivation performance of the passivation layer 120. In some embodiments, the metal paste can be printed on the top surface of the passivation layer 120 using a screen printing process.

[0083] The metal paste is heat-treated, and at least a portion of the metal paste penetrates the first modified film layer 10 and electrically contacts the doped layer 110. Because the first modified film layer 10 is a laser-treated passivation layer 120, the metal paste is more easily sintered in the first modified film layer 10. Based on this, the temperature used for the heat treatment can be lower while maintaining the sintering depth. This prevents the sintering temperature from being too high and damaging the passivation layer 120 and the doped layer 110, thereby avoiding damage to the passivation layer 120 and the doped layer 110 in the area where the first gate electrode 140 is to be formed. This reduces the metal composite between the formed first gate electrode 140 and the passivation layer 120 and the doped layer 110, thereby improving the fill factor, short-circuit current, and open-circuit voltage, and enhancing the photoelectric conversion performance of the solar cell.

[0084] Specifically, in some embodiments, the heat treatment temperature is 450° C. to 800° C., for example, 450° C. to 550° C., 550° C. to 600° C., 600° C. to 680° C., 680° C. to 750° C., or 750° C. to 800° C. Within this temperature range, the heat treatment temperature is not too high, thereby preventing the sintering process from damaging the passivation layer 120 and the doping layer 110. Furthermore, within this temperature range, the heat treatment temperature is not too low, thereby allowing the metal slurry to burn through to a predetermined depth at this heat treatment temperature.

[0085] In some embodiments, the metal paste has a burn-through depth of 20 nm to 200 nm, for example, 20 nm to 50 nm, 50 nm to 80 nm, 80 nm to 100 nm, 100 nm to 130 nm, 130 nm to 160 nm, or 160 nm to 200 nm. Within this range, the metal paste's burn-through depth is not too deep, thereby preventing damage to the doped layer 110 or even the substrate 100 caused by the metal paste sintering too deeply in the doped layer 110. Furthermore, by setting the burn-through depth to be not too deep, the heat treatment temperature during the sintering process can be correspondingly reduced. Furthermore, within this range, the metal paste's burn-through depth is not too shallow, thereby increasing the contact area between the formed first gate electrode 140 and the doped layer 110, reducing the contact resistance between the first gate electrode 140 and the doped layer 110, improving metal contact recombination, and increasing the carrier transmission rate to the first gate electrode 140.

[0086] refer to Figure 7 In some embodiments, when the laser processing area includes: a plurality of spaced-apart second regions 20, laser processing the laser processing area on the top surface of the passivation layer 120 is: laser processing the top surface of the passivation layer 120 in the second region 20. Based on this process, reference Figure 15In some embodiments, the passivation layer 120 includes a region where the first gateline electrode 140 is to be formed, and the second region 20 overlaps with a portion of the region where the first gateline electrode 140 is to be formed. The first gateline electrode 140 includes a first portion 141 and a second portion 142. The first portion 141 penetrates the first modified film layer 10 in the second region 20 and electrically contacts the doped layer 110, while the second portion 142 contacts a portion of the passivation layer 120 on the side facing the substrate 100. In other words, the portion of the first gateline electrode 140 corresponding to the second region 20 is sintered at a deeper depth, allowing the first portion 141 to form electrical contact with the doped layer 110 and collect carriers in the doped layer 110. The portion of the first gateline electrode 140 corresponding to the region where the first gateline electrode 140 is to be formed, excluding the second region 20, is sintered at a shallower depth, allowing the second portion 142 to penetrate a portion of the passivation layer 120 and contact the passivation layer 120. Since only a portion of the first gateline electrode 140 penetrates the passivation layer 120, damage to the passivation layer 120 caused by the first gateline electrode 140 can be reduced, preserving the relatively intact morphology of the passivation layer 120 and thereby reducing the adverse effects on the passivation performance of the passivation layer 120 caused by the first gateline electrode 140 penetrating the passivation layer 120. In other embodiments, the first gateline electrode 140 may further include a third portion located on the top surface of the passivation layer 120. That is, during the sintering process of the metal paste, since a portion of the passivation layer 120 in the region where the gateline is to be formed has not been laser treated, when the metal paste is sintered at a lower sintering temperature, the metal paste corresponding to the region where the gateline is to be formed that has not been laser treated may not penetrate the passivation layer 120. As a result, the first gateline electrode 140 formed in this region does not form electrical contact with the passivation layer 120, preserving the intact morphology of this portion of the passivation layer 120 and maintaining the good passivation performance of the passivation layer 120.

[0087] The first portion 141 is in electrical contact with the doped layer 110 and is responsible for collecting carriers in the doped layer 110. Therefore, the sintering depth of the first portion 141 needs to be relatively deep, that is, the thickness of the first portion 141 needs to be relatively large. This increases the contact area between the first portion 141 and the doped layer 110, thereby reducing the contact resistance between the first portion 141 and the doped layer 110. This reduces the metal contact recombination between the first portion 141 and the doped layer 110 and improves the carrier collection efficiency of the first gate electrode 140. Furthermore, the sintering depth of the first portion 141 needs to be relatively shallow to prevent the first gate electrode 140 from penetrating the doped layer 110 and damaging the passivation capability of the doped layer 110 and the substrate 100. Based on the above considerations, in some embodiments, the top surfaces of the first portion 141 and the second portion 142 are flush, and the ratio of the thickness of the first portion 141 to the thickness of the second portion 142 is 1.5 to 10, for example, 1.5 to 2, 2 to 3, 3 to 3.5, 3.5 to 4.5, 4.5 to 6, 6 to 7, 7 to 8.5, or 8.5 to 10. Within this range, the thickness of the first portion 141 is greater than the thickness of the second portion 142, allowing the first portion 141 to form a good ohmic contact with the doped layer 110. Furthermore, within this range, the thickness of the first portion 141 is not excessively thick compared to the thickness of the second portion 142, thereby preventing the first portion 141 from penetrating the doped layer 110.

[0088] refer to Figure 16 In some embodiments, the method further includes forming an anti-reflection layer 150 on the second surface. Specifically, in some embodiments, when the doped layer 110 on the first surface is a doped conductive layer, the second surface of the substrate 100 has an emitter 101, and the anti-reflection layer 150 is located on the surface of the emitter away from the substrate 100. In other embodiments, when the doped layer 110 on the first surface is an emitter, the second surface of the substrate 100 has a tunneling layer and a doped conductive layer, and the anti-reflection layer 150 is located on the surface of the doped conductive layer away from the substrate 100. The anti-reflection layer 150 is used to reduce the reflection of incident light by the second surface of the substrate 100, thereby increasing the absorption and utilization rate of the incident light by the substrate 100. In some embodiments, the anti-reflection layer 150 can be a single-layer or multi-layer structure, and the material of the anti-reflection layer 150 can be at least one of aluminum oxide, silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the anti-reflection layer 150 can be formed using a PECVD process.

[0089] In some embodiments, the process further includes forming a second gateline electrode 160, with the second gateline electrode 160 being located on the second surface of the substrate 100. In some embodiments, when the second surface of the substrate 100 has an emitter, the second gateline electrode 160 penetrates the anti-reflection layer 150 and electrically contacts the emitter. In other embodiments, when the second surface of the substrate 100 has a doped conductive layer, the second gateline electrode 160 penetrates the anti-reflection layer 150 and electrically contacts the doped conductive layer. It is worth noting that the method for forming the second gateline electrode 160 can be the same as the method for forming the first gateline electrode 140. That is, a laser process can be performed on the second surface of the substrate 100 to modify at least a portion of the anti-reflection layer 150, and then a sintering process can be used to sinter the metal paste to form the second gateline electrode 160. For specific methods, refer to the description of forming the first gateline electrode 140.

[0090] In the solar cell fabrication method provided in the above-described embodiment, a laser treatment is performed on the laser-treated region on the top surface of the passivation layer 120, converting at least a portion of the passivation layer 120 into the first modified film layer 10. In other words, the laser treatment does not remove part of the passivation layer 120, but rather preserves the intact morphology of the laser-treated passivation layer 120. The modified passivation layer 120 after laser treatment makes it easier to burn through the first modified film layer 10 during the sintering process to form the first gate electrode 140. This allows for a lower sintering temperature, thereby preventing damage to the doped layer 110, emitter, or substrate 100 caused by excessively high sintering temperatures. Furthermore, because the intact morphology of the passivation layer 120 is preserved after laser treatment, damage to the substrate 100 and the passivation layer 120 corresponding to the non-laser-treated region can be reduced.

[0091] Although the present application is disclosed as above with preferred embodiments, it is not intended to limit the claims. Any person skilled in the art may make several possible changes and modifications without departing from the concept of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims of the present application.

[0092] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A method for preparing a solar cell, characterized in that: include: providing a substrate having a first surface; forming a doping layer and a passivation layer stacked in sequence along a direction away from the first surface of the substrate on the first surface of the substrate, wherein the passivation layer has an area to be laser processed; Performing a laser process on a region to be laser processed on the top surface of the passivation layer to form a laser processed region, wherein the laser process converts at least a portion of the thickness of the passivation layer corresponding to the laser processed region into a first modified film layer, the passivation layer having a region to be formed with a first gate line electrode, and the laser processed region at least partially overlaps with the region to be formed with the first gate line electrode; A first gate line electrode is formed on the first surface of the substrate by using a sintering process, and at least a portion of the first gate line electrode penetrates the first modified film layer and is in electrical contact with the doping layer.

2. The method for preparing a solar cell according to claim 1, wherein: The laser power of the laser process is 15W to 45W, the laser frequency is 100kHz to 1500kHz, the laser wavelength is 250nm to 1320nm, the laser pulse width is 1ps to 50000ps, and the laser line scanning speed is 2000mm / s to 50000mm / s.

3. The method for preparing a solar cell according to claim 1 or 2, wherein: The sintering process includes: printing metal paste on the top surface of the passivation layer in the area where the first gate line electrode is to be formed; The metal paste is heat-treated, so that at least a portion of the metal paste penetrates the first modified film layer and electrically contacts the doping layer.

4. The method for preparing a solar cell according to claim 3, wherein: The heat treatment temperature is 450°C to 800°C.

5. The method for preparing a solar cell according to claim 4, wherein: The burn-through depth of the metal slurry is 20 nm to 200 nm.

6. The method for preparing a solar cell according to claim 1 or 2, characterized in that: The area of the passivation layer other than the laser processed area is a first area, and the density of the passivation layer in the first area is greater than the density of the first modified film layer.

7. The method for preparing a solar cell according to claim 1, wherein: The area to be laser processed includes: a plurality of spaced-apart second regions, and laser processing the area to be laser processed on the top surface of the passivation layer is: laser processing the top surface of the passivation layer in the second regions.

8. The method for preparing a solar cell according to claim 7, wherein: The passivation layer has a region where a first gate line electrode is to be formed, the second region overlaps with a portion of the region where the first gate line electrode is to be formed, the first gate line electrode includes: a first part and a second part, the first part penetrates the first modified film layer in the second region and is in electrical contact with the doped layer, and the second part contacts a portion of the passivation layer on a side facing the substrate.

9. The method for preparing a solar cell according to claim 8, wherein: The top surfaces of the first portion and the second portion are flush with each other, and the ratio of the thickness of the first portion to the thickness of the second portion is 1.5-10.

10. The method for preparing a solar cell according to claim 7, wherein: Multiple second regions are arranged in an array, including: multiple columns of second regions arranged at intervals along a first direction, multiple columns of second regions arranged at intervals along a second direction, the first direction is the extension direction of the first gate line electrode, and the second direction is the arrangement direction of multiple first gate line electrodes.

11. The method for preparing a solar cell according to claim 10, wherein: The second regions in one column are staggered with the second regions in an adjacent column in the first direction; or the second regions in one column are aligned with the second regions in an adjacent column in the second direction.

12. The method for preparing a solar cell according to claim 1, wherein: The laser process also converts at least a portion of the doped layer corresponding to the laser processed area into a second modified film layer, and at least a portion of the first gate line electrode penetrates the first modified film layer and is in electrical contact with the second modified film layer.

13. The method for preparing a solar cell according to claim 3, wherein: The area to be laser processed overlaps with the area to be formed with the first gate line electrode.

14. The method for preparing a solar cell according to claim 1, wherein: The doping ion type of the doping layer is the same as the doping ion type of the substrate, and the material of the doping layer is at least one of doped amorphous silicon, doped polycrystalline silicon or doped microcrystalline silicon.

15. The method for preparing a solar cell according to claim 14, wherein: Also includes: A tunneling dielectric layer is formed, wherein the tunneling dielectric layer is located between the doping layer and the first surface of the substrate.

16. The method for preparing a solar cell according to claim 1, wherein: The doping ion type of the doping layer is different from the doping ion type of the substrate, and the material of the doping layer is the same as that of the substrate.

17. The method for preparing a solar cell according to claim 1, wherein: The material of the passivation layer is at least one of silicon oxide, silicon nitride, aluminum oxide or silicon oxynitride.

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