General calibration system and method for DAC sampling system transmission path delay error

Abstract

The application discloses a universal calibration system and method for transmission path delay error of a DAC sampling system, belongs to the field of DAC sampling, and comprises the following steps: injecting a sampling clock; converting a digital signal into an analog signal output through a multi-channel input DA chip; and connecting the DA with an FPGA through a serial peripheral interface. The FPGA is used to realize first-stage speed-up through parallel-to-serial conversion primitives or a parallel-to-serial conversion IP core, and the DA is used to realize second-stage speed-up by synthesizing multiple-phase signals. According to the sampling rate of the DA and a parallel-to-serial conversion coefficient, the FPGA is configured to send a test signal with a corresponding frequency, the FPGA dynamically sets an output delay control primitive through a virtual IO to output a time delay parameter, the phase relationship of data lines is observed at a DA data receiving end, all data lines in a channel and among channels are aligned, the FPGA sends an actual signal by completing digital signal source switching, and output delay calibration is completed. The application can adapt to the fact that DA data line PCB wiring is not processed to be equal in length, and can correct data output delay.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of DAC sampling, more particularly, to a general calibration system and method for transmission path delay error of a DAC sampling system. BACKGROUND

[0002] At present, modern electronic signals show the characteristics of complexity and diversity, especially the rapid growth of wideband and non-stationary characteristics. The frequency domain test instrument mainly based on sweep frequency has been increasingly difficult to meet the seamless testing requirements of wideband and transient signals. High-precision sampling has become a bottleneck problem of modern time-domain test instruments. The higher the sampling rate and sampling accuracy, the stronger the signal restoration capability. In recent years, the sampling rate of DAC has been greatly improved, but it is still difficult to balance high speed and high precision, which is limited by the manufacturing process of analog devices at the present stage. With the popularization of digital technology, higher and higher requirements are put forward for the sampling rate and sampling accuracy of digital-to-analog converter (DAC). Not only does the data acquisition system require high sampling rate, but also high sampling accuracy. In practical applications, the high dependence on real-time sampling rate and sampling accuracy has become a bottleneck problem of modern time-domain test instruments. The maximum sampling rate of DAC is limited by its resolution: high sampling rate requires short conversion time, while high resolution requires long conversion time, which is a pair of contradictions between resolution and sampling rate. The restriction between the two has become the main factor for the slow development of DAC technology; meanwhile, factors such as materials and chip technology also limit the rapid improvement of DAC technology indicators.

[0003] The parallel sampling structure of DAC (TIDAC) introduces channel mismatch while improving the sampling rate, which produces various errors. The introduction of these errors leads to non-uniform sampling and seriously reduces the performance of the DAC system. In theory, time-alternating sampling can well solve the contradiction between high sampling rate and high resolution, but in practical applications, channel mismatch errors caused by process, clock delay, inconsistent power supply, etc. of each DA chip will cause spectrum clutter, which greatly reduces the performance. The error is mainly the time phase error caused by the inconsistency of channel delay. The existence of channel mismatch error will seriously reduce the signal-to-noise ratio (SINAD) and the spurious-free dynamic range (SFDR) of the system. Due to the phase delay of the sampling clock between channels, it is difficult to be accurate and unbiased, which will lead to non-uniform sampling of the sampling signal and seriously reduce the system performance. Whether high-speed DAC devices or high-speed time-domain test instruments apply the parallel alternating sampling technology TIDAC, it is difficult to achieve high precision at high sampling speed, and the effective number of bits is still low, which is limited by the inherent error of the TIDAC sampling technology.

[0004] TIDAC is one of the effective methods to improve the sampling rate of digital-to-analog conversion system. However, this method brings channel mismatch error while improving the sampling rate. The time error between channels is the main source of non-uniform error. With the further improvement of the sampling rate requirement, the number of parallel channels will gradually increase, and the resources consumed by the correction of channel mismatch error will rise exponentially. In order to realize higher speed sampling, the high-speed sampling operation of the parallel DAC sampling system is realized by alternately sampling the same input data sample through multiple parallel channels. This increases the number of channels of the DAC system, which will inevitably increase the difficulty of system design. The existing technology often uses time interleaving parallel sampling of multi-channel DA chip to improve the sampling rate. That is, the parallel alternately sampling of M-channel DA chip with a sampling rate of f s / M is used, and the sampling clock between channels has a phase difference of 360 / M degrees. After splicing the parallel data obtained by sampling, the sampling rate of the whole sampling system can be equivalent to f s In the parallel DAC sampling system, the manufacturing process between the internal channels of the DA chip cannot be completely the same, which will introduce non-uniform error. When the PCB is designed, the distribution positions of the IO pins of the FPGA are different, which leads to the inconsistency of the time from the IO pin to the latch in the FPGA, and also introduces non-uniform error. On the printed circuit board, the paths between DA and FPGA may introduce non-uniform error due to via, impedance mismatch, etc. In short, multiple stages may cause inconsistent time delay of parallel multi-channel sampling data, which presents non-uniform sampling when the FPGA performs data splicing processing, that is, the data alignment problem. When the DA sampling rate is high, this problem is particularly obvious, which seriously affects the performance of the sampling system. SUMMARY

[0005] The purpose of the present application is to overcome the shortcomings of the prior art, provide a general calibration system and method for transmission path delay error of DAC sampling system, which can adapt to the change of sampling frequency and correct the transmission path delay error of DA sampling data from the latch in the FPGA.

[0006] The purpose of the present application is achieved by the following scheme:

[0007] A general calibration system for transmission path delay error of DAC sampling system, comprising: a clock source CLK, an output signal S, an integrated M-channel high-speed digital-to-analog conversion DA chip, a large-scale programmable gate array FPGA and a built-in program of the FPGA.

[0008] The digital signal transmitted by the clock source CLK and the FPGA configuration is converted by the integrated M-channel high-speed digital-to-analog conversion DA chip. The FPGA configures the DA chip through the SPI interface, and the FPGA connects the DA chip through the high-speed parallel interface to form a high-speed sampling system.

[0009] The FPGA uses high-speed parallel-to-serial conversion primitives OSERDES or parallel-to-serial conversion IP core SelectIO to convert parallel data into serial data and inject the serial data into the DA chip, so as to realize the first-stage speed increase; the DA chip is configured by the FPGA, so as to complete multi-phase synthesis of multi-channel input digital signals, realize parallel-to-serial conversion, and realize the second-stage speed increase.

[0010] The FPGA built-in program sends a test signal with a corresponding multi-frequency division frequency according to a sampling rate of the DA chip, sets a virtual input and output, controls a DAC data line output delay in real time, dynamically sets a delay value into a FPGA delay control statement, and observes whether phases of output digital signals are consistent through an oscilloscope, so as to adjust a compensation delay value required for equal length of each data line in real time and complete the whole calibration.

[0011] Further, the first-stage speed increase is completed by the FPGA, which converts multiple parallel branch data into serial data through the high-speed parallel-to-serial conversion primitives OSERDES or the parallel-to-serial conversion IP core SelectIO, so as to realize the first-stage speed increase.

[0012] Further, the second-stage speed increase is completed by the DA chip, and the FPGA configures the DA chip through an SPI interface to realize multi-phase synthesis of multi-channel digital signal sources, so as to realize the second-stage speed increase.

[0013] Further, a sampling frequency of the clock source CLK is fs and does not exceed a highest sampling rate of the DA chip.

[0014] Further, the FPGA built-in program is realized by a state machine design idea, and specifically, the state machine is divided into an idle state Idle, a DA multi-phase synthesis configuration state Synthesis, a FPGA test signal sending state Test_in, a delay parameter calibration state Align, a DA data line injection alignment judgment state Judgment, and a FPGA actual digital signal sending state Test_out.

[0015] A universal calibration method for a transmission path delay error of a DAC sampling system, based on the system as described above, and comprising the following steps:

[0016] S1, the high-speed sampling system is powered on, after the FPGA program is loaded, a reset signal pulse is generated to make the state machine in an idle state Idle; when the system is powered on for the first time, a clock period is waited or a sampling clock is changed, the state machine jumps into the Synthesis state, and the FPGA sends a configuration pulse to complete the multi-phase synthesis of the DA.

[0017] S2, after the configuration is completed, the state machine enters a Test_In state, the FPGA sends a test signal of a corresponding multi-path frequency division frequency according to a DA chip sampling rate; after the test signal is sent, the state machine enters an Align state, a time delay calibration is started, a virtual IO is set to control a time delay of each data line, and a dynamic time delay control statement is inserted;

[0018] S3, after the time delay parameter is controlled, the state machine enters a JudgeMent state, whether all data lines of the DA are aligned after calibration is observed through an oscilloscope; if not all are aligned, the Align state is returned, the time delay parameter of the data line that is not aligned is adjusted, and whether the data line is aligned is judged again; if all data lines of the DA are aligned, the state machine enters a Test_Out state, the FPGA switches a digital signal source, and sends an actual signal;

[0019] S4, after the digital signal source is switched successfully, the state machine returns to the Idle state, a cycle of the time delay parameter calibration is completed, and the next process is started.

[0020] Further, after step S4, the following steps are included:

[0021] S5, after the time delay parameter calibration is completed, the FPGA can configure and send a plurality of actual signals, and the plurality of actual signals include a point frequency signal and a modulated signal.

[0022] Further, in step S1, the following sub-step is included: after the high-speed sampling system is powered on, a high and low pulse reset signal is generated in the FPGA as needed, the reset is completed to enter the idle state, and a clock period or a sampling frequency change is waited for; when the clock period or the sampling frequency change is waited for for the first time, the state machine jumps into a DA configuration multi-phase synthesis state, and after the configuration is completed, the FPGA configuration test sequence state Test_In is entered.

[0023] Further, in step S2, the following sub-step is included: in the Test_In state, the FPGA sends a test signal of a corresponding multi-path frequency division frequency according to a DA chip sampling rate, a virtual logic analyzer ILA is added in the FPGA to observe whether the test signal is successfully sent, when it is observed that the parallel multi-path data are all test signals, it is indicated that the FPGA configuration test signal is successfully sent, a time delay calibration instruction is started, and the time delay parameter calibration Align state is entered.

[0024] Further, in step S3, the sub-step of: in the Align state, by setting a virtual IO in the FPGA program, controlling the DAC data line output delay in real time, and dynamically placing the delay value into the FPGA delay control statement ODELAY, observing whether the phases of the data lines injected by the FPGA output to the DA are consistent through the oscilloscope at the DA end, and adjusting the compensation delay value required for equal length of each data line in real time, is included. After the delay parameter is dynamically placed into the delay statement, it is judged whether the calibrated DA data lines are aligned JudgeMent. If the DA data lines are uneven, it is jumped to the Align state to calibrate again. If the DA data lines are all aligned, it is jumped to the FPGA configuration to send the actual signal state Test_Out. In the Test_Out state, the FPGA completes the digital signal source switching and sends the actual signal. At this time, the DA outputs the actual sampling signal, and the state machine enters the idle state Idle to complete a cycle of input delay self-calibration at the current sampling frequency. When the sampling clock of the system changes, the delay calibration process is started again.

[0025] The beneficial effects of the present application include:

[0026] The hardware system of the present application is simple in structure. The present application adopts a two-stage speed-up core architecture design. The high-speed sampling system is composed of four parts: a clock source CLK, a signal source S, an integrated M-channel high-speed analog-to-digital conversion DA chip, and a large-scale programmable gate array FPGA. The DA chip is connected to the FPGA through a serial peripheral interface SPI, and the specific configuration of the DA is realized through the FPGA. The parallel-to-serial conversion is realized through the high-speed parallel-to-serial conversion primitive OSERDES or the parallel-to-serial conversion IP core SelectIO, realizing the first-stage speed-up. The second-stage speed-up is realized through the FPGA configuration of the DA as a multi-phase synthesis of parallel multi-channel input signals. In the first-stage speed-up implementation, the number of parallel channels is increased, which can further reduce the clock frequency of the branch signal, facilitate the internal logic processing of the FPGA chip, and reduce the timing pressure.

[0027] The software program design idea of the present application is clear and easy to implement. The program architecture of the state machine makes the delay calibration process more hierarchical, which is beneficial to the control of the FPGA on the DA and the expansion of the subsequent state, and at the same time enhances the readability and standardization of the program. The virtual IO (VIO) is set in the FPGA program to control the DAC data line output delay in real time, and the delay value is dynamically placed into the FPGA delay control statement. Whether the phases of the output digital signals are consistent is observed through the oscilloscope, and the compensation delay value required for equal length of each data line is adjusted in real time to complete the entire calibration.

[0028] The present application can adapt to the change of the sampling frequency of the sampling system, and can also realize effective compensation of the output delay in the high-speed variable sampling system. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0030] Figure 1 The hardware architecture block diagram of the high-speed DAC sampling system in the embodiment of the present application is shown in the figure.

[0031] Figure 2 The jump chart of the output delay calibration state machine realized by the FPGA in the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0032] All the features disclosed in the embodiments of the present specification, or all the steps of the methods or processes impliedly disclosed, can be combined and / or extended, replaced, or substituted with any other features or steps, except for those mutually exclusive features and / or steps.

[0033] In order to solve the problems in the background, the inventors of the present application found that: at present, the realization of high-speed DAC sampling is mainly based on the parallel time round-robin sampling mode, and the delay parameters of the DAC are mostly avoided in the hardware design, requiring the data lines between the FPGA and the DAC to be equal in length. The DAC chip internally has a polyphase processing function, which can correct the time delay of the polyphase input digital signal and ensure correct sampling. However, under the condition that the data lines between the FPGA and the DAC are not equal in length, how to correct the transmission path delay error of the DA sampling data from the internal latch of the FPGA has not been solved, and the present application aims to provide a corresponding solution.

[0034] In order to solve the above technical problems, the embodiment of the present application provides a general calibration system and method for transmission path delay error of a DAC sampling system, which relates to the alignment and calibration of multi-channel parallel data output delay of a high-speed sampling system composed of a FPGA and a high-speed parallel interface DAC device. Specifically, under the condition that the data lines between the FPGA and the DAC are not equal in length in the PCB design, a general calibration method is provided, which can adapt to the change of sampling frequency and correct the transmission path delay error of the DA sampling data from the internal latch of the FPGA.

[0035] As Figure 1As shown, according to the embodiment concept of the application, the clock source CLK and the digital signal transmitted by the FPGA configuration are transmitted through one integrated M-channel high-speed digital-to-analog conversion DA chip, the FPGA configures the DA chip through an SPI interface, and the large-scale programmable gate array FPGA is connected with the DA chip through a high-speed parallel interface to form a high-speed sampling system; the FPGA uses a high-speed parallel-to-serial conversion primitive OSERDES or a parallel-to-serial conversion IP core SelectIO to convert parallel data into serial data and inject the serial data into the DA chip, so as to realize first-stage speed increase; the FPGA configures the DA chip, so as to complete multi-phase synthesis of the multi-channel input digital signal, realize parallel-to-serial conversion, and realize second-stage speed increase. The FPGA built-in program transmits a signal of a corresponding multi-channel frequency division frequency according to the sampling rate of the DA chip, sets a virtual input and output (VIO), controls the output delay of the DAC data line in real time, dynamically sets the delay value into the FPGA delay control statement, and observes whether the phases of the output digital signals are consistent through an oscilloscope, adjusts the compensation delay value required for equal length of each data line in real time, and completes the whole calibration.

[0036] In the specific implementation process, the high-speed sampling system includes a hardware architecture part and a software implementation part, the hardware architecture part includes a clock source CLK with a sampling frequency fs not exceeding the highest sampling rate of a DA, an output signal S, an integrated M-channel high-speed analog-to-digital conversion DA chip, and a large-scale programmable gate array FPGA, wherein the clock source CLK and the FPGA digital signal source are transmitted through one integrated M-channel high-speed analog-to-digital conversion DA chip, and the DA chip is connected with the large-scale programmable gate array (FPGA) through a serial peripheral interface (SPI). The whole hardware architecture adopts a two-stage speed increase design, the FPGA uses a high-speed parallel-to-serial conversion primitive OSERDES or a parallel-to-serial conversion IP core SelectIO to convert low-speed parallel data into high-speed serial data, realizes first-stage speed decrease, the FPGA configures the DA chip through a serial port SPI, completes synthesis of multi-phase digital signals, realizes parallel-to-serial conversion, and realizes second-stage speed increase.

[0037] The high-speed sampling system adopts a two-stage speed increase hardware architecture design, the first-stage speed increase design is completed by the FPGA, the Serdes_1, Serdes_M+1,..., and Serdes_(N-1)M+1 multi-parallel branch data are converted into serial data through a high-speed parallel-to-serial conversion OSERDES primitive or a parallel-to-serial conversion IP core SelectIO, and the clock frequency of each branch is 1 / (M*N) of the system sampling rate, so as to realize first-stage speed increase. The second-stage speed increase design is completed by the DA chip, the FPGA configures the DA chip through an SPI, multi-channel digital signal sources are synthesized in multiple phases, the DAC1, DAC2, DAC3,..., and DACM are connected in parallel through the SPI, and the multi-channel digital signal sources are converted into serial data through the DAC1, DAC2, DAC3,..., and DACM, so as to realize second-stage speed increase. MThe phase relationship between the channels corresponds to 0*360° / M, 1*360° / M, 2*360° / M, …, (M-1)*360° / M respectively, and the sampling rate of each channel is 1 / M of the system sampling rate, so as to realize the second speed-up.

[0038] In the software implementation part, the state machine design idea is adopted. The FPGA program adopts the state machine. The state machine is divided into an idle state Idle, a DA multiphase synthesis state Synthesis, an FPGA test signal sending state Test_in, a time delay parameter calibration state Align, a state Judgment for judging whether the DA data lines are aligned, and an FPGA actual digital signal sending state Test_out. The FPGA built-in program sends the test signal of the corresponding multiphase frequency signal according to the DA chip sampling rate, sets the virtual IO (VIO), controls the DAC data line output delay in real time, and dynamically sets the delay value into the FPGA delay control statement (ODELAY). Whether the phases of the data lines injected by the FPGA are consistent is observed through the oscilloscope, the compensation delay value required for the equal length of each data line is adjusted in real time, and the whole calibration is completed. After the time delay parameter calibration is completed, the FPGA can send the actual signal of multiple channels, which can be a simple point frequency signal or a complex modulated signal.

[0039] In the specific implementation process, the complete calibration process of the software implementation part is as follows: after the high-speed sampling system is powered on and the FPGA program is loaded, a reset signal pulse is generated to make the state machine in the idle state; when the first power-on waits for a clock period or the sampling clock changes, the state machine jumps into the Synthesis state, and the FPGA sends the configuration pulse to complete the multiphase synthesis of the DA; after the configuration is completed, the state machine enters the Test_In state, and the FPGA sends the test signal of the corresponding multiphase frequency according to the DA chip sampling rate; after the test signal is sent, the state machine enters the Align state, starts the time delay calibration, sets the virtual IO (VIO) to control the delay of each data line, and dynamically sets the delay control statement; after the time delay parameter is controlled, the state machine enters the Judgment state, and whether all the DA data lines are aligned after calibration is observed through the oscilloscope; if not, return to the Align state, adjust the time delay parameter of the unaligned data line, and then judge whether the data line is aligned; if all the DA data lines are aligned, the state machine enters the Test_Out state, the FPGA switches the digital signal source, and sends the actual signal; after the digital signal source is successfully switched, the state machine returns to the Idle state, completes the cycle of the time delay parameter calibration, and waits for the start of the next process.

[0040] Further elaboration is as follows: Figure 2As shown, in the software implementation part, based on the state machine design idea, the FPGA implementation output time delay calibration state machine jump, specifically including the following steps: after system power on, FPGA internal on-demand generation of a high, low pulse reset signal, reset complete into an empty waiting state (Idle), waiting for a clock period or sampling frequency change; the first power on waiting for a clock period or sampling frequency change, state machine jump into the DA configuration polyphase synthesis state Synthesis state, configuration complete into FPGA configuration test sequence state (Test_In); in Test_In state, FPGA according to DA chip sampling rate sends corresponding test signal of multi-channel frequency divider frequency, in FPGA add virtual logic analyzer (ILA) to observe whether the test signal is successfully sent, when observing that the parallel multi-channel data is all test signal, indicating that FPGA configuration sends test signal successfully, start delay calibration instruction, enter the delay parameter calibration Align state. In Align state, through the setting of virtual IO (VIO) in FPGA program, real-time control DAC data line output delay, and the delay value is dynamically placed into FPGA delay control statement (ODELAY), through oscilloscope observation DA end whether the phase of FPGA output injection DA data line is consistent, real-time adjustment of each data line equal length need compensation delay value; when the delay parameter is dynamically placed into the delay statement, judge whether the calibrated DA data line is aligned (JudgeMent), if the DA data line is uneven, jump to Align state again for calibration; if the DA data line has been aligned, jump to FPGA configuration to send actual signal state Test_Out. In Test_Out state, FPGA completes the digital signal source switching, sends the actual signal, at this time DA outputs the actual sampling signal, the state machine enters the empty waiting state Idle, completes the input time delay self-calibration cycle under the current sampling frequency. When the system sampling clock changes, the time delay calibration process needs to be started again.

[0041] The method of the embodiment of the application comprises the following steps: an external sampling clock is injected, a digital signal is converted into an analog signal output through a multi-channel input DA chip, and the DA is connected with an FPGA to form a high-speed sampling system through a serial peripheral interface. The FPGA uses parallel-serial conversion primitives or parallel-serial conversion IP cores to realize first-stage speed-up, and the DA realizes second-stage speed-up by synthesizing multiple-phase signals. According to the sampling rate fs of the DA chip and the coefficient N of parallel-serial conversion, the FPGA configures to send a test signal of fs / (N*M), the FPGA dynamically sets the time delay parameter to an output delay control primitive through a virtual IO, and the phase relationship of data lines is observed at the data receiving end of the DA chip through an oscilloscope. All data lines in the channel and between channels are aligned, the FPGA sends an actual signal by switching the digital signal source, and the output delay calibration of the system is completed. The application provides a general calibration scheme capable of adapting to the non-equal-length processing of DA data line PCB wiring and correcting data output delay.

[0042] Embodiment 1

[0043] A general calibration system for transmission path delay error of a DAC sampling system, characterized by comprising: a clock source CLK, an output signal S, an integrated M-channel high-speed analog-to-digital conversion DA chip, a large-scale programmable gate array FPGA and an FPGA built-in program.

[0044] The clock source CLK and the digital signal configured to be sent by the FPGA pass through the integrated M-channel high-speed digital-to-analog conversion DA chip, the FPGA configures the DA chip through an SPI interface, and the FPGA connects the DA chip to form a high-speed sampling system through a high-speed parallel interface.

[0045] The FPGA uses high-speed parallel-serial conversion primitives OSERDES or parallel-serial conversion IP cores SelectIO to convert parallel data into serial data and inject the serial data into the DA chip, so as to realize first-stage speed-up. The FPGA configures the DA chip to complete the multi-phase synthesis of multi-channel input digital signals, realize parallel-serial conversion, and realize second-stage speed-up.

[0046] The FPGA built-in program sends a test signal of a corresponding multi-frequency division frequency according to the sampling rate of the DA chip, sets a virtual input and output, controls the DAC data line output delay in real time, dynamically sets the delay value into the FPGA delay control statement, observes whether the phases of the output digital signals are consistent through an oscilloscope, adjusts the compensation delay value required for equal length of each data line in real time, and completes the entire calibration.

[0047] Embodiment 2

[0048] On the basis of embodiment 1, the first-stage speed-up is completed by the FPGA, which converts multiple parallel branch data into serial data through the high-speed parallel-serial conversion primitives OSERDES or parallel-serial conversion IP cores SelectIO, so as to realize the first-stage speed-up.

[0049] Embodiment 3

[0050] On the basis of Embodiment 1, the second-stage speed-up design is completed by a DA chip, and the FPGA configures the DA chip through an SPI interface to perform multi-phase synthesis on a multi-channel digital signal source, thereby realizing the second-stage speed-up.

[0051] Embodiment 4

[0052] On the basis of Embodiment 1, the sampling frequency of the clock source CLK is fs and does not exceed the highest sampling rate of the DA chip.

[0053] Embodiment 5

[0054] On the basis of Embodiment 1, the FPGA built-in program is realized by using a state machine design idea, and specifically, the state machine is divided into an empty waiting state Idle, a DA multi-phase synthesis configuration state Synthesis, an FPGA test signal sending state Test_in, a time delay parameter calibration state Align, a DA data line alignment judgment state Judgment, and an FPGA actual digital signal sending state Test_out.

[0055] Embodiment 6

[0056] A general calibration method for transmission path delay error of a DAC sampling system, based on the system as described in Embodiment 5, and comprising the following steps:

[0057] S1, after the high-speed sampling system is powered on and the FPGA program is loaded, a reset signal pulse is generated to make the state machine in an empty waiting state Idle; when the system is powered on for the first time or the sampling clock changes, the state machine jumps into the Synthesis state, and in the Synthesis state, the FPGA sends a configuration pulse to complete the multi-phase synthesis of the DA;

[0058] S2, after the configuration is completed, the state machine enters the Test_In state, and the FPGA sends test signals of corresponding multi-frequency division frequencies according to the sampling rate of the DA chip; after the test signals are sent, the state machine enters the Align state, starts time delay calibration, sets a virtual IO to control the time delay of each data line, and dynamically inserts a time delay control statement;

[0059] S3, after the time delay parameters are controlled, the state machine enters the Judgment state, and whether all the data lines of the DA are aligned is observed by capturing waveforms through an oscilloscope; if not, the Align state is returned, the time delay parameters of the unaligned data lines are adjusted, and then whether the data lines are aligned is judged again; if all the data lines of the DA are aligned, the state machine enters the Test_Out state, and the FPGA switches the digital signal source to send actual signals;

[0060] S4, after the digital signal source is switched successfully, the state machine returns to the Idle state, a cycle of time delay parameter calibration is completed, and the next process is started.

[0061] Embodiment 7

[0062] On the basis of embodiment 6, after step S4, the following steps are included:

[0063] S5, after the time delay parameter calibration is completed, the FPGA can configure to send a plurality of actual signals, and the plurality of actual signals include a point frequency signal and a modulated signal.

[0064] Embodiment 8

[0065] On the basis of embodiment 6, in step S1, the following sub-step is included: after the high-speed sampling system is powered on, a high and low pulse reset signal is generated in the FPGA as needed, the reset is completed to enter the idle state, and a clock period or a sampling frequency change is waited for; when the first power-on waits for a clock period or a sampling frequency change, the state machine jumps into the DA configuration multi-phase synthesis state, and after the configuration is completed, the FPGA configuration test sequence state Test_In is entered.

[0066] Embodiment 9

[0067] On the basis of embodiment 6, in step S2, the following sub-step is included: in the Test_In state, the FPGA sends a test signal of a corresponding plurality of frequency division frequencies according to the DA chip sampling rate, a virtual logic analyzer ILA is added in the FPGA to observe whether the test signal is successfully sent, when it is observed that the parallel plurality of data are all test signals, it is indicated that the FPGA configuration to send the test signal is successful, a time delay calibration instruction is started, and the time delay parameter calibration Align state is entered.

[0068] Embodiment 10

[0069] Based on the embodiment 6, in the step S3, the sub-step of including is comprised: in the Align state, the output delay of the DAC data line is controlled in real time by setting the virtual IO in the FPGA program, and the delay value is dynamically set in the FPGA delay control statement ODELAY, whether the phases of the data lines injected by the FPGA output to the DA are consistent is observed by the oscilloscope at the DA end, and the compensation delay value required for the real-time adjustment of the equal length of each data line is observed; after the delay parameter is dynamically set in the delay statement, whether the calibrated DA data lines are aligned is judged, if the DA data lines are uneven, the state is jumped to the Align state to calibrate again; if the DA data lines are all aligned, the state is jumped to the FPGA configuration to send the actual signal state Test_Out; in the Test_Out state, the FPGA completes the digital signal source switching and sends the actual signal, at this time, the DA outputs the actual sampling signal, the state machine enters the idle state Idle, and the cycle of the input delay self-calibration under the current sampling frequency is completed; when the sampling clock of the system changes, the delay calibration process needs to be started again.

[0070] The units described in the embodiments of the present application can be implemented in the form of software, or can be implemented in the form of hardware, and the described units can also be arranged in a processor. In some cases, the names of these units do not constitute a limitation on the units themselves.

[0071] According to an aspect of the present application, a computer program product or computer program is provided, which includes computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device executes the method provided in the various optional implementation manners described above.

[0072] As another aspect, the present application also provides a computer readable medium, which can be included in the electronic device described in the above embodiments, or can exist independently without being assembled into the electronic device. The computer readable medium carries one or more programs, which, when executed by the electronic device, enable the electronic device to implement the method described in the above embodiments.

[0073] The parts not involved in the present application are the same as or can be realized by the prior art.

[0074] The above technical solution is only one embodiment of the present application, and for those skilled in the art, on the basis of the application disclosed application method and principle, various types of improvements or variations can be easily made, and are not limited to the method described in the above embodiment of the present application, therefore the above described method is only preferred, and does not have the meaning of limitation.

[0075] In addition to the above examples, those skilled in the art can obtain other embodiments by being inspired or modified according to the above disclosure or by utilizing the knowledge or technology in the related field, the features of each embodiment can be interchanged or replaced, and the modifications and changes made by those skilled in the art do not deviate from the spirit and scope of the present application, and therefore should be within the protection scope of the claims of the present application.

Claims

1. A universal calibration system for DAC sampling system transfer path delay error, characterized in that, The system comprises a clock source CLK, an output signal S, M-channel high-speed analog-to-digital conversion DA chips, a large-scale programmable gate array FPGA and a built-in program of the FPGA. The clock source CLK and a digital signal transmitted by FPGA configuration are converted into analog signals by the M-channel high-speed DA chips, the FPGA configures the DA chips through an SPI interface, and the FPGA connects the DA chips through a high-speed parallel interface to form a high-speed sampling system. The FPGA converts parallel data into serial data by using a high-speed parallel-to-serial conversion primitive OSERDES or a parallel-to-serial conversion IP core SelectIO and injects the serial data into the DA chips to realize first-stage speedup; the FPGA configures the DA chips to complete multi-phase synthesis of multi-channel input digital signals, realize parallel-to-serial conversion and realize second-stage speedup. The built-in program of the FPGA transmits test signals of corresponding multi-channel frequency division frequencies according to a sampling rate of the DA chips, sets virtual input and output, controls output delay of the DAC data line in real time, dynamically sets a delay value into a delay control statement of the FPGA, observes whether phases of output digital signals are consistent through an oscilloscope, adjusts a compensation delay value required for equal length of each data line in real time, and completes the whole calibration. The first-stage speedup is completed by the FPGA, which converts multiple parallel branch data into serial data by using the high-speed parallel-to-serial conversion primitive OSERDES or the parallel-to-serial conversion IP core SelectIO to realize the first-stage speedup. The second-stage speedup is completed by the DA chips, and the FPGA configures the DA chips through the SPI interface to complete multi-phase synthesis of multi-channel digital signal sources to realize the second-stage speedup. The built-in program of the FPGA is realized by using a state machine design idea, specifically, the state machine is divided into an idle state Idle, a DA multi-phase synthesis configuration state Synthesis, an FPGA test signal transmission state Test_in, a delay parameter calibration state Align, a DA data line alignment judgment state Judgment and an FPGA actual digital signal transmission state Test_out. The sampling frequency of the clock source CLK is fs and does not exceed the highest sampling rate of the DA chips.

2. The universal calibration system for DAC sampling system transfer path latency error according to claim 1, wherein, Based on the system of claim 1, the following steps are included:

3. A general calibration method for DAC sampling system transfer path delay error, characterized in that, S1, after the high-speed sampling system is powered on and the FPGA program is loaded, a reset signal pulse is generated to make the state machine in an idle state Idle; when the state machine jumps into the Synthesis state for the first time after power-on or when a sampling clock changes, the FPGA transmits a configuration pulse to complete multi-phase synthesis of the DA chips in the Synthesis state; S2, after the configuration is completed, the state machine enters the Test_In state, the FPGA transmits test signals of corresponding multi-channel frequency division frequencies according to a sampling rate of the DA chips; after the test signal transmission is completed, the state machine enters the Align state, delay calibration is started, a virtual IO is set to control delay of each data line, and a delay control statement is dynamically set. ​ S3, after controlling the time delay parameter, the state machine enters the JudgeMent state, and whether all the data lines of DA are aligned after calibration is observed by oscilloscope; if not, it returns to the Align state, adjusts the time delay parameter of the unaligned data line, and then judges whether the data line is aligned; if all the data lines of DA are aligned, the state machine enters the Test_Out state, and the FPGA switches the digital signal source to send the actual signal; S4, after the digital signal source is switched successfully, the state machine returns to the Idle state, completes a cycle of time delay parameter calibration, and waits for the start of the next process.

4. The universal calibration method of DAC sampling system transfer path delay error according to claim 3, characterized in that, After step S4, the following steps are included: S5, after completing the time delay parameter calibration, the FPGA can be configured to send multiple actual signals, including a point frequency signal and a modulated signal.

5. The universal calibration method of DAC sampling system transfer path delay error according to claim 3, characterized in that, In step S1, the following sub-steps are included: after the high-speed sampling system is powered on, a high and low pulse reset signal is generated in the FPGA as needed, the reset is completed to enter the idle state, and a clock period or sampling frequency change is waited for; when waiting for a clock period or sampling frequency change for the first time, the state machine jumps to the DA configuration multi-phase synthesis state Synthesis state, and enters the FPGA configuration test sequence state Test_In after configuration is completed.

6. The universal calibration method of DAC sampling system transfer path delay error according to claim 3, characterized in that, In step S2, the following sub-steps are included: in the Test_In state, the FPGA sends a test signal with a corresponding multi-frequency frequency according to the DA chip sampling rate, and a virtual logic analyzer ILA is added in the FPGA to observe whether the test signal is successfully sent; when observing that the parallel multi-channel data is a test signal, it indicates that the FPGA configuration sends the test signal successfully, and the time delay calibration instruction is started, and the time delay parameter calibration Align state is entered.

7. The universal calibration method of DAC sampling system transfer path delay error according to claim 3, characterized in that, In step S3, the following sub-steps are included: in the Align state, a virtual IO is set in the FPGA program to control the DAC data line output delay in real time, and the delay value is dynamically placed in the FPGA delay control statement ODELAY; whether the phase of the data line injected by the FPGA output to the DA is consistent is observed by the oscilloscope at the DA end, and the compensation delay value required for equalizing each data line is adjusted in real time; after the time delay parameter is dynamically placed in the delay statement, whether the DA data line is aligned after calibration is judged JudgeMent; if the DA data line is uneven, it jumps to the Align state again for calibration; if the DA data line is aligned, it jumps to the FPGA configuration actual signal sending state Test_Out; In the Test_Out state, the FPGA completes the digital signal source switching and sends the actual signal, at which time the DA outputs the actual sampling signal, and the state machine enters the idle state to complete a cycle of input time delay self-calibration under the current sampling frequency; when the sampling clock of the system changes, the time delay calibration process is started again.

Images